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WO2021134752A1 - Convertisseur continu-continu de mode de courant - Google Patents

Convertisseur continu-continu de mode de courant Download PDF

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Publication number
WO2021134752A1
WO2021134752A1 PCT/CN2020/070110 CN2020070110W WO2021134752A1 WO 2021134752 A1 WO2021134752 A1 WO 2021134752A1 CN 2020070110 W CN2020070110 W CN 2020070110W WO 2021134752 A1 WO2021134752 A1 WO 2021134752A1
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WIPO (PCT)
Prior art keywords
switch
state
duration
converter system
timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/070110
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English (en)
Inventor
Wei Zhao
Jianzhang XIE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
Original Assignee
Texas Instruments Japan Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to CN202080091587.5A priority Critical patent/CN114981747B/zh
Priority to PCT/CN2020/070110 priority patent/WO2021134752A1/fr
Priority to US16/876,897 priority patent/US11750078B2/en
Publication of WO2021134752A1 publication Critical patent/WO2021134752A1/fr
Anticipated expiration legal-status Critical
Priority to US18/221,012 priority patent/US12388349B2/en
Priority to US19/291,807 priority patent/US20250364896A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to integrated circuits and, more particularly, to a current mode DC-DC converter system.
  • a current mode DC-DC converter may include a current loop that determines on or off time of a switch in each switching cycle by sensing an inductor current flowing through an inductor that is coupled to a switch node of the DC-DC converter, thereby regulating the inductor current.
  • a pulse-width-modulation (PWM) signal that controls the switch is regulated based on the sensed inductor current, the on-time or off-time determined based on input and output voltages of the DC-DC converter.
  • PWM pulse-width-modulation
  • the PWM signal is regulated based on the sensed inductor current, and a clock signal with a fixed target frequency.
  • a DC-DC converter system for example, a switch mode DC-DC converter, usually includes a switch operable between on and off states based on a frequency signal, for example, a pulse-width-modulation (PWM) signal, to generate an output DC voltage to a load by periodically storing energy from a source that provides an input DC voltage in a magnetic field of an inductor or a transformer and releasing the energy from the magnetic field.
  • PWM pulse-width-modulation
  • the present disclosure provides a DC-DC converter system including a first switch coupled to a switching node and operable between first and second states, and a controller, coupled to the first switch, and configured to switch the first switch between the first and second states based on an input voltage and an output voltage of the DC-DC converter system.
  • the controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the DC-DC converter system, a second timer configured to determine a second duration based on a predetermined duration substantially equal to or greater than a minimum duration of the first state of the first switch and the input and output voltages, and logic circuitry coupled to the first and second timers and configured to generate an expiration signal upon expiration of both the first and second durations; and a control logic unit, configured to switch the first switch from the second state to the first state based on the expiration signal.
  • a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the DC-DC converter system, a second timer configured to determine a second duration based on a predetermined duration substantially equal to or greater than a minimum duration of the first state of the first switch and the input and output voltages, and logic circuitry coupled to the first and second timers and configured to generate an expiration signal upon expiration of both
  • the present disclosure provides a controller for switching a first switch of a DC-DC converter system.
  • the controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the DC-DC converter system, a second timer configured to determine a second duration based on input and output voltages of the DC-DC converter system and a predetermined duration substantially equal to or greater than a minimum duration of a first state of the first switch, and logic circuitry coupled to the first and second timers and configured to generate an expiration signal upon expiration of both the first and second durations; and a control logic unit, configured to switch the first switch froma second state to the first state based on the expiration signal.
  • the present disclosure provides a DC-DC converter system including: a first switch coupled to a switching node of the DC-DC converter system and a voltage supply node, and operable between first and second states; a first timer including a first capacitive element with a first capacitance, a first timing switching coupled in parallel with the first capacitive element, a first current source coupled in series with the first capacitive element and configured to source or sink a first current to or from the first capacitive element, and a first comparator with a first input terminal coupled to the first capacitive element, a second input terminal configured to receive a first reference voltage, and an output terminal configured to generate a first timer expired signal upon expiration of a first duration determined based on the first capacitance, the first current source and the first reference voltage; a second timer including a second capacitive element with a second capacitance, a second timing switching coupled in parallel with the second capacitive element; a second current source coupled in series with the second capacitive element and
  • FIG. 1 is a schematic block diagram of a DC-DC converter system in accordance with a first implementation of the present disclosure
  • FIGS. 2A-2D show schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 1;
  • FIG. 3 is a schematic block diagram of a DC-DC converter system in accordance with a second implementation of the present disclosure
  • FIG. 4 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 3;
  • FIG. 5 is a schematic block diagram of a DC-DC converter system in accordance with a third implementation of the present disclosure.
  • FIG. 6 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 5;
  • FIG. 7 is a schematic block diagram of a DC-DC converter system in accordance with a fourth implementation of the present disclosure.
  • FIG. 8 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 7;
  • FIG. 9 is a schematic block diagram of a DC-DC converter system in accordance with a fifth implementation of the present disclosure.
  • FIG. 10 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 9;
  • FIG. 11 is a schematic block diagram of a DC-DC converter system in accordance with a sixth implementation of the present disclosure.
  • FIG. 12 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 11;
  • FIG. 13 is a schematic block diagram of a DC-DC converter system in accordance with a seventh implementation of the present disclosure.
  • FIG. 14 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 13;
  • FIG. 15 is a schematic block diagram of a DC-DC converter system in accordance with an eighth implementation of the present disclosure.
  • FIG. 16 is a schematic circuit diagrams of a timer unit of the DC-DC converter system of FIG. 15;
  • FIG. 17 is a flow chart of a method of operating a DC-DC converter system in accordance with an implementation of the present disclosure.
  • the present disclosure relates to current mode DC-DC converter systems.
  • FIG. 1 a schematic block diagram of a DC-DC converter system 100 in accordance with a first implementation of the present disclosure is shown. More particularly, FIG. 1 shows an adaptive off-time current mode boost DC-DC converter system with peak current control topology.
  • the system 100 includes a first switch 102 coupled between a switch node SW and a voltage supply node, for example, a ground node GND, and a second switch 104 coupled between the switch node SW and an output node VOUT of the system 100, thereby allowing a current flowing from the switch node SW to the output node VOUT.
  • the first and second switches 102 and 104 also named respectively as low side and high side switches, can be transistors, for example, N-channel MOSFETs that are respectively controlled by gate drive signals LSD_ON and HSD_ON to alternately operable between first and second states, e.g.
  • the system 100 also includes an input inductor 106 coupled between an input node VIN and the switch node SW, and an output capacitive element 108 coupled between the output node VOUT and the ground node GND.
  • the system 100 includes a controller 110 coupled to the first and second switches 102 and 104 to generate a PWM signal to alternately switch on and off the first and second switches 102 and 104 through a driver unit 112 which generates the gate drive signals LSD_ON and HSD_ON based on the PWM signal.
  • the driver unit 112 can be either a part of or separate from the controller 110.
  • the controller 110 includes a sensing unit 114 configured to generate a control signal Sc based on a difference between a sensing voltage Vs proportional to an inductor current IL through the inductor 106 and a control voltage Vc proportional to a difference between a reference voltage VREF and a feedback voltage VFB proportional to the output voltage VOUT, generated by an amplifier 116.
  • the sensing unit 114 includes a comparator 118 configured to generate the control signal Sc to switch the first switch 102 from the on state to the off state if the sensing voltage Vs increases to the control voltage Vc.
  • the sensing voltage Vs is proportional to a current Is flowing through the first switch 102 and obtained through a current-to-voltage (I/V) unit 120, for example, by sensing a voltage across a sensing resistor (not shown) coupled between the first switch 102 and the ground node GND.
  • I/V current-to-voltage
  • the controller 110 includes a control logic 124 configured to switch the first switch 102 from the on state to the off state through the driver unit 112, based on the control signal Sc.
  • a minimum duration of the on state, also known as a minimum on-time Ton_min, of the first switch is usually limited due to various factors of the DC-DC converter system 100, such as blanking time of inductor current IL sensing, delay caused by the comparator 118, the control logic 124 and/or the driver unit 112.
  • the minimum on-time of the first switch 102 limits the range of a ratio of output voltage VOUT to the input voltage VIN.
  • the controller 110 also includes a timer unit 122 configured to determine a preferred duration of the off state, also known as an off-time Toff, of the first switch 102 based on a target switching frequency fsw of the DC-DC converter system 100, the minimum on-time Ton_min of the first switch, and the input and output voltages VIN and VOUT of the system 100.
  • a timer unit 122 configured to determine a preferred duration of the off state, also known as an off-time Toff, of the first switch 102 based on a target switching frequency fsw of the DC-DC converter system 100, the minimum on-time Ton_min of the first switch, and the input and output voltages VIN and VOUT of the system 100.
  • the timer unit 122 is further configured to generate an expiration signal S T to switch the first switch 102 from the off state to the on state when the preferred off-time Toff expires.
  • the control logic 124 is configured to generate the PWM signal based on the control signal Sc and the expiration signal S T .
  • the control logic 124 can be an edge-triggered SR flip flop that asserts the PWM signal based on the expiration signal S T and de-asserts the PWM signal based on the control signal Sc.
  • FIG. 2A shows an example schematic circuit diagram of a timer unit 200, such as the timer unit 122 of the DC-DC converter system 100 of FIG. 1.
  • the timer unit 200 includes a first timer 202 configured to generate a first timer expired signal S T1 based on a first duration T1.
  • the first duration T1 is a nominal duration of the second state, e.g.
  • the off state, of the first switch 102 determined based on the target switching frequency fsw of the DC-DC converter system 100 and the input and output voltages VIN and VOUT, such that the DC-DC converter system operating at the target switching frequency fsw converts the input voltage VIN to the output voltage VOUT by keeping the first switch 102 at the off state for the nominal duration in each target switching cycle T.
  • the first duration T1 is determined in accordance with the equation below:
  • T the target switching cycle
  • the first timer 202 includes a first capacitive element 204 with a capacitance C1.
  • the first capacitive element 204 is coupled in parallel with a first charging control switch 206 that is controlled by the gate drive signal LSD_ON, and in series with a first current source 208 configured to source a first charging current Ic1 to the first capacitive element 204.
  • Ic1 VOUT/R1.
  • Charging the first capacitive element 204 is triggered upon the first switch 102 being switched from the on state to the off state.
  • the first capacitive element 204 is coupled between a non-inverting input of the first capacitive element 210 and the ground node GND.
  • the first capacitive element 210 is configured to generate a first timer expired signal S T1 when a voltage across the first capacitive element 204 increased to the reference voltage K*VIN. Accordingly, the first duration T1 is determined by the first timer 202 in accordance with the equation below:
  • K ⁇ R1 is resistance of a resistor 236 of a charging path of the first timer 202 shown in FIG. 2C, and K ⁇ R1 ⁇ C1 is configured to be substantially equal to the target
  • the switching cycle T 1/fsw of the DC-DC converter system 100 within acceptable error range resulting from inherent errors of the first capacitive element 210 and the resistor 236.
  • the first charging current Ic1 and the reference voltage Vref1 can be other values as long as meeting the equation below:
  • the second timer 212 is configured to be triggered substantially simultaneously with the first timer based on the gate drive signal LSD_ON, and to generate a second timer expired signal S T2 based on a second duration T2 that is determined based on the minimum on-time Ton_min of the first switch 102 and the input and output voltages VIN and VOUT.
  • the second duration T2 is provided in accordance with the equations below:
  • K ⁇ R2 is resistance of a resistor 242 of a charging path of the second timer 212 shown in FIG. 2D, and K ⁇ R2 ⁇ C2 is configured to be substantially equal to or slightly greater, e.g. 10ns greater, than the minimum on-time Ton_min of the first switch 102.
  • the second timer 212 includes a second charging switch 220 configured to be switched off simultaneously with switching off the first charging switch 206, and K ⁇ R2 ⁇ C2 is configured to be substantially equal to the minimum on-time Ton_min of the first switch 102, such that the second duration equals an off-time of the first switch 102 determined under the condition that the on-time of the first switch 102 is the minimum on-time Ton_min.
  • the second timer 212 includes a second charging switch 220 configured to be switched off simultaneously with switching off the first charging switch 206, and K ⁇ R2 ⁇ C2 is configured to be slightly, e.g. 10ns, greater, than the minimum on-time Ton_min of the first switch 102 to ensure the second duration longer than an off-time of the first switch 102 determined under the condition that the on-time of the first switch 102 is the minimum on-time Ton_min.
  • K ⁇ R2 ⁇ C2 is configured to be substantially equal to the minimum on-time Ton_min of the first switch 102
  • the second timer 212 further includes a delay unit 222 such that the second charging switch 220 is configured to be switched off slightly later, e.g. 50ns or more, than switching off the first charging switch 206 to ensure the second duration longer than an off-time of the first switch 102 determined under the condition that the on-time of the first switch 102 is the minimum on-time Ton_min.
  • the second timer 212 further includes a second comparator 224 with an inverting input coupled to another reference voltage generator to receive another reference voltage Vref2.
  • the second charging current Ic2 and the reference voltage Vref2 can be other values as long as meeting the equation below:
  • the timer unit 200 also includes a logic gate 218 configured to generate the expiration signal S T upon both the first and second timer expired signals S T1 and S T2 being asserted.
  • a logic gate 218 configured to generate the expiration signal S T upon both the first and second timer expired signals S T1 and S T2 being asserted.
  • the second duration T2 is smaller than the first duration T1
  • the preferred duration of the off state of the first switch 102 is determined by the first duration T1, which is the nominal duration of the off state of the first switch 102 determined based on the target switching frequency fsw and the input and output voltages of the system 100.
  • an actual switching cycle of the DC-DC converter system 100 is configured to be K ⁇ R2 ⁇ C2 ⁇ VOUT/ (VOUT-VIN) , with is greater than the target switching cycle of the DC-DC converter system 100.
  • FIG. 2B shows an example schematic circuit diagram of the reference voltage generator 226 that provides the reference voltage K ⁇ VIN.
  • the reference voltage generator 226 includes a voltage divider 228 generating the reference voltage K ⁇ VIN proportional to the input voltage VIN.
  • FIG. 2C shows an example schematic circuit diagram of a current source 230, for example, the first current source 208 of the timer unit 200 of FIG. 2.
  • the first current source 230 includes an error amplifier 232 having an output terminal coupled to a gate node of a transistor 234, a non-inverting input terminal configured to receive a reference voltage K ⁇ VOUT which can be provided in a similar manner as the reference voltage generator 220 shown in FIG. 2B, and an inverting input terminal coupled to a source node of the transistor 234.
  • FIG. 2D shows an example schematic circuit diagram of another current source 240, for example, the second current source 216 of the timer unit 200 of FIG. 2.
  • the second current source 240 has a structure similar to that of the first current source 230 except that a voltage difference across the resistor 242 is configured to be VOUT-VIN.
  • the control logic unit 124 is configured to switch the first switch 102 from the off state to the on state based on the expiration signal S T . Therefore, the duration of the off state, i.e., the off time Toff, of the first switch 102 is configured to be a greater one between the first and second duration T1 and T2.
  • the off-time Toff of the first switch e.g. the low side switch
  • the off-time Toff′ determined in accordance with the equation below:
  • Toff′ T ⁇ VIN/VOUT (6)
  • an on duty cycle range of the system is limited between Ton_min/T and 1, and thus a ratio of VOUT to VIN range is limited between T/ (T-Ton_min) and ⁇ .
  • operation ranges of other conventional adaptive on-time/off-time current mode DC-DC converter systems with other topologies are also limited by the nominal off-time and minimum on-time of the system, or a nominal on-time and a minimum-off time of the system. Table 1 lists the operation ranges of conventional adaptive on-time/off-time current mode DC-DC converter systems with different topologies.
  • the proposed adaptive off-time current mode boost DC-DC converter system 100 dynamically extends the off-time Toff of the first switch 102 when the off-time determined based on the minimum on-time Ton_min and the input and output voltages VIN and VOUT is greater than the nominal off-time of the DC-DC converter system.
  • the off-time of the first switch 102 can be extended to Ton_min ⁇ VIN/ (VOUT-VIN) when a target ratio of VOUT to VIN is less than T/ (T-Ton_min)
  • the range of on duty cycle can be extended between 0 and 1
  • the range of VOUT/VIN can be extended between 1 and ⁇ .
  • FIG. 3 shows a schematic block diagram of a DC-DC converter system 300 in accordance with a second implementation of the present disclosure. More particularly, FIG. 3 shows an adaptive on-time current mode boost DC-DC converter system with valley current control topology.
  • the DC-DC converter system 300 is substantially similar to the DC-DC converter system 100 of FIG. 1 except that the sensing voltage Vs is generated proportional to a current flowing through the second switch 304, i.e. the high side switch, the comparator 318 is configured to generate the control signal Sc when the sensing voltage Vs decreases to the control voltage Vc, and the control logic 324 is configured to switch on the first switch 302 based on the control signal Sc and to switch off the first switch 302 based on the expiration signal S T generated by the timer unit 322.
  • FIG. 4 shows an example schematic circuit diagram of a timer unit 400, such as the timer unit 322 of the DC-DC converter system 300 of FIG. 3.
  • the timer unit 400 includes a first timer 402 configured to generate a first timer expired signal S T1 based on a first duration T1.
  • the first duration T1 is a nominal duration of the on state, i.e. a nominal on-time Ton, of the first switch 302 determined based on a target switching frequency fsw of the DC-DC converter system 300 and input and output voltages VIN and VOUT in accordance with the equation below:
  • T the target switching cycle of the system 300
  • T 1/fsw.
  • the first timer 402 is configured to determine the first duration T1, i.e., the nominal on-time of the first switch 302, in accordance with the equation below:
  • the timer unit 400 also includes a second timer 412 with a structure similar to that of the first timer 402 except that the second timer 412 is configured to generate a second timer expired signal S T2 based on a second duration T2 provided in accordance with the equations below:
  • K ⁇ R2 ⁇ C2 is configured to be substantially equal to or slightly greater, e.g. 10ns greater, than aminimumduration of the off state, i.e., the minimum off-time Toff_min, of the first switch 302.
  • the first and second timer 402 and 412 are configured to start timing upon the second switch 304 being switched from the on state to the off state, i.e, when the first switch 302 is switched from the off state to the on state. Similar to the timer unit 200 of FIG. 2, the timer unit 400 is configured to generate an expiration signal S T upon both of the first and second timer expired signals S T1 and S T2 being asserted.
  • the on-time of the first switch 302 can be extended to Toff_min ⁇ (VOUT-VIN) /VIN when a target ratio of VOUT to VIN is greater than T/Toff_min
  • the range of on duty cycle can be extended between 0 and 1
  • the range of VOUT/VIN can be extended between 1 and ⁇ .
  • FIG. 5 in combination with FIG. 6 shows a schematic block diagram of a DC-DC converter system 500 in accordance with a third implementation of the present disclosure. More particularly, FIG. 5 shows an adaptive on-time current mode buck DC-DC converter system with valley current control topology. Similar to the adaptive on-time current mode boost DC-DC converter system 300 shown in FIG. 3 in combination with the timer unit 400 of FIG. 4, the DC-DC converter system 500 is configured to switch off the first switch 502, i.e. the high side switch, based on an expiration signal S T generated by the timer unit 522.
  • the timer unit 522 shown as the timer unit 600 of FIG.
  • the first duration T1 is determined based on a nominal duration of the on state, e.g. a nominal on-time Ton, of the first switch 602 determined based on the switching frequency fsw and the input and output voltages VIN and VOUT of the DC-DC converter system 500
  • the second duration T2 is determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum duration of the off state, also known as minimum off-time Toff_min, of the first switch 502. Similar to the DC-DC converter system 300 of FIG.
  • the duration of the on state, i.e., the on-time, of the first switch 502 can be extended to Toff_min ⁇ VOUT/ (VIN-VOUT) when a target ratio of VOUT to VIN is greater than 1-Toff_min/T, the range of on duty cycle can be extended between 0 and 1, and the range of VOUT/VIN can be extended between 0 and 1.
  • FIG. 7 in combination with FIG. 8 shows a schematic block diagram of a DC-DC converter system 700 in accordance with a fourth implementation of the present disclosure. More particularly, FIG. 7 shows an adaptive off-time current mode buck DC-DC converter system with peak current control topology. Similar to the adaptive on-time current mode buck DC-DC converter system 500 shown in FIG. 5 in combination with the timer unit 600 of FIG. 6, the DC-DC converter system 700 is configured to switch on the first switch 702, i.e. the high side switch, based on the expiration signal S T generated by the timer unit 722. The timer unit 722, shown as the timer unit 800 of FIG.
  • the second duration T2 is determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum on-time Ton_min of the first switch 702. Similar as the DC-DC converter system 500 of FIG.
  • Ton_min ⁇ (VIN-VOUT) /VOUT when a target ratio of VOUT to VIN is less than Ton_min/T the range of on duty cycle can be extended between 0 and 1
  • the range of VOUT/VIN can be extended between 0 and 1.
  • Table 2 lists the operation ranges of adaptive on-time/off-time current mode DC-DC converter systems with different topologies in accordance with the first to fourth implementations of the present disclosure.
  • FIG. 9 a schematic block diagram of a DC-DC converter system 900 in accordance with a fifth implementation of the present disclosure is shown. More particularly, FIG. 9 shows a fixed frequency current mode boost DC-DC converter system with peak current control topology.
  • the DC-DC converter system 900 is substantially similar to the DC-DC converter system 100 of FIG. 1 except that the sensing voltage Vs provided to the comparator 918 is proportional to a combination of the current flowing through the first switch 902 and a slope compensation signal, and the control logic 924 is configured to switch on the first switch 902 based on a clock signal CLK generated by the timer unit 922, for example, a rising edge of the clock signal CLK.
  • FIG. 10 shows an example schematic circuit diagram of a timer unit 1000, such as the timer unit 922 of the DC-DC converter system 900 of FIG. 9.
  • the timer unit 1000 is substantially similar to the timer unit 200 of FIG. 2, except that the timer unit 922 further includes a one-shot signal generator 1022 coupled to the switches 1006 and 1020 to provide a one-shot signal RST based on the clock signal CLK, such that the first and second timers 1002 and 1012 start timing upon the first switch 902 being switched from the off state to the on state.
  • the first timer 1002 is configured to generate a first timer expired signal S T1 based on a first duration T1.
  • the first duration T1 is provided in accordance with the equations below:
  • T1 K ⁇ R1 ⁇ C1
  • the timer unit 1000 also includes a second timer 1012 configured to generate a second timer expired signal S T2 based on a second duration T2 that is determined based on a minimum duration of the on state, i.e., a minimum on-time Ton_min, of the first switch 902 and the input and output voltages VIN and VOUT.
  • the second duration T2 is determined based on the input and output voltages VIN and VOUT, and a predetermined duration substantially equal to greater than the minimum on-time Ton_min of the first switch 902.
  • the second duration T2 is provided in accordance with the equations below:
  • K ⁇ R2 ⁇ C2 is configured to be substantially equal to or slightly greater, e.g. 10ns greater, than the minimum on-time Ton_min of the first switch 902.
  • the timer unit 1000 further includes a gate logic 1018 configured to generate, for example, a rising edge, of the clock signal CLK based on the first and second timer expired signals S T1 and S T2 , wherein the cycle of the clock signal CLK is configured to be the larger one of the first and second duration T1 and T2.
  • a gate logic 1018 configured to generate, for example, a rising edge, of the clock signal CLK based on the first and second timer expired signals S T1 and S T2 , wherein the cycle of the clock signal CLK is configured to be the larger one of the first and second duration T1 and T2.
  • a cycle of a clock signal CLK that periodically switches the first switch from a second state, e.g. the off state, to a first state, e.g. the on state, is fixed by the target switching frequency fsw of the conventional system.
  • Ton_min/T Ton_min/T
  • 1-Toff_min/T a range of a ratio of VOUT to VIN
  • operation ranges of other conventional fixed frequency current mode DC-DC converter systems with other topologies are also limited by the target switching cycle and minimum on or off time of the first switch of the system. Table 3 lists the operation ranges of conventional fixed frequency current mode DC-DC converter systems with different topologies.
  • the proposed fixed frequency current mode boost DC-DC converter system 900 dynamically extends the switching cycle when a switching cycle determined based on the minimum on-time Ton_min and the input and output voltages VIN and VOUT is greater than the target switching cycle of the DC-DC converter system.
  • Ton_min VOUT/ (VOUT-VIN) when a target ratio of VOUT to VIN is less than T/ (T-Ton_min)
  • the range of on duty cycle can be extended between 0 and 1-Toff_min/T
  • the range of VOUT/VIN can be extended between 1 and T/Toff_min.
  • FIG. 11 in combination with FIG. 12 shows a schematic block diagram of a DC-DC converter system 1100 in accordance with a sixth implementation of the present disclosure. More particularly, FIG. 11 shows a fixed current mode boost DC-DC converter system with valley current control topology. Similar to the timer unit 1000 of FIG. 10, the timer unit 1200 is configured to generate a clock signal CLK with a cycle determined based on a larger one between the target switching cycle of the DC-DC converter system 1100 and an adjusted cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum off time Toff_min of the first switch 1102 of the DC-DC converter system 1100. The control logic 1124 is configured to switch off the first switch 1102 upon, for example, a rising edge, of the clock signal CLK.
  • FIG. 13 in combination with FIG. 14 shows a schematic block diagram of a DC-DC converter system 1300 in accordance with a seventh implementation of the present disclosure. More particularly, FIG. 13 shows a fixed current mode buck DC-DC converter system with peak current control topology. Similar to the timer unit 1000 of FIG. 10, the timer unit 1400 is configured to generate a clock signal CLK with a cycle determined based on a larger one between the target switching cycle of the DC-DC converter system 1300 and an adjusted cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum on time Ton_min of the first switch 1302 of the DC-DC converter system 1300.
  • the control logic 1324 is configured to switch on the first switch 1302 upon, for example, a rising edge, of the clock signal CLK.
  • FIG. 15 in combination with FIG. 16 shows a schematic block diagram of a DC-DC converter system 1500 in accordance with an eighth implementation of the present disclosure. More particularly, FIG. 15 shows a fixed current mode buck DC-DC converter system with valley current control topology. Similar to the timer unit 1200 of FIG. 12, the timer unit 1200 is configured to generate a clock signal CLK with a cycle determined based on a larger one between the target switching cycle of the DC-DC converter system 1500 and an adjusted cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than the minimum on time Toff_min of the first switch 1502 of the DC-DC converter system 1500.
  • the control logic 1524 is configured to switch off the first switch 1502 upon, for example, a rising edge, of the clock signal CLK.
  • Table 4 lists the operation ranges of fixed frequency current mode DC-DC converter systems with different topologies in accordance with the fifth to eighth implementations of the present disclosure.
  • the DC-DC converter system includes the first switch 102 coupled between the switch node SW and a voltage supply node, for example, a ground node GND.
  • the inductor 106 is coupled between the switch node SW and the voltage input node VIN
  • second switch 104 is coupled between the switch node SW and the voltage output node VOUT.
  • the first switch 102 is configured to periodically allow the inductor current IL to flow there through.
  • Other topologies of current mode DC-DC converter systems with the same mechanism to sensing a load current and regulate the DC-DC converter system are possible as well, such as the DC-DC converter systems 300 to 1500 respectively shown in FIGS. 3-15.
  • control logic 124 generates a PWM signal to switch the first switch 102 from a first state, e.g. on state, to a second state, e.g. off state, through the driver unit 112.
  • the first timer 202 of the timer unit 122 starts timing a first duration T1, and substantially simultaneously, the second timer 212 of the timer unit 122 starts timing a second duration T2 that is determined based on input and output voltages VIN and VOUT of the DC-DC converter system 100 and a minimum duration of the first state of the first switch 102, i.e., the minimum on-time Ton_min, of the first switch 102.
  • the first and second timers 202 and 212 are configured to start timing upon the first switch 102 being switched from the first state to the second state
  • the first duration T1 is a nominal duration of the second state of the first switch 102 determined based on a target switching frequency fsw of the DC-DC converter system and the input and output voltages
  • the second duration T2 is an adjusted duration of the second state of the first switch determined based on the input and output voltages VIN and VOUT and a predetermined duration substantially equal to greater than a minimum duration of the first state of the first switch.
  • the first duration T1 is a nominal duration of the off state, i.e., a nominal off time Toff, of the first switch 102, and provided in accordance with the equations below:
  • fsw is atarget switching frequency of the DC-DC converter system 100.
  • the second duration T2 is an adjusted duration of the off state, i.e., an adjusted off-time, of the first switch 102 determined based on the input and output voltages VIN and VOUT and a predetermined duration Ton_min′ substantially equal to or greater than a minimum duration of the on state, i.e., a minimum on-time Ton_min, of the first switch 102.
  • the second duration T2 is provided in accordance with the equations below:
  • Ton_min′ is the predetermined duration substantially equal to or slightly greater, e.g. 10ns greater, than the minimum on-time Ton_min of the first switch 902.
  • the first and second timers start timing upon the first switch 902 being switched from the second state to the first state, e.g., for the DC-DC converter system 900, from the off state to the on state.
  • the first duration T1 is the target switching cycle T of the DC-DC converter system 900.
  • the second duration T2 is an adjusted switching cycle determined based on the input and output voltages VIN and VOUT and a predetermined duration Ton_min′ substantially equal to or greater than the minimum on time Ton_min of the first switch 902.
  • the second duration T2 is provided in accordance with the equations below:
  • Ton_min′ is the predetermined duration substantially equal to or slightly greater, e.g. 10ns greater, than the minimum on-time Ton_min of the first switch 902.
  • the sensing unit 114 generates a control signal Sc to switch the first switch 102 from the first state, e.g. the on state, to the second state, e.g. the off state, based on a difference between a sensed voltage Vs proportional to the inductor current IL and a difference between a reference voltage VREF and a feedback voltage VFB proportional to the output voltage VOUT.
  • switching the first switch from the first state to the second state comprises switching the first switch from the on state to the off state upon a current through the first switch increasing to a peak value determined based on the difference between the feedback voltage VFB of the output voltage VOUT and the reference voltage VREF and expiration of a minimum on-time of the first switch.
  • switching the first switch from the first state to the second state comprises switching the first switch from an off state to an on state upon a current through the second switch decreasing to a valley value determined based on a difference between the feedback voltage VFB of the output voltage VOUT and a reference voltage VREF and expiration of a minimum off-time of the first switch.
  • the timer unit 122 generates an expiration signal S T to switch the first switch 102 from the second state to the first state upon expiration of both the first and second timers.
  • Couple is used throughout the specification.
  • the term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B by direct connection, or in a second example device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un système convertisseur (100) comprenant un premier commutateur (102) et un dispositif de commande (110) conçu pour commuter le premier commutateur (102) entre des premier et second états sur la base de tensions d'entrée et de sortie du système convertisseur (100), le dispositif de commande (110) comprenant : une unité de temporisation (200) comprenant un premier temporisateur (202) conçu pour déterminer une première durée sur la base d'une fréquence de commutation cible du système convertisseur (100), et un second temporisateur (212) conçu pour déterminer une seconde durée sur la base d'une durée prédéfinie égale ou supérieure à une durée minimale du premier état du premier commutateur (102) et des tensions d'entrée et de sortie ; et une unité logique de commande (124), conçue pour commuter le premier commutateur (102) du second état vers le premier état à l'expiration à la fois des première et seconde durées.
PCT/CN2020/070110 2020-01-02 2020-01-02 Convertisseur continu-continu de mode de courant Ceased WO2021134752A1 (fr)

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CN202080091587.5A CN114981747B (zh) 2020-01-02 2020-01-02 电流模式dc-dc转换器
PCT/CN2020/070110 WO2021134752A1 (fr) 2020-01-02 2020-01-02 Convertisseur continu-continu de mode de courant
US16/876,897 US11750078B2 (en) 2020-01-02 2020-05-18 Adaptive off-time or on-time DC-DC converter
US18/221,012 US12388349B2 (en) 2020-01-02 2023-07-12 Adaptive off-time or on-time DC-DC converter
US19/291,807 US20250364896A1 (en) 2020-01-02 2025-08-06 Adaptive off-time or on-time dc-dc converter

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FI20215492A1 (en) * 2021-04-28 2022-10-29 Nordic Semiconductor Asa DC voltage regulator for low-current device
CN114825897B (zh) * 2022-05-06 2023-05-26 电子科技大学 一种自适应死区时间控制电路

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CN114981747B (zh) 2024-02-09
US11750078B2 (en) 2023-09-05
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US20230353037A1 (en) 2023-11-02
US20210211047A1 (en) 2021-07-08
US20250364896A1 (en) 2025-11-27

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