WO2021127809A1

WO2021127809A1 - Imaging apparatus and imaging method

Info

Publication number: WO2021127809A1
Application number: PCT/CN2019/127325
Authority: WO
Inventors: Takamasa Sakuragi
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2021-07-01
Anticipated expiration: 2022-06-23
Also published as: CN114846785A; CN114846785B

Abstract

One embodiment of this application may relate to an imaging apparatus including a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor, and a first capacitor, wherein, the first capacitor is charged while the switch is ON, and wherein after the switch turns OFF, using electric power charged at the first capacitor, the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit and output an output signal.

Description

IMAGING APPARATUS AND IMAGING METHOD

TECHNICAL FIELD

Embodiments described below relate to, for example, an imaging apparatus/method for still images and/or movies.

BACKGROUND

Imaging apparatuses and imaging methods for still images and/or movies are widely used in general. For example, digital cameras, cellular phones, terminal devices, and automobiles (car-mounted cameras) they are not limitations/restrictions.

SUMMARY

This summary including aspects shown below may relate to, for example, an imaging apparatus/method for still images and/or movies. It should be understood that disclosure below does not limit or restrict the pending application/invention.

The first aspect is an imaging apparatus including a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor, and a first capacitor, wherein, the first capacitor is charged while the switch is ON, and wherein after the switch turns OFF, using electric power charged at the first capacitor, the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit and output an output signal.

The second aspect is the imaging apparatus according to the above-described aspect, wherein the ramp signal comprises a first and a second ramp signals.

The third aspect is the imaging apparatus according to the above-described aspects, wherein the ramp signal comprises a predetermined voltage difference between the first and second ramp signals.

The fourth aspect is the imaging apparatus according to the above-described aspects, wherein when the first ramp signal reaches a same level with the pixel signal, the comparator reverses the output signal.

The fifth aspect is the imaging apparatus according to the above-described aspects, wherein when a voltage which has the same voltage level with the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.

The sixth aspect is the imaging apparatus according to the above-described aspects, wherein the capacitance of the first capacitor is large enough to drive the comparator.

The seventh aspect is the imaging apparatus according to the above-described aspects, wherein when the second ramp signal reaches the same level with the pixel signal, the comparator finishes its comparison operation.

The eighth aspect is the imaging apparatus according to the above-described aspects, wherein when the switch is OFF, the comparator is disconnected from a common power supply of the imaging apparatus.

The ninth aspect is the imaging apparatus according to the above-described aspects, wherein the first and second ramp signals are ramping-up signals.

The tenth aspect is the imaging apparatus according to the above-described aspects, wherein the first and second ramp signals are ramping-down signals.

The eleventh aspect is an imaging method of an imaging apparatus including a comparator, a pixel and a control circuit, the imaging method including: charging a first capacitor of the comparator while a switch of the comparator is ON; after the switch turns OFF, comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using electric power charged at the first capacitor; and outputting an output signal.

The twelfth aspect is the imaging method according to the above-described aspect, wherein the ramp signal comprises a first and a second ramp signals.

The thirteenth aspect is the imaging method according to the above-described aspects, wherein the ramp signal comprises a predetermined voltage difference between the first and second ramp signals.

The fourteenth aspect is the imaging method according to the above-described aspects, wherein when the first ramp signal reaches the same level with the pixel signal, the comparator reverses the output signal.

The fifteenth aspect is the imaging method according to the above-described aspects, wherein when a voltage which has a same voltage level with the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.

The sixteenth aspect is the imaging method according to the above-described aspects, wherein a capacitance of the first capacitor is large enough to drive the comparator.

The seventeenth aspect is the imaging method according to the above-described aspects, wherein when the second ramp signal reaches the same level with the pixel signal, the comparator finishes its comparison operation.

The eighteenth aspect is the imaging method according to the above-described aspects, wherein when the switch is OFF, the comparator is disconnected from a common power supply of the imaging apparatus.

The nineteenth aspect is the imaging method according to the above-described aspects, wherein the first and second ramp signals are ramping-up signals.

The twentieth aspect is the imaging method according to the above-described aspects, wherein the first and second ramp signals are ramping-down signals.

The above disclosure does not limit or restrict the present application/invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram of an imaging apparatus described in one embodiment.

FIG. 2 is a circuit diagram of one embodiment.

FIG. 3 is a timing chart of one embodiment.

FIG. 4 is a circuit diagram of one embodiment.

FIG. 5 is a timing chart of one embodiment.

DESCRIPTION OF EMBODIMENTS

The disclosure below includes mere examples. The scope of the present invention and application should not be considered to be limited by the embodiments shown below.

FIG. 1 shows a schematic diagram of an imaging apparatus of one embodiment. An imaging apparatus 100 includes a camera module 110, pixels 120, AD (analog to digital) converter 130, and a T/G (timing generator) 140. The imaging apparatus 100 can include a logic circuit 150 in place to the T/G 140. The imaging apparatus 100 can further include, for example, a set of lens, battery, memory, and screen or panel. The imaging apparatus 100 can further include, for example, a processor, harddisk, optical drive, transceiver, speaker and a microphone.

The camera module 110 includes the pixels 120, AD converter 130 and T/G 140. As described above, the T/G 140 can be replaced with the logic circuit 150 outside the camera module 110. The camera module 110 can be an image sensor circuit shown in FIG. 2.

The pixels 120 can be CMOS (complementary metal oxide semiconductor) image sensors, CCD (charge coupled device) image sensors, or other devices. The pixels 120 can be constituted by multiple pixels. The pixels 120 can further include a color filter. The pixels 120 receive light via lens not shown in the drawings and output analog signals corresponding to strength of the received light.

The AD converter 130 inputs analog signals from the pixels 120 and outputs digital signals indicating strength of the light received by the pixels 120. A processor not shown in the drawings can receive the digital signals from the AD converter 130 and generate image data. This processor can store the image data, for example, in a memory. The image data can be a still image or a portion of a movie.

The T/G 140 (or logic circuit 150) outputs pulse signals indicating operation timing based on which constitutional elements of the imaging apparatus 100 conduct operations. For example, the AD converter 130 can compare voltage of the analog signals output from the pixels 120 with a reference voltage which is not shown in FIG. 1 when inputting a timing signal from the T/G 140 (or logic circuit 150) .

Hereinafter, details of the AD converter 130 is explained in reference to the drawings.

Imaging apparatuses can include AD converters, for example, single slope AD converters (SS ADCs) . In general, it has been desired to reduce the power consumption of SS ADCs without causing side effects.

For example, it may be possible to reduce the power consumption of AD convertors (other than SS ADC) just by reducing a bias current of comparators included in AD convertors. One example of reduced consumption bias circuits is realized using a dynamic bias circuit. On the other hand, less bias currents may cause the performance of the comparators less effective, for example, analogue-to-digital conversion performance: lower speed, bigger noise, and /or lower AD precision.

As explained above, in general, it has been desired to reduce the power consumption of ADCs. It should be noted that it is not preferable to apply dynamic bias circuits for the comparators, which can reduce the power consumption of AD convertors, to SS ADCs.

Because, in general, comparators with dynamic bias circuits can compare input signals corresponding to the input digital signals, while in SS ADCs, those digital signals cannot be generated during AD conversion operations.

In general, there is possibility that dynamic bias comparators may cause big “streaking noise” . This is because dynamic bias circuits cause large amount of changes in the power supply current of a comparator. This may negatively influence the quality of images.

Hereafter, the first embodiment is to be explained. FIG. 2 illustrates an image sensor circuit including two input-pixel signal lines (Vpixel1 and Vpixel2) and two single slope ADCs. The image sensor circuit shown in FIG. 2 shows a simplified constitution for easier explanation of their operations. In an actual image sensor, far more ADCs are to be placed, typically column-wise, to accommodate the number of the pixel signal outputs. The image sensor circuit shown in FIG. 2 corresponds to the camera module shown in FIG. 1.

Input-pixel signal lines Vpixel1 and Vpixel2 are included in pixels 120 shown in FIG. 1. Each of input-pixel signal lines Vpixel1 and Vpixel2 corresponds to one pixel. I1 and I2 shown in FIG. 2 are comparators. The comparator I1 receives signals via the input-pixel signal line Vpixel1 from a pixel which is not shown in FIG. 2. The comparator I2 inputs signals via the input-pixel signal line Vpixel1 from a pixel which is not shown in FIG. 2.

VRAMP1 and VRAMP2 shown in FIG. 2 indicate ramp reference voltages supplied via lines. The comparator I1 receives the ramp reference voltage VRAMP1 from a terminal 3. The comparator I1 receives the ramp reference voltage VRAMP2 from a terminal 2. The comparator 2 has the same constitution with the comparator I1. The ramp reference voltages VRAMP1 and VRAMP2 can be output from a control circuit not shown in FIG. 2 (for example, the logic circuit 150 shown in FIG. 1) .

VDD_common shown in GIG. 2 is a common power supply shared with all or part of the comparators. The comparator I1 receives the common power supply VDD_common via a terminal 1 and conducts operations thereof. The comparator I2 has the same constitution with the comparator I1. The common power supply VDD_common can be supplied from a power source circuit which is not shown in the drawings.

The comparator I1 receives ramp reference voltages VRAMP1/VRAMP2 and an input pixel voltage (hereinafter, Vpixel1 for easy understanding) and conducts a comparison operation. The comparator I1 outputs signals indicating its comparison results from a terminal Vout1 shown in FIG. 2. The comparator I2 outputs signals indicating its comparison results from a terminal Vout2 shown in FIG. 2.

The comparator I1 includes transistors M1、M2、M3、M4、M6、M7、M8、M9, and M10. The comparator I1 includes capacitors Cp, C _G, and C _S. The comparator I1 includes a switch SW1. The comparator I1 includes terminals 1 to 5. The terminal 1 is connected to the common power supply VDD_common. The terminal 2 receives the ramp reference voltage VRAMP2. The terminal 3 receives the ramp reference voltage VRAMP1. The terminal 4 is connected to the input pixel signal line Vpixel1. Output signals from the comparator I1 are output from the terminal 5 and supplied to the counter circuit I3.

The comparator I2 has the substantially the same constitution with the comparator I1. There are small differences between them. The terminal 4 of the comparator I2 is connected to the input pixel signal line Vpixel2, and output signals of the comparator I2 are supplied to the counter circuit I4 via the terminal 5.

The counter circuit I3 receives output signals from the terminal Vout1. The counter circuit I3 receives a clock signal (CLK) . For a predetermined time period, the counter circuit I3 counts clocks included in the clock signal while the counter circuit detects the output signal from the terminal Vout1. The clock signal (CLK) can be output by a control circuit shown in the drawings (for example, the logic circuit 150 of FIG. 1) .

The counter circuit I4 receives output signals from the terminal Vout2. The counter circuit I4 receives a clock signal (CLK) . For a predetermined time period, the counter circuit 4 counts clocks included in the clock signal while the counter circuit detects the output signal from the terminal Vout1. The clock signal (CLK) can be provided by a control circuit shown in the drawings (for example, the logic circuit 150 of FIG. 1) .

The operation of the image sensor circuit shown in FIG. 2 is described in reference to a timing chart shown in FIG. 3. In FIG. 3, there is an assumption that 1st pixel signal level (hereinafter, Vpixel1 for easy understanding) corresponding to the input pixel signal line Vpixel1 is lower than the 2nd pixel signal level (hereinafter, Vpixel2 for easy understanding) corresponding to the input pixel signal line Vpixel2. In actual use, the 1st pixel signal level Vpixel1 can be higher than or the same level with the second pixel signal level Vpixel2. A horizontal axis of FIG. 3 is a time axis.

In FIG. 3, the ramp reference voltage VRAMP2 is higher than the ramp reference voltage VRAMP1 and precisely tracks the ramp reference voltage VRAMP1 with a predetermined offset level (Vth) . The ramp reference voltage VRAMP1 is initially at a predetermined initial level (Vinit) . At a predetermined timing, the ramp reference voltage VRAMP1 starts ramping up at a constant rate from Vinit. For example, the ramp reference voltage start ramping up when a user operates the imaging apparatus to take a picture or film a movie. When the ramp reference voltage VRAMP1 starts ramping up, the ramp reference voltage VRAMP2 simultaneously start ramping up at the same rate with VRAMP 1 from a predetermined level of (Vinit + Vth) , which is higher than VRAMP 1. Both ramp reference voltages VRAMP1 and VRAMP2 suspend to ramp up at the same timing and keep themselves at predetermined levels.

The offset level Vth is a predetermined voltage and can be designed to be a voltage with which the transistor M5 shown in FIG. 2 flows a target bias current. The transistor M5 has a source terminal which is grounded. When the voltage is applied to the gate terminal of the transistor M5, the transistor M5 acts as a current source for the comparator.

The transistor M5 shown in FIG. 2 can be a MOS transistor. The drain current (Id) of the transistor M5 is decided, for example, as shown below.

Id = k*W/L* (Vgs -Vt) ² - (1)

In an equation (1) , k: constant, W: channel width, L: channel length, Vgs: voltage difference between the gate terminal and the source terminal, and Vt: threshold voltage.

If it is assumed that “k” , “W” , “L” , and “Vt” are all known, and the target drain current Id can be decided or predetermined, “Vgs” can be automatically calculated using equation (1) . Vth equals Vgs when the source terminal is grounded and Vth is applied to a gate terminal. Thus, the predetermined offset level Vth is applied to the gate terminal of the transistor M5.

Here, the target drain current Id can be decided in consideration of, for example, a power consumption, random noise, voltage gain, transient response and etc. of the comparator I1 and I2.

In Fig. 2, each pixel signal (Vpixel1 or Vpixel2 for easy understanding) is fed to a negative input (terminal 4) of the comparator I1 (or I2) , the comparator I1 (or I2) compares the pixel signal Vpixel1 (or Vpixel2) with the ramp reference voltage Vramp1. The other ramp references Vramp2 is used to apply a voltage to the gate terminal of the transistor M5. This reference Vramp2 can be supplied through a sample/hold circuit which is not shown in the drawings. The transistor M5 acts as a bias current source for the comparator I1 (or I2) .

Hereafter, a basic operation of the comparator I1/I2 is explained. The comparators I1, I2 in this embodiment can be differential amplifiers. The comparators I1 and I2 have the same constitution including transistors M1 to M5. The transistors M1 and M2 can be NMOS differential input transistors, which are driven by the current source transistor M5. The transistors M3 and M4 act as load transistors for the input transistors M1 and M2. The transistors M3 and M4 can be understood as a current mirror circuit.

In this embodiment, it is assumed that the size of transistors M1 and M2 are the same, and the size of transistors M3 and M4 are the same. When a gate terminal voltage of the transistor M1 is higher than that of the transistor M2, the drain current of the transistor M1 (IdM1) is larger than that of the transistor M2 (IdM2) . The drain current of the transistor M1 (IdM1) equals the drain current of the transistor M3 (IdM3) . Since the transistors M3 and M4 act as a current mirror circuit, the drain current of the transistor M3 is mirrored to the drain current of the transistor M4 (IdM3 = IdM4) .

The output current of the comparator I1 (or I2) is generated by a difference between the drain current of the transistor M2 and the drain current of the transistor M4 (IdM4 -IdM2) . Since the drain current from the transistor M2 is smaller than that of the transistor M1, difference of the drain currents between the transistors M1 and M2 (IdM1 -IdM2) goes out of the comparator I1 (or I2) from the output terminal 5. The output terminal impedance can be designed to have a high value, and thus, the output voltage can rise accordingly.

In Fig. 2, each signal from a pixel (input pixel voltage Vpixel1/Vpixel2) is fed to a negative input (terminal 4) of the comparator I1 (or I2) . The comparator I1 (or I2) compares the pixel signals with the ramp reference voltage (Vramp1) . The other ramp references (Vramp2) is used to supply voltage through a sample/hold circuit to a gate terminal of the transistor M5 via the transistor M7. The transistor M5 acts as a bias current source for the comparator I1 (or I2) .

As mentioned above, the predetermined offset level Vth can be designed to be a voltage level for the bias current source transistor M5 so as to flow the target bias current to the comparator I1 (or I2) . The comparator I1 (or I2) can have a voltage gain which is a sufficient level to compare the input signals when the ramp reference signal Vramp1 reaches the same level with the input pixel signal (Vpixel1/Vpixel2) . The timing that this thing happens refers to “T5” shown in FIG. 3.

As shown in FIG. 2, the output from the comparator I1 (or I2) is supplied to the counter circuit I3 (or I4) through a terminal Vout1 (or Vout2) . The counter circuit I3 (or I4) counts a number of pulses supplied from the terminal CLK while an output voltage level of the output from the comparator I1 (or I2) stays at a low level. This condition corresponds to “T1” to “T5” shown in FIG. 3. In a similar manner, while the ramp reference voltage VRAMP1 is lower than the input pixel voltage Vpixel2, the counter circuit I4 counts a number of pulses applied through the terminal CLK. Therefore, an output value from the counter circuit I3 can be different from an output value of the counter circuit I4. For example, the logic circuit 150 shown in FIG. 1 can receive the output value from the counter circuit I3 (or I4) and generate an image using the output digital value.

In FIG. 3, at a timing T1, when a pulse ΦPW goes high, the switch SW1 turns ON. The common power supply VDD_common is supplied through the switch SW1 to the local power line Vdd1 (or Vdd2) of the comparator I1 (or I2) . The capacitor Cp, which is a reservoir capacitor is charged so as to be the same voltage with the common power supply VDD_common. Before “T1” , the switch SW1 stays off, and the capacitor Cp, which has one grounded terminal is not charged. The pulse ΦPW and other pulse signals can be supplied from, for example, the logic circuit 150 or T/G 140.

AT the timing T1, the pulse ΦPW goes high and the switch SW1 turns ON accordingly. The capacitor Cp is then charged from the timing T1 to T2. At the timing T2, the pulse ΦPW goes low and the switch SW1 turns OFF, the local power line Vdd1 (or Vdd2) of the comparator I1 (or I2) is disconnected from the common power supply VDD_common. After T3, the comparator I1 (or I2) conducts its operations using a power stored in the capacitor Cp. Therefore, for example, it is possible to isolate the local power line of each comparator from each other when the comparators I1 (or I2) is on comparing function, and thus, it is possible to reduce negative influence caused by the power-line-related cross talk between the comparators (I1, I2) . That can lead to improving the quality of images obtained by the imaging apparatus 100 due to the less-cross-talk power lines, and more stable power supply lines. In addition, the comparator I1 (or I2) consumes power only when it needs to do the comparing operation, and thus, it is possible to reduce the power consumption of the imaging apparatus 100. It should be noted that the imaging apparatus 100 may include millions of or more pixels and comparators. The power consumption of those whole circuits can be dramatically reduced, which is a great benefit for apparatuses of obtaining higher resolution images.

At a timing T3, pulse Φ1 supplied from the logic circuit 150 or T/G 140 goes high, and the transistors M8 and M10 in the comparator I1 (or I2) turn ON. One terminal of the capacitor C _G is connected to the terminal 4 via the transistor M8, and the input pixel voltage Vpixel1 (or Vpixel2) is applied to the terminal 4. The another terminal of the capacitor C _G is connected to the ground terminal of the comparator I1 (or I2) via the transistor M10.

In FIG. 3, when the pulse Φ1 goes high, the pulse Φres applied to the gate terminal of the transistor M6 goes high at the same time. The transistors M6, which has the grounded source terminal turns ON, and then, the capacitor Cs connected to both the drain and source terminals of the transistor M6 is discharged. The source terminal of the transistor M5 is connected to the capacitor Cs, and thus, a voltage level of the source terminal of the transistor M5 goes to the ground level.

At a timing T4, the pulse Φ1 goes low, and the pulse Φ2 supplied by the logic circuit 150 or T/G 140 goes high. The transistors M8 and M10 turns off due to the pulse Φ1 applied to their gate terminals. One terminal of the capacitor C _G is disconnected from the terminal 4 when the transistor M8 turns off. Another terminal of the capacitor C _G is disconnected from the grounded terminal of the comparator I1 (or I2) when the transistor M10 turns off.

At the timing T4, the transistor M7 turns on due to the pulse Φ2 applied to the gate terminal of the transistor M7. One terminal of the capacitor C _G is connected to terminal 2 via the transistor M7. At the timing T4, the transistor M9 turns on due to the pulse Φ2 applied to the gate terminal of the transistor M9. Another terminal of the capacitor C _G is connected to the gate terminal of the transistor M5 via the transistor M9. The transistor M5 acts as a current source in the comparator I1. Since the ramp reference voltage Vramp2 is applied to the terminal 2, and the charge on the capacitor C _G is preserved, that is, a voltage difference between two terminals of the capacitor C _G stays constant, it can be understood that, the gate voltage of the transistor M5 ( “VGATE” shown in FIG. 2) can be calculated with the following equation “Vinit +Vth -Vpixel1” . In case of the comparator I2, this equation is “Vinit + Vth –Vpixel2” .

At a timing T5 shown in FIG. 3, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel1. Since the voltage increase in the ramp reference voltage Vramp1 applied to the comparator I1 is obtained by “Vpixel1 –Vinit” , and the voltage difference between ramp reference voltages Vramp1 and Vramp2 is Vth, a voltage applied to the gate terminal of the transistor M5 in the comparator I1 can be obtained in accordance with an equation shown below.

{ (Vinit +Vth -Vpixel1) + (Vpixel1 -Vinit) } = Vth

This means that the transistor M5 can flow a bias current which is large enough to drive the comparator I1, the output of the comparator I1 turns high level with some amount of delay time responding to its input voltage changes. These responses are shown as “Vout1” and “ibias1” in FIG. 3.

At a timing T6 shown in FIG. 3, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel2. Since a voltage increase in the ramp reference voltage Vramp1 of the comparator I2 is (Vpixel2 -Vinit) wherein the voltage difference between ramp reference voltages Vramp1 and Vramp2 is Vth, it can be understood that a voltage (VGATE) applied to the gate terminal of the transistor M5 included in the comparator I2 is obtained by an equation shown below. This is similar to the comparator I1.

{ (Vinit +Vth -Vpixel2) + (Vpixel2 -Vinit) } = Vth

This means that the transistor M5 can flow a bias current which is large enough to drive the comparator I2, the output of the comparator I2 turns high level with some amount of delay time responding to its input voltage changes. These responses are shown as “Vout2” and “ibias2” in FIG. 3.

As mentioned above, since the bias current of each comparator I1/I2 flows only when the level of the ramp reference Vramp1 approaches its input pixel signal level (Vpixel1 or Vpixel2) , the power consumption of the comparators I1 and I2 is reduced compared to that of the comparators in some conventional SS ADCs which are driven by constant current sources. Furthermore, a timing at which the bias current flows in the comparator I1/I2 can be automatically controlled by input signal levels and ramp reference levels (Vramp1/Vramp2) .

The capacitance of the capacitor Cp shown in FIG. 2 is used for operating the comparator I1/I2 after T2 shown in FIG. 3. At the timing T2, the switch SW1 turns off, and the comparator I1/I2 is disconnected from the common power supply VDD_common. When implementing the comparing operation with the comparator I1/I2, it may be helpful to have information of how the capacitance of the capacitor Cp can be estimated, and how the comparators (I1/I2) disclosed above properly operate with their localized power lines (Vdd1/Vdd2) after being disconnected from the common power line (VDD_common) .

Before estimating the capacitance of the capacitor Cp (here, simply “Cp” for easy understanding) , it can be understood that a total charge which flows into the capacitor Cs during a comparing process of the comparator I1/I2 is less than Vth *Cs. In this equation, “Cs” indicates a capacitance of the capacitor Cs for easy understanding. A minimum power supply voltage applied to the capacitor Cs for a proper operation of the comparator I1/I2 can be estimated based on various aspects, for example, voltage gain, input-output time delay, input offset voltage, and output dynamic range of the comparator I1/I2. In order to achieve these specifications required to achieve the ADC specifications, the drain-source voltage of each transistors in the comparator I1/I2 is required to maintain a voltage which is higher than, so called, the saturation voltage (Vds_min) which is calculated in accordance with an equation shown below. Vds_min = Vgs-Vt

Hence, the minimum power supply voltage (Vdd_min) can be estimated as shown below by summing the saturation voltage Vds_min of each transistor M4, M2, and M5. It is assumed that the size of these transistors are the same in this embodiment.

Vdd_min = 3 *Vds_min

The capacitance of the capacitor Cp is required to be larger than “Cs *Vth /(VDD_common -Vdd_min) ” . In accordance with such a calculation, the minimum capacitance of the capacitor Cp can be estimated. Such minimum capacitance may reduce the power consumption of the imaging apparatus 100. In addition, when the comparator I1/I2 is placed in a chip, a silicon area shared by the capacitor Cp can be minimized by using such calculation results. The minimum silicon area can contribute to the low cost imaging apparatus 100.

Hereinafter, the second embodiment is explained. FIG. 4 shows comparators I1 and I2. Reference numerals of FIG. 3 corresponds to FIG. 2. The comparator I1/I2 includes transistors M1 to M10, in which M1, M2, M5, M6, M7, M8, M9, M10 are all PMOS transistors, while M3 and M4 are NMOS transistors, terminals 1 to 5, capacitors C _G, Cp, and Cs, and a switch SW1. It should be noted that the transistors M1 to M10 are different from FIG. 2. I3 and I4 are counter circuits. CLK supplies clock signals from, for example, the T/G 140 or logic circuit 150 shown in FIG. 1. FIG. 5 is a timing chart when the comparator I1/I2 conducts operations. In Fig. 4 and Fig. 5, it is assumed that a pixel signal level Vpixel1 is higher than a pixel signal level Vpixel2, a ramp reference voltage VRAMP2 is lower than a ramp reference voltage VRAMP1, and ramp the reference voltage VRAMP2 precisely tracks the ramp reference voltage VRAMP1 with a predetermined offset level (Vth) . The ramp reference voltage VRAMP1 ramps down at a constant rate from a predetermined initial level (Vinit) . Operations of transistors M1 to M4 are similar to FIG. 2.

In FIG. 4, each pixel signal/voltage (Vpixel1 and Vpixel2 for easy understanding) is supplied to a negative input (terminal 4) of the comparator I1 (or I2) which compares the pixel signal Vpixel1 (or Vpixel2) with the ramp reference voltage (VRAMP1) . Another ramp reference voltage (VRAMP2) can supply a voltage through a sample/hold circuit to a gate terminal of the transistor M5 which acts as a bias current source for the comparator I1 (or I2) .

As explained above, “Vth” can be designed to be a voltage level for the bias current source transistor (M5) to flow a bias current to the comparator I1 (or I2) . Therefore, the comparator I1 (or I2) can have a voltage gain which is large enough to compare input signals when the ramp reference voltage Vramp1 reaches the same voltage as the input pixel signal Vpixel1 (or Vpixel2) .

As explained above, the counter circuit I3 (or I4) inputs an signal output from the comparator I1 (or I2) . The counter circuit I3 (or I4) counts the number of pulses given through a CLK terminal while the output signal from the comparator I1 (or I2) stays at a low level.

In FIG. 5, at a timing T1, a pulse ΦPW goes high, and the switch SW1 turns ON accordingly. A common power supply VDD_common is supplied to a local power line of each comparator (Vdd1, Vdd2) through the switch SW1, and charge a reservoir capacitor Cp so as to be the same level as VDD_common. The capacitor Cp is charged from the timing T1 to T2.

At a timing T2, the pulse

goes low, and the switch SW1 turns OFF. The local power line (Vdd1/Vdd2 shown as Vdd in FIG. 4) of each comparator (I1, I2) is disconnected from the common power line (VDD_common) . At a timing T3, a pulse Φ1 which has been at a high level and applied to a gate terminal of the transistors M8 and M10, goes low. Therefore, the transistors M8 and M10 in the comparator I1 (or I2) turns ON. One terminal of the capacitor C _G is connected to terminal 4 via the transistor M10. The terminal 4 receives the input pixel signal Vpixel1 (or Vpixel2) , while another terminal of the capacitor C _G is connected to Vdd1 derived form the common power supply VDD_common via the transistor M8. After the timing T3, the comparator I1 (or I2) conducts its operations using a power stored in the capacitor Cp. Therefore, for example, it is possible to isolate the local power line of each comparator from each other when the comparators I1 (or I2) is on comparing function, and thus, it is possible to reduce negative influence caused by the power-line-related cross talk between the comparators (I1, I2) .

When the pulse Φ1 which has been at a high level and applied to the gate terminal of the transistors M8 and M10, goes low, at the same time, a pulse Φres applied to a gate terminal of the transistor M6 goes low The transistors M8, M10, and M6 turn ON. The capacitor Cs connected to the transistor M6 is discharged, and a voltage applied to the source terminal of the transistor M5 reaches a level which is the same as Vdd1/Vdd2, that is, the same level as the common power supply VDD_common.

At a timing T4, the pulse Φ1 goes high, and a pulse Φ2 goes low at the same time. Transistors M8 and M10 receiving the pulse Φ1 on their gate nodes turn OFF, and transistors M7 and M9 receiving the pulse Φ2 on their gate nodes turn ON. Therefore, both terminals of the capacitor C _G are disconnected from the terminal 4 (via the transistor M10) and the common power supply Vdd (via the transistor M8) and connected to the terminal 2 (via the transistor M9) and the gate terminal of the transistor M5 (via the transistor M7) . The transistor M5 acts as a current source of the comparator I1 (or I2) . The ramp reference voltage VRAMP2 is applied to the terminal 2, and thus, the charge on the capacitor C _G is preserved. A voltage difference between two terminals of the capacitor C _G remains, and a voltage on the gate terminal of the transistor M5 is calculated by “Vinit -Vth + Vdd -Vpixelx (x = 1 or 2 ) ” .

At a timing T5, the ramp reference voltage VRAMP1 reaches the input pixel signal Vpixel1. A voltage decrease in the ramp reference voltage VRAMP1 applied to the comparator I1 is (Vinit -Vpixel1) , a voltage difference between the ramp reference voltage VRAMP1 and VRAMP2 is Vth, and thus, a gate terminal of the transistor M5 in the comparator I1 reaches a voltage as shown below.

(Vinit -Vth + Vdd1 -Vpixel1) - (Vinit -Vpixel1) = Vdd1 -Vth

This equation means that the transistor M5 can flow a bias current which is large enough to drive the comparator I1, and an output signal of the comparator I1 turns low level with some delay time responding to its inputs voltage change. There responses are shown as “Vout1” and “ibias1” in FIG. 5

At a timing T6, the ramp reference voltage VRAMP1 reaches the input pixel signal Vpixel2. A voltage decrease in the ramp reference voltage VRAMP1 applied to the comparator I2 is (Vinit -Vpixel2) , and a voltage difference between ramp reference voltages VRAMP1 and VRAMP2 is Vth. A voltage applied to a gate terminal of the transistor M5 in the comparator I2 is calculated by an equation as shown below.

(Vinit -Vth +Vdd2 -Vpixel2) - (Vinit -Vpixel2) = Vdd2 -Vth

This means that if the transistor M5 can flow a bias current which is large enough to drive the comparator I2, the output of the comparator I2 turns low level with some amount of delay time responding to its input voltage changes. These responses are shown shown as “Vout2” and “ibias2” in FIG. 5.

It can be understood that imaging apparatuses generally have a large number of pixels arranged along multiple columns and rows. Timing charts included in FIG. 3 and/or FIG. 5 can be applied to such pixels, and for example, pixels on each column or row can be simultaneously operated in accordance with the same timing described in FIG. 3 or FIG. 5. The logic circuit 150 or T/G 140 may output signals and/or pulses so as to control the comparator I1/I2.

The above-described embodiments can have various advantages. First, for example, a bias current of each of the above-described comparators in a SS ADCs depends on a voltage difference between an input signal and a ramp reference voltage which are applied to the comparator. The bias current of the comparator starts flowing just when the ramp reference voltage level becomes close to the input signal level. Therefore, the dynamic bias circuit completely fits SS ADCs, and in addition, reduce the power consumption of the SS ADCs.

Second, for example, a local power line of each of the above-described comparators in the SS ADCs is connected to a common power supply (VDD_common) through the switch (SW1) . Such separated local power lines respectively have the reservoir capacitors (Cp) .

As described in the above embodiments, just before starting the AD conversion these switches (SW1) turn off, and at the same time, local power lines of each comparator corresponding to a pixel arranged on one column is disconnected from the common (sensor) power supply line (VDD_common) .

The supply current for each column comparator is provided by the reservoir capacitor (Cp) , not by the common (sensor) power supply line (VDD_common) . Therefore, negative influences, for example, fluctuation generated in each local power line (Vdd1/Vdd2) do not propagate to other local power lines, and thus, for example, “the streaking noise “can be eliminated.

In addition to the embodiments above, this application may have other aspects. For example, the first aspect is an imaging apparatus including a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor, and a first capacitor, wherein, the first capacitor is charged while the switch is ON, and wherein after the switch turns OFF, using electric power charged at the first capacitor, the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit and output an output signal.

The fourth aspect is the imaging apparatus according to the above-described aspects, wherein when the first ramp signal reaches the same level with the pixel signal, the comparator reverses the output signal.

The fifth aspect is the imaging apparatus according to the above-described aspects, wherein when a voltage which has a same voltage level with the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.

The sixth aspect is the imaging apparatus according to the above-described aspects, wherein a capacitance of the first capacitor is large enough to drive the comparator.

The fifteenth aspect is the imaging method according to the above-described aspects, wherein when a voltage which has the same voltage level with the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.

The sixteenth aspect is the imaging method according to the above-described aspects, wherein the capacitance of the first capacitor is large enough to drive the comparator.

The embodiments disclosed above are examples, and it should be understood that the scope of the present invention and this application are not limited or restricted by such disclosure.

Claims

An imaging apparatus comprising a comparator, a pixel and a control circuit, wherein

the comparator comprises a switch, a first transistor, and a first capacitor, wherein,

the first capacitor is charged while the switch is ON, and wherein

after the switch turns OFF, using electric power charged at the first capacitor, the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit and output an output signal.
The imaging apparatus according to Claim 1, wherein the ramp signal comprises a first and a second ramp signals.
The imaging apparatus according to Claim 2, wherein the ramp signal comprises a predetermined voltage difference between the first and second ramp signals.
The imaging apparatus according to Claim 1, wherein when the first ramp signal reaches a same level with the pixel signal, the comparator reverses the output signal.
The imaging apparatus according to Claim 1, wherein when a voltage which has a same voltage level with the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.
The imaging apparatus according to Claim 1, wherein a capacitance of the first capacitor is large enough to drive the comparator.
The imaging apparatus according to Claim 1, wherein when the second ramp signal reaches a same level with the pixel signal, the comparator finishes its comparison operation.
The imaging apparatus according to Claim 1, wherein when the switch is OFF, the comparator is disconnected from a common power supply of the imaging apparatus.
The imaging apparatus according to Claim 1, wherein the first and second ramp signals are ramping-up signals.
The imaging apparatus according to Claim 1, wherein the first and second ramp signals are ramping-down signals.
An imaging method of an imaging apparatus comprising a comparator, a pixel and a control circuit, the imaging method comprising:

charging a first capacitor of the comparator while a switch of the comparator is ON;

after the switch turns OFF, comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using electric power charged at the first capacitor; and

outputting an output signal.
The imaging method according to Claim 11, wherein the ramp signal comprises a first and a second ramp signals.
The imaging method according to Claim 12, wherein the ramp signal comprises a predetermined voltage difference between the first and second ramp signals.
The imaging method according to Claim 11, wherein when the first ramp signal reaches a same level with the pixel signal, the comparator reverses the output signal.
The imaging method according to Claim 11, wherein when a voltage which has a same voltage level with the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.
The imaging method according to Claim 11, wherein a capacitance of the first capacitor is large enough to drive the comparator.
The imaging method according to Claim 11, wherein when the second ramp signal reaches the same level with the pixel signal, the comparator finishes its comparison operation.
The imaging method according to Claim 11, wherein when the switch is OFF, the comparator is disconnected from a common power supply of the imaging apparatus.
The imaging method according to Claim 11, wherein the first and second ramp signals are ramping-up signals.
The imaging method according to Claim 11, wherein the first and second ramp signals are ramping-down signals.