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WO2021199665A1 - Dispositif d'imagerie à semi-conducteurs, procédé de production de dispositif d'imagerie à semi-conducteurs, et appareil électronique - Google Patents

Dispositif d'imagerie à semi-conducteurs, procédé de production de dispositif d'imagerie à semi-conducteurs, et appareil électronique Download PDF

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Publication number
WO2021199665A1
WO2021199665A1 PCT/JP2021/003985 JP2021003985W WO2021199665A1 WO 2021199665 A1 WO2021199665 A1 WO 2021199665A1 JP 2021003985 W JP2021003985 W JP 2021003985W WO 2021199665 A1 WO2021199665 A1 WO 2021199665A1
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WO
WIPO (PCT)
Prior art keywords
conductor
substrate
region
insulating film
solid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/003985
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English (en)
Japanese (ja)
Inventor
出羽　恭子
澁木　俊一
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of WO2021199665A1 publication Critical patent/WO2021199665A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors

Definitions

  • the present disclosure relates to a solid-state image sensor, a method for manufacturing the solid-state image sensor, and an electronic device.
  • solid-state image sensors which are the core components of digital cameras
  • CMOS Complementary Metal Oxide Semiconductor
  • miniaturization and thinning of solid-state image sensors are being studied as digital cameras become more sophisticated and multifunctional.
  • a solid-state imaging device including a laminated substrate (semiconductor chip) in which the multilayer wiring layers are bonded to each other has been proposed (see Patent Document 1).
  • the present disclosure has been made in view of such a situation, and a method for manufacturing a solid-state image sensor and a solid-state image sensor capable of suppressing the generation of voids at the joint surface between the first substrate and the second substrate.
  • the purpose is to provide electronic devices as well.
  • the solid-state imaging device includes a first substrate on which a plurality of first conductors including a first conductor portion and a second conductor portion are formed, and a first substrate. It includes a third conductor portion that is joined to the first substrate and is arranged so as to face the first conductor portion and a fourth conductor portion that is arranged so as to face the second conductor portion.
  • a first substrate comprising a second substrate on which a plurality of second conductors are formed, and the first conductor and the second conductor overlapping each other on the joint surface between the first substrate and the second substrate.
  • the first wiring region where the first conductor portion and the third conductor portion of the surface are arranged and the second wiring region where the second conductor portion and the fourth conductor portion are arranged Is also characterized in that it has a predetermined bonding force between the first substrate and the second substrate and is equal to or higher than a predetermined value.
  • the solid-state imaging device includes a first substrate on which a plurality of first conductors including a first conductor portion and a second conductor portion are formed, and a first substrate.
  • a plurality of second conductors are joined and include a third conductor portion arranged to face the first conductor portion and a fourth conductor portion arranged to face the second conductor portion.
  • the second region where the first insulating film formed around the body and the second conductor overlap, and the second insulating film and the first conductor formed around the second conductor are formed.
  • a first region having an overlapping third region and a fourth region on which the first insulating film and the second insulating film overlap, and the first conductor portion and the third conductor portion of the joint surface are arranged.
  • the ratio of the area of the fourth region per unit area in the wiring region of It is characterized by being different from the ratio of the area.
  • the solid-state imaging device includes a first substrate on which a plurality of first conductors including a first conductor portion and a second conductor portion are formed, and a first substrate.
  • a plurality of second conductors are joined and include a third conductor portion arranged to face the first conductor portion and a fourth conductor portion arranged to face the second conductor portion.
  • the second region where the first insulating film formed around the body and the second conductor overlap, and the second insulating film and the first conductor formed around the second conductor are formed.
  • It has a third region that overlaps and a fourth region in which the first insulating film and the second insulating film overlap, and the difference between the maximum value and the minimum value of the ratio of the area of the fourth region per unit area is It is characterized in that the value is equal to or less than a predetermined value at any position on the joint surface.
  • a plurality of first conductors including a first conductor portion and a second conductor portion are formed on a first semiconductor substrate.
  • a plurality of second conductors including the conductor portion of the above are formed to form a second substrate, the first conductor and the second conductor face each other, and the first substrate and the second substrate are formed.
  • the first region where the first conductor and the second conductor overlap, and the second where the first insulating film and the second conductor formed around the first conductor overlap each other.
  • the ratio of the area of the fourth region to the unit area is the first wiring region and the second conductor portion in which the first conductor portion and the third conductor portion of the joint surface are arranged.
  • the first value is equal to or higher than a predetermined value having a predetermined bonding force between the first substrate and the second substrate. It is characterized in that a substrate and a second substrate are arranged and joined.
  • the electronic device is joined to a first substrate on which a plurality of first conductors including a first conductor portion and a second conductor portion are formed, and a first substrate.
  • a plurality of second conductors including a third conductor portion arranged to face the first conductor portion and a fourth conductor portion arranged to face the second conductor portion are formed.
  • a first region in which the first conductor and the second conductor overlap each other on the joint surface between the first substrate and the second substrate, and the first conductor are provided.
  • the first substrate and the second are at any position of the first wiring region in which the third conductor portion is arranged and the second wiring region in which the second conductor portion and the fourth conductor portion are arranged. It is characterized by including a solid-state imaging device having a predetermined bonding force with the substrate and having a predetermined value or more.
  • FIG. 1 It is an enlarged cross-sectional view which shows the structure in the vicinity of the joint surface of the solid-state image pickup apparatus which concerns on 1st Embodiment of this disclosure.
  • FIG. 1 It is a plan schematic diagram which shows the wiring area WA, the dummy wiring area DA, and other area OA in the solid-state image sensor. Insulator of the fourth region A4 per unit area in the solid-state imaging device in which the ratio of the area of the fourth region A4 in the wiring region WA, the dummy wiring region DA and the other region OA is 48%, 73% and 18%, respectively. It is a graph which shows the frequency of the area ratio.
  • FIG. 5 is an enlarged cross-sectional view showing a configuration in the vicinity of a joint surface of a solid-state image sensor when the joint position between the first substrate and the second substrate deviates from a predetermined position. It is a top view which shows the minimum structure of the 1st conductor and the 2nd conductor in the vicinity of the joint surface of the solid-state image pickup apparatus which concerns on 2nd Embodiment of this disclosure. It is an enlarged plan view which shows an example of the arrangement of the 1st conductor and the 2nd conductor in the vicinity of the joint surface of the solid-state image pickup apparatus which concerns on 2nd Embodiment of this disclosure.
  • the present disclosure relates to a solid-state image sensor formed by joining a first substrate and a second substrate.
  • the present disclosure also relates to a method for manufacturing a solid-state image sensor formed by joining a first substrate and a second substrate, and an electronic device having the solid-state image sensor. According to the present disclosure, when the first substrate and the second substrate are bonded, a decrease in bonding strength at the bonding surface between the first substrate and the second substrate is suppressed at any position on the bonding surface. be able to.
  • voids (air bubbles) that cannot be partially bonded may be formed on the bonding surface between the first substrate and the second substrate.
  • the joint surface in the case of a solid-state image sensor that does not have a region in which the insulating film exposed on the joint surface of the first substrate and the insulating film exposed on the joint surface of the second substrate are directly bonded, the joint surface. In, the joining strength immediately after joining becomes low. Then, when the bonding strength at the bonding surface between the substrates becomes low, voids (air bubbles) are likely to be formed on the bonding surface between the first substrate and the second substrate.
  • the cause of voids is mainly the difference in joint strength.
  • the bonding strength between copper and copper immediately after bonding the substrate and the bonding strength in the region where copper and the insulating film are directly bonded are lower than the bonding strength in the region where the insulating film and the insulating film are directly bonded. Therefore, in order to make it difficult for the first substrate and the second substrate to be separated from each other, the first insulating film provided on the first substrate and the second insulating film provided on the second substrate are formed. It is necessary to secure a certain ratio or more of the area to be directly joined even in the area of the joint surface throat.
  • the present disclosure provides a technique for suppressing a decrease in bonding strength between substrates caused by bonding deviation between substrates so that the bonding strength becomes a certain level or higher at any position on the bonding surface.
  • FIG. 1 is a block diagram showing a configuration example of the solid-state image sensor according to the present disclosure.
  • the solid-state image sensor 1 is configured as, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • the solid-state image sensor 1 has a pixel region (pixel array) 3 in which a plurality of pixels 2 are regularly arranged in a two-dimensional array on a semiconductor substrate (for example, a Si substrate) (not shown), and a peripheral circuit unit.
  • CMOS Complementary Metal Oxide Semiconductor
  • Pixel 2 has a photoelectric conversion unit (for example, a photodiode) and a plurality of pixel transistors (MOS transistors).
  • the plurality of pixel transistors can be composed of, for example, three transistors, a transfer transistor, a reset transistor, and an amplification transistor. Further, the plurality of pixel transistors may be composed of four transistors by adding a selection transistor. Since the equivalent circuit of a unit pixel is the same as the well-known technique, detailed description thereof will be omitted.
  • the pixel 2 can be configured as one unit pixel or can have a shared pixel structure.
  • This pixel sharing structure is a structure in which a plurality of photodiodes share a transistor other than the floating diffusion and the plurality of transfer transistors. That is, in the shared pixel, the photodiode and the transfer transistor constituting the plurality of unit pixels are configured by sharing the other pixel transistor.
  • the peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.
  • the vertical drive circuit 4 is composed of, for example, a shift register.
  • the vertical drive circuit 4 selects the pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixel in line units. That is, the vertical drive circuit 4 selectively scans each pixel 2 of the pixel array 3 in a row-by-row manner in the vertical direction. Then, the vertical drive circuit 4 supplies a pixel signal based on the signal charge generated according to the amount of received light in the photoelectric conversion unit of each pixel 2 through the vertical signal line L1 to the column signal processing circuit 5.
  • the column signal processing circuit 5 is arranged for each row of pixels 2, for example.
  • the column signal processing circuit 5 performs signal processing such as noise removal for each pixel string for the signal output from the pixel 2 for one row.
  • the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise peculiar to pixel 2, signal amplification, and A / D (Analog / Digital) conversion. ..
  • a horizontal selection switch (not shown) is provided in the output stage of the column signal processing circuit 5 so as to be connected to the horizontal signal line L2.
  • the horizontal drive circuit 6 is composed of, for example, a shift register.
  • the horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuits 5, and outputs pixel signals from each of the column signal processing circuits 5 to the horizontal signal line L2.
  • the output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line L2 and outputs the signals.
  • the output circuit 7 may, for example, perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.
  • the control circuit 8 receives an input clock and data for instructing an operation mode and the like, and outputs data such as internal information of the solid-state image sensor 1. Further, the control circuit 8 obtains a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. Generate. Then, the control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like. The input / output terminal 9 exchanges signals with the outside.
  • FIGS. 2 to 4 are schematic views showing an example of a laminated structure of the solid-state image sensor 1 according to the present disclosure.
  • An example of a laminated structure of the solid-state image sensor 1 to which the present disclosure is applied will be described with reference to FIGS. 2 to 4.
  • the solid-state image sensor 1a shown in FIG. 2 is composed of a first substrate 11 and a second substrate 12.
  • the pixel array 23 and the control circuit 24 are mounted on the first substrate 11.
  • a logic circuit 25 including a signal processing circuit is mounted on the second substrate 12.
  • the first substrate 11 and the second substrate 12 are electrically connected to each other to form a solid-state image sensor 1a as one substrate.
  • the solid-state image sensor 1b shown in FIG. 3 is composed of a first substrate 11 and a second substrate 12.
  • the pixel array 23 is mounted on the first substrate 11.
  • a control circuit 24 and a logic circuit 25 including a signal processing circuit are mounted on the second substrate 12. Then, the first substrate 11 and the second substrate 12 are electrically connected to each other to form a solid-state image sensor 1b as one substrate.
  • the solid-state image sensor 1c shown in FIG. 4 is composed of a first substrate 11 and a second substrate 12.
  • a pixel array 23 and a control circuit 24-1 for controlling the pixel array 23 are mounted on the first substrate 11.
  • a control circuit 24-2 for controlling the logic circuit 25 and a logic circuit 25 including a signal processing circuit are mounted on the second substrate 12. Then, the first substrate 11 and the second substrate 12 are electrically connected to each other to form a solid-state image sensor 1c as one substrate.
  • CMOS image sensor two or more substrates may be bonded together.
  • a substrate provided with a memory element array, a substrate provided with other circuit elements, and the like are added, and three or more substrates are bonded together to form one laminated substrate. It is also possible to configure a CMOS image sensor.
  • FIG. 5 is a cross-sectional view showing a configuration example of the solid-state imaging device 1A according to the first embodiment of the present disclosure.
  • the solid-state image sensor 1A is a back-illuminated CMOS (Complementary MOS) image sensor, and is an example of the solid-state image sensor 1.
  • the back-illuminated CMOS image sensor is a CMOS image sensor in which the light receiving portion is arranged at the upper part of the circuit portion and has higher sensitivity and lower noise than the front-illuminated type.
  • FIG. 6 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1A.
  • FIG. 7 is a cross-sectional view taken along the line AA of FIG. 6, which is an enlarged cross-sectional view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1A.
  • the solid-state image sensor 1A joins the first substrate 30 on which the plurality of first conductors 38 are formed and the first substrate 30 on which the plurality of second conductors 58 are formed.
  • the second substrate 50 is provided.
  • the first wiring 38a that is electrically conductive with the lower layer wiring 36 and the second wiring 58a that is electrically conductive with the multilayer wirings 55a and 55b and the upper layer wiring 56 are rectangular. It is formed in a shape.
  • the first wiring 38a and the second wiring 58a are arranged so that at least a part of the first wiring 38a and the second wiring 58a overlap each other in a plan view.
  • the first wiring 38a and the second wiring 58a having the same outer shape in the plan view are arranged so as to intersect each other in the plan view.
  • Such a configuration is shown.
  • the first wiring 38a and the second wiring 58a may be extended in the same direction and arranged so as to be displaced and overlap each other in a plan view.
  • the first wiring 38a and the second wiring 58a may not have the same outer shape in a plan view and may have different sizes.
  • the first wiring 38a is provided so as to extend in the left-right direction in FIG.
  • the second wiring 58a is provided so as to extend in the vertical direction (an example of a direction intersecting with the first wiring 38a) in FIG.
  • the first wiring 38a and the second wiring 58a are joined to each other at a portion where the first wiring 38a and the second wiring 58a overlap each other.
  • the first conductor 38 and the second conductor 58 overlap each other on the joint surface 40 between the first substrate 30 and the second substrate 50. It has a first region A1.
  • the solid-state image sensor 1A has a second region A2 on the joint surface 40 in which the first insulating film 37 and the second conductor 58 formed around the first conductor 38 overlap each other.
  • the solid-state image sensor 1A has a third region A3 on the joint surface 40 in which the second insulating film 57 formed around the second conductor 58 and the first conductor 38 overlap each other.
  • the solid-state image sensor 1A has a fourth region A4 in which the first insulating film 37 and the second insulating film 57 overlap each other on the joint surface 40.
  • the first region A1 to the fourth region A4 are formed by arranging the first wiring 38a and the second wiring 58a so as to intersect each other in a plan view.
  • the ratio of the area of the fourth region A4 per unit area (hereinafter, may be referred to as the insulator area ratio) is set to a predetermined value or more at any position of the joint surface 40. Be placed.
  • the first wiring 38a (an example of the first conductor portion) that is electrically conductive with the lower layer wiring 36 and the lower layer It includes a wiring 36 and a first dummy wiring 38b (an example of a second conductor portion) having no electrical continuity.
  • the first wiring 38a includes, for example, a connection pad for connecting the first substrate 30 and the second substrate 50, lateral wiring, an electromagnetic shield, and the like.
  • the second conductor 58 As the second conductor 58, the second wiring 58a (an example of the third conductor portion) that electrically conducts with the multi-layer wiring 55a and 55b and the upper layer wiring 56, and the wiring 55a. , 55b and the upper layer wiring 56 and a second dummy wiring 58b (an example of a fourth conductor portion) having no electrical continuity.
  • the second conductor 58 may include, for example, a connection pad for connecting the first substrate 30 and the second substrate 50, lateral wiring, an electromagnetic shield, and the like.
  • the first conductor 38 and the second conductor 58 for performing Cu-Cu bonding are such that a part of the wiring is exposed on the bonding surface 40 which is the surface of the wiring layer of the first substrate 30 and the second substrate 50. Is formed in.
  • the first conductor 38 and the second conductor 58 may or may not be electrically connected between the first substrate 30 and the second substrate 50 by Cu-Cu bonding.
  • the connection pad for connecting the first substrate 30 and the second substrate 50 includes the pixels of the second substrate 50 (photodiode PD or pixel transistor serving as a photoelectric conversion unit) and signal processing of the first substrate 30. Connect with the circuit.
  • the lateral wiring is a connection portion for supplying electric power supplied from the outside to each portion in the chip.
  • the electromagnetic shield electrically shields between the first substrate 30 and the second substrate 50 with a Cu-Cu connection so that unintended electrical noise does not affect each wiring or transistor.
  • first dummy wiring 38b and the second dummy wiring 58b do not function as a path for a pixel signal, and improve the joint strength between the first substrate 30 and the second substrate 50, dishing, and erosion. Is placed to suppress the. That is, the first dummy wiring 38b and the second dummy wiring 58b are electrically connected to the photodiode PD serving as the photoelectric conversion unit and the first wiring 38a and the second wiring 58a that are electrically connected to the photodiode PD. Is separated.
  • the first dummy wiring 38b and the second dummy wiring 58b can be floated, but are electrically connected to a fixed potential such as a reference potential (GND) or a power supply voltage (VDD).
  • the wiring area WA (an example of the first wiring area) of the solid-state image sensor 1A is provided with a first wiring 38a and a second wiring 58a including a connection pad, a lateral wiring, and an electromagnetic shield. Further, a first dummy wiring 38b and a second dummy wiring 58b are provided in the dummy wiring region DA (an example of the second wiring region) of the solid-state image sensor 1A.
  • the first substrate 30 and the second substrate 50 are also formed with wiring that is not exposed on the joint surface 40.
  • the first wiring 38a that is electrically conductive with the lower layer wiring 36, the multilayer wirings 55a and 55b, and the upper layer wiring 56 are electrically conductive.
  • Wiring 58a of 2 is formed.
  • a first dummy wiring 38b and a second dummy wiring 58b are formed in the dummy wiring region DA of the solid-state image sensor 1A.
  • the dummy wiring area DA has been illustrated as an example of the “second wiring area”, but the present invention is not limited to this.
  • the "second wiring region” it may be a region (another region OA) in which a conductor other than the first dummy wiring 38b and the second dummy wiring 58b is formed.
  • the ratio of the area of the fourth region A4 (insulator area ratio) in which the first insulating film 37 and the second insulating film 57 overlap each other per unit area is the joint surface 40.
  • the value is equal to or higher than the predetermined value at any of the positions.
  • the bonding force between the first substrate 30 and the second substrate 50 can be maintained above a certain value.
  • the ratio of the area of the fourth region A4 in which the first insulating film 37 and the second insulating film 57 overlap each other per unit area is a predetermined value at any position of the joint surface 40. It is as follows.
  • the ratio of the area of the fourth region A4 per unit area is equal to or greater than a predetermined value having a predetermined bonding force between the first substrate 30 and the second substrate 50.
  • the ratio of the area of the fourth region A4 per unit area is preferably 15% or more and 70% or less.
  • the joint area between the first wiring 38a and the second wiring 58a becomes a certain ratio or more.
  • the ratio of the area of the fourth region A4 per unit area is the surface condition of the first insulating film 37 and the second insulating film 57 to be joined, and the first insulating film 37 for each joining position.
  • the preferable ratio changes depending on the ratio of the second insulating film 57. Therefore, the preferable value of the ratio of the area of the fourth region A4 per unit area varies over a wide numerical range.
  • the "ratio of the area of the fourth region A4 per unit area” is the ratio of the area of the fourth region A4 per unit area on the joint surface 40.
  • the joint surface 40 includes all of the wiring region WA and the dummy wiring region DA of the solid-state image sensor 1A, and all other regions OA except the wiring region WA and the dummy wiring region DA. Therefore, the solid-state image sensor 1A is designed so that the ratio of the area of the fourth region A4 per unit area is equal to or greater than a predetermined value in any of the wiring region WA, the dummy wiring region DA, and the other region OA. Will be done.
  • the ratio of the area of the plurality of fourth regions A4 in the wiring area WA is different from the ratio of the area of the plurality of fourth regions A4 in the dummy wiring area DA. Further, it is preferable that the difference between the maximum value and the minimum value of the ratio of the area of the fourth region A4 per unit area (insulator area ratio) is equal to or less than a predetermined value at any position of the joint surface 40. .. Further, it is more preferable that the ratio of the area of the fourth region A4 per unit area in the dummy wiring region DA is larger than the ratio of the area of the fourth region A4 per unit area in the wiring region WA.
  • the difference between the maximum value and the minimum value of the ratio of the area of the fourth region A4 (insulator area ratio) per unit area of 5 mm ⁇ 5 mm is preferably 10% or less, for example.
  • the difference between the maximum value and the minimum value of the ratio of the area of the fourth region A4 per unit area is% or less, the first substrate 30 and the second substrate 50 are to some extent at any position of the joint surface 40. It is preferable because it joins uniformly and voids are less likely to occur on the joint surface 40.
  • the "difference between the maximum value and the minimum value of the ratio of the area of the fourth region A4 per unit area" is defined as that of the plurality of fourth regions A4 in the plurality of predetermined regions of the joint surface 40 partitioned by the unit area.
  • the difference between the maximum value and the minimum value of the area ratio is defined by the difference between the ratio of the area of the plurality of fourth regions A4 in the wiring region WA and the ratio of the area of the plurality of fourth regions A4 in the dummy wiring region DA.
  • the above-mentioned “difference” may be a difference at any two locations of the connection pad of the wiring region WA, the lateral wiring, and the electromagnetic shield, or may be a difference at two locations in the dummy wiring region DA. good.
  • the above-mentioned “maximum value” and “minimum value” are the maximum value and the maximum value among the values obtained by calculating the ratio of the area of the fourth region A4 from the coverage rate per unit area of the layout of the joint surface 40 of the solid-state image sensor 1. This is the minimum value.
  • the "difference between the maximum value and the minimum value of the ratio of the area of the fourth region A4 per unit area" becomes large. .. That is, when the difference between the maximum value and the minimum value of the ratio of the area of the fourth region A4 per unit area is less than or equal to a predetermined value, the portion where the wiring density is locally increased on the entire surface of the layout is small. .. Therefore, joining the first substrate 30 and the second substrate 50 is preferable because the bonding properties of the bonding surface 40 become uniform and voids are less likely to occur on the bonding surface 40.
  • FIG. 8 is a schematic plan view showing a wiring region WA, a dummy wiring region DA, and another region OA in a solid-state image sensor.
  • FIGS. 9, 10 and 11 are graphs showing the frequency of the ratio of the area of the fourth region A4 per unit area (insulator area ratio) in the solid-state image sensor shown in FIG.
  • the graph of FIG. 9 shows the ratio of the area of the fourth region A4 in the wiring region WA, the dummy wiring region DA, and the other region OA to 48%, 73%, and 18%, respectively, per unit area of the solid-state imaging device 1A.
  • It is a graph which shows the frequency of the insulator area ratio of the 4th region A4.
  • the graph of FIG. 10 shows the unit area in the solid-state imaging device 1A in which the ratios of the areas of the fourth region A4 in the wiring region WA, the dummy wiring region DA, and the other region OA are 48%, 76%, and 18%, respectively. It is a graph which shows the frequency of the insulator area ratio of the 4th region A4 per hit. That is, in the solid-state image sensor shown in FIG. 10, the ratio of the area of the fourth region in the dummy wiring region DA is slightly higher than that in the case shown in FIG. In such a solid-state image sensor, poor bonding occurs at the bonding surface between the first substrate and the second substrate.
  • the graph of FIG. 11 shows the unit in the solid-state imaging device 1A in which the ratio of the area of the fourth region A4 in the wiring region WA, the dummy wiring region DA, and the other region OA is 48%, 73%, and 13%, respectively. It is a graph which shows the frequency of the insulator area ratio of the 4th region A4 per area. That is, in the solid-state image sensor shown in FIG. 11, the ratio of the area of the fourth region in the other region OA is slightly lower than that in the case shown in FIG. In such a solid-state image sensor, poor bonding occurs at the bonding surface between the first substrate and the second substrate.
  • the ratio of the area of the fourth region A4 (insulator area ratio) to the bonding area of the first substrate 30 and the second substrate 50 is 15% or more and 70% or less.
  • the first conductor 38 and the second conductor 58 in the vicinity of the joint surface 40 of the first substrate 30 and the second substrate 50 which is a characteristic configuration of the present embodiment, will be described in detail.
  • the first wiring 38a and the second wiring 58a are arranged so that at least a part of the first wiring 38a and the second wiring 58a overlap each other in a plan view.
  • the first wiring 38a and the second wiring 58a are arranged so as to intersect each other in a plan view.
  • the first wiring 38a is provided so as to extend in the left-right direction in FIG.
  • the second wiring 58a is provided so as to extend in the vertical direction (an example of a direction intersecting with the first wiring 38a) in FIG.
  • first wiring 38a and the second wiring 58a are arranged so that the long side of the first wiring 38a and the long side of the second wiring 58a are orthogonal to each other in a plan view. As shown in FIG. 7, the first wiring 38a and the second wiring 58a are joined to each other at a portion where the first wiring 38a and the second wiring 58a overlap each other.
  • the first dummy wiring 38b and the second dummy wiring 58b which have no electrical continuity with other portions, intersect each other in a plan view. It is arranged to do.
  • the first dummy wiring 38b is provided so as to extend in the left-right direction in FIG.
  • the second dummy wiring 58b is provided so as to extend in the vertical direction (an example of a direction intersecting with the first dummy wiring 38b) in FIG.
  • the first dummy wiring 38b and the second dummy wiring 58b are arranged so that the long side of the first dummy wiring 38b and the long side of the second dummy wiring 58b are orthogonal to each other in a plan view. .. As shown in FIG. 7, the first dummy wiring 38b and the second dummy wiring 58b are joined to each other at a portion where the first dummy wiring 38b and the second dummy wiring 58b overlap each other.
  • the first insulating film 37 of the first substrate 30 and the second substrate 50 are second.
  • the ratio of the area where the insulating film 57 is directly bonded to the insulating film 57 can be made substantially constant at any position of the bonding surface 40.
  • the ratio of the area where the first insulating film 37 and the second insulating film 57 are directly bonded is referred to as an "insulator area ratio”.
  • a first substrate 30 on which a logic circuit 32 is formed, a pixel array, and a control circuit are formed. It has a laminated semiconductor substrate in which the second substrate 50 is bonded to the second substrate 50.
  • the pixel array and the control circuit have the same configuration as the pixel array 23 and the control circuit 24 of the solid-state image sensor 1a shown in FIG.
  • the first substrate 30 and the second substrate 50 are attached so that the surface on which the first conductor 38 is exposed and the surface on which the second conductor 58 is exposed face each other.
  • the first substrate 30 and the second substrate 50 are directly joined by the first wiring 38a and the second wiring 58a, and the first dummy wiring 38b and the second dummy wiring 58b are directly joined. Arranged like this.
  • the first substrate 30 has a configuration in which a logic circuit 32 constituting a peripheral circuit is formed on a first semiconductor substrate 31 made of silicon (Si).
  • the logic circuit 32 is formed of a plurality of MOS transistors including CMOS transistors. As shown in FIG. 5, a plurality of regions on the surface side (upper side in FIG. 5) of the first semiconductor substrate 31 on which the logic circuit 32 is formed are interposed via a first insulating film 37 which is an interlayer insulating film.
  • the wirings 35a to 35c of the layers (three layers in this embodiment) and the lower layer wiring 36 of one layer are formed.
  • the wirings 35a to 35c are, for example, copper (Cu) wiring by the dual damascene method, and the lower layer wiring 36 is, for example, aluminum (Al) wiring.
  • Each MOS transistor is formed and configured in the semiconductor well region on the surface side of the first semiconductor substrate 31.
  • Each MOS transistor has a gate electrode formed via a gate insulating film with respect to a pair of source / drain regions and a pair of source / drain regions.
  • Each MOS transistor is separated by, for example, an element separation region separated by an element separator having an STI structure.
  • the multilayer wiring layer 34 is composed of the wirings 35a to 35c, the lower layer wiring 36, and the first conductor 38 composed of the first wiring 38a and the first dummy wiring 38b.
  • the MOS transistor, the wiring 35a, and the wirings 35a to 35c of the adjacent upper and lower layers are connected to each other by the conductive first via 33.
  • the first conductor 38 is made of metal.
  • the first conductor 38 is provided so as to be exposed on a surface (joint surface 40) facing the second substrate 50.
  • the first wiring 38a of the first conductor 38 is electrically connected to the lower layer wiring 36 and the wirings 35a, 35b, 35c via the first via 33, and is used as wiring.
  • a pixel array in which a plurality of pixels are two-dimensionally arranged in a row is formed on a second semiconductor substrate 51 made of thinned silicon (Si).
  • Each pixel is formed by a photodiode PD serving as a photoelectric conversion unit and a plurality of pixel transistors.
  • a plurality of MOS transistors forming a control circuit are formed on the second semiconductor substrate 51.
  • On the surface side (lower side in FIG. 5) of the second semiconductor substrate 51 a plurality of layers (three layers in this embodiment) wirings 55a and 55b and an upper layer are interposed via a second insulating film 57 which is an interlayer insulating film.
  • Wiring 56 is formed.
  • the wirings 55a and 55b and the upper layer wiring 56 are copper (Cu) wirings formed by, for example, the dual damascene method.
  • a color filter 59a and an on-semiconductor chip are placed on the effective pixel array via an insulating film and a flattening film.
  • a lens 59b is provided.
  • an on-semiconductor chip lens 59b can be formed on an optical black region (not shown) formed via an insulating film of CIS 52.
  • the multilayer wiring layer 54 is composed of the wirings 55a and 55b, the upper layer wiring 56, and the second conductor 58 composed of the second wiring 58a and the second dummy wiring 58b.
  • the multilayer wiring layer 54 of the second substrate 50 between the corresponding pixel transistor and the wiring 55a, and between the adjacent upper and lower layer wirings 55a and 55b and the upper layer wiring 56 are connected by a conductive second via 53.
  • the second conductor 58 is made of metal.
  • the second conductor 58 is provided so as to be exposed on a surface (joint surface 40) facing the first substrate 30.
  • the second wiring 58a of the second conductor 58 is electrically connected to the lower layer wiring 36 and the wirings 55a and 55b via the second via 53 and is used as wiring.
  • the first substrate 30 and the second substrate 50 are arranged so that the multilayer wiring layers (multilayer wiring layers 34 and 54) of each other face each other, and the first wiring 38a and the second wiring are arranged on the joint surface 40.
  • By directly joining the 58a they are electrically connected.
  • a first insulating film 37 is formed in the vicinity of the joint surface 40 of the first substrate 30.
  • a second insulating film 57 is formed in the vicinity of the joint surface 40 of the second substrate 50.
  • the direct joining of the first wiring 38a and the second wiring 58a is performed by, for example, thermal diffusion joining.
  • the first insulating film 37 and the second insulating film 57 other than the first wiring 38a and the second wiring 58a are joined by plasma joining or using an adhesive.
  • an extremely thin and uniform insulating thin film is formed on the surfaces of the multilayer wiring layers (multilayer wiring layers 34 and 54) of each other.
  • a film (not shown) may be formed and the first substrate 30 and the second substrate 50 may be bonded by plasma bonding or the like.
  • a manufacturing method of the solid-state image sensor 1A will be shown with reference to FIG. First, a method of manufacturing the second substrate 50 will be described.
  • a semiconductor well region is formed in a predetermined region of a second semiconductor wafer (hereinafter, referred to as a second semiconductor substrate 51) formed of silicon (Si).
  • a photodiode PD that serves as a photoelectric conversion unit for each pixel is formed in this semiconductor well region.
  • the device separation region can be formed first.
  • Each photodiode PD is formed so as to extend in the depth direction of the semiconductor well region.
  • the photodiode PD is formed in an effective pixel array that constitutes the pixel array 23 (see FIG. 2).
  • a plurality of pixel transistors constituting each pixel are formed on the surface side of the semiconductor well region of the second semiconductor substrate 51.
  • the pixel transistor can be composed of, for example, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.
  • Each pixel transistor is formed with a pair of source / drain regions and a gate electrode formed via a gate insulating film.
  • An interlayer insulating film is formed on the upper surface side of the second semiconductor substrate 51, and a plurality of layers (three layers in this embodiment) wirings 55a and 55b and an upper layer wiring 56 and a second layer wiring 56 are formed of metal through the interlayer insulating film. And the via 53 of the above.
  • the wirings 55a and 55b and the upper layer wiring 56 can be formed by the dual damascene method. That is, after forming a connection hole and a wiring groove by via first in the interlayer insulating film at the same time to form a Cu diffusion barrier metal film and a Cu seed film for preventing Cu diffusion, a Cu material layer is formed by a plating method. Embed.
  • the Cu diffusion barrier metal film examples include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), and titanium nitride. Examples thereof include zirconium (TiZrN) and alloy films containing these.
  • CMP chemical mechanical polishing
  • an insulating film such as silicon nitride (SiN), silicon carbide (SiC), silicon carbide (SiCN), or silicon oxide (SiON) can be used. This step is repeated to form the three-layer wirings 55a and 55b and the upper layer wiring 56.
  • a Cu diffusion barrier insulating film is formed on the interlayer insulating film on which the wirings 55a and 55b and the upper layer wiring 56 are formed, and then an insulating film having no Cu diffusion barrier property is formed.
  • the Cu diffusion barrier insulating film the above-mentioned insulating film such as silicon nitride (SiN), silicon carbide (SiC), silicon carbide (SiCN), and silicon oxide (SiON) can be used.
  • the insulating film having no Cu diffusion barrier property is formed of, for example, a silicon oxide (SiO 2 ) film, a SiCOH film, or the like.
  • the insulating film having no Cu diffusion barrier property and the Cu diffusion barrier metal film on the outermost surface are patterned by via-first using lithography and etching techniques to selectively form openings that are via holes.
  • an opening of the portion corresponding to the second wiring 58a and a via hole of the portion corresponding to the second via 53 are formed.
  • a second via 53 and a second conductor 58 (second) that are electrically connected to the upper layer wiring 56 by embedding a Cu material in the opening and the via hole using the dual damascene method.
  • the wiring 58a and the second dummy wiring 58b) are formed.
  • the second wiring 58a is formed as a fourth metal layer.
  • the second substrate 50 on which the wirings 55a and 55b formed of metal, the upper layer wiring 56, and the second conductor 58, and the multilayer wiring layer 54 including the second insulating film 57 are formed is formed.
  • a semiconductor well region is formed in a predetermined region of a first semiconductor wafer (hereinafter referred to as a first semiconductor substrate 31) formed of silicon (Si).
  • a plurality of MOS transistors forming the logic circuit 32 are formed in the semiconductor well region.
  • the MOS transistor can be formed in the device separation region after forming, for example, an element separator having an STI structure.
  • An interlayer insulating film is formed on the upper surface side of the first semiconductor substrate 31, and the wirings 35a, 35b and 35c of a plurality of layers (three layers in this embodiment) and the lower layer wiring 36 are formed of metal through the interlayer insulating film. , Forming the first via 33.
  • the wirings 35a, 35b and 35c can be formed by the dual damascene method. That is, after forming a connection hole and a wiring groove by via first in the interlayer insulating film at the same time to form a Cu diffusion barrier metal film and a Cu seed film for preventing Cu diffusion, a Cu material layer is formed by a plating method. Embed.
  • the Cu diffusion barrier metal film examples include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), and titanium nitride. Examples thereof include zirconium (TiZrN) and alloy films containing these.
  • CMP chemical mechanical polishing
  • the Cu barrier insulating film for example, an insulating film such as silicon nitride (SiN), silicon carbide (SiC), silicon carbide (SiCN), or silicon oxide (SiON) can be used. This step is repeated to form wirings 35a to 35c formed of three layers of metal. Further, the lower layer wiring 36 is formed by simultaneously forming a connection hole by via first and a wiring groove in the interlayer insulating film and embedding an Al material layer.
  • a Cu diffusion barrier insulating film is formed on the interlayer insulating film in which the wirings 35a to 35c and the lower layer wiring 36 are formed, and then an insulating film having no Cu diffusion barrier property is formed.
  • the Cu diffusion barrier insulating film the above-mentioned insulating film such as silicon nitride (SiN), silicon carbide (SiC), silicon carbide (SiCN), and silicon oxide (SiON) can be used.
  • the insulating film having no Cu diffusion barrier property is formed of, for example, a silicon oxide (SiO 2 ) film, a SiCOH film, or the like.
  • the insulating film having no Cu diffusion barrier property and the Cu diffusion barrier metal film on the outermost surface are patterned by via-first using lithography and etching techniques to selectively form openings that are via holes.
  • an opening of the portion corresponding to the first wiring 38a and a via hole of the portion corresponding to the first via 33 are formed.
  • a first via 33 and a first conductor 38 (first) that are electrically connected to the lower layer wiring 36 by embedding a Cu material in the opening and the via hole using the dual damascene method.
  • the wiring 38a and the first dummy wiring 38b) are formed.
  • the second wiring 58a is formed as a fifth metal layer.
  • the first substrate 30 on which the wirings 35a to 35c formed of metal, the lower layer wiring 36 and the first conductor 38, and the multilayer wiring layer 34 including the first insulating film 37 are formed is formed. ..
  • the first substrate 30 and the second substrate 50 are arranged and joined so that the multilayer wiring layers 34 and 54 face each other.
  • the fourth region A4 per unit area has a predetermined bonding force between the first substrate 30 and the second substrate 50 at any position of the wiring region WA and the dummy wiring region DA.
  • the first substrate 30 and the second substrate 50 are arranged so that the area ratio is equal to or greater than a predetermined value.
  • the first conductor 38 exposed from the first substrate 30 and the second conductor 58 exposed from the second substrate 50 are joined. More specifically, the first wiring 38a and the second wiring 58a, the first dummy wiring 38b and the second dummy wiring 58b are joined, respectively.
  • the first wiring 38a and the second wiring 58a arranged so as to intersect each other in a plan view are directly joined at a portion overlapping each other.
  • the first dummy wiring 38b and the second dummy wiring 58b arranged so as to intersect each other in a plan view are directly joined at a portion overlapping each other.
  • the first conductor 38 and the second conductor 58 are thermally diffused and joined by heat treatment.
  • the heat treatment temperature at this time can be about 100 ° C. or higher and 500 ° C. or lower.
  • the first insulating film 37 and the second insulating film 57 which are interlayer insulating films, are surface-treated and plasma-bonded.
  • the first insulating film 37 and the second insulating film 57 can also be joined with an adhesive.
  • the second semiconductor substrate 51 is ground and polished to a thin film by using a CMP method or the like so that the required film thickness of the photodiode PD remains from the back surface side.
  • a color filter 59a and an on-semiconductor chip lens 59b are formed on the photodiode PD corresponding to the effective pixel array via the flattening film.
  • a light-shielding film may be formed on the photodiode PD corresponding to the optical black region via an insulating film.
  • the bonded first substrate 30 and the second substrate 50 are cut into semiconductor chips that are separated into semiconductor chips to obtain the solid-state image sensor 1A shown in FIG.
  • the first wiring 38a and the second wiring 58a, the first dummy wiring 38b and the second dummy wiring 58b, the wirings 35a to 35c, the wirings 55a and 55b, and the lower layer wiring 36 and the upper layer wiring 56 are conductive. It is desirable that the material is made of a material having a high light-shielding property and easy to join. As a material having such properties, in addition to Cu, a single material such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), or a single material, or Alloys can be used. Further, the film thicknesses of the first wiring 38a and the second wiring 58a and the first dummy wiring 38b and the second dummy wiring 58b are determined according to the wavelength of the light on the light emitting first substrate 30 side. desirable.
  • a photodiode PD, a transistor, a multilayer wiring layer, or the like is formed on a semiconductor wafer, the semiconductor wafers are joined to each other, and then cut to form a semiconductor chip, that is, a so-called wafer-wafer.
  • the solid-state imaging device 1A is formed by joining has been described, but the present invention is not limited to this.
  • one of the first substrate 30 and the second substrate 50 is set as a chip substrate in which a semiconductor chip is formed in advance, and a wafer-chip junction in which a semiconductor chip (chip substrate) is bonded onto a semiconductor wafer.
  • the solid-state image sensor 1A may be formed by the above.
  • both the first substrate 30 and the second substrate 50 are made into semiconductor chips in advance, and the solid-state image sensor 1A is formed by chip-chip bonding in which semiconductor chips (chip substrates) are bonded to each other. It may be formed.
  • the first substrate 30 or the second substrate 50 is a chip substrate as in wafer-chip bonding and chip-chip bonding, it is compared with the wafer-wafer bonding described in this embodiment.
  • the method of holding the chip substrate at the time of joining, the method of pressing the chip substrate with a pin, the thickness of the chip substrate, and the like are changed during wafer-chip bonding and chip-chip bonding, the bonding speed at the time of chip substrate bonding and the direction vector in which the bonding proceeds change, so that the chip substrates behave differently from wafer-to-wafer bonding.
  • the bonding speed and direction vector are uniform in the radial direction.
  • the chip substrate is rectangular, there are differences in the bonding speed and direction vector from the center of the chip substrate.
  • the influence of the width of the oxide film region at the edge of the substrate and the corner at the edge of the chip, which are related to the entrainment of the junction vector cannot be ignored.
  • variations in bonding force can be suppressed even in the case of wafer-chip bonding and chip-chip bonding.
  • the ratio of the area of the fourth region to the unit area in the solid-state image sensor 1A is the above-mentioned bonding speed and direction vector.
  • the difference may be considered as an offset for determination.
  • the sign of the offset can be positive for factors that promote bonding and negative for factors that inhibit bonding, for example.
  • the sign of the offset is negative for the factor that promotes joining, and the factor that hinders it is positive. Can be.
  • the method of pressing the pins and the device of the bonding device at the time of substrate bonding are devised. Take measures such as going and devising the layout.
  • the conductor has been described as a dummy, but the use of the conductor is not limited to the dummy, and the conductor can be used for purposes such as dummy wiring and alignment marks.
  • the solid-state image sensor 1A has the following effects.
  • the conductor 38 and the second conductor 58 are joined. That is, in the solid-state imaging device 1A, the first wiring 38a and the second wiring 58a intersect in a plan view, and the first dummy wiring 38b and the second dummy wiring 58b intersect in a plan view.
  • the first substrate 30 and the second substrate 50 are arranged.
  • the joint area between the first conductor 38 and the second conductor 58 (the area of the first region A1) becomes substantially constant even when one of the substrates is slightly displaced from the predetermined position. ..
  • the area of the fourth region A4 where the first insulating film 37 and the second insulating film 57 overlap is also substantially constant. Therefore, the solid-state image sensor 1A has the bonding strength of the first substrate 30 and the second substrate 50 even when the position shift occurs when the first substrate 30 and the second substrate 50 are bonded.
  • the stability is high, and voids are less likely to occur on the joint surface 40.
  • the ratio of the area of the fourth region A4 per unit area (insulator area ratio) on the joint surface 40 is preferably 15% or more and 70% or less in any region.
  • Solid-state image sensor according to the second embodiment
  • the solid-state image sensor (image sensor) according to the second embodiment of the present disclosure will be described with reference to FIGS. 15 to 18.
  • the first conductor 38 and the second conductor 58 intersect each other in a plan view, and the first insulating film 37 and the second insulating film 57 overlap each other on the joint surface 40.
  • the solid-state image sensor 1A in which the ratio of the areas of the four regions A4 is equal to or larger than a predetermined value has been described.
  • the solid-state image sensor 1B which is a modification of the solid-state image sensor 1A, will be described.
  • the solid-state image sensor 1B differs from the solid-state image sensor 1A in that the first conductor 138 and the second conductor 158 are provided in place of the first conductor 38 and the second conductor 58.
  • FIGS. 15 and 16 show a configuration in the vicinity of the joint surface of the solid-state image sensor 1A when the joint position between the first substrate 30 and the second substrate 50 deviates from a predetermined position.
  • FIG. 15 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1A when the joint position between the first substrate 30 and the second substrate 50 deviates from a predetermined position.
  • FIG. 16 is a cross section taken along the line BB of FIG. 15, and shows a configuration in the vicinity of the joint surface of the solid-state image sensor 1B when the joint position between the first substrate 30 and the second substrate 50 deviates from a predetermined position. It is an enlarged sectional view.
  • the causes of this deviation include a deviation due to a process such as a dimensional deviation of the mask, an alignment deviation of the exposure apparatus, and an alignment deviation of the joining apparatus, and a deviation when the pattern is shifted for the purpose of shading.
  • a deviation of less than or equal to the maximum deviation amount ⁇ expected in advance occurs when the first substrate 130 and the second substrate 150 are bonded, a decrease in bonding strength is suppressed and a void is formed. Can be suppressed.
  • FIG. 17 is a plan view showing the minimum configuration of the first conductor 138 and the second conductor 158 in the vicinity of the joint surface of the solid-state image sensor 1B.
  • FIG. 18 is an enlarged plan view showing an example of the configuration of the first conductor 138 and the second conductor 158 in the vicinity of the joint surface of the solid-state image sensor 1B.
  • the first conductor 138 is either the first wiring 138a or the first dummy wiring 138b.
  • the second conductor 158 is the second wiring 158a when the first conductor 138 is the first wiring 138a, and the first conductor 138 is the first dummy wiring 138b. , The second dummy wiring 158b.
  • the cross-sectional configuration of the portion of the solid-state image sensor 1B other than the configuration near the joint surface is the same as the configuration of the solid-state image sensor 1A shown in FIG.
  • the first conductor 138 and the second conductor 158 are arranged so as to intersect each other in a plan view.
  • the first conductor 138 is provided so as to extend in the left-right direction in FIG.
  • the second conductor 158 is provided so as to extend in the vertical direction (an example of a direction intersecting with the first conductor 138) in FIG.
  • the first conductor 138 and the second conductor 158 are arranged so as to intersect with each other in the dummy wiring region DA.
  • the first conductor 138 is provided so as to extend in the left-right direction in FIG.
  • the second conductor 158 is provided so as to extend in the vertical direction (an example of a direction intersecting with the first conductor 138) in FIG.
  • the first conductor 138 (first conductor 138) in the vicinity of the joint surface of the solid-state imaging device 1B has a long side length (length in the stretching direction of the pattern) La and a short side. (Length in the direction orthogonal to the stretching direction) Wa is formed in a rectangular shape.
  • the second conductor 158 (second conductor 158) in the vicinity of the joint surface of the solid-state imaging device 1B has a long side length (length in the stretching direction of the pattern) Lb and a short side length (stretching). It is formed in a rectangular shape of Wb (length in the direction orthogonal to the direction).
  • a plurality of (n) first conductors 138 provided parallel to each other and a plurality (m) second conductors provided parallel to each other are provided. It has a plurality of wiring groups having a body 158.
  • the two first conductors 138 provided parallel to each other are arranged at a pitch Pa in the pattern width direction (vertical direction in FIG. 18).
  • the three second conductors 158 provided parallel to each other are arranged at a pitch Pb in the pattern width direction (left-right direction in FIG. 18).
  • the wiring group composed of the two first conductors 138 and the three second conductors 158 has a pattern extending direction of the first conductor 138 with respect to the adjacent wiring groups (left and right in FIG. 18). They are arranged at a pitch Qa in the direction) and a pitch Qb in the pattern width direction (vertical direction in FIG. 18) of the first conductor 138.
  • the ratio of the area of the fourth region A4 is constant even when a deviation of less than or equal to the maximum deviation amount ⁇ assumed in advance occurs when the first substrate 130 and the second substrate 150 are joined.
  • the sizes of the first conductor 138 and the second conductor 158 are adjusted so as to be. That is, the first conductor 138 and the second conductor 158 are formed so that the insulator area ratio is constant at a preset value.
  • the amount of deviation ⁇ depends on the position accuracy of the joining device that joins the first substrate 130 and the second substrate 150. Therefore, the dimensions of the first conductor 138 and the second conductor 158 are designed according to the positional accuracy of the joining device.
  • Insulator area ratio (Dss) in the dummy wiring region DA is represented by the following equation (1).
  • Insulator area ratio (Dss) ⁇ Qa ⁇ Qb- (La ⁇ Wa ⁇ n + Lb ⁇ Wb ⁇ m-Wa ⁇ Wb ⁇ n ⁇ m) ⁇ / (Qa ⁇ Qb) ⁇ ⁇ ⁇ (1)
  • the pattern width W of the first dummy wiring 138b and the second dummy wiring 158b is determined so as to satisfy the following equation (3) from the step constraint.
  • the length La of the first conductor 138 and the pattern width Wb of the second conductor 158 are determined to satisfy the following equation (4) due to the alignment deviation constraint based on the maximum deviation amount ⁇ of the alignment deviation. .. That is, the difference between the length of the long side of the first conductor 138 and the length of the short side of the second conductor 158 is more than twice the maximum deviation amount ⁇ assumed in advance.
  • the shapes of the first conductor 138 and the second conductor 158 satisfying the above formulas (1) to (6) will be specifically described.
  • the pattern width W satisfying the equation (4) is given by W ⁇ 1.8 ⁇ m. Further, the pattern width W satisfying the equation (5) is given by W ⁇ 2.8 ⁇ m. Further, due to the restrictions of the equations (3) and (6), 0.5 ⁇ W ⁇ 2.3 is a preferable range in the solid-state image sensor 1B.
  • the pattern width W of the first conductor 138 and the second conductor 158 is preferably in the range of W ⁇ 1.8 ⁇ m from the results of both.
  • the pattern width Wa and length La of the first conductor 138 and the pattern width Wb and length Lb of the second conductor 158 described in the present embodiment are the above-mentioned insulator area ratio (Dss) and the above-mentioned insulator area ratio (Dss). If the deviation constraint is satisfied, it can be set freely.
  • the pitch Pa between the first conductors 138, the pitch Pb between the second conductors 158, and the pitches Qa and Qb between the wiring groups also deviate from the above-mentioned insulator area ratio (Dss). If the restrictions are met, it can be set freely.
  • the dimensions of the first conductor 138 and the second conductor 158 are designed based on the constraints described above.
  • the bonding area between the first insulating film 137 and the second insulating film 157 (insulator) even if the bonding is misaligned at the time of bonding. Area ratio) can be constant.
  • the stability of the bonding strength between the first substrate 130 and the second substrate 150 (neither shown) on the bonding surface 140 is increased, and voids are generated by preventing bonding defects on the bonding surface 140. It becomes difficult.
  • the solid-state image sensor 1B according to the present embodiment has the following effects in addition to the effect of the first embodiment.
  • the shapes of the first insulating film 137 and the second insulating film 157 are designed according to the maximum amount ⁇ of the misalignment between the first substrate 130 and the second substrate 150. Can be done.
  • the bonding area (insulator area ratio) between the first insulating film 137 and the second insulating film 157 can be kept constant even if the bonding is misaligned at the time of bonding. Therefore, the stability of the bonding strength between the first substrate 130 and the second substrate 150 (neither shown) on the bonding surface 140 becomes high, and voids are generated by preventing the bonding failure on the bonding surface 140. It becomes difficult.
  • Solid-State Image Sensor of Third Embodiment the solid-state image sensor (image sensor) according to the third embodiment of the present disclosure will be described with reference to FIGS. 19 to 27.
  • the first conductor 38 and the second conductor 58 intersect each other in a plan view, and the first insulating film 27 and the second insulating film 57 per unit area on the joint surface 40.
  • the solid-state image sensor 1A in which the ratio of the area of the fourth region A4 that overlaps with the above is equal to or more than a predetermined value has been described.
  • the shapes of the first conductor 38 and the second conductor 58 are defined in more detail with respect to the deviation between the first substrate 30 and the second substrate 50.
  • the solid-state image sensors 1C to 1F will be described.
  • FIG. 19 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1C, which is the first example.
  • the two first wirings 238a and the two second wirings 258a are arranged so as to intersect each other in the plan view in the wiring region WA.
  • the first wiring 238a is provided so as to extend in the left-right direction in FIG.
  • the second wiring 258a is provided so as to extend in the vertical direction (an example of a direction intersecting with the first wiring 238a) in FIG.
  • a plurality of first dummy wirings 238b and second dummy wirings 258b are arranged so as to intersect each other in the dummy wiring region DA.
  • the first dummy wiring 238b is provided so as to extend in the left-right direction in FIG.
  • the second dummy wiring 258b is provided so as to extend in the vertical direction (an example of a direction intersecting with the first dummy wiring 238b) in FIG.
  • the first dummy wiring 238b and the second dummy wiring 258b are formed, for example, in the same size.
  • the shape (planar shape) exposed on the joint surface 240 of the first dummy wiring 238b and the second dummy wiring 258b is a rectangular shape having a length L in the extending direction of the pattern and a pattern width W.
  • the first dummy wiring 238b is arranged at a pitch P with respect to the adjacent first dummy wiring 238b.
  • the second dummy wiring 258b is also arranged at a pitch P with respect to the adjacent second dummy wiring 258b.
  • the first dummy wiring 238b and second dummy wiring 258b it is arranged to overlap in the area W 2. It is preferable that the second dummy wiring 258b is overlapped at a position inside the distance of the maximum deviation amount ⁇ or more from both ends of the first dummy wiring 238b in the left-right direction.
  • the insulator area ratio (Dss) is determined so as to satisfy the following equation (12) from the overlap constraint of the first insulating film 237 and the second insulating film 257.
  • the pattern width W of the first dummy wiring 238b and the second dummy wiring 258b is determined so as to satisfy the following equation (13) from the step constraint.
  • the pattern width W satisfying the equation (14) is given by W ⁇ 8.8 ⁇ m.
  • FIG. 20 shows equations (11) to (14) in the solid-state image sensor 1C.
  • the range of W that satisfies the constraints of the equations (11) and (12) is W ⁇ 4.7 from the intersection of the equations (11) and (12). This value satisfies the constraint of equation (14).
  • 0.5 ⁇ W ⁇ 4.7 is a preferable range in the solid-state image sensor 1C.
  • the pattern width W satisfying the equation (14) is given by W ⁇ 2.3 ⁇ m.
  • FIG. 21 shows equations (11) to (15) in the solid-state image sensor 1D. As shown in FIG. 21, the range of W that satisfies the constraints of the equations (11) and (12) is W ⁇ 2.3 because there is no intersection of the equations (11) and (12). Further, due to the restrictions of the equations (13) and (15), 0.5 ⁇ W ⁇ 2.3 is a preferable range in the solid-state image sensor 1D.
  • FIG. 22 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1E, which is the third example.
  • the two first wirings 238a and the two second wirings 258a are arranged so as to intersect each other in the plan view in the wiring region WA.
  • the first wiring 238a is provided so as to extend in the left-right direction in FIG. 22.
  • the second wiring 258a is provided so as to extend in the vertical direction (an example of a direction intersecting with the first wiring 238a) in FIG. 22.
  • one first dummy wiring 238b and three second dummy wirings 258b are arranged intersecting each other in the dummy wiring area DA.
  • the first dummy wiring 238b is provided so as to extend in the left-right direction in FIG. 22.
  • the second dummy wiring 258b is provided so as to extend in the vertical direction (an example of a direction intersecting with the first dummy wiring 238b) in FIG. 22.
  • a plurality of wiring groups (four in the present embodiment) in which one first dummy wiring 238b and three second dummy wirings 258b are arranged intersecting with each other are formed.
  • FIG. 23 shows equations (1) to (6) in the solid-state image sensor 1E.
  • the range of W that satisfies the constraints of the equations (1) and (2) is W ⁇ 1.8 because there is no intersection of the equations (1) and (2).
  • 0.5 ⁇ W ⁇ 1.8 is a preferable range in the solid-state image sensor 1D.
  • FIG. 24 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1F, which is the third example.
  • the two first wirings 238a and the two second wirings 258a are arranged so as to intersect each other in a plan view in the wiring region WA.
  • the first wiring 238a is provided so as to extend in the left-right direction in FIG. 24.
  • the second wiring 258a is provided so as to extend in the vertical direction (an example of a direction intersecting with the first wiring 238a) in FIG. 24.
  • first dummy wirings 238b and one second dummy wiring 258b are arranged so as to intersect each other in the dummy wiring area DA.
  • the first dummy wiring 238b is provided so as to extend in the left-right direction in FIG. 24.
  • the second dummy wiring 258b is provided so as to extend in the vertical direction (an example of a direction intersecting with the first dummy wiring 238b) in FIG. 24.
  • a plurality of wiring groups (nine in the present embodiment) in which two first dummy wirings 238b and one second dummy wiring 258b are arranged intersecting with each other are formed.
  • the pattern width W satisfying the formula (4) is given by W ⁇ 2.3 ⁇ m
  • the pattern width W satisfying the formula (5) is given by W ⁇ 1.8 ⁇ m.
  • the pattern width W satisfying the equation (1) is given by W ⁇ 1.6 ⁇ m.
  • FIG. 25 shows equations (1) to (6) in the solid-state image sensor 1F. As shown in FIG. 25, the range of W that satisfies the constraints of the equations (1) and (2) is W ⁇ 1.6. Further, due to the restrictions of the equations (3) and (6), 0.5 ⁇ W ⁇ 1.6 is a preferable range in the solid-state image sensor 1F.
  • the first dummy wiring 238b and bonding area between the second dummy wiring 258b remains at W 2.
  • the bonding area between the first dummy wiring 238b and second dummy wiring 258b is changed from W 2 May be done.
  • the joint area between the first dummy wiring 238b and the second dummy wiring 258b becomes constant (W 2 )
  • the joint area between the first dummy wiring 238b and the second insulating film 257, the second The joint area between the dummy wiring 258b and the first insulating film 237 is also constant. Therefore, the bonding area (insulator area ratio) between the first insulating film 237 and the second insulating film 257 is also constant. From the above, the stability of the bonding strength between the first substrate 230 and the second substrate 250 on the bonding surface 240 becomes high, and voids are less likely to occur on the bonding surface 240.
  • FIGS. 26 and 27 show other configuration examples of the solid-state image sensors 1C to 1F.
  • the outer peripheral region of the first region A1 where the first dummy wiring 238b and the second dummy wiring 258b overlap in a plan view is the first dummy wiring 238b and the first dummy wiring 238b. It may be secured as the joint region BA with the dummy wiring 258b of 2.
  • the joining region BA is preferably a region at least inside the alignment deviation amount ⁇ from the outer circumference of the first region A1, for example. Further, in the solid-state image pickup devices 1C to 1F shown in FIG.
  • the first insulating film 237 and the second insulating film 257 are provided in a region other than the bonding region BA between the first dummy wiring 238b and the second dummy wiring 258b. It may be arranged.
  • the junction region BA is a region outside the region surrounded by the broken line in FIG. 26, and the arrangement region of the first insulating film 237 and the second insulating film 257 (hereinafter referred to as the insulating film arrangement region) IA is , The area surrounded by the broken line in FIG. 26.
  • the shape of the insulating film arrangement region IA surrounded by the broken line in FIG. 26 is rectangular, but the shape is not limited to this.
  • the insulating film arrangement region IA may have any shape such as a circle or a polygon.
  • a plurality of insulating films may be arranged in the insulating film arrangement region IA.
  • the solid-state image sensors 1C to 1F shown in FIG. 27 show an example in which a plurality of rectangular insulating films are arranged in a stripe shape in the insulating film arrangement region IA.
  • the solid-state image sensors 1C to 1F according to the present embodiment have the following effects in addition to the effects of the first embodiment.
  • the shapes of the first conductor 238 and the second conductor 258 (the first) according to the maximum amount ⁇ of the misalignment between the first substrate 230 and the second substrate 250.
  • the dimensions of the first wiring 238a and the second wiring 258a, and the first dummy wiring 238b and the second dummy wiring 258b) can be designed.
  • the insulator area ratio (Dss) becomes constant at a preset value, and the stability of the bonding strength between the first substrate 230 and the second substrate 250 on the bonding surface 240 becomes high. Voids are less likely to occur.
  • Solid-state image sensor according to the fourth embodiment
  • the solid-state image sensor (image sensor) according to the fourth embodiment of the present disclosure will be described with reference to FIGS. 28 to 30.
  • the first conductor 38 and the second conductor 58 intersect each other in a plan view, and the first insulating film 37 and the second insulating film 57 per unit area on the joint surface 40.
  • the solid-state image sensor 1G having a configuration in which the first conductor 38, the second conductor 58, the first insulating film 37, and the second insulating film 57 are inverted will be described. do. That is, in the solid-state image sensor 1G, the rectangular first insulating film 337 and the second insulating film 357 are arranged so that at least a part of them overlap each other and intersect with each other in a plan view. In the solid-state image sensor 1G, a first conductor 338 and a second conductor 358 are provided around the first insulating film 337 and the second insulating film 357.
  • FIG. 28 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1G.
  • FIG. 29 is a CC cross section of FIG. 28, which is an enlarged cross section showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1G.
  • the overall configuration of the solid-state image sensor 1G that is, the cross-sectional configuration of the portion other than the configuration near the joint surface of the solid-state image sensor 1G is the same as the configuration of the solid-state image sensor 1A shown in FIG.
  • the solid-state image sensor 1G is joined to the first substrate 330 on which the first conductor 338 is formed and the first substrate 330 on which the second conductor 358 is formed.
  • a second substrate 350 is provided.
  • the first via 33 is connected to the first conductor 338
  • the second via 35 is connected to the second conductor 358.
  • the display of the first via 33 and the second via 35 shown in FIG. 8 is omitted.
  • the solid-state image sensor 1G includes a rectangular first insulating film portion 337a and a second insulating film portion 357a, and a rectangular first dummy insulating film portion 337b and a second dummy insulating film portion 357b. doing.
  • the first insulating film portion 337a and the second insulating film portion 357a are provided at positions corresponding to the first wiring 38a and the second wiring 58a of the solid-state image sensor 1A according to the first embodiment, respectively. ing.
  • the solid-state image sensor 1G includes a first insulating film portion 337a and a first dummy insulating film portion 337b as the first insulating film 337. Further, the solid-state image sensor 1G includes a second insulating film portion 357a and a second dummy insulating film portion 357b as the second insulating film 357.
  • the rectangular first dummy insulating film portion 337b and the second dummy insulating film portion 357b are arranged so that at least a part of them overlap each other in a plan view.
  • the rectangular first dummy insulating film portion 337b and the second dummy insulating film portion 357b are arranged so as to intersect each other in a plan view.
  • the first dummy insulating film portion 337b is provided so as to extend in the left-right direction in FIG. 28.
  • the second dummy insulating film portion 357b is provided so as to extend in the vertical direction (an example of a direction intersecting with the first dummy insulating film portion 337b) in FIG. 28. As shown in FIG. 28, the first dummy insulating film portion 337b and the second dummy insulating film portion 357b are joined to each other at a portion where the first dummy insulating film portion 337b and the second dummy insulating film portion 357b overlap each other. Has been done.
  • a portion other than the first insulating film 337 and the second insulating film 357 is a conductor (first). 338 and the second conductor 358).
  • the cross-sectional configuration of the portion of the solid-state image sensor 1G other than the configuration near the joint surface 340 is the same as the configuration of the solid-state image sensor 1A shown in FIG.
  • the first conductor 338 and the second conductor 358 overlap each other on the joint surface 340 between the first substrate 330 and the second substrate 350. It has a first region A1.
  • the solid-state image sensor 1G has a second region A2 on the joint surface 340 in which the first insulating film 337 formed by being surrounded by the first conductor 338 and the second conductor 358 overlap each other.
  • the solid-state image sensor 1G has a third region A3 on the joint surface 340 in which the second insulating film 357 formed by being surrounded by the second conductor 358 and the first conductor 338 overlap each other.
  • the solid-state image sensor 1G has a fourth region A4 in which the first insulating film 337 and the second insulating film 357 overlap each other on the joint surface 340.
  • the first region A1 to the fourth region A4 are formed by arranging the first insulating film 337 and the second insulating film 357 so as to partially overlap each other in a plan view.
  • the ratio of the area of the fourth region A4 (insulator area ratio) is arranged so as to be equal to or more than a predetermined value with respect to the bonding area between the first substrate 330 and the second substrate 350.
  • the conductor area ratio (Dcc) is a preset value.
  • the sizes of the first insulating film 337 and the second insulating film 357 are determined so as to be constant.
  • the dimensions of the first insulating film 337 and the second insulating film 357 are designed according to the positional accuracy of the joining device.
  • FIG. 28 is an enlarged plan view showing a configuration in the vicinity of the joint surface of the solid-state image sensor 1G.
  • the two first insulating films 337 and the second insulating film 357 are arranged so as to intersect each other in a plan view in the wiring region WA.
  • nine first insulating films 337 and nine second insulating films 357 are arranged so as to intersect each other in a plan view in the dummy wiring region DA.
  • the first insulating film 337 and the second insulating film 357 are formed, for example, in the same size.
  • the shape (planar shape) exposed on the joint surface 340 of the first insulating film 337 and the second insulating film 357 is the length L in the stretching direction of the pattern and the pattern width (length in the direction orthogonal to the stretching direction) W. It has a rectangular shape.
  • the first insulating film 337 is arranged at a pitch P with respect to the adjacent first insulating film 337.
  • the second insulating film 357 is also arranged at a pitch P with respect to the adjacent second insulating film 357.
  • a first insulating film 337 and the second insulating film 357 are arranged to overlap in the area W 2. It is preferable that the second insulating film 357 is overlapped at a position inside the first insulating film 337 with a maximum deviation amount ⁇ or more from both ends in the left-right direction.
  • the conductor area ratio (Dcc) ⁇ P 2- L 2 + (L-W) 2 ⁇ / P 2 ... (21)
  • the insulator area ratio (Dss) is determined so as to satisfy the following equation (22) due to the overlap constraint between the first insulating film 337 and the second insulating film 357.
  • Insulator area ratio (Dss) ⁇ Dss0 ...
  • the conductor area ratio (Dcc) is determined so as to satisfy the following equation (26) from the overlap constraint of the first dummy wiring 338b and the second dummy wiring 358b. Dcc ⁇ Dcc0 ... (26)
  • the shapes of the first insulating film 337 and the second insulating film 357 satisfying the above equations (21) to (26) will be specifically described.
  • the pattern width W satisfying the equation (24) is given by W ⁇ 8.8 ⁇ m.
  • the pattern width W satisfying the formula (22) is given by W ⁇ 6.12 ⁇ m, and the pattern width W satisfying the formula (23) is given by W ⁇ 5 ⁇ m.
  • the conductor area ratio (Dcc) satisfying the formula (26) is given by Dcc ⁇ 0.16.
  • FIG. 30 shows equations (21) to (25) in the above-mentioned example.
  • the solid-state image sensor 1G according to the present embodiment has the following effects in addition to the effect of the first embodiment.
  • the shapes of the first insulating film 337 and the second insulating film 357 are designed according to the maximum amount ⁇ of the misalignment between the first substrate 330 and the second substrate 350. Can be done.
  • the insulator area ratio (Dss) becomes constant at a preset value, and the stability of the bonding strength between the first substrate 330 and the second substrate 350 on the bonding surface 340 becomes high. Voids are less likely to occur.
  • FIG. 31 is a diagram showing examples of use of solid-state image sensors 1A to 1G according to the first to fourth embodiments according to the present technology as an image sensor.
  • the solid-state image sensors 1A to 1G according to the first to fourth embodiments described above are used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, as described below.
  • Any one of the solid-state image pickup devices 1A to 1G according to the first to fourth embodiments can be used as the device used in the field of the above, the field of agriculture, and the like.
  • the first to fourth implementations are applied to devices for taking images to be used for appreciation, such as digital cameras, smartphones, and mobile phones with a camera function.
  • devices for taking images to be used for appreciation such as digital cameras, smartphones, and mobile phones with a camera function.
  • Any one of the solid-state imaging devices 1A to 1G according to the embodiment can be used.
  • in-vehicle sensors that photograph the front, rear, surroundings, inside of a vehicle, etc., and monitor traveling vehicles and roads for safe driving such as automatic stop and recognition of the driver's condition.
  • One of the solid-state imaging devices 1A to 1G according to the first to fourth embodiments is used as a device used for traffic such as a surveillance camera and a distance measuring sensor for measuring distance between vehicles. Can be used.
  • devices used in home appliances such as television receivers, refrigerators, and air conditioners in order to photograph a user's gesture and operate the device according to the gesture.
  • Any one of the solid-state imaging devices 1A to 1G according to the fourth embodiment can be used.
  • the first to fourth implementations are applied to devices used for medical care and healthcare, such as endoscopes and devices that perform angiography by receiving infrared light.
  • devices used for medical care and healthcare such as endoscopes and devices that perform angiography by receiving infrared light.
  • Any one of the solid-state imaging devices 1A to 1G according to the embodiment can be used.
  • a surveillance camera for crime prevention for example, a camera for personal authentication, and other devices used for security include the solid-state image sensors 1A to 1G according to the first to fourth embodiments. Any one can be used.
  • a skin measuring device for photographing the skin, a microscope for photographing the scalp, and the like which are used for cosmetology, include the solid-state image sensor 1A according to the first to fourth embodiments. Any one of ⁇ 1G can be used.
  • any of the solid-state image sensors 1A to 1G according to the first to fourth embodiments for devices used for sports such as action cameras and wearable cameras for sports applications. Or one can be used.
  • a device used for agriculture such as a camera for monitoring the state of a field or a crop, and any of the solid-state image sensors 1A to 1G according to the first to fourth embodiments. Or one can be used.
  • FIG. 32 is a schematic configuration diagram of the electronic device 1000 of the present disclosure.
  • the electronic device 1000 according to the fifth embodiment includes a solid-state imaging device 1 (1A to 1G), an optical lens 1002, a shutter device 1003, a drive circuit 1004, and a signal processing circuit 1005.
  • the electronic device 1000 of the fifth embodiment shows an embodiment when the solid-state image sensor 1 according to the first embodiment of the present disclosure is used as the solid-state image sensor 1 in an electronic device (for example, a camera).
  • the optical lens 1002 forms an image of the image light (incident light 1006) from the subject on the image pickup surface of the solid-state image pickup device 1.
  • the shutter device 1003 controls the light irradiation period and the light blocking period for the solid-state image sensor 1.
  • the drive circuit 1004 supplies a drive signal that controls the transfer operation of the solid-state image sensor 1 and the shutter operation of the shutter device 1003.
  • the signal transfer of the solid-state image sensor 1 is performed by the drive signal (timing signal) supplied from the drive circuit 1004.
  • the signal processing circuit 1005 performs various signal processing on the signal (pixel signal) output from the solid-state image sensor 1.
  • the video signal after signal processing is stored in a storage medium such as a memory or output to a monitor.
  • the electronic device 1000 to which the solid-state image sensor 1 can be applied is not limited to the camera, but can also be applied to other electronic devices.
  • it may be applied to an imaging device such as a camera module for mobile devices such as mobile phones and tablet terminals.
  • the solid-state image sensor 1 according to the first embodiment is used as the electronic device as the solid-state image sensor 1, but other configurations may be used.
  • the solid-state image sensor 1 according to the second embodiment or the solid-state image sensor 1 according to a modified example may be used for an electronic device.
  • the present technology can have the following configurations.
  • the ratio of the area of the fourth region to the unit area is the first wiring region in which the first conductor portion and the third conductor portion of the joint surface are arranged, the second conductor portion, and the said.
  • a fourth region in which the first insulating film and the second insulating film overlap each other The ratio of the area of the fourth region to the unit area in the first wiring region in which the first conductor portion and the third conductor portion of the joint surface are arranged, and the second conductor portion and the said.
  • the ratio of the area of the fourth region to the unit area in the second wiring region is larger than the ratio of the area of the fourth region to the unit area in the first wiring region (2) or (3).
  • the first conductor and the second conductor are arranged so that the long side of the first conductor and the long side of the second conductor are orthogonal to each other in a plan view.
  • the first conductor and the second conductor have a rectangular shape, and the rectangular center of the first conductor and the rectangular center of the second conductor overlap in a plan view.
  • the solid-state image sensor according to (6) or (7) above (9)
  • the difference between the length of the long side of the first conductor and the length of the short side of the second conductor is the maximum presumed at the time of joining the first substrate and the second substrate.
  • the m second conductors are arranged so as to intersect with the first conductor, and the m second conductors are arranged at a pitch Pa.
  • the difference (La—Wb) between the length La of the long side of the first conductor and the length Wb of the short side of the second conductor is the difference between the first substrate and the second substrate.
  • the solid-state imaging device which satisfies the relationship of La—Wb ⁇ Pa (m-1) + 2 ⁇ with respect to the maximum deviation amount ⁇ assumed in advance at the time of joining.
  • (11) The solid-state image sensor according to any one of (1) to (5) above, wherein the first insulating film and the second insulating film are arranged so as to intersect each other in a plan view. (12) The difference between the length of the long side of the first insulating film and the length of the short side of the second insulating film is the maximum presumed at the time of joining the first substrate and the second substrate.
  • the solid-state image sensor which is at least twice the deviation amount ⁇ .
  • the outer peripheral region of the first region is a bonding region between the first conductor and the second conductor.
  • the region other than the outer peripheral region of the first region is any one of (1) to (12) above, which is an insulating film arrangement region in which the first insulating film and the second insulating film are arranged.
  • the solid-state image sensor according to the description (14) The solid-state image sensor according to (13) above, wherein a plurality of the insulating film arrangement regions are provided in the insulating film arrangement area.
  • Any of the above (1) to (14) in which the difference between the maximum value and the minimum value of the ratio of the area of the fourth region per unit area is equal to or less than a predetermined value at any position of the joint surface.
  • a solid-state image sensor in which the difference between the maximum value and the minimum value of the ratio of the area of the fourth region per unit area is equal to or less than a predetermined value at any position of the joint surface.
  • a plurality of first conductors including the first conductor portion and the second conductor portion are formed on the first semiconductor substrate to form the first substrate.
  • a second conductor portion on the second semiconductor substrate including a third conductor portion arranged to face the first conductor portion and a fourth conductor portion arranged to face the second conductor portion.
  • a second substrate is formed by forming a plurality of conductors of The first conductor and the second conductor face each other, and the first conductor and the second conductor overlap each other on the joint surface between the first substrate and the second substrate.
  • the ratio of the areas of the four regions is the first wiring region in which the first conductor portion and the third conductor portion of the joint surface are arranged, the second conductor portion, and the fourth conductor portion.
  • the first substrate and the second substrate have a predetermined bonding force between the first substrate and the second substrate at any position of the second wiring region in which the first substrate and the second substrate are arranged.
  • the ratio of the area of the fourth region to the unit area is the first wiring region in which the first conductor portion and the third conductor portion of the joint surface are arranged, the second conductor portion, and the said.

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Abstract

La présente invention supprime l'apparition de vides au niveau de l'interface de liaison entre un premier substrat et un second substrat qui forment un dispositif d'imagerie à semi-conducteurs. Un dispositif d'imagerie à semi-conducteurs comprend : un premier substrat sur lequel est formée une pluralité de premiers conducteurs qui comprennent une première partie conductrice et une deuxième partie conductrice; et un second substrat qui est lié au premier substrat et a formé sur celui-ci une pluralité de seconds conducteurs qui comprennent une troisième partie conductrice qui est placée à l'opposé de la première partie conductrice et une quatrième partie conductrice qui est placée à l'opposé de la deuxième partie conductrice. L'interface de liaison entre le premier substrat et le second substrat possède une quatrième région dans laquelle un premier film isolant qui est formé autour des premiers conducteurs et un second film isolant qui est formé autour des seconds conducteurs se chevauchent, et la fraction de la zone de la quatrième région par unité de surface est au moins une valeur prescrite qui se traduit par une force de liaison prescrite entre le premier substrat et le second substrat à n'importe quel emplacement dans une première région de câblage de l'interface de liaison dans laquelle la première partie conductrice et la troisième partie conductrice sont agencées et une seconde région de câblage de l'interface de liaison dans laquelle la deuxième partie conductrice et la quatrième partie conductrice sont agencées.
PCT/JP2021/003985 2020-03-30 2021-02-03 Dispositif d'imagerie à semi-conducteurs, procédé de production de dispositif d'imagerie à semi-conducteurs, et appareil électronique Ceased WO2021199665A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164870A (ja) * 2011-02-08 2012-08-30 Sony Corp 固体撮像装置とその製造方法、及び電子機器
JP2015135938A (ja) * 2013-12-19 2015-07-27 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
JP2018200958A (ja) * 2017-05-26 2018-12-20 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、固体撮像素子の製造方法および電子機器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164870A (ja) * 2011-02-08 2012-08-30 Sony Corp 固体撮像装置とその製造方法、及び電子機器
JP2015135938A (ja) * 2013-12-19 2015-07-27 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
JP2018200958A (ja) * 2017-05-26 2018-12-20 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、固体撮像素子の製造方法および電子機器

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