WO2021196175A1

WO2021196175A1 - Methods and apparatus for clock frequency adjustment based on frame latency

Info

Publication number: WO2021196175A1
Application number: PCT/CN2020/083263
Authority: WO
Inventors: Bo Du; Yongjun XU; Riliang PENG
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2020-04-03
Filing date: 2020-04-03
Publication date: 2021-10-07
Anticipated expiration: 2022-10-03

Abstract

The present disclosure relates to methods and apparatus for display processing. The apparatus can determine a frame latency of one or more frames of a plurality of frames in a display. In some aspects, the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time. The apparatus can also communicate the determined frame latency of each of the one or more frames in the display. Additionally, the apparatus can adjust or maintain a clock frequency based on the frame latency of each of the one or more frames. The apparatus can also adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames. Moreover, the apparatus can analyze the frame latency of the one or more frames.

Description

METHODS AND APPARATUS FOR CLOCK FREQUENCY ADJUSTMENT BASED ON FRAME LATENCY

TECHNICAL FIELD

The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display or frame processing.

INTRODUCTION

Computing devices often utilize a graphics processing unit (GPU) to accelerate the rendering of graphical data for display. Such computing devices may include, for example, computer workstations, mobile phones such as so-called smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of concurrently executing multiple applications, each of which may need to utilize the GPU during execution. A device that provides content for visual presentation on a display generally includes a GPU.

Typically, a GPU of a device is configured to perform the processes in a graphics processing pipeline. However, with the advent of wireless communication and smaller, handheld devices, there has developed an increased need for improved graphics processing.

SUMMARY

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a display processing unit (DPU) , a GPU, a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, or a CPU. The apparatus can determine a frame latency of one or more frames of a plurality of frames in a display. In some aspects, the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time. The apparatus can also calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames. The apparatus can also communicate the determined frame latency of each of the one or more frames in the display. Further, the apparatus can communicate the calculated frame latency information for the one or more frames from a display module to a graphics module. The apparatus can also analyze the frame latency of each of the one or more frames. Additionally, the apparatus can adjust or maintain a clock frequency based on the frame latency of each of the one or more frames. The apparatus can also increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold. Moreover, the apparatus can maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold. The apparatus can also adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames.

The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram that illustrates an example content generation system in accordance with one or more techniques of this disclosure.

FIG. 2 illustrates an example GPU in accordance with one or more techniques of this disclosure.

FIG. 3 illustrates an example timing diagram in accordance with one or more techniques of this disclosure.

FIG. 4 illustrates an example diagram of display processing in accordance with one or more techniques of this disclosure.

FIG. 5 illustrates an example diagram of display processing in accordance with one or more techniques of this disclosure.

FIG. 6 illustrates an example diagram of display processing in accordance with one or more techniques of this disclosure.

FIG. 7 illustrates an example flowchart of an example method in accordance with one or more techniques of this disclosure.

DETAILED DESCRIPTION

When a GPU is experiencing performance issues, there may be unwanted results for a frame or display, such as janks or frame drops. In these instances, a jank or frame drop may indicate the GPU is not performing at a sufficient level. However, present GPU algorithms may not be sensitive or fast enough to adjust a GPU clock frequency quickly. Based on this, present GPU algorithms may cause continuous janks or frame drops in subsequent frames. For example, when a GPU is running too slowly and experiencing janks, GPU algorithms may not adjust the GPU clock frequency fast enough to quickly avoid janks. Aspects of the present disclosure can increase the adjustment speed of the GPU clock frequency, such that janks can be quickly reduced or eliminated. In some aspects, the present disclosure can detect a frame latency or jank in a current display frame, and then adjust the GPU clock frequency such that in the subsequent display frame the frame latency or jank is reduced or eliminated. Aspects of the present disclosure can also efficiently implement a proper GPU clock frequency in order to optimize the amount of power expended.

Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements” ) . These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units) . Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs) , general purpose GPUs (GPGPUs) , central processing units (CPUs) , application processors, digital signal processors (DSPs) , reduced instruction set computing (RISC) processors, systems-on-chip (SOC) , baseband processors, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software, being configured to perform one or more functions. In such examples, the application may be stored on a memory, e.g., on-chip memory of a processor, system memory, or any other memory. Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or sub-components of a single component.

Accordingly, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise a random access memory (RAM) , a read-only memory (ROM) , an electrically erasable programmable ROM (EEPROM) , optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.

In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and/or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

As used herein, instances of the term “content” may refer to “graphical content, ” “image, ” and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech. In some examples, as used herein, the term “graphical content” may refer to a content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term “graphical content” may refer to a content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.

In some examples, as used herein, the term “display content” may refer to content generated by a processing unit configured to perform displaying processing. In some examples, as used herein, the term “display content” may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer) . A display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate display content. For example, a display processing unit may be configured to perform composition on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended.

FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of an SOC. The device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, the device 104 may include a processing unit 120, and a system memory 124. In some aspects, the device 104 can include a number of optional components, e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to the display 131 may refer to the one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this can be referred to as split-rendering.

The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. In some examples, the device 104 may include a display processor, such as the display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before presentment by the one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of: a liquid crystal display (LCD) , a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

Memory external to the processing unit 120, such as system memory 124, may be accessible to the processing unit 120. For example, the processing unit 120 may be configured to read from and/or write to external memory, such as the system memory 124. The processing unit 120 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 may be communicatively coupled to each other over the bus or a different connection.

The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM) , electrically erasable programmable ROM (EEPROM) , flash memory, a magnetic data media or an optical storage media, or any other type of memory.

The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

The processing unit 120 may be a central processing unit (CPU) , a graphics processing unit (GPU) , a general purpose GPU (GPGPU) , or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card that is installed in a port in a motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , arithmetic logic units (ALUs) , digital signal processors (DSPs) , discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

In some aspects, the content generation system 100 can include an optional communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and/or transmitting function described herein with respect to the device 104.

Referring again to FIG. 1, in certain aspects, the graphics processing pipeline 107 may include a determination component 198 configured to determine a frame latency of one or more frames of a plurality of frames in a display. In some aspects, the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time. The determination component 198 can also be configured to calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames. The determination component 198 can also be configured to communicate the determined frame latency of each of the one or more frames in the display. The determination component 198 can also be configured to communicate the calculated frame latency information for the one or more frames from a display module to a graphics module. The determination component 198 can also be configured to analyze the frame latency of each of the one or more frames. The determination component 198 can also be configured to adjust or maintain a clock frequency based on the frame latency of each of the one or more frames. The determination component 198 can also be configured to increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold. The determination component 198 can also be configured to maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold. The determination component 198 can also be configured to adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames. As described herein, a device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA) , a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU) , but, in further embodiments, can be performed using other components (e.g., a CPU) , consistent with disclosed embodiments.

GPUs can process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which can regulate how a graphics context will be processed. For example, context register packets can include information regarding a color format. In some aspects of context register packets, there can be a bit that indicates which workload belongs to a context register. Also, there can be multiple functions or programming running at the same time and/or in parallel. For example, functions or programming can describe a certain operation, e.g., the color mode or color format. Accordingly, a context register can define multiple states of a GPU.

Context states can be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD) , a vertex shader (VS) , a shader processor, or a geometry processor, and/or in what mode the processing unit functions. In order to do so, GPUs can use context registers and programming data. In some aspects, a GPU can generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, can use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states can change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.

FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure. As shown in FIG. 2, GPU 200 includes command processor (CP) 210, draw call packets 212, VFD 220, VS 222, vertex cache (VPC) 224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, L2 cache (UCHE) 238, and system memory 240. Although FIG. 2 displays that GPU 200 includes processing units 220-238, GPU 200 can include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units can be used by GPUs according to the present disclosure. GPU 200 also includes command buffer 250, context register packets 260, and context states 261.

As shown in FIG. 2, a GPU can utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and/or draw call data packets, e.g., draw call packets 212. The CP 210 can then send the context register packets 260 or draw call data packets 212 through separate paths to the processing units or blocks in the GPU. Further, the command buffer 250 can alternate different states of context registers and draw calls. For example, a command buffer can be structured in the following manner: context register of context N, draw call (s) of context N, context register of context N+1, and draw call (s) of context N+1.

Aspects of mobile devices or smart phones can utilize buffer mechanisms to distribute or coordinate a buffer between an application rendering side of the device, e.g., a GPU or CPU, and a display or composition side of the device, e.g., a display engine. For instance, some mobile devices can utilize a buffer queue mechanism to distribute or coordinate a buffer between an application rendering side and a display or composition side, which can include a buffer compositor or a hardware composer (HWC) . In some aspects, the application rendering side can be referred to as a producer, while the display or composition side can be referred to as a consumer. Additionally, a synchronization divider or fence can be used to synchronize content between the application rendering side and the display or composition side. Accordingly, a fence can be referred to as a synchronization divider, and vice versa.

A variety of factors can be performance indicators for display processing between an application rendering side and a display or composition side. For instance, frames per second (FPS) and janks, i.e., delays or pauses in frame rendering or composition, are key performance indicators (KPI) . In some aspects, a jank can be a perceptible pause in the rendering of a software application’s user interface. Both FPS and janks are KPIs in game performance and/or device display capability. In some applications, janks can be the result of a number of factors, such as slow operations or poor interface design. In some instances, a jank can also correspond to a change in the refresh rate of the display at the device. Janks are important to gaming applications because if the display fresh latency is not stable, this can impact the user experience. Accordingly, some aspects of the mobile gaming industry are focused on reducing janks and increasing FPS.

Applications can run at a variety of different FPS modes. In some aspects, applications can run at 30 FPS mode. In other aspects, applications can run at different FPS modes, e.g., 20 or 60 FPS. Aspects of the present disclosure can include a current frame latency time, which can refer to the time difference between when a previous frame completes being displayed and when a current frame completes being displayed. The frame latency time can also refer to the time between successive refreshing frames. The frame latency time can also be based on a frame rate. For instance, the frame latency time for each frame can be 33.33 ms (e.g., corresponding to 30 FPS) , 16.67 ms (e.g., corresponding to 60 FPS) , or 50 ms (e.g., corresponding to 20 FPS) .

Jank reduction technology can be utilized in a number of different scenarios. For instance, slow frames, e.g., frames under 30 FPS, may optimize janks reduction differently than fast frames. For example, there may be frame pacing issues for frames under 30 FPS, which may utilize a different janks reduction technology than faster frames. In some aspects, different mechanisms or designs may have the ability to detect janks. Also, once janks are detected, other mechanisms can be triggered. For example, a compositor can be directly triggered to bypass a vertical synchronization (VSYNC) time in order to avoid janks. In some aspects, the threshold of the janks reduction technology may be platform dependent, which may need certain tuning efforts.

As indicated herein, if a frame takes too long to be rendered and is not ready for transmission to a display at a scheduled VSYNC time, this can result in a delayed frame display time and a corresponding jank. As such, janks can be the result of a delayed frame rendering. In some aspects, a frame buffer or buffer queue can queue frames waiting to be sent to the display. If a frame takes too long to be rendered, then the frame may not be consumed or sent to the buffer queue by the scheduled VSYNC time.

In some aspects, a compositor may consume a frame or help send the frame buffer to the display. If the renderer takes too long to render a frame, then the compositor may be delayed in consuming the frame, so the frame will be delayed in being transmitted to the display. As such, a delay in rendering can cause a resulting delay in frame consumption or display transmission. In some aspects, if a frame has not finished rendering by a scheduled VSYNC time, then the frame will not be consumed by the compositor until the next VSYNC time. In these aspects, if there are no frames in the buffer queue, then the compositor may not be triggered to consume the frame. As the frame is not consumed, this can result in a jank.

In some aspects of GPU hardware implementation, a GPU can support a GPU clock frequency (clk freq) or a set of GPU clock frequencies. Each of the GPU clock frequencies may include a specific GPU power level, which can also correspond to a specific GPU performance level. In some aspects of GPU software or driver implementation, the GPU clock frequency can be dynamically adjusted by a GPU dynamic clock voltage scaling (dcvs) algorithm, e.g., according to a GPU workload. Accordingly, the GPU dcvs algorithm can adjust the clock frequency of the GPU.

The GPU clock frequency can control the speed at which the GPU is running. The GPU clock frequency can also correspond to the amount of power utilized, e.g., as the amount of voltage utilized corresponds to the GPU clock frequency. As such, if the GPU utilizes a higher clock frequency, the GPU may expend an increased amount of power. In some aspects, GPU software or driver can continuously collect GPU workloads for previous frames from a GPU hardware’s internal performance counter over a certain time interval. Then the GPU software or driver can instruct the GPU dcvs algorithm to dynamically adjust the GPU clock frequency to match current GPU workloads.

In some instances, the GPU dcvs algorithm can be power oriented. For instance, the GPU dcvs algorithm may not be performance oriented by default. Based on this, the GPU dcvs algorithm can attempt to determine a minimum GPU clock frequency to match current GPU workloads. If the GPU dcvs algorithm is power oriented, it may be focused on conserving power, not optimizing performance. As such, when janks are experienced, the GPU dcvs algorithm may not increase the GPU clock frequency fast enough to eliminate these janks.

In some aspects, when a GPU is experiencing performance issues, there may be many occurrences of janks or frame drops. However, as mentioned above, a GPU may not adjust or increase the GPU clock frequency to a higher level fast enough to quickly eliminate these janks. In these instances, a jank or frame drop may indicate the GPU is not performing at a sufficiently high level, so the GPU clock frequency may need to be adjusted or increased. However, present GPU algorithms are not sensitive or fast enough to adjust the GPU clock frequency quickly. Based on this, present GPU algorithms may cause continuous janks or frame drops in subsequent frames. In addition, the average frame rate may reduce, so the average GPU workload may be even further reduced. As such, GPU algorithms may not sufficiently increase the GPU clock frequency, which may run into a negative feedback loop.

As indicated above, when a jank is experienced in a certain frame, GPUs may not adjust the GPU clock frequency fast enough to avoid janks in subsequent frames. For example, when the GPU is running too slowly and experiencing janks, GPU algorithms may not adjust the GPU clock frequency fast enough to quickly avoid janks. Accordingly, there is a present need to increase the adjustment speed of the GPU clock frequency, such that janks can be quickly reduced or eliminated. There is also a need to efficiently implement a proper GPU clock frequency, such that the amount of power expended can be optimized.

Aspects of the present disclosure can increase the adjustment speed of the GPU clock frequency, such that janks can be quickly reduced or eliminated. In some aspects, the present disclosure can detect a frame latency or jank in a current display frame, and then adjust the GPU clock frequency such that in the subsequent display frame the frame latency or jank is reduced or eliminated. Aspects of the present disclosure can also efficiently implement a proper GPU clock frequency, such that the amount of power expended is optimized. Accordingly, aspects of the present disclosure can efficiently increase the GPU clock frequency to reduce janks, while at the same time optimizing the amount of power utilized.

Aspects of the present disclosure can collect or determine the display frame latency information at the DPU, which can directly reflect the risk of a jank or frame drop. Display frame latency information can also be useful in deciding a workable or optimized GPU running clock frequency at the GPU. Additionally, aspects of the present disclosure can utilize a novel GPU dcvs algorithm based on display frame latency. As indicated above, some aspects of the present disclosure can collect or determine this display frame latency at the DPU. In some aspects, the DPU hardware may start transmitting display frame data at each VSYNC boundary. Also, each VSYNC boundary may occur at a certain period, e.g., every 16.67 ms for a 60 FPS display or panel.

Additionally, the DPU software or kernel driver may wait for the synchronization fence or pipe to be signaled before it transmits or communicates a new frame to the DPU hardware. In some aspects, a display or panel can include multiple overlapping buffers or sections within the display. Each of the buffers or sections can include a synchronization fence in order to synchronize with other buffers or sections. Also, each of the overlapping sections can be stored in a buffer prior to being transmitted to the display. For instance, a display can include multiple buffers or sections, and a synchronization fence can be utilized to synchronize the buffers or sections of the display. Also, each synchronization fence can help to determine when the GPU completes rendering each buffer or section of the display.

FIG. 3 illustrates timing diagram 300 in accordance with one or more techniques of this disclosure. As shown in FIG. 3, timing diagram 300 includes frame 301, frame 302, frame 303, frame 304, GPU rendering process 310, and frame display process 320. Also, timing diagram 300 includes frame

rendering completion times

312, 313, and 314, which are the rendering completion time for

frames

302, 303, and 304, respectively. Timing diagram 300 also includes a number of vertical synchronization (VSYNC) times, e.g., VSYNC 331, VSYNC 332, VSYNC 333, VSYNC 334, and VSYNC 335. Timing diagram 300 also includes latency threshold 340 and frame latency 350. FIG. 3 shows that the time period between two VSYNC times, e.g., VSYNC 332 and VSYNC 333, is a VSYNC period.

As shown in FIG. 3, if the GPU completes rendering a frame prior to the next VSYNC time, then the frame will be transmitted to the display without any interruptions or janks. For example, frame 302 completes rendering prior to VSYNC 332, so frame 302 is sent to the display without any janks. In some instances, in order to avoid a jank, the GPU may need to complete rendering a frame prior to a latency threshold, e.g., latency threshold 340, before the next VSYNC time. For instance, if the GPU completes rendering a frame after the next VSYNC time, then a jank or frame drop may be experienced. When this occurs, the frame may not be transmitted to the display on time, so the previous frame may be displayed again at the display. As shown in FIG. 3, frame 303 completes rendering after VSYNC 333, which can cause a jank or frame drop. Based on this, frame 303 may not be transmitted to the display, so frame 302 is displayed again.

In some aspects, the DPU may begin transferring lines or sections of the frame to the display at a VSYNC time. For instance, the DPU can transfer lines or sections of the frame to the display in a certain amount of time. For example, the DPU can transfer the entire frame in around 15 ms. If the frame rendering completion time occurs prior to the next VSYNC time, then the DPU can transfer all the lines or sections of the frame smoothly by the next VSYNC time, or within one VSYNC period. As indicated above, if a GPU does not finish rendering a frame by the next VSYNC time, the frame may not be ready to be transferred at the subsequent VSYNC time, which can produce a jank or frame drop.

In some aspects, a display frame latency can be equal to a difference between a rendering completion time of each frame and the next VSYNC boundary. For example, the frame latency 350 of frame 304 is equal to the difference between frame rendering completion time 314 and VSYNC 335. Also, the frame rendering completion time can be referred to as an input fence time stamp. If the GPU finishes rendering a frame before the next VSYNC time, the frame latency may be negative. For instance, as the frame rendering completion time is less than the next VSYNC time, subtracting the VSYNC boundary from the frame rendering completion time can produce a negative result. If the GPU finishes rendering a frame after the next VSYNC time, then the frame latency may be positive. In this instance, as the frame rendering completion time is greater than the next VSYNC boundary, subtracting the VSYNC boundary from the frame rendering completion time can produce a positive result.

In some instances, aspects of the present disclosure can collect a maximum display frame latency by the DPU driver and transmit it to the GPU driver. This can occur when several frames are displayed simultaneously. Also, aspects of the present disclosure may compare the maximum display frame latency to a latency threshold. As indicated above, this latency threshold can be an amount of time or gap between a frame rendering completion time and the next VSYNC time. For example, the latency threshold can be a number of ms, e.g., -1 ms, prior to a subsequent VSYNC time. In some aspects, the latency threshold can be pre-selected or be a previously determined amount, e.g., -1 ms. Additionally, the latency threshold can be adjustable or tunable, e.g., based on the GPU workload.

In some aspects, if the display frame latency is less than a latency threshold, there may be no risk of missing the next VSYNC time. Accordingly, in this scenario, there may be no jank or frame drop. As both the display frame latency and the latency threshold may be negative, a display frame latency that is less than a latency threshold may extend farther away from the next VSYNC time. For example, in FIG. 3, frame latency 350 extends farther away from VSYNC 335 than latency threshold 340, but frame latency 350 may be referred to as less than latency threshold 340 if both values are negative. Also, if the display frame latency is greater than a latency threshold, there may be a risk of missing the next VSYNC time. In this scenario, there may or may not be a jank or a frame drop. If display frame latency is greater than zero (0) , then the frame rendering completion time may occur after the next VSYNC time. This scenario may cause a jank or the frame to be dropped.

Some aspects of the present disclosure can also feedback or transmit display frame latency information from the DPU to the GPU. For example, this frame latency information can include the frame latency of one or more display frames. Moreover, the GPU software or kernel driver can provide a callback function to the DPU software or kernel driver. In turn, the DPU software may call back this information in each frame display cycle. As such, the GPU software can obtain the display frame latency information on a frame-by-frame basis.

Additionally, aspects of the present disclosure can adjust or maintain the display frame latency information as an input parameter of the GPU dcvs algorithm. In some aspects, a previous or original GPU dcvs algorithm may include a GPU hardware internal performance counter as an input parameter. In an updated GPU dcvs algorithm, aspects of the present disclosure can extend the GPU dcvs algorithm to include the display frame latency information as a second input parameter. This may achieve an improved control for the GPU running clock frequency.

Further, aspects of the present disclosure can determine or identify a display frame latency parameter. As indicated above, if the display frame latency is greater than the latency threshold value, such that the frame rendering completion time occurs after the start of the latency threshold, aspects of the present disclosure may increase the GPU clock frequency to a higher level. Otherwise, the present disclosure may run the previous GPU dcvs algorithm and fallback to the previous GPU clock frequency. This can occur if the display frame latency is less than or equal to the latency threshold value, such that the frame rendering completion time occurs before the start of the latency threshold. Accordingly, if the display frame latency is greater than the latency threshold value, the GPU clock frequency can be increased to reduce any potential janks. If the display frame latency is less than the latency threshold value, then the GPU clock frequency can be maintained.

FIG. 4 illustrates diagram 400 of display processing in accordance with one or more techniques of this disclosure. As shown in FIG. 4, diagram 400 includes a number of steps or processes for DPU 410, e.g., a DPU software pipeline, and GPU 420, e.g., a GPU software pipeline. As displayed in FIG. 4,

steps

412, 414, and 416 can be performed by DPU 410. Also, steps 422, 424, 426, 428, and 430 can be performed by GPU 420.

At step 412, the DPU 410 can wait for all synchronization fences or pipes input fences to be signaled. At step 414, DPU 410 can calculate or determine the display frame latency information. Also, at step 414, DPU 410 can communicate the display frame latency information to the GPU, i.e., call the GPU callback function to feedback the display frame latency information. At step 416, DPU 410 can transmit the current frame data to the display panel.

At step 422, GPU 420 can perform idle checking. At step 424, GPU 420 can read or receive the display frame latency information communicated from the DPU. At step 426, GPU 420 can read or receive the GPU hardware performance counter for a GPU busy rate. This GPU hardware performance counter can indicate whether the GPU workload is high, or include another GPU performance indicator. Also, the GPU hardware performance counter can help to determine if the GPU clock frequency should be adjusted. Accordingly, the GPU clock frequency can be adjusted based on the GPU hardware performance counter. At step 428, GPU 420 can run a GPU dcvs algorithm. At step 430, GPU 420 can adjust a GPU running clock frequency, e.g., based on the display frame latency information, the GPU dcvs algorithm, or the GPU hardware performance counter.

FIG. 5 illustrates diagram 500 of display processing in accordance with one or more techniques of this disclosure. As shown in FIG. 5, diagram 500 includes a number of steps or processes for a GPU dcvs algorithm 510. At step 512, the GPU dcvs algorithm 510 can include an entry point. As shown in step 514 in FIG. 5, aspects of the present disclosure, e.g., the GPU dcvs algorithm 510, can determine whether the display frame latency is greater than a latency threshold. In some aspects, if the display frame latency is greater than a latency threshold, at step 516, the present disclosure can increase the GPU clock frequency. If the display frame latency is less than or equal to a latency threshold, at step 518, the present disclosure can maintain the GPU clock frequency, e.g., by utilizing the original or previous GPU dcvs algorithm. Thus, aspects of the present disclosure can adjust the GPU dcvs algorithm in order to adjust the GPU clock frequency. At step 520, the GPU dcvs algorithm 510 can include an exit point.

FIG. 6 illustrates diagram 600 of display processing in accordance with one or more techniques of this disclosure. More specifically, diagram 600 includes components of display processing for clock frequency adjustment based on frame latency. As shown in FIG. 6, diagram 600 includes GPU 610, DPU 620, display 630, and frames 640. GPU 610 can include clock frequency 612. FIG. 6 illustrates the communication of each of these components during display or frame processing. For instance, GPU 610 can communicate with DPU 620, and vice versa, and DPU 620 can communicate with display 630. In some instances, GPU 610, DPU 620, and display 630 can communicate one or more frames, e.g., frames 640.

As shown in FIGs. 3-6, aspects of the present disclosure can include a number of different techniques for clock frequency adjustment. For instance, aspects of the present disclosure, e.g., GPUs, DPUs, compositors, hardware composers, frame processors, or CPUs herein, can utilize frame latency for clock frequency adjustment. In some aspects, GPUs and DPUs herein, e.g., GPU 610 and DPU 620, can determine a frame latency of one or more frames, e.g., frames 640, of a plurality of frames in a display, e.g., display 630. The frame latency of each of the one or more frames, e.g., frame latency 350, can be equal to a difference between a rendering completion time, e.g., frame rendering completion time 314, of the frame, e.g., frame 304, and a vertical synchronization (VSYNC) time, e.g., VSYNC 335.

GPUs and DPUs herein can also calculate frame latency information for the one or more frames, e.g., frames 640, based on the frame latency of each of the one or more frames. GPUs and DPUs herein can also communicate the determined frame latency of each of the one or more frames, e.g., frames 640, in the display, e.g., display 630. Further, GPUs and DPUs herein can communicate the calculated frame latency information for the one or more frames from a display module to a graphics module, e.g., frames 640.

GPUs and DPUs herein can also analyze the frame latency of each of the one or more frames, e.g., frame latency 350. Additionally, GPUs and DPUs herein can adjust or maintain a clock frequency, e.g., clock frequency 612, based on the frame latency of each of the one or more frames, e.g., frame latency 350. In some instances, the clock frequency, e.g., clock frequency 612, can be a graphics processing unit (GPU) clock frequency. In some aspects, the clock frequency, e.g., clock frequency 612, can be adjusted or maintained based on the calculated frame latency information for the one or more frames, e.g., frames 640.

GPUs and DPUs herein can also increase the clock frequency, e.g., clock frequency 612, when the frame latency of each of the one or more frames, e.g., frame latency 350, is greater than a frame latency threshold, e.g., latency threshold 340. In some aspects, the frame latency threshold, e.g., latency threshold 340, can be adjustable or tunable. In some aspects, the frame latency threshold can be adjustable or tunable based on the clock frequency, e.g., clock frequency 612. Moreover, GPUs and DPUs herein can maintain the clock frequency, e.g., clock frequency 612, when the frame latency of each of the one or more frames, e.g., frame latency 350, is less than or equal to a frame latency threshold, e.g., latency threshold 340.

In some aspects, the clock frequency, e.g., clock frequency 612, can be adjusted or maintained based on a dynamic clock voltage scaling (dcvs) algorithm, e.g., GPU dcvs algorithm 510. GPUs and DPUs herein can also adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm, e.g., GPU dcvs algorithm 510, based on the frame latency of each of the one or more frames, e.g., frame latency 350.

Additionally, the clock frequency, e.g., clock frequency 612, can be adjusted or maintained based on a GPU performance counter. In some aspects, the GPU performance counter can include at least one performance parameter. Moreover, the frame latency of the one or more frames, e.g., frame latency 350, can be determined by a display processing unit (DPU) , e.g., DPU 620. Also, the frame latency of the one or more frames, e.g., frame latency 350, can be communicated to a GPU, e.g., GPU 610.

FIG. 7 illustrates an example flowchart 700 of an example method in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus, e.g., a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, a display processing unit (DPU) , a CPU, a GPU, or an apparatus for display or frame processing.

At 702, the apparatus can determine a frame latency of one or more frames of a plurality of frames in a display, as described in connection with the examples in FIGs. 3, 4, 5, and 6. In some aspects, the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time, as described in connection with the examples in FIGs. 3, 4, 5, and 6. At 704, the apparatus can calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.

At 706, the apparatus can communicate the determined frame latency of each of the one or more frames in the display, as described in connection with the examples in FIGs. 3, 4, 5, and 6. At 708, the apparatus can communicate the calculated frame latency information for the one or more frames from a display module to a graphics module, as described in connection with the examples in FIGs. 3, 4, 5, and 6. At 710, the apparatus can analyze the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.

At 712, the apparatus can adjust or maintain a clock frequency based on the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6. In some instances, the clock frequency can be a graphics processing unit (GPU) clock frequency, as described in connection with the examples in FIGs. 3, 4, 5, and 6. In some aspects, the clock frequency can be adjusted or maintained based on the calculated frame latency information for the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.

At 714, the apparatus can increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold, as described in connection with the examples in FIGs. 3, 4, 5, and 6. In some aspects, the frame latency threshold can be adjustable or tunable, as described in connection with the examples in FIGs. 3, 4, 5, and 6. At 716, the apparatus can maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold, as described in connection with the examples in FIGs. 3, 4, 5, and 6.

In some aspects, the clock frequency can be adjusted or maintained based on a dynamic clock voltage scaling (dcvs) algorithm, as described in connection with the examples in FIGs. 3, 4, 5, and 6. At 718, the apparatus can adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.

Additionally, the clock frequency can be adjusted or maintained based on a GPU performance counter, as described in connection with the examples in FIGs. 3, 4, 5, and 6. In some aspects, the GPU performance counter can include at least one performance parameter, as described in connection with the examples in FIGs. 3, 4, 5, and 6. Moreover, the frame latency of the one or more frames can be determined by a display processing unit (DPU) , as described in connection with the examples in FIGs. 3, 4, 5, and 6. Also, the frame latency of the one or more frames can be communicated to a GPU, as described in connection with the examples in FIGs. 3, 4, 5, and 6.

In one configuration, a method or apparatus for graphics processing is provided. The apparatus may be a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, a display processing unit (DPU) , a CPU, a GPU, or an apparatus for frame or graphics processing. In one aspect, the apparatus may be the processing unit 120 within the device 104, or may be some other hardware within device 104 or another device. The apparatus may include means for determining a frame latency of one or more frames of a plurality of frames in a display, where the frame latency of each of the one or more frames may be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time. The apparatus may also include means for communicating the determined frame latency of each of the one or more frames in the display. The apparatus may also include means for adjusting or maintaining a clock frequency based on the frame latency of each of the one or more frames. The apparatus may also include means for increasing the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold. The apparatus may also include means for maintaining the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold. The apparatus may also include means for analyzing the frame latency of each of the one or more frames, wherein the clock frequency is adjusted or maintained based on the analyzed frame latency of each of the one or more frames. The apparatus may also include means for calculating frame latency information for the one or more frames based on the frame latency of each of the one or more frames. The apparatus may also include means for communicating the calculated frame latency information for the one or more frames from a display module to a graphics module. The apparatus may also include means for adjusting or maintaining the dcvs algorithm based on the frame latency of each of the one or more frames.

The subject matter described herein can be implemented to realize one or more benefits or advantages. For instance, the described display processing techniques can be used by compositors, frame compositors, composers, hardware composers, frame composers, frame processors, display processors, DPUs, CPUs, GPUs, or other display or frame processors to enable the aforementioned clock frequency adjustment. This can also be accomplished at a low cost compared to other display or frame processing techniques. Moreover, the display or frame processing techniques herein can improve or speed up data processing or execution. Further, the display or frame processing techniques herein can improve the data utilization and/or resource efficiency of DPUs or GPUs. Additionally, the display or frame processing techniques herein can include clock frequency adjustments based on frame latency that can optimize the amount of power utilized. Clock frequency adjustment techniques herein can also increase the clock frequency in order to reduce the amount of janks experienced.

Further disclosure is included in the Appendix.

In accordance with this disclosure, the term “or” may be interrupted as “and/or” where context does not dictate otherwise. Additionally, while phrases such as “one or more” or “at least one” or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise.

In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD) , laser disc, optical disc, digital versatile disc (DVD) , floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

The code may be executed by one or more processors, such as one or more digital signal processors (DSPs) , general purpose microprocessors, application specific integrated circuits (ASICs) , arithmetic logic units (ALUs) , field programmable logic arrays (FPGAs) , or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor, ” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

Various examples have been described. These and other examples are within the scope of the following claims.

Appendix

A novel display frame latency based GPU DCVS

Problem statement

1. In most of GPU vendor's HW implementation, GPU can support a set/list of GPU clk freq, and each GPU clk freq is binding to a specific GPU power level, which is also binding to a specific GPU performance level.

2. In most of GPU vendor's SW/Driver implementation, GPU clk freq is dynamically adjusted by a GPU dcvs (dynamically clock voltage scale) algorithm according to current GPU's work loads.

3. GPU SW/Driver is continuously collecting the GPU's work loads in the past few frames from GPU HW's internal perf counter in a certain time interval, then input to the GPU dcvs algorithm to dynamically adjust the GPU clk freq to match the current GPU's work loads.

4. GPU dcvs algorithm is mainly power oriented, not performance oriented by default, it is trying the best to find a minimum GPU clk freq to match the current GPU's work loads.

5. In those customer reported GPU performance issues, we observed that there are many janks/frame drops occurred, but the GPU dcvs does not adjust GPU clk freq to higher level. We analyzed such issue and identify the root cause is that when there is a jank/frame drop, which indicate the GPU performance is not enough, so we need to adjust GPU clk freq to higher, but current GPU dcvs algorithm is not so sensitive to adjust the GPU clk freq quickly, so cause the continuous janks/frame drops in next frames, then the average frame rate became very Iow, and the average GPU work loads became even Iow, so GPU dcvs algorithm don't have chance to adjust GPU clk freq to higher level, which runs into a negative circle.

Invention

As we can easily collect the display frame latency info in DPU side, which directly reflect the risk of jank/frame drop, it should be very useful info to decide a workable GPU running clk freq in GPU side. Here we proposed a novel GPU dcvs invention based on display frame latency:

There are 3 parts in our invention:

Part 1 -collect the display frame latency info in DPU side:

DPU HW should start display data transmitting at each Vsync boundary which comes in a certain period like 16.7ms for 60fps display. DPU SW (kernel driver) must wait for all pipes' input fences to be signaled before it kick off the new frame to DPU HW.

The display frame latency = input fence time stamp of each frame -Vsync boundary

As there are several frames are displayed simultaneously, the maximum display frame latency is collected in DPU driver and pass to GPU driver, and the maximum display frame latency is compared to one Threshold (< 0) , such as -1.0ms,

If display frame latency < Threshold, it has no risk to miss the next vsync, and there is no jank/frame drop.

If display frame latency > Threshold, it has the risk to miss the next vsync, it may cause jank/frame drop.

If display frame latency > 0, it will definitely miss the next vsync, then cause a jank/frame drop.

Part 2 -Feedback the display frame latency info from DPU side to GPU side:

GPU SW (kernel driver) provide one callback function to DPU SW (kernel driver) , DPU SW call this callback in each frame display cycle. So GPU SW can get the display frame latency info frame by frame.

Part 3 -Accept the display frame latency info as new input parameter of GPU dcvs algorithm:

The original GPU dcvs algorithm only take GPU HW internal perf counter as input parameter.

In the new GPU dcvs algorithm in our proposal, we extend the GPU dcvs algorithm to take the display frame latency info as the second input parameters to achieve a better control for GPU running clk freq. we firstly check the display frame latency parameter, if it is bigger than the Threshold value, we raise the GPU running clk to higher level directly; otherwise, let it runs into the original GPU dcvs algorithm flow.

Detection

It is easy to detection this invention with the method below:

Capture systrace in a GPU heavy using case, and check if GPU clk freq can be adjusted to higher freq timely when there is a potential or existing jank/frame drop.

If you can see a timely GPU clk freq raising at the potential or existing jank/frame drop time, then it is very possible our invention is applied; otherwise if you see the GPU clk freq keeps running in a lower freq due to the continuous jank/frame drop, then our invention is not applied.

Claims

A method of display processing, comprising:

determining a frame latency of one or more frames of a plurality of frames in a display, wherein the frame latency of each of the one or more frames is equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time;

communicating the determined frame latency of each of the one or more frames in the display; and

adjusting or maintaining a clock frequency based on the frame latency of each of the one or more frames.
The method of claim 1, wherein adjusting or maintaining the clock frequency based on the frame latency of each of the one or more frames comprises:

increasing the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold.
The method of claim 2, wherein the frame latency threshold is adjustable or tunable.
The method of claim 1, wherein adjusting or maintaining the clock frequency based on the frame latency of each of the one or more frames comprises:

maintaining the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold.
The method of claim 1, further comprising:

analyzing the frame latency of each of the one or more frames, wherein the clock frequency is adjusted or maintained based on the analyzed frame latency of each of the one or more frames.
The method of claim 1, further comprising:

calculating frame latency information for the one or more frames based on the frame latency of each of the one or more frames.
The method of claim 6, further comprising:

communicating the calculated frame latency information for the one or more frames from a display module to a graphics module.
The method of claim 6, wherein the clock frequency is adjusted or maintained based on the calculated frame latency information for the one or more frames.
The method of claim 1, wherein the clock frequency is adjusted or maintained based on a dynamic clock voltage scaling (dcvs) algorithm.
The method of claim 9, further comprising:

adjusting or maintaining the dcvs algorithm based on the frame latency of each of the one or more frames.
The method of claim 1, wherein the clock frequency is adjusted or maintained based on a graphics processing unit (GPU) performance counter.
The method of claim 11, wherein the GPU performance counter includes at least one performance parameter.
The method of claim 1, wherein the clock frequency is a graphics processing unit (GPU) clock frequency.
The method of claim 1, wherein the frame latency of the one or more frames is determined by a display processing unit (DPU) .
The method of claim 1, wherein the frame latency of the one or more frames is communicated to a graphics processing unit (GPU) .
An apparatus for display processing, comprising:

a memory; and

at least one processor coupled to the memory and configured to:

determine a frame latency of one or more frames of a plurality of frames in a display, wherein the frame latency of each of the one or more frames is equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time;

communicate the determined frame latency of each of the one or more frames in the display; and

adjust or maintain a clock frequency based on the frame latency of each of the one or more frames.
The apparatus of claim 16, wherein to adjust or maintain the clock frequency based on the frame latency of each of the one or more frames comprises the at least one processor configured to:

increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold.
The apparatus of claim 17, wherein the frame latency threshold is adjustable or tunable.
The apparatus of claim 16, wherein to adjust or maintain the clock frequency based on the frame latency of each of the one or more frames comprises the at least one processor configured to:

maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold.
The apparatus of claim 16, wherein the at least one processor is further configured to:

analyze the frame latency of each of the one or more frames, wherein the clock frequency is adjusted or maintained based on the analyzed frame latency of each of the one or more frames.
The apparatus of claim 16, wherein the at least one processor is further configured to:

calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames.
The apparatus of claim 21, wherein the at least one processor is further configured to:

communicate the calculated frame latency information for the one or more frames from a display module to a graphics module.
The apparatus of claim 21, wherein the clock frequency is adjusted or maintained based on the calculated frame latency information for the one or more frames.
The apparatus of claim 16, wherein the clock frequency is adjusted or maintained based on a dynamic clock voltage scaling (dcvs) algorithm.
The apparatus of claim 24, wherein the at least one processor is further configured to:

adjust or maintain the dcvs algorithm based on the frame latency of each of the one or more frames.
The apparatus of claim 16, wherein the clock frequency is adjusted or maintained based on a graphics processing unit (GPU) performance counter, wherein the GPU performance counter includes at least one performance parameter.
The apparatus of claim 16, wherein the frame latency of the one or more frames is determined by a display processing unit (DPU) .
The apparatus of claim 16, wherein the frame latency of the one or more frames is communicated to a graphics processing unit (GPU) .
An apparatus for display processing, comprising:

means for determining a frame latency of one or more frames of a plurality of frames in a display, wherein the frame latency of each of the one or more frames is equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time;

means for communicating the determined frame latency of each of the one or more frames in the display; and

means for adjusting or maintaining a clock frequency based on the frame latency of each of the one or more frames.
A computer-readable medium storing computer executable code for display processing, the code when executed by a processor causes the processor to:

determine a frame latency of one or more frames of a plurality of frames in a display, wherein the frame latency of each of the one or more frames is equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time;

communicate the determined frame latency of each of the one or more frames in the display; and

adjust or maintain a clock frequency based on the frame latency of each of the one or more frames.