[go: up one dir, main page]

WO2021021415A1 - Micro-del et procédé de fabrication de micro-del - Google Patents

Micro-del et procédé de fabrication de micro-del Download PDF

Info

Publication number
WO2021021415A1
WO2021021415A1 PCT/US2020/041515 US2020041515W WO2021021415A1 WO 2021021415 A1 WO2021021415 A1 WO 2021021415A1 US 2020041515 W US2020041515 W US 2020041515W WO 2021021415 A1 WO2021021415 A1 WO 2021021415A1
Authority
WO
WIPO (PCT)
Prior art keywords
leds
micro
gan
silicon substrate
combination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2020/041515
Other languages
English (en)
Inventor
Errol Antonio C. SANCHEZ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2021021415A1 publication Critical patent/WO2021021415A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00
    • H01L25/0753—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/817—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN

Definitions

  • Embodiments of the present disclosure generally relate to micro-LEDs, and methods of forming micro-LEDs.
  • a method for manufacturing red micro-LEDs on the same substrate, such as a silicon wafer, with pre existing blue micro-LEDs and/or green micro-LEDs, is disclosed.
  • Micro-LEDs are being considered for use in next- generation display devices.
  • conventional attempts of micro-LED pixels utilize red, green, and blue micro-LEDs.
  • Blue and green micro-LEDs are typically built from a stack of layers based on hexagonal (wurtzite) gallium nitride (GaN), with the active emitter layers incorporating varying concentrations of Indium (InGaN) to modulate the color.
  • the stack of layers are either grown as blanket films that are subsequently patterned and etched into micrometer-sized structures, or grown selectively as micrometer structures in pre-defined areas opened in between dielectric layers.
  • These micro- LEDs are generally formed on sapphire due to the lattice-matching between sapphire and hexagonal GaN.
  • Sapphire substrates are generally limited in size (usually a diameter of four inches or less), and therefore, present challenges when scaling upward to produce enough micro-LEDs for mass production of large-screen display devices. While several development efforts of micro-LEDs on more abundant and larger silicon substrates are in progress, such as by selective growth of various structures of both hexagonal (wurtzite) GaN and cubic (zinc-blende) GaN crystal phases on both ⁇ 1 11 > and ⁇ 100> Si wafers, attempts so far have been deficient.
  • red micro-LEDs based on GaN perform poorly for a variety of technical reasons beyond the lattice-mismatch between the high indium- containing GaN emitter and the underlying GaN/sapphire or GaN/Si.
  • Red micro- LEDs based on InGaP grown on GaAs substrates have improved performance and are more common.
  • micro- LEDs from multiple substrates are utilized.
  • the micro-LEDs from the different substrates are diced and positioned (often referred to as a “pick-and-place” operation) onto a suitable host substrate, such as the one that eventually becomes a display device.
  • The“picking-and-placing” of thousands of micro sized LEDs is tedious, time- consuming, expensive, and has its own technical limitations.
  • Embodiments of the present disclosure generally relate to micro- LEDs, and methods of forming micro-LEDs.
  • a method for manufacturing red micro-LEDs on the same substrate, such as a silicon wafer, with pre-existing blue micro-LEDs and/or green micro-LEDs, is disclosed.
  • a method of processing a substrate that includes masking GaN-based blue micro-LEDs, GaN-based green micro-LEDs, ora combination thereof disposed on a silicon substrate disposed in a processing system.
  • the method further includes forming a plurality of AllnGaP-based red micro-LEDs on the silicon substrate.
  • a device that includes a silicon substrate, a plurality of GaN-based blue micro-LEDs disposed on the silicon substrate, a plurality of GaN-based green micro-LEDs disposed on the silicon substrate, and a plurality of AllnGaP-based red micro-LEDs disposed on the silicon substrate.
  • a non-transitory computer readable medium storing instructions that, when executed by a processor of a system, perform operations that include forming a plurality of GaN-based blue micro-LEDs on a silicon substrate, forming a plurality of GaN-based green micro- LEDs on the silicon substrate, masking the plurality of GaN-based blue micro- LEDs and the plurality of GaN-based green micro-LEDs on the silicon substrate, and forming a plurality of AllnGaP-based red micro-LEDs on the silicon substrate.
  • Figure 1 is a flow diagram of a method for forming micro-LEDs on a substrate according to at least one embodiment.
  • Figure 2 schematically illustrates a starting substrate structure on which micro-LEDs may be formed according to at least one embodiment.
  • Figures 3A-3E schematically illustrate a substrate during operations associated with the flow diagram of Figure 1 according to at least one embodiment.
  • Figures 4A-4B schematically illustrate formation of micro-LEDs on a substrate, according to at least one embodiment.
  • Figure 5 is an processing system, according to at least one embodiment.
  • Embodiments of the present disclosure generally relate to micro- LEDs, and methods of forming micro-LEDs.
  • a method for manufacturing AllnGaP-based red micro-LEDs on the same substrate, such as a silicon wafer, with pre-existing GaN-based blue micro-LEDs and/or green micro-LEDs, is disclosed.
  • FIG. 1 is a flow diagram of a method 100 for forming micro-LEDs on a substrate, according to at least one embodiment.
  • a gallium nitride (GaN) layer is deposited on a ⁇ 1 1 1 > surface of a silicon substrate.
  • Metal Organic Chemical Vapor Deposition (MOCVD) can be used as the deposition method, but either Hydride Vapor Phase Epitaxy (HVPE) or a lower temperature method, such as molecular beam epitaxy (MBE) may also be used.
  • HVPE Hydride Vapor Phase Epitaxy
  • MBE molecular beam epitaxy
  • the lattices of GaN and the ⁇ 1 1 1 > silicon surface are sufficiently similar to allow a quality GaN layer to be formed thereon.
  • the deposition of GaN is a blanket deposition on the surface of a ⁇ 11 1 > silicon wafer, to a thickness having a range of about 500 nanometers to about 10 micrometers, such as about 1 micrometer to about 5 micrometers, or about 2 micrometers to about 4 micrometers.
  • One or more transition layers of AIN and/or AIGaN are utilized between the silicon surface and the GaN to facilitate device formation.
  • the AIN layer(s) may be deposited to a thickness of about 100 nanometers (nm) to about 200 nm.
  • the AIGaN layer(s) may be deposited to a thickness of about 200 nm to about 800 nm.
  • a ⁇ 100> silicon substrate 200 (e.g., having a ⁇ 100> exposed upper surface 220) may be utilized.
  • the ⁇ 100> exposed upper surface 220 may be first processed by, e.g., using a homoepitaxial growth process, to generate ⁇ 1 1 1 > surfaces 222 prior to GaN deposition in operation 102.
  • the ⁇ 1 1 1 > surfaces 222 may be formed from ⁇ 100> exposed upper surface 220 by the formation of faceted surfaces.
  • the ⁇ 1 1 1 > surfaces 222 facilitate GaN deposition in a predetermined crystallographic orientation.
  • a mask 253 such as silicon oxide or other oxide, is disposed on the upper surface 220 of the silicon substrate 200.
  • Crystalline silicon 260 is epitaxially formed on exposed areas of the ⁇ 100> exposed upper surface 220 of the si l i con substrate 200 to a height Hi which exceeds a height h ⁇ of the mask, resulting in the ⁇ 1 1 1 > surfaces 222 (e.g., faceted surfaces) of the formed crystalline silicon 260 (e.g., a faceted epitaxial silicon feature) being present above the mask 253.
  • the ⁇ 1 1 1 > surfaces 222 may be, for example, a silicon pyramid, pointed strip, or other similar feature.
  • the ⁇ 1 1 1 > surfaces 222 are grown by selective epitaxy deposition, for example, at a temperature of about 800 degrees Celsius or more.
  • the ⁇ 1 1 1 > surfaces 222 have a ⁇ 1 1 1 > crystallographic orientation which facilitates growth of c-plane wurtzite GaN thereon (e.g., GAN layer or structure 262).
  • GaN is formed selectively on the ⁇ 1 1 1 > surfaces 222 to a thickness of about 200 nanometers to about 1000 nanometers, such as 400 nanometers to about 800 nanometers.
  • AIN and AIGaN transitional layers may similarly be used prior to the GaN deposition on the ⁇ 1 1 1 > surfaces 222.
  • the crystalline silicon 260 formed as described above has a height Hi .
  • Height Hi is about equal to a height of the GaAs featured formed during subsequent operation 1 12 of Figure 1.
  • the height Hi of the crystalline silicon 260 feature above an upper surface of a mask 253 is about 40 nm to about 400 nm.
  • the epitaxial formation of the ⁇ 1 1 1 > surfaces 222 may be halted before a peak or apex forms between the ⁇ 1 1 1 > surfaces 222, to mitigate GaN bridging. Additionally or alternatively, it is contemplated that any formed peaks may be polished off the silicon prior to formation of GaN, for example, by chemical mechanical polishing.
  • a GaN l a y e r o r structure 262 in the form of vertical rods are grown on upper surface 220 (which may be a ⁇ 1 11 > surface) of a silicon substrate 200.
  • the GaN layer or structure 262 is formed by depositing a mask, such as a silicon oxide mask, on the silicon substrate 200, and patterning the mask 253 to expose predetermined areas of the silicon substrate 200 for selective growth of the rods.
  • the rods are then formed in the openings of the mask 253 using a deposition process, such as MOCVD, and aided by a nucleation layer such as AIN having a thickness of about 2 nm to about 50 nm.
  • the rods may have diameters from a few hundred to a few thousand nanometers, such as about 300 nm or about 3000 nm, and heights that are about three to about eight times the diameter of each respective rod.
  • FIG. 3A depicts an example of the resulting GaN rod structures, e.g., blue and green micro-LEDs 350.
  • the GaN layer or structure 262 is then further processed in operation 104 to develop respective areas for green micro-LEDs and blue micro-LEDs.
  • Such areas may be developed by application of appropriate active emitter layers thereon by, e . g . , forming multi-quantum wells (MQWs) with alternating layers of indium gallium nitride (InGaN) and GaN, each layer being about two to four nanometers thick.
  • MQWs multi-quantum wells
  • the indium concentration of the InGaN layer is selected to provide a desired color output (e.g., green) for the micro-LED.
  • MQWs with higher indium concentrations emit at longer wavelengths.
  • Green color for example requires higher indium concentration than blue color.
  • the bulk GaN layer below the MQW is doped, either n-type or p-type, and an oppositely doped GaN layer or structure 262 above the MQW is also utilized so as to form a diode.
  • the oppositely doped GaN layer, along with other layer details that may be designed-in to enhance micro-LED performance, such as strain relief layers, electron blocking layers, cladding layers, etc., are also contemplated for inclusions in operation 104 around the MQW formation.
  • Metallic contacts are also applied to the doped layers to finish off the micro- LED, but in this method, are applied after completing all the operations covered in Figure 1 (e.g., after operation 1 14).
  • blanket deposition of the MQWs on top of the doped blanket GaN from operation 102 can target one particular indium concentration of the InGaN layers, followed by masking and etching, to create micrometer- sized areas for the micro-LEDs of one color, either blue or green, but not both. Stated otherwise, MQWs for blue and green micro- LEDs are formed separately. It is contemplated, however, in another example of operation 104 that, separate larger areas on the blanket GaN allocated for the other color, may be masked with silicon oxide prior to the above operations for forming the first color (e.g., blue) micro-LED.
  • the first color e.g., blue
  • wet etching and exposing those allocated (e.g., masked) areas then allows subsequent formation therein of the second color (e.g., green) micro-LEDs.
  • Mask and wet etch processes are selected to minimize or avoid damage to the previously-formed micro-LEDs.
  • Existing active emitter layers of the blue micro-LEDs can also be damaged if the typically high temperature (> about 800°C) process of MOCVD or HVPE are used for the active layers of the green micro-LEDs.
  • This can be avoided by using low temperature sources of nitrogen (such as hydrazine, or plasma activation of either N 2 or NH 3 ) for deposition below 700 degrees Celsius such as 650 degrees Celsius.
  • plasma activated N2 or NHs is utilized at pressures below about 10 torr, such as below about 5 torr or below about 3 torr.
  • Hydrazine in the absence of plasma may be utilized at a pressure below about 400 torr, such as below about 300 torr. It is contemplated that etching to form the micrometer sized areas could possibly damage the active emitter layers at the edge of the shapes, resulting in lower light output efficiency. Passivation layers to mitigate the possible damage caused by etching can optionally be applied at some later operation after completing all the operations covered in Figure 1.
  • both blue and green micro- LEDs may be formed using a blanket deposition.
  • the blanket GaN formed on the substrate in operation 102 is patterned to form first areas of micrometer sized GaN corresponding to locations for forming blue micro-LEDs and second areas of micrometer sized GaN corresponding to locations for forming green micro-LEDs.
  • MQWs at one indium concentration for blue are then formed on the first locations while masking the second locations, and subsequently MQWs at a higher indium concentration for green are formed on the second locations while masking the first locations.
  • low-temperature nitrogen sources may be utilized for the second locations to achieve predetermined thermal budgets.
  • the micrometer- sized areas patterned from blanket layers to form the micro- LEDs in this example or the previous example can have any shape such as a round disc, a square, or a rectangle.
  • the sizes of the shapes can range from less than about a micrometer to a few micrometer, such as from about 0.8um to about 8um, however other sizes are also contemplated.
  • MQWs may be formed on both the first locations and the second locations simultaneously and without masks by taking advantage of pattern dependence (also termed micro-loading) in MOCVD.
  • the first locations e.g., locations for respective micro-LEDs of a first color
  • second locations e.g., locations for respective micro-LEDs of a second color
  • the lower concentration of indium results in a blue emission, while a relatively higher concentration results in a green emission.
  • the first locations can be spaced about 0.2 micrometers to about 1 .2 micrometers apart (e.g., about 1.2 micrometer pitch) while the second locations can be spaced about 1 micrometer to about 2 micrometers apart, such as about 1.6 micrometers apart.
  • Such spacing results in an indium concentration of about 15 atomic percent InGaN in the MQW of the blue micro-LEDs, and about 25 atomic percent InGaN in the MQW of the green micro-LEDs.
  • both the green micro-LEDs and blue micro-LEDs respective areas are developed simultaneously during the same deposition of MQWs by taking advantage of the MOCVD micro-loading phenomena. That is, areas created in operation 102 with lower areal density of structures will have at operation 104 active emitter layers with higher indium concentration (longer wavelength emission such as green) than the other areas with higher areal density of structures. Such outcomes at operation 104 are similarly achieved when using the example of GaN rod structures from operation 102.
  • FIG. 3A schematically illustrates a substrate 352 having either blue or green or both micro-LEDs 350 thereon (completed after operation 104 of Figure 1 ). While Figure 3A depicts, as one example, rod GaN structures used for micro-LEDs, e.g. , blue and green micro-LEDs 350, other structures for operation 104 may be used. Figures 3B-3E schematically illustrate the example structures associated with operations 106-114 of Figure 1.
  • the mask 353 illustrated in Figure 3B may partially include the pre-existing mask already deposited at operation 104 over the blue micro-LEDs, or alternatively, the mask existing over the blue micro-LEDs may be removed, and a fresh mask may be positioned over the substrate and then patterned to expose predetermined areas for red micro-LED formation.
  • the mask 353 is formed from silicon oxide. Presence of the mask 353 protects the blue and green micro-LEDs 350 during formation of red micro-LEDs during subsequent processing.
  • the mask 353 is patterned corresponding to predetermined regions of formation for red micro-LEDs.
  • the regions may be in the shape of, e.g., a square or a rectangular stripe.
  • a photoresist 354 is applied over the mask 353, as shown in Figure 3B, to facilitate lithographic patterning.
  • the mask 353 is removed by a fluorine-based wet or dry etchant, such as HF, CF 4 , or NF 3 , to expose portions of the substrate surface 351 at the bottom of a well or opening 355 (e.g. , a trench opening) within the mask 353, as shown in Figure 3C. Completion of operation 108 leads to the formation of a plurality of openings 355.
  • the substrate surface 351 is cleaned by exposure to a wet or dry etchant.
  • a wet or dry etchant In one example of operation 1 10, where the blue and green micro-LEDs 350 were earlier formed on the substrate 352 having ⁇ 1 11 > orientation, the exposed areas of th e su bstrate su rface 351 depicted in Figure 3C already have a desirable crystallographic orientation for gallium arsenide (GaAs) growth.
  • GaAs gallium arsenide
  • the exposed areas of the substrate surface 351 are first subjected (prior to etching in operation 110 to clean the substrate 352) to an etching process, such as a wet etch using tetramethylammonium hydroxide or dry etch using CI2, to form V-shaped facets 356 into the su bstrate surface 351 as depicted in Figure 3D.
  • the resulting or V-shaped facets 356 have the ⁇ 1 1 1 > crystallographic orientation that facilitates formation of GaAs material 358 within openings 355 in the mask 353.
  • Cleaning of the su bstrate surface 351 is performed at low temperatures in line with predetermined thermal budgets.
  • the Applied Materials SiCoNiTMdry clean is one example useful for application with aspects of this disclosure.
  • GaAs material 358 is formed on the exposed, etched, and/or cleaned surfaces of the substrate (e.g., substrate surface 351 having ⁇ 1 1 1 > orientation or V-shaped facets 356 of the substrate 352).
  • the GaAs material 358 is selectively grown during a chemical vapor deposition process, such as metal organic chemical vapor deposition, using gallium-containing precursor gases, arsenic-containing precursor gases, or a combination thereof, including trimethylgallium, triethylgallium, arsine, and tertiarybutylarsine.
  • the GaAs material 358 is formed vertically upwards within the openings 355 in the mask 353, using the ⁇ 1 1 1 > crystallographic orientation of the underlying exposed areas of the substrate surface 351 as an epitaxial template. As the GaAs material 358 height exceeds the height of the mask 353 features during the deposition process, it is contemplated that the shape and width of the GaAs material 358 may change. Facet formation may occur as the height of the GaAs material 358 exceeds the height of the mask 353.
  • the GaAs material 358 may taper outward at surface 357 such that a width of the GaAs material 358 formed in each respective mask 353 feature has a width greater than a width of the respective opening 355 in the mask 353 at a height above the upper surface of the mask 353.
  • Such a formation may be influenced by the crystallographic tendencies of the GaAs material 358 during formation as facilitated by the deposition conditions, including temperature, flow of growth precursors, and growth rate.
  • the base portion of the GaAs material 358 (and the openings 355) have a width within a range of about 100 nanometers to about 1000 nanometers.
  • the width of the GaAs material 358 above the mask 353 may be grown to about 200nm to about 2000nm depending on, at least, the predetermined height, the opening 355, and/or the chosen growth conditions.
  • the process temperature may be maintained at less than 650C, such as 600C, to avoid damage to the previously developed GaN blue and/or green micro-LEDs 350.
  • MQWs 359 are formed at operation 1 14 on the upper surface of the GaAs as shown in Figure 3D.
  • the MQWs 359 for the red micro-LEDs are formed of alternating layers of aluminum indium gallium phosphide (AllnGaP) and indium gallium phosphide (InGaP), which are formed via, e.g., MOCVD at a temperature of about 650 degrees Celsius or less.
  • Each respective opening 355 formed in the patterning of operation 108 includes a GaAs material 358 feature with a MQW 359 formed thereon, resulting in a plurality of red micro-LEDs.
  • the mask 353 formed over the blue and green micro- LEDs 350 is removed, and further processing may occur.
  • contacts may be applied to the micro-LEDs.
  • the substrate may be diced into units which each include red green blue (RGB) micro- LEDs.
  • RGB red green blue
  • the masking and deposition operation described above are selected to position a respective red, green, and blue micro-LED in close proximity to one another to facilitate dicing into RGB units, e.g., an RGB pixel.
  • dicing may be omitted, and the substrate having RGB micro-LEDs thereon is bonded directly to a substrate having a predetermined CMOS layout formed thereon.
  • the RGB micro-LED layout is selected to correspond to the predetermined CMOS layout. Because dicing and pick-and-place operations are omitted in such an example, throughput is increased and manufacturing costs are reduced.
  • Figure 3E illustrates a plan view of an area on the substrate 352, e.g., a silicon substrate.
  • the area 360 includes blue micro-LEDs
  • the area 361 includes green micro-LEDs
  • the area 362 includes red micro-LEDs all formed on a single substrate 352. While the substrate 352 is shown with a plurality of micro-LEDs clustered together for each color (RGB), any number of micro-LEDs for each color may be designed into an area, depending on, e.g., the size of each emitting GaN and GaAs microstructure, the light output or intensity for each color, and/or the area size to be filled.
  • RGB red micro-LEDs
  • a designated area includes one round-shaped blue micro-LED structure, one round-shaped green micro-LED structure, and one red micro-LED stripe.
  • a designated area includes a cluster of a different number of each respective color LED.
  • the designated area could include a cluster of three square-shaped blue micro-LEDs, ten round-shaped green micro-LEDs, and five red micro-LED stripes. Lines delineating different areas (e.g., individual pixel areas) may be defined in patterning according to device design parameters.
  • each micro-LED may be adjusted to form micro-LEDs of different physical dimensions.
  • the red micro- LEDs of area 362 are shown in Figure 3E as having different dimensions than the blue micro-LEDs of area 360 and green micro-LEDs of area 361 , it is contemplated that the dimensions of each may be adjusted to form micro- LEDs of similar physical dimensions.
  • the dimensions of each micro-LED may be adjusted to form micro-LEDs of similar light (e.g., intensity) output.
  • FIGS 4A-4B schematically illustrate formation of micro-LEDs on a silicon substrate 452, according to another embodiment.
  • the blue and green micro-LEDs are formed by masking an upper surface
  • the silicon substrate 452 includes areas 461 , 462, and 463 of green, blue, and red (respectively) micro-LEDs. Notably, the spacing between adjacent green micro-LEDs in area
  • FIG. 5 is a processing system 530 according to at least one embodiment.
  • the processing system 530 may be one system utilized to practice aspects of the disclosure. However, it is contemplated that other processing systems may additionally or alternatively be utilized.
  • the processing system 530 includes a factory interface 532 for receiving cassettes 534.
  • the factory interface 532 is coupled to a buffer station 536 through which substrates are transferred by a factory interface robot 538. Substrates are received from the buffer station 536 by a transfer robot 540 positioned in a transfer chamber 542.
  • the transfer chamber is coupled to one or more processing chambers 500a-500e.
  • processing chambers 500a-500e may include, for example, one or more cleaning chambers such as SiCoNi® chambers, one or more MOCVD chambers, available from Applied Materials, of Santa Clara, California, and one or more passivation chambers, such as one or more ALD passivation chambers for AI2O3, S1O2, AIN, or one or more CVD passivation chambers for AI2O3, S1O2, AIN, or H2S, available from Applied Materials, of Santa Clara, California. While five processing chambers 500a-500e are shown, it is contemplated that more or less processing chambers may be utilized. Additionally, while the processing chambers 500a-500e are shown in a clustered configuration, it is contemplated that the process chambers may operate in a non-clustered configuration.
  • cleaning chambers such as SiCoNi® chambers, one or more MOCVD chambers, available from Applied Materials, of Santa Clara, California
  • passivation chambers such as one or more ALD passivation chamber
  • a processor 548 is coupled to the processing system 530 to control aspects thereof.
  • the processor 548 can include a processor that executes program code instructions stored on a tangible, non-transitory computer- readable medium to perform and/or control various operations described herein.
  • the computer-readable medium can include any suitable memory for storing instructions, such as read-only memory (ROM), random access memory (RAM), flash memory, an electrically erasable programmable ROM (EEPROM), a hard disk drive, a compact disc ROM (CD-ROM), a floppy disk, punched cards, magnetic tape, and the like.
  • the processor 548 can control operations of the processing system 530 to facilitate operations of methods described herein.
  • a method of processing a substrate comprising: masking GaN-based blue micro-LEDs, GaN-based green micro-LEDs, or a combination thereof disposed on a silicon substrate disposed in a processing system; and forming a plurality of AllnGaP-based red micro-LEDs on the silicon substrate.
  • Clause 3 The method of Clause 1 or Clause 2, wherein the GaN- based blue micro-LEDs, the GaN-based green micro-LEDs, or combination thereof are GaN structures selectively deposited prior to masking GaN-based blue micro-LEDs, GaN-based green micro-LEDs, or a combination thereof.
  • Clause 4 The method of Clause 3, wherein the GaN-based blue micro-LEDs, the GaN-based green micro-LEDs, or combination thereof are formed on ⁇ 1 1 1 > facetted epitaxially grown silicon features.
  • Clause 5 The method of Clause 3 or Clause 4, wherein the GaN- based blue micro-LEDs, the GaN-based green micro-LEDs, or combination thereof are formed on ⁇ 1 1 1 > surfaces of features etched into the silicon substrate.
  • Clause 6 The method of any one of Clauses 3-5, wherein the GaN- based blue micro-LEDs, the GaN-based green micro-LEDs, or combination thereof comprise vertical rods.
  • Clause 7 The method of any one of Clauses 1-6, wherein the GaN- based blue micro-LEDs, the GaN-based green micro-LEDs, or combination thereof are formed from blanket layers.
  • Clause 8 The method of any one of Clauses 1 -7, wherein the masking GaN-based blue micro-LEDs, the GaN-based green micro-LEDs, or a combination thereof comprises masking both of the GaN-based blue micro-LEDs and the GaN-based green micro-LEDs.
  • Clause 9 The method of The method of any one of Clauses 1-8, wherein the processing system includes a transfer chamber coupled to a cleaning chamber, a MOCVD chamber, and a passivation chamber.
  • a device comprising: a silicon substrate; a plurality of GaN- based blue micro-LEDs disposed on the silicon substrate; a plurality of GaN- based green micro-LEDs disposed on the silicon substrate; and a plurality of AllnGaP-based red micro-LEDs disposed on the silicon substrate.
  • a non-transitory computer readable medium storing instructions that, when executed by a processor of a system, perform operations comprising: forming a plurality of GaN-based blue micro-LEDs on a silicon substrate disposed in a processing system; forming a plurality of GaN-based green micro-LEDs on the silicon substrate; masking the plurality of GaN-based blue micro-LEDs, the plurality of GaN-based green micro-LEDs, or a combination thereof on the silicon substrate; and forming a plurality of AllnGaP-based red micro-LEDs on the silicon substrate.
  • Clause 12 The non-transitory computer readable medium of Clause 1 1 , wherein the forming a plurality of AllnGaP-based red micro-LEDs on the silicon substrate comprises selectively depositing GaAs structures in patterned areas at temperatures less than 650°C.
  • Clause 13 The non-transitory computer readable medium of Clause 1 1 or Clause 12, wherein the plurality of GaN-based blue micro-LEDs, the plurality of GaN-based green micro-LEDs, or a combination thereof are GaN structures selectively deposited prior to the masking.
  • Clause 14 The non-transitory computer readable medium of Clause 13, wherein the plurality of GaN-based blue micro-LEDs, the plurality of GaN- based green micro-LEDs, or a combination thereof are formed on ⁇ 1 1 1 > surfaces of features etched into the silicon substrate.
  • Clause 15 The non-transitory computer readable medium of Clause 13 or Clause 14, wherein the plurality of GaN-based blue micro-LEDs, the plurality of GaN-based green micro-LEDs, or a combination thereof are formed on ⁇ 1 1 1 > facetted epitaxially grown silicon features.
  • Clause 16 The non-transitory computer readable medium of any one of Clauses 13-15, wherein the plurality of GaN-based blue micro-LEDs, the plurality of GaN-based green micro-LEDs, or a combination thereof comprise vertical rods.
  • Clause 17. The non-transitory computer readable medium of any one of Clauses 1 1-16, wherein the plurality of GaN-based blue micro-LEDs, the plurality of GaN-based green micro-LEDs, or a combination thereof are formed from blanket layers.
  • Clause 18 The non-transitory computer readable medium of any one of Clauses 1 1-17, wherein the masking comprises masking both of the GaN- based blue micro-LEDs and the GaN-based green micro-LEDs.
  • Clause 19 The non-transitory computer readable medium of any one of Clauses 1 1-18, wherein the processing system includes a transfer chamber coupled to a cleaning chamber, a MOCVD chamber, and a passivation chamber.
  • Clause 20 The non-transitory computer readable medium of any one of Clauses 1 1-19, wherein the forming a plurality of AllnGaP-based red micro- LEDs on the silicon substrate comprises selectively depositing GaAs structures in patterned areas at temperatures less than 600°C.
  • deposition techniques such as MOCVD
  • MBE molecular beam epitaxy
  • the present disclosure include methods for forming red, blue, and green micro-LEDs on a single substrate. Formation of red, blue, and green micro-LEDs on silicon substrates can , at least, provide increased productivity, due to a reduced number of operations, the omission of pick-and- place processes, and the increased size of silicon substrates compared to conventionally-used sapphire substrates.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Devices (AREA)

Abstract

Des modes de réalisation de la présente invention concernent, d'une manière générale, des micro-DEL, ainsi que des procédés de formation de micro-DEL. Dans un mode de réalisation, l'invention concerne un procédé de traitement d'un substrat qui consiste à masquer des micro-DEL bleues à base de GaN, des micro-DEL vertes à base de GaN, ou une combinaison de celles-ci disposée sur un substrat de silicium agencé dans un système de traitement, et former une pluralité de micro-DEL rouges à base d'AllnGaP sur le substrat de silicium. Dans un autre mode de réalisation, l'invention concerne un dispositif qui comprend un substrat de silicium, une pluralité de micro-DEL bleues à base de GaN disposées sur le substrat de silicium, une pluralité de micro-DEL vertes à base de GaN disposées sur le substrat de silicium, et une pluralité de micro-DEL rouges à base d'AllnGaP disposées sur le substrat de silicium. Dans un autre mode de réalisation, l'invention concerne un support informatique non transitoire stockant des instructions qui, lorsqu'elles sont exécutées par un processeur d'un système, réalisent des opérations de formation de micro-DEL.
PCT/US2020/041515 2019-07-28 2020-07-10 Micro-del et procédé de fabrication de micro-del Ceased WO2021021415A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962879479P 2019-07-28 2019-07-28
US62/879,479 2019-07-28
US201962900058P 2019-09-13 2019-09-13
US62/900,058 2019-09-13

Publications (1)

Publication Number Publication Date
WO2021021415A1 true WO2021021415A1 (fr) 2021-02-04

Family

ID=74230535

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2020/041515 Ceased WO2021021415A1 (fr) 2019-07-28 2020-07-10 Micro-del et procédé de fabrication de micro-del

Country Status (2)

Country Link
TW (1) TW202107674A (fr)
WO (1) WO2021021415A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4080575A1 (fr) * 2021-04-22 2022-10-26 Epinovatech AB Procédé pour former une matrice d'éléments dels de différentes couleurs
US12068726B2 (en) 2020-02-14 2024-08-20 Epinovatech Ab Monolithic microwave integrated circuit front-end module
US12355442B2 (en) 2020-03-13 2025-07-08 Epinovatech Ab Field-programmable gate array device
US12382656B2 (en) 2018-04-22 2025-08-05 Epinovatech Ab Reinforced thin-film device
US12395027B2 (en) 2020-05-07 2025-08-19 Epinovatech Ab Induction machine
US12456734B2 (en) 2020-01-24 2025-10-28 Epinovatech Ab Solid-state battery layer structure and method for producing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5211352B2 (ja) * 2008-10-17 2013-06-12 国立大学法人北海道大学 半導体発光素子アレー、およびその製造方法
WO2014204921A1 (fr) * 2013-06-18 2014-12-24 Glo-Usa, Inc. Retrait de structures semi-conductrices en 3d par gravure sèche
US20170092485A1 (en) * 2012-05-04 2017-03-30 Stc.Unm Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
US20170301825A1 (en) * 2013-06-07 2017-10-19 Glo Ab Multicolor led and method of fabricating thereof
US20190214529A1 (en) * 2016-09-30 2019-07-11 Intel Corporation High performance light emitting diode and monolithic multi-color pixel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5211352B2 (ja) * 2008-10-17 2013-06-12 国立大学法人北海道大学 半導体発光素子アレー、およびその製造方法
US20170092485A1 (en) * 2012-05-04 2017-03-30 Stc.Unm Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
US20170301825A1 (en) * 2013-06-07 2017-10-19 Glo Ab Multicolor led and method of fabricating thereof
WO2014204921A1 (fr) * 2013-06-18 2014-12-24 Glo-Usa, Inc. Retrait de structures semi-conductrices en 3d par gravure sèche
US20190214529A1 (en) * 2016-09-30 2019-07-11 Intel Corporation High performance light emitting diode and monolithic multi-color pixel

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12382656B2 (en) 2018-04-22 2025-08-05 Epinovatech Ab Reinforced thin-film device
US12456734B2 (en) 2020-01-24 2025-10-28 Epinovatech Ab Solid-state battery layer structure and method for producing the same
US12068726B2 (en) 2020-02-14 2024-08-20 Epinovatech Ab Monolithic microwave integrated circuit front-end module
US12355442B2 (en) 2020-03-13 2025-07-08 Epinovatech Ab Field-programmable gate array device
US12395027B2 (en) 2020-05-07 2025-08-19 Epinovatech Ab Induction machine
EP4080575A1 (fr) * 2021-04-22 2022-10-26 Epinovatech AB Procédé pour former une matrice d'éléments dels de différentes couleurs
WO2022223580A1 (fr) * 2021-04-22 2022-10-27 Epinovatech Ab Procédé de formation d'une matrice d'éléments del de couleurs différentes
JP2024515361A (ja) * 2021-04-22 2024-04-09 エピノバテック、アクチボラグ 異なる色のｌｅｄ素子の製造
JP7735427B2 (ja) 2021-04-22 2025-09-08 エピノバテック、アクチボラグ 異なる色のｌｅｄ素子の製造

Also Published As

Publication number Publication date
TW202107674A (zh) 2021-02-16

Similar Documents

Publication Publication Date Title
WO2021021415A1 (fr) Micro-del et procédé de fabrication de micro-del
US10586829B2 (en) Full-color monolithic micro-LED pixels
JP7154133B2 (ja) 異なる色のｌｅｄを含むモノリシックマルチカラー直視型ディスプレイおよびそれを製造する方法
US8492185B1 (en) Large area nonpolar or semipolar gallium and nitrogen containing substrate and resulting devices
JP4092927B2 (ja) Ｉｉｉ族窒化物系化合物半導体、ｉｉｉ族窒化物系化合物半導体素子及びｉｉｉ族窒化物系化合物半導体基板の製造方法
JP4903189B2 (ja) 半極性窒化物単結晶薄膜の成長方法及びこれを用いた窒化物半導体発光素子の製造方法
EP2389693B1 (fr) Dispositif de diode électroluminescente et son procédé de fabrication
US9660135B2 (en) Enhanced performance active pixel array and epitaxial growth method for achieving the same
CN101752487A (zh) 半导体器件制造方法
JP2023519983A (ja) Ｌｅｄ前駆体
US20160380153A1 (en) Substrate, method of preparing the same, and light-emitting diode using the substrate
US8501597B2 (en) Method for fabricating group III-nitride semiconductor
TWI755047B (zh) 併入應變鬆弛結構的ｌｅｄ前驅物
JP2018536618A (ja) 結晶基板上で半極性窒化層を得る方法
US20190058087A1 (en) Light emitting diodes
CN115552566B (zh) Ⅲ族氮化物结构及其制作方法
CN115461841B (zh) Ⅲ族氮化物结构及其制作方法
US10636882B2 (en) Method for forming a semiconductor structure and a semiconductor structure manufactured thereof
US11201263B2 (en) Surface roughening method for light emitting device and light emitting device
WO2022077254A1 (fr) Procédé de fabrication d'une structure de del miniature
US11011376B2 (en) Method of manufacturing semiconductor structure with an epitaxial layer
US20210210656A1 (en) Method for micro-led epitaxial wafer manufacturing and micro-led epitaxial wafer
US12057311B2 (en) Method for manufacturing a semiconductor device using a patterned dielectric mask and semiconductor device
KR101647303B1 (ko) 기판, 이를 제조하는 방법 및 이를 이용하는 발광 다이오드
KR101636702B1 (ko) 기판, 이를 제조하는 방법 및 이를 이용하는 발광 다이오드

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20846694

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20846694

Country of ref document: EP

Kind code of ref document: A1