WO2020238306A1 - Dc-ac inverter protection circuit for lithium battery and energy storage device - Google Patents

Abstract

The present application discloses a DC-AC inverter protection circuit for a lithium battery and an energy storage device. The inverter protection circuit comprises a switch control circuit, a pulse width modulation integrated circuit, a compensation resistor, a compensation capacitor, a coupler receiving end, a bypass capacitor, a timing resistor, a timing capacitor and a pull-up resistor. The pulse width modulation integrated circuit comprises a power supply pin, a first output pin, a second output pin, a non-inverting input pin, an inverting input pin, a compensation pin, a timing resistor pin, a timing capacitor pin, a reference voltage pin, an oscillator, an error amplifier and a comparator. The energy storage device comprises the inverter protection circuit. The present application reduces the peak-to-peak current of a lithium battery, so that the lithium battery is able to work within a rated charging and discharging rate.

Description

Lithium battery DC-AC inverter protection circuit and energy storage equipment Technical field

This application relates to the technical field of lithium batteries, in particular to a lithium battery DC-AC (direct current-alternating current) inverter protection circuit and energy storage equipment.

Background technique

With the promotion of new energy, energy storage equipment that uses lithium batteries for inverter has also been widely used. Generally speaking, the charge and discharge rate of lithium batteries is only 1C or 2C. During the inversion process, the charging and discharging rate of the lithium battery exceeding 1C or 2C will greatly reduce the working life of the lithium battery, and will cause the battery to overheat, and there is a risk of fire.

The disclosure of the above background technical content is only used to assist the understanding of the inventive concept and technical solution of this application. It does not necessarily belong to the prior art of this application. In the absence of clear evidence that the above content has been disclosed on the filing date of this application Below, the aforementioned background technology should not be used to evaluate the novelty and inventive step of this application.

Summary of the invention

The application provides a lithium battery DC-AC inverter protection circuit and energy storage device, which can reduce the peak-to-peak current of the lithium battery, so that the lithium battery can work within a rated charge and discharge rate.

In the first aspect, this application also provides a lithium battery DC-AC inverter protection circuit, including a switch control circuit, pulse width modulation integrated circuit, compensation resistor, compensation capacitor, coupler receiver, bypass capacitor, timing resistor, timing Capacitors and pull-up resistors;

The pulse width modulation integrated circuit includes a power supply pin, a first output pin, a second output pin, a non-inverting input pin, an inverting input pin, a compensation pin, a timing resistor pin, a timing capacitor pin, and a reference Voltage pin, oscillator, error amplifier and comparator;

The switch control circuit is connected to the power supply pin;

The first output pin and the second output pin are used to output signals to control a boost MOS tube in a lithium battery DC-AC inverter circuit;

One end of the compensation capacitor is connected to the compensation pin, and the other end of the compensation capacitor is grounded; both ends of the compensation resistor are respectively connected to the compensation pin and the inverting input pin;

The receiving end of the coupler is used in conjunction with the transmitting end of the coupler in the lithium battery DC-AC inverter circuit; the collector of the receiving end of the coupler is connected to the in-phase input pin, and the coupler receives The emitter of the terminal is grounded, and the collector of the receiving terminal of the coupler is also connected to the reference voltage pin through the pull-up resistor;

Two ends of the bypass capacitor are respectively connected to the collector and the emitter of the receiving end of the coupler;

One end of the timing resistor is connected to the timing resistor pin, and the other end of the timing resistor is grounded; one end of the timing capacitor is connected to the timing capacitor pin, and the other end of the timing capacitor is grounded;

The timing resistor pin and the timing capacitor pin are connected to the oscillator; the oscillator is connected to the comparator to input a triangular wave signal to the comparator; the in-phase input pin and the reverse The phase input pins are respectively connected with two input terminals of the error amplifier; the output terminal of the error amplifier and the compensation pin are commonly connected to the comparator to input a signal to the comparator.

In some preferred embodiments, the switch control circuit includes a first triode, a second triode, a first resistor, and a second resistor;

The emitter of the first triode and one end of the first resistor are used to connect to the positive electrode of the lithium battery; the collector of the first triode is connected to the power supply pin; The base of a triode is connected to the collector of the second triode through the second resistor; the other end of the first resistor is connected to the base of the first triode and the first triode. Between two resistors;

The base of the second triode is used to control the inverter output; the emitter of the second triode is grounded.

In some preferred embodiments, the second triode is an NPN type triode.

In some preferred embodiments, the receiving end of the coupler is an optical coupler receiving end.

In some preferred embodiments, it further includes a first filter capacitor, one end of the first filter capacitor is connected to the power supply pin, and the other end of the first filter capacitor is grounded.

In a second aspect, the present application provides an energy storage device including the above-mentioned lithium battery DC-AC inverter protection circuit.

In some preferred embodiments, it further includes a driving circuit of a MOS transistor bridge circuit; the MOS transistor bridge circuit includes at least one half bridge, and the half bridge includes two MOS transistors;

The drive circuit includes a single-chip microcomputer, a half-bridge drive circuit, a gate circuit, a bleeder circuit, and a discharge circuit; the half-bridge drive circuit includes a drive chip with dead time control;

The single-chip microcomputer can generate at least one set of complementary sinusoidal pulse width modulation driving signals, and the single-chip microcomputer can set the dead time of the sinusoidal pulse width modulation driving signals;

The half-bridge drive circuit can amplify and convert the set of complementary sinusoidal pulse width modulation drive signals;

The gate circuit can transmit the signal sent by the half-bridge driving circuit to the MOS tube to drive the MOS tube;

The bleeder circuit is connected to the gate and the source of the MOS tube for discharging the voltage between the gate and the source when the MOS tube is turned off;

The discharge circuit is connected to the gate and the source of the MOS tube, and is used for discharging the capacitance between the gate and the source when the MOS tube is turned off.

In some preferred embodiments, the gate circuit includes a drive resistor and a diode, one end of the drive resistor is connected to an output pin of the drive chip, and one end of the diode is connected to the other end of the drive resistor. Connected, the other end of the diode is connected to the gate of the MOS tube; the bleeder circuit includes a bleeder resistor and a triode, the base of the triode is connected between the driving resistor and the diode, the triode The emitter is connected to one end of the bleeder resistor, the collector of the triode is connected to the source of the MOS tube, and the other end of the bleeder resistor is connected to the gate of the MOS tube; the discharge The circuit includes a discharge resistor connected between the gate and the source of the MOS tube.

In some preferred embodiments, the two MOS transistors are a high-end MOS transistor and a low-end MOS transistor respectively;

The half-bridge drive circuit also includes a fast recovery diode and a bootstrap capacitor;

One end of the fast recovery diode is connected to the start voltage pin of the driving chip, and the other end of the fast recovery diode is used for connecting a voltage to provide a high-side driving voltage;

One end of the bootstrap capacitor is connected to the start-up voltage pin of the driver chip, and the other end of the bootstrap capacitor is connected to the source of the high-side MOS transistor, thereby raising the power supply voltage to drive the high-side MOS transistor .

In some preferred embodiments, the MOS transistor bridge circuit includes two half-bridges, and the two half-bridges form an H-bridge; the voltage access pin and the ground pin of the drive chip are connected to Input capacitor for energy storage and filtering.

Compared with the prior art, the beneficial effects of this application are:

This application can reduce the peak-to-peak current of the lithium battery, so that the lithium battery can work within the rated charge and discharge rate, thereby protecting the lithium battery and prolonging the service life of the lithium battery.

Description of the drawings

1 is a schematic diagram of the circuit structure of a lithium battery DC-AC inverter protection circuit according to the first embodiment of the application;

2 is a schematic diagram of the internal circuit structure of the pulse width modulation integrated circuit according to the first embodiment of the application;

3 is a schematic diagram of the circuit structure of a lithium battery DC-AC inverter circuit 400 according to the first embodiment of the application;

4 is a schematic diagram of the structure of the energy storage device according to the second embodiment of the application;

FIG. 5 schematically shows a part of the circuit structure of the MOS transistor bridge circuit of the second embodiment of the present application;

FIG. 6 schematically shows the circuit structure of the single-chip microcomputer in the second embodiment of the present application;

FIG. 7 schematically shows the circuit structure of the half-bridge drive circuit, the gate circuit, the bleeder circuit, the discharge circuit and the H-bridge of the second embodiment of the present application;

FIG. 8 is a schematic flowchart of the driving method of the MOS transistor bridge circuit according to the second embodiment of the application.

Detailed ways

In order to make the technical problems, technical solutions, and beneficial effects to be solved by the embodiments of the present application clearer, the following further describes the present application in detail with reference to FIGS. 1 to 8 and embodiments. It should be understood that the specific embodiments described here are only used to explain the application, and not used to limit the application.

It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top" The orientation or positional relationship indicated by "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply The device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the application.

In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present application, “a plurality of” means two or more than two, unless otherwise specifically defined.

First embodiment

This embodiment provides a lithium battery DC-AC inverter protection circuit 300. 1 and 3, the inverter protection circuit 300 is used to protect the boost MOS tube in the lithium battery DC-AC inverter circuit 400.

1, the inverter protection circuit 300 includes a switch control circuit 31, a pulse width modulation integrated circuit U5, a compensation resistor R43, a compensation capacitor C4, a coupler receiving terminal U4B, a bypass capacitor C29, a timing resistor R45, a timing capacitor C32, and upper Pull resistor R41.

The pulse width modulation integrated circuit U5 is also called a PWM (Pulse Width Modulation, pulse width modulation) IC chip. 1 and 2, the pulse width modulation integrated circuit U5 includes a power supply pin Vcc, a power supply pin Vc, a first output pin OutA, a second output pin OutB, a non-inverting input pin In+, and an inverting input pin In -Compensation pin Comp, timing resistor pin RT, timing capacitor pin CT, reference voltage pin Vref, oscillator O1, error amplifier OP32 and comparator U33. In this embodiment, the pulse width modulation integrated circuit U5 is an existing pulse width modulation integrated circuit.

1, the switch control circuit 31 is used to provide power to the pulse width modulation integrated circuit U5, and can control the turning on and off of the inverter circuit 400. The switch control circuit 31 is connected to the power supply pin Vcc and the power supply pin Vc.

Referring to FIG. 1, the first output pin OutA and the second output pin OutB are used to output signals to control the boost MOS transistor in the lithium battery DC-AC inverter circuit 400. In this embodiment, the first output pin OutA and the second output pin OutB are respectively connected to the terminal Gate1-PP and the terminal Gate2-PP; referring to FIG. 3, the terminal Gate1-PP is connected to the boost MOS transistors Q6 and Q6 and The boost MOS tube Q7 is connected; the terminal Gate2-PP is connected with the boost MOS tube Q8 and the boost MOS tube Q9.

One end of the compensation capacitor C4 is connected to the compensation pin Comp, and the other end of the compensation capacitor C4 is grounded. Referring to FIG. 2, the output terminal of the error amplifier OP32 built in the pulse width modulation integrated circuit U5 is connected to the compensation pin Comp, so the compensation capacitor C4 is actually the compensation capacitor at the output terminal of the error amplifier OP32. The compensation capacitor C4 is grounded, which is mainly used to ensure that the voltage of the compensation pin Comp is stable and form a pole control.

Referring to Figure 1, both ends of the compensation resistor R43 are respectively connected to the compensation pin Comp and the inverting input pin In-. The inverting input pin In- is used to input a signal to the error amplifier OP32. Therefore, the compensation resistor R43 is the compensation resistor at the input end of the error amplifier OP32.

Referring to FIG. 3, the secondary circuit of the transformer of the inverter circuit 400 is provided with a coupler transmitting terminal U4A. The coupler receiving end U4B is used in conjunction with the coupler transmitting end U4A. In this embodiment, the coupler is an optical coupler; therefore, the coupler transmitting end U4A is the optical coupler transmitting end, and the coupler receiving end U4B is the optical coupler receiving end; the coupler transmitting end U4A is provided with a light-emitting diode, After the secondary circuit of the transformer works, the current flowing through the light-emitting diode determines the conduction status of the CE pole of the receiver U4B of the coupler in the form of optical coupling, that is, the current. In other embodiments, the coupler is a magnetic isolator.

Referring to Figure 1, the collector of the receiver U4B of the coupler is connected to the in-phase input pin In+. The emitter of the receiver U4B of the coupler is grounded. The collector of the receiving end U4B of the coupler is also connected to the reference voltage pin Vref through a pull-up resistor R41. The reference voltage pin Vref can output a certain voltage.

The two ends of the bypass capacitor C29 are respectively connected to the collector and the emitter of the receiver U4B of the coupler.

One end of the timing resistor R45 is connected to the timing resistor pin RT, and the other end of the timing resistor R45 is grounded.

One end of the timing capacitor C32 is connected to the timing capacitor pin CT, and the other end of the timing capacitor C32 is grounded. In this embodiment, the timing capacitor C32 is charged by a current source built into the pulse width modulation integrated circuit U5.

Referring to Figure 2, the timing resistor pin RT and the timing capacitor pin CT are connected to the oscillator O1. The oscillator O1 is connected to the comparator U33 to input a triangular wave signal to the comparator U33. The capacitance of the timing capacitor C32 determines the slope of the triangle wave. If the timing capacitor C32 has a large capacitance, the charging speed will be slower to reach the maximum value; otherwise, it will be faster. The timing resistor R45 controls the voltage of the timing capacitor C32 through a built-in switch to discharge; the high resistance of the timing resistor R45 results in slow discharge.

Referring to Figure 2, the non-inverting input pin In+ and the inverting input pin In- are respectively connected to two input ends of the error amplifier OP32. The output terminal of the error amplifier OP32 and the compensation pin Comp are connected to the comparator U33 to input a signal to the comparator U33. The comparator U33 is used to generate the PWM signal.

Referring to FIG. 1, the switch control circuit 31 operates to provide power to the pulse width modulation integrated circuit U5, so that the pulse width modulation integrated circuit U5 operates. The pulse width modulation integrated circuit U5 generates a reference voltage and outputs it to the pull-up resistor R41 through the reference voltage pin Vref, so as to provide the coupler receiving terminal U4B with a voltage that generates a C-E pole current. After the inverter circuit 400 works, the light-emitting diode at the transmitting end U4A of the coupler is turned on to emit light, and the receiving end U4B of the coupler receives the light and generates a photocurrent. The bypass capacitor C29 is a bypass filter capacitor, which can smooth the C-E pole voltage at the receiving end U4B of the coupler and reduce system instability caused by spike interference. The collector of the receiver U4B of the coupler is connected to the non-inverting input pin In+, which is also connected to the positive input of the error amplifier OP32, so the signal fed back by the optocoupler is compared with the negative input of the error amplifier OP32, and the error amplifier OP32 outputs the signal . The output signal is fed back to the compensation pin Comp, and then transmitted to the inverting input pin In- through the compensation resistor R43, that is, output to the inverting input terminal of the error amplifier OP32, forming a negative feedback. The output signal of the error amplifier OP32 is input to the comparator U33 and compared with the triangle wave signal input from the oscillator O1 to the comparator U33, thereby changing the duty cycle of the PWM driving signal and controlling the boost MOS tube of the primary circuit of the transformer , And finally adjust the output voltage of the transformer secondary. Specifically, if the output voltage of the transformer secondary is lower than the preset voltage, the output signal of the error amplifier OP32 becomes larger, which increases the duty cycle of the PWM drive signal, which in turn increases the output voltage of the transformer secondary; otherwise, the error The output signal of the amplifier OP32 is reduced, which reduces the output voltage of the transformer secondary.

The secondary circuit of the transformer generates a feedback signal through the transmitter U4A of the coupler, and the feedback signal determines the size of the in-phase input signal of the in-phase input pin In+ through the optocoupler isolation.

In a conventional application example, the collector of the coupler receiving end U4B is connected to the compensation pin Comp, so that the isolated feedback signal directly determines the duty cycle of the PWM drive signal or whether to turn off the PWM drive signal. This will make the charge and discharge rate of the lithium battery relatively large.

Take a certain energy storage device as an example. The parameters of the energy storage device are: 500WH, 4 strings, 17 parallel, 68 lithium batteries, charge and discharge rate 1C (36AH), lithium battery voltage 12.4V-16.8VDC, inverter output voltage 230V/50Hz, inverter output The power is 500W.

In a conventional application example, after testing, the battery peak-to-peak current of this certain energy storage device is 70.5A, which greatly exceeds the charge and discharge rate of 1C (36AH) of the lithium battery. Using the lithium battery DC-AC inverter protection circuit 300 of this embodiment, after testing, the battery peak-to-peak current of this certain energy storage device is 25.5A, which is about 60% lower than the conventional application example, which can meet the requirements of lithium battery The charge and discharge rate is 1C (36AH). For a conventional application example, in a certain test, the inverter output AC voltage is 233.2V and the power is 522.8W; for the lithium battery DC-AC inverter protection circuit 300 of this embodiment, in a certain test, The AC voltage of the variable output is 231.4V, and the power is 517.6W. It can be seen that the output power of the energy storage device using the lithium battery DC-AC inverter protection circuit 300 of this embodiment can meet the specification greater than 230VAC/500W.

According to the foregoing, this embodiment can reduce the peak-to-peak current of the lithium battery, so that the lithium battery can work within the rated charge and discharge rate, thereby protecting the lithium battery and prolonging the service life of the lithium battery.

This embodiment will be further described below.

1, the switch control circuit 31 includes a first transistor Q10, a second transistor Q11, a first resistor R40, and a second resistor R42.

The emitter of the first triode Q10 is connected to one end of the first resistor R40, and the emitter of the first triode Q10 is also connected to the positive electrode Vbat of the lithium battery. The collector of the first transistor Q10 is connected to the power supply pin Vcc and the power supply pin Vc. The base of the first triode Q10 is connected to the collector of the second triode Q11 through a second resistor R42. The other end of the first resistor R40 is connected between the base of the first transistor Q10 and the second resistor R42.

The base of the second transistor Q11 is connected to the I/O (input/output) output port of the micro-control unit for controlling the inverter output. The emitter of the second transistor Q11 is grounded.

The first transistor Q10 is a PNP power transistor. The first resistor R40 and the second resistor R42 serve as bias conditions for turning on the second transistor Q11.

The second transistor Q11 is an NPN transistor with a built-in bias resistor.

When the emitter of the first transistor Q10 is connected to the battery voltage, the second transistor Q11 has not reached saturation conduction; the base of the first transistor Q10 is infinitely close to the emitter of the first transistor Q10, so The first transistor Q10 is in an off state. The pulse width modulation integrated circuit U5 will not work, and the inverter circuit of the energy storage device will not output voltage.

When a voltage of +3.3V is applied to the B-E poles of the second transistor Q11, the C-E poles of the second transistor Q11 are saturated and turned on. The first resistor R40 and the second resistor R42 divide the voltage, so that the E-B pole of the second transistor Q11 is in forward conduction, and the E-C pole of the first transistor Q10 is in saturation conduction. The pulse width modulation integrated circuit U5 reaches the working voltage and starts to output the PWM signal to drive the push-pull boost MOS tube in the inverter circuit 400. Finally, the inverter circuit 400 outputs an AC voltage.

Referring to FIG. 1, the inverter protection circuit 300 of this embodiment further includes a first filter capacitor C30. One end of the first filter capacitor C30 is connected to the power supply pin Vcc and the power supply pin Vc, and the other end of the first filter capacitor C30 is grounded. The first filter capacitor C30 is the filter capacitor of the power supply input pin Vcc of the pulse width modulation integrated circuit U5, which is mainly used to filter the input interference signal and smooth the VCC (the power supply voltage of the circuit).

1, the inverter protection circuit 300 of this embodiment further includes a shutdown resistor R44, a dead time control resistor R46, and a soft-start external capacitor C31. The pulse width modulation integrated circuit U5 also includes a shutdown pin Shuntdown, a dead time control pin Dis, and a soft start pin SS.

Referring to Figure 1, one end of the shutdown resistor R44 is connected to the shutdown pin Shuntdown, and the other end is grounded. The turn-off resistor R44 is used to turn off the drive signal output of the pulse width modulation integrated circuit U5 when the abnormal operation of the inverter circuit is detected.

Referring to Fig. 1, both ends of the dead time control resistor R46 are respectively connected to the dead time pin Dis and the timing capacitor pin CT. By changing the dead time control resistor R46, the interval at which the two PWM signals driving the push-pull boost MOS tube are high at the same time can be set. The dead time control resistor R46 has a large resistance value, and the dead time will be large, which will eventually cause the energy transmitted by the inverter to decrease.

Referring to Figure 1, one end of the soft-start external capacitor C31 is connected to the soft-start pin SS, and the other end is grounded. When VCC (the supply voltage of the circuit) reaches the starting voltage, the reference voltage of the pulse width modulation integrated circuit U5 will provide a constant current, which charges the soft-start external capacitor C31. Until the soft-start external capacitor C31 voltage reaches the set value. The pulse width modulation integrated circuit U5 will output a PWM signal to drive the push-pull boost MOS tube in the inverter circuit 400 to turn on and off.

The setting of timing resistor R45 and timing capacitor C32 determines the switching frequency and duty cycle. By changing the resistance of the timing resistor R45 and the capacitance of the timing capacitor C32, the PWM switching frequency and the PWM duty cycle can be changed to determine the maximum power value output by the inverter circuit.

The current of the CE pole of the receiver U4B of the coupler determines that the forward input voltage of the error amplifier OP32 becomes higher or lower, which affects the duty cycle of the PWM signal, and ultimately affects the increase or change of the bus voltage after the inverter boost. low.

1, the pulse width modulation integrated circuit U5 also includes a synchronization signal input pin SYNC, a synchronization pulse output pin OSC, and a ground pin GND.

Second embodiment

Referring to FIG. 4, this embodiment provides an energy storage device including an inverter protection circuit 300, an inverter circuit 400 and a MOS tube bridge circuit 100. The inverter protection circuit 300 is connected to the inverter circuit 400 to protect the inverter circuit 400. The inverter circuit 400 and the MOS tube bridge circuit 100 are used to supply power to the MOS tube bridge circuit 100.

Referring to FIG. 5, the MOS tube bridge circuit 100 includes two half bridges and a driving circuit 200, and the two half bridges form an H bridge. The driving circuit 200 is used to drive the H bridge so that the H bridge controls the load. The line where the H bridge is located is the H bridge power line. In other embodiments, the MOS transistor bridge circuit includes a half bridge.

Each half-bridge includes two MOS transistors, namely an upper-arm MOS transistor and a lower-arm MOS transistor. For the H bridge, it includes the left upper bridge arm MOS transistor Q12, the left lower bridge arm MOS transistor Q14, the right upper bridge arm MOS transistor Q13, and the right lower arm MOS transistor Q15. Among them, the line where the upper left bridge arm MOS transistor Q12 is located and the line where the lower left bridge arm MOS transistor Q14 is located are both high-frequency MOS transistor lines, and the line where the upper right bridge arm MOS transistor Q13 is located and the line where the lower right bridge arm MOS transistor Q15 is located are both It is a low-frequency MOS tube circuit.

The driving circuit 200 of this embodiment includes a single-chip microcomputer 1, two half-bridge driving circuits 2, four gate circuits 3, four bleeder circuits 4, and four discharge circuits 5. One half-bridge driving circuit 2 drives the upper left arm MOS transistor Q12 and the lower left arm MOS transistor Q14, and the other half-bridge driving circuit 2 drives the upper right arm MOS transistor Q13 and the lower right arm MOS transistor Q15. The left upper bridge arm MOS tube Q12, the left lower bridge arm MOS tube Q14, the right upper bridge arm MOS tube Q13, and the right lower arm MOS tube Q15 correspond to a bleeder circuit 4 and a discharge circuit 5, respectively.

The single-chip microcomputer 1 can generate two complementary sinusoidal pulse width modulation (Sinusoidal Pulse Width Modulation, SPWM) driving signals. In other words, the single-chip microcomputer 1 can output four driving signals. A group of complementary sinusoidal pulse width modulation drive signals are used to make the left upper bridge arm MOS transistor Q12 and the left lower bridge arm MOS transistor Q14 turn on and off complementary, that is, one turns on and the other turns off. Another set of complementary sinusoidal pulse width modulation drive signals is used to turn on and off the right upper MOS transistor Q13 and the right lower MOS transistor Q15, that is, one is turned on and the other is turned off. The single chip microcomputer 1 can set the dead time of each sine pulse width modulation driving signal. A group of complementary sinusoidal pulse width modulation driving signals generated by the single-chip microcomputer 1 is transmitted to one half-bridge driving circuit 2, and the other group is transmitted to another half-bridge driving circuit 2.

Each half-bridge driving circuit 2 includes a driving chip. In this embodiment, referring to FIG. 7, the first half-bridge driving circuit 2 includes a driver chip U7, and the second half-bridge driving circuit 2 includes a driver chip U17. Among them, the driving chip is controlled by the dead time, and the dead time generated by the driving chip can be superimposed on the driving signal with the dead time generated by the single-chip microcomputer. The half-bridge driving circuit 2 can amplify and convert a group of complementary sinusoidal pulse width modulation driving signals; among them, conversion mainly refers to reverse processing of two driving signals and inverting the two driving signals. The amplified and converted two sinusoidal pulse width modulation drive signals are respectively delivered to the two gate circuits 3. In this embodiment, the driving chip is an integrated half-bridge driving amplifier circuit, and the dead time of the driving chip is 450 nS.

Each gate circuit 3 can transmit the signal from the half-bridge driving circuit 2 to the MOS tube to drive the MOS tube. Specifically, referring to FIG. 5, one end of the first gate circuit 3 is connected to the high-side output pin DRV_Hi of the first half-bridge driving circuit 2, and the other end is connected to the gate of the left upper bridge MOS transistor Q12; One end of the gate circuit 3 is connected to the low-end output pin DRV_Lo of the first half-bridge drive circuit 2, and the other end is connected to the gate of the left lower bridge arm MOS transistor Q14; one end of the third gate circuit 3 It is connected to the high-end output pin DRV_Hi of the second half-bridge drive circuit 2, and the other end is connected to the gate of the upper right-side MOS transistor Q13; one end of the fourth gate circuit 3 is connected to the second half-bridge drive circuit The low-end output pin DRV_Lo of 2 is connected, and the other end is connected to the gate of the lower right-side MOS transistor Q15.

A bleeder circuit 4 is connected between the gate and the source of each MOS tube. The bleeder circuit 4 is used to discharge the voltage Vgs between the gate and the source when the MOS tube is turned off.

A discharge circuit 5 is also connected between the gate and the source of each MOS tube. The discharge circuit 5 is used for discharging the capacitance Cgs between the gate and the source when the MOS tube is turned off.

This embodiment will be described in conjunction with the driving method of the MOS transistor bridge circuit of this embodiment. Referring to Fig. 8, the driving method of this embodiment includes steps S1 to S5.

Step S1: Generate two complementary sinusoidal pulse width modulation drive signals, and set the dead time of the sinusoidal pulse width modulation drive signal. In this embodiment, step S1 is completed by the single chip microcomputer 1 and the sinusoidal pulse width modulation driving signal is sent to the two half-bridge driving circuits 2.

Step S2: Amplify and convert a group of complementary sinusoidal pulse width modulation drive signals. In this embodiment, after each half-bridge drive circuit 2 receives a set of complementary sinusoidal pulse width modulation drive signals, it amplifies and converts the signals, and then sends the two signals to the two gate circuits 3 respectively.

Step S3, transmitting the amplified and converted signal to the MOS tube to drive the MOS tube. In this embodiment, step S3 is completed by the gate circuit 3.

Step S4, discharging the voltage between the gate and the source when the MOS tube is turned off. In this embodiment, step S4 is completed by the bleeder circuit 4.

Step S5: Discharging the capacitance between the gate and the source when the MOS tube is turned off. In this embodiment, step S5 is completed by the discharge circuit 5.

According to the above, the single-chip microcomputer 1 adopts a complementary upper and lower tube driving mode, which can set the dead time of four output driving signals, and the half-bridge driving circuit 2 has dead time control. When the MOS tube is turned off, the bleeder circuit 4 discharges the voltage Vgs between the gate and the source of the MOS tube, and the discharge circuit 5 discharges the capacitance Cgs between the gate and the source of the MOS tube. In this way, the MOS transistors can quickly respond to complementary drive signals, realize the complementary turn-on and turn-off of the upper and lower transistors, and reduce the risk of direct conduction of the upper and lower MOS transistors of the H bridge under abnormal conditions.

Referring to FIG. 7, the first gate circuit 3 includes a driving resistor R112 and a diode D18. One end of the driving resistor R112 is connected to the high-end output pin DRV_Hi of the driving chip U7. One end of the diode D18 is connected to the other end of the driving resistor R112, and the other end of the diode D18 is connected to the gate of the MOS transistor Q12.

The first bleeder circuit 4 includes a bleeder resistor R49 and a transistor Q17. In this embodiment, the transistor Q17 is a PNP type transistor. The base of the transistor Q17 is connected between the driving resistor R112 and the diode D18, the emitter of the transistor Q17 is connected to one end of the bleeder resistor R49, the collector of the transistor Q17 is connected to the source of the MOS transistor Q12, and the other of the bleeder resistor R49 One end is connected to the gate of the MOS transistor Q12.

The first discharge circuit 5 includes a discharge resistor R114 connected between the gate and the source of the MOS transistor Q12.

Referring to FIG. 7, the driving signal is output from the half-bridge driving circuit 2, and enters the gate of the MOS transistor Q12 through the driving resistor R112 and the diode D18. Since the base of the transistor Q17 is connected between the driving resistor R112 and the diode D18, the driving signal will also enter the base of the transistor Q17. In order to switch the MOS transistor Q12 from the on state to the off state, the driving signal is converted from a high level to a low level, the gate of the MOS transistor Q12 is low, and the base of the transistor Q17 is also low. In this way, when the MOS transistor Q12 is turned off, the voltage Vgs between the gate and the source of the MOS transistor Q12 will be discharged through the emitter and collector of the bleeder resistors R49 and Q17. The capacitor Cgs will be discharged through the discharge resistor R114. One signal can trigger the MOS transistor Q12 to turn off, the discharge circuit 4 to discharge, and the discharge circuit 5 to discharge at almost the same time, so that the MOS transistor Q12 can be quickly and reliably turned off, and the driving circuit can also be simplified.

The second gate circuit 3, the second bleeder circuit 4, and the second discharge circuit 5 are similar, and a brief description is given here. The second gate circuit 3 includes a driving resistor R53 and a diode D21. One end of the driving resistor R53 is connected to the low-end output pin DRV_Lo of the driving chip U7. The second bleeder circuit 4 includes a bleeder resistor R117 and a transistor Q19. The second discharge circuit 5 includes a discharge resistor R119.

The third gate circuit 3, the third bleeder circuit 4, and the third discharge circuit 5 are similar, and a brief description is given here. The third gate circuit 3 includes a driving resistor R50 and a diode D19. One end of the driving resistor R50 is connected to the high-end output pin DRV_Hi of the driving chip U17. The third bleeder circuit 4 includes a bleeder resistor R113 and a transistor Q18. The third discharge circuit 5 includes a discharge resistor R115.

The fourth gate circuit 3, the fourth bleeder circuit 4, and the fourth discharge circuit 5 are similar, and a brief description is given here. The fourth gate circuit 3 includes a driving resistor R54 and a diode D22. One end of the driving resistor R54 is connected to the low-end output pin DRV_Lo of the driving chip U17. The fourth bleeder circuit 4 includes a bleeder resistor R120 and a transistor Q20. The fourth discharge circuit 5 includes a discharge resistor R122.

The upper left arm MOS tube Q12 and the upper right arm MOS tube Q13 are high-end MOS tubes. The left bottom MOS tube Q14 and the right bottom MOS tube Q15 are low-end MOS tubes. Each half-bridge driving circuit 2 also includes a fast recovery diode and a bootstrap capacitor.

The first half-bridge driving circuit 2 includes a fast recovery diode D17 and a bootstrap capacitor C33. One end of the fast recovery diode D17 is connected to the startup voltage pin Vboot of the driving chip 21, and the other end of the fast recovery diode D17 is used to connect the voltage +12VPRI to provide the high-side driving voltage. One end of the bootstrap capacitor C33 is connected to the startup voltage pin Vboot of the driver chip 21, and the other end of the bootstrap capacitor C33 is connected to the source of the high-side MOS transistor Q12. The bootstrap capacitor C33 uses the characteristic that the voltage across the capacitor cannot change suddenly. When a certain voltage is maintained at both ends of the capacitor, the negative terminal voltage of the capacitor is increased, and the positive terminal voltage remains at the original voltage difference of the negative terminal, which is equal to the voltage at the positive terminal by the negative terminal. When it is lifted up, the source potential of the upper left-side MOS transistor Q12 is raised to meet the withstand voltage between the gate and the source of the upper-side MOS transistor and normal drive. The bootstrap capacitor C33 is actually a positive feedback capacitor, used to increase the supply voltage to drive the high-side MOS transistor Q12.

The second half-bridge driving circuit 2 is similar, including fast recovery diode D20 and bootstrap capacitor C38.

An input capacitor C35 for energy storage and filtering is connected between the voltage access pin VCC of the first driving chip U7 and the ground pin GND. Between the voltage access pin VCC of the second drive chip U17 and the ground pin GND is connected an input capacitor C39 for energy storage and filtering. The input capacitor C35 and the input capacitor C39 are mainly used for energy storage and filtering.

The single-chip microcomputer 1 includes a micro-control unit U801, a DC bus current detection circuit, a clock signal generating circuit and a peripheral capacitor.

In this embodiment, the micro control unit U801 is a 32-bit control chip. The micro-control unit U801 and its surrounding circuits form a complementary drive signal generating circuit, and its main function is to send two sets of complementary sinusoidal pulse width modulation drive signals. The drive signals output by the terminals Gate1L_Inv and Gate1H_Inv of the microcontroller unit U801 drive the lower and upper MOS transistors of a half-bridge respectively, and the drive signals output by the terminals Gate2L_Inv and the terminal Gate2H_Inv drive the other half respectively. The lower arm MOS tube and the upper arm MOS tube of the bridge.

The micro control unit U801 can use a 20PIN MCU, which can reduce some peripheral circuits and reduce the area of the PCB.

Referring to Figure 6, the DC bus current detection circuit includes a comparator U819, a resistor R807, a resistor R809, a capacitor C805, a resistor R805, a capacitor C872, and a capacitor C875. The DC bus current detection circuit is connected to the micro-control unit U801, and is used to trigger the micro-control unit U801 to stop outputting the sinusoidal pulse width modulation drive signal when the output load exceeds the limit value, so that the SPWM drive is turned off. That is, if it is detected that the output load exceeds the limit value, the output of the sinusoidal pulse width modulation drive signal is stopped.

The clock signal generating circuit is connected with the micro control unit U801 to input a clock signal for calculation to the micro control unit U801. Referring to Fig. 6, the clock signal generating circuit is a circuit for generating the external clock signal of the micro-control unit U801, including crystal oscillator Y801, capacitor C819, capacitor C820 and resistor R815.

Referring to FIG. 6, the peripheral capacitors specifically include a capacitor C811, a capacitor C813, and a capacitor C812, which are used to supply power to the micro-control unit U801 and to filter interference noise, which can ensure the stable operation of the micro-control unit U801.

Resistor R810, capacitor C838 and resistor R816 are peripheral circuits that the micro-control unit U801 needs to configure for normal operation.

The terminal Vbus_Meas is used to connect the feedback weak current signal of the DC bus voltage. The resistor R811 and the capacitor C842 form an RC low-pass filter circuit.

The terminal Uac_FB_Inv is used to connect the AC output voltage feedback signal. Resistor R812 and capacitor C848 form an RC low-pass filter circuit.

Referring to Figure 7, when the DC high-voltage bus +360VPRI works normally, the working voltage +12VPRI required by the driving chip U7 and the driving chip U17 and the working voltage +3V3PRI required by the micro-control unit U801 will be generated through the step-down circuit. The clock calculated internally by the micro control unit U801 will be obtained through the external crystal oscillator Y801. The micro control unit U801 confirms that the SPWM drive signal is generated according to the detected weak feedback signal of the DC bus voltage and the voltage feedback signal of the AC output connected to the terminal Uac_FB_Inv.

A set of complementary sinusoidal pulse width modulation drive signals output by the terminal Gate1L_Inv and the terminal Gate1H_Inv are input to the low-end input pin IN_Lo and the high-end input pin IN_Hi of the driver chip U7. The driver chip U7 outputs signals for driving the lower left-side MOS transistor Q14 and the upper left-side MOS transistor Q12 through the low-side output pin DRV_Lo and the high-side output pin DRV_Hi.

A set of complementary sinusoidal pulse width modulation drive signals output by the terminal Gate2L_Inv and the terminal Gate2H_Inv are input to the low-end input pin IN_Lo and the high-end input pin IN_Hi of the driver chip U17. The driver chip U17 outputs signals for driving the lower right-side MOS transistor Q15 and the upper right-side MOS transistor Q13 through the low-side output pin DRV_Lo and the high-side output pin DRV_Hi.

Referring to Figure 6, there are multiple pins on the micro control unit U801, including pin VSS, pin BOOT0, pin PB7, pin PB6, pin PB5, pin PB4, pin PB3, pin PA15, pin Pin PA14, Pin PA13, Pin PA12, Pin PA11, Pin PA10, Pin PA9, Pin PA8, Pin VDD, Pin PB1, Pin PB0, Pin PA7, Pin PA6, Pin PA5 , Pin PA4, Pin PA3, Pin PA1, Pin PA0, Pin VDDA, Pin NRST, Pin OSC_OUT and Pin OSC_IN. Each pin is connected to the corresponding circuit. Among them, the pin OSC_OUT and the pin OSC_IN are connected, the pin PA6 is connected to the terminal Gate1H_Inv, the pin PB6 is connected to the terminal Gate1L_Inv, the pin PA8 is connected to the terminal Gate2H_Inv, and the pin PA7 is connected to the terminal Gate2L_Inv. Pin PA10 is connected to one end of resistor R808. The pin PA9 is connected to one end of the resistor R820.

Referring to Figure 7, the driver chip is also provided with pin IN_Lo, pin IN_Hi, and pin Bridge. The pins IN_Lo and IN_Hi of the driver chip U7 are respectively connected to the terminal Gate1L_Inv and the terminal Gate1H_Inv. The pins IN_Lo and IN_Hi of the driver chip U17 are respectively connected to the terminal Gate2L_Inv and the terminal Gate2H_Inv.

The third embodiment

This embodiment provides an energy storage device, including the above-mentioned driving circuit 200 and at least one half bridge.

The energy storage device of this embodiment is specifically a 500W portable energy storage new energy product, and the product specifications are:

500WH 4 series, 17 parallel, a total of 68 iron lithium 186501C (36AH) discharge lithium battery energy storage equipment, battery voltage 12.4V to 16.8VDC, inverter output voltage 230V/50Hz/500W;

The charging can meet the 12VDC charging of the car cigarette lighter, the 15VDC voltage charging of the adapter and the outdoor or indoor 10V to 25VDC solar panel charging;

The inverter output is pure sine wave output, which can meet the output of 100V to 230VAC, 50/60Hz.

Fourth embodiment

This embodiment provides an energy storage device, including a processor, a memory, and one or more programs, where one or more programs are stored in the memory and configured to be executed by the processor, and the one or more programs include Instructions for executing the above driving method.

The above content is a further detailed description of the application in combination with specific/preferred implementations, and it cannot be determined that the specific implementation of the application is limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, without departing from the concept of this application, they can also make several substitutions or modifications to the described implementations, and these substitutions or modifications should be regarded as It belongs to the protection scope of this application.

Claims (10)

A lithium battery DC-AC inverter protection circuit, which is characterized in that it includes a switch control circuit, a pulse width modulation integrated circuit, a compensation resistor, a compensation capacitor, a coupler receiving end, a bypass capacitor, a timing resistor, a timing capacitor and a pull-up resistance; The pulse width modulation integrated circuit includes a power supply pin, a first output pin, a second output pin, a non-inverting input pin, an inverting input pin, a compensation pin, a timing resistor pin, a timing capacitor pin, and a reference Voltage pin, oscillator, error amplifier and comparator; The switch control circuit is connected to the power supply pin; The first output pin and the second output pin are used for outputting signals to control a boost MOS tube in a lithium battery DC-AC inverter circuit; One end of the compensation capacitor is connected to the compensation pin, and the other end of the compensation capacitor is grounded; both ends of the compensation resistor are respectively connected to the compensation pin and the inverting input pin; The receiving end of the coupler is used in conjunction with the transmitting end of the coupler in the lithium battery DC-AC inverter circuit; the collector of the receiving end of the coupler is connected to the in-phase input pin, and the coupler receives The emitter of the terminal is grounded, and the collector of the receiving terminal of the coupler is also connected to the reference voltage pin through the pull-up resistor; Both ends of the bypass capacitor are respectively connected to the collector and the emitter of the receiving end of the coupler; One end of the timing resistor is connected to the timing resistor pin, and the other end of the timing resistor is grounded; one end of the timing capacitor is connected to the timing capacitor pin, and the other end of the timing capacitor is grounded; The timing resistor pin and the timing capacitor pin are connected to the oscillator; the oscillator is connected to the comparator to input a triangular wave signal to the comparator; the in-phase input pin and the inverter The phase input pins are respectively connected to the two input terminals of the error amplifier; the output terminal of the error amplifier and the compensation pin are commonly connected to the comparator to input a signal to the comparator. The lithium battery DC-AC inverter protection circuit according to claim 1, wherein the switch control circuit comprises a first triode, a second triode, a first resistor and a second resistor; The emitter of the first triode and one end of the first resistor are used to connect to the positive electrode of the lithium battery; the collector of the first triode is connected to the power supply pin; The base of a triode is connected to the collector of the second triode through the second resistor; the other end of the first resistor is connected to the base of the first triode and the second triode. Between two resistors; The base of the second triode is used to control the inverter output; the emitter of the second triode is grounded. The lithium battery DC-AC inverter protection circuit according to claim 2, wherein the second triode is an NPN type triode. The lithium battery DC-AC inverter protection circuit according to claim 1, wherein the receiving end of the coupler is an optocoupler receiving end. The lithium battery DC-AC inverter protection circuit according to any one of claims 1 to 4, further comprising a first filter capacitor, one end of the first filter capacitor is connected to the power supply pin, The other end of the first filter capacitor is grounded. An energy storage device, characterized by comprising the lithium battery DC-AC inverter protection circuit according to any one of claims 1 to 5. The energy storage device according to claim 6, further comprising a driving circuit of a MOS transistor bridge circuit; the MOS transistor bridge circuit includes at least one half bridge, and the half bridge includes two MOS transistors; The drive circuit includes a single-chip microcomputer, a half-bridge drive circuit, a gate circuit, a bleeder circuit, and a discharge circuit; the half-bridge drive circuit includes a drive chip with dead time control; The single-chip microcomputer can generate at least one group of complementary sinusoidal pulse width modulation driving signals, and the single-chip microcomputer can set the dead time of the sinusoidal pulse width modulation driving signals; The half-bridge drive circuit can amplify and convert the set of complementary sinusoidal pulse width modulation drive signals; The gate circuit can transmit the signal sent by the half-bridge driving circuit to the MOS tube to drive the MOS tube; The bleeder circuit is connected to the gate and the source of the MOS tube for discharging the voltage between the gate and the source when the MOS tube is turned off; The discharge circuit is connected to the gate and the source of the MOS tube, and is used for discharging the capacitance between the gate and the source when the MOS tube is turned off. The energy storage device according to claim 7, characterized in that: The gate circuit includes a drive resistor and a diode, one end of the drive resistor is connected to an output pin of the drive chip, one end of the diode is connected to the other end of the drive resistor, and the other end of the diode Connected with the gate of the MOS tube; The bleeder circuit includes a bleeder resistor and a triode, the base of the triode is connected between the drive resistor and the diode, the emitter of the triode is connected to one end of the bleeder resistor, and the collector of the triode The electrode is connected to the source of the MOS tube, and the other end of the bleeder resistor is connected to the gate of the MOS tube; The discharge circuit includes a discharge resistor connected between the gate and the source of the MOS tube. The energy storage device according to claim 8, wherein: The two MOS tubes are respectively a high-end MOS tube and a low-end MOS tube; The half-bridge driving circuit also includes a fast recovery diode and a bootstrap capacitor; One end of the fast recovery diode is connected to the start voltage pin of the driving chip, and the other end of the fast recovery diode is used for connecting a voltage to provide a high-side driving voltage; One end of the bootstrap capacitor is connected to the start-up voltage pin of the driver chip, and the other end of the bootstrap capacitor is connected to the source of the high-side MOS transistor, thereby raising the power supply voltage to drive the high-side MOS transistor . The energy storage device according to any one of claims 7 to 9, wherein the MOS tube bridge circuit includes two half bridges, and the two half bridges form an H bridge; the voltage of the drive chip is connected An input capacitor for energy storage and filtering is connected between the input pin and the ground pin.

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