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WO2020224240A1 - Circuit goa, panneau d'affichage et dispositif d'affichage - Google Patents

Circuit goa, panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2020224240A1
WO2020224240A1 PCT/CN2019/121003 CN2019121003W WO2020224240A1 WO 2020224240 A1 WO2020224240 A1 WO 2020224240A1 CN 2019121003 W CN2019121003 W CN 2019121003W WO 2020224240 A1 WO2020224240 A1 WO 2020224240A1
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WIPO (PCT)
Prior art keywords
film transistor
thin film
pull
node
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/121003
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English (en)
Chinese (zh)
Inventor
薛炎
韩佰祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020224240A1 publication Critical patent/WO2020224240A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the invention relates to the field of display, in particular to a liquid crystal display panel and a driving method thereof.
  • the scan lines of display panels are driven by external integrated circuits, which can control the scan lines at all levels.
  • the line scan driver circuit can be integrated on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the display device Narrow bezel.
  • IGZO Indium Gallium Zinc Oxide
  • the current method to reduce GOA power consumption is to use the DC-AC signal input method.
  • the thin film transistor (TFT) in the pull-up module is the thin film transistor with the largest aspect ratio in the GOA circuit, the dynamic power consumption caused by the parasitic capacitance is relatively large.
  • the DC-AC method can eliminate the dynamic power consumption of the TFT, it will cause the TFT to be subjected to the stress of Vds all the time, making the threshold voltage (Vth) of the TFT prone to forward bias, resulting in output signal distortion serious.
  • the purpose of the present invention is to provide a GOA circuit, a display panel and a display device, which can avoid output signal distortion.
  • the present invention provides a GOA circuit, wherein the GOA circuit includes m cascaded GOA units, and the nth level GOA unit includes:
  • Pull up control module for pulling up the potential of the first node
  • the first pull-up module is used to pull up the potential of the n-th level transmission signal
  • the second pull-up module is used to pull up the potential of the first output terminal, which includes:
  • the pull-up unit includes a pull-up thin film transistor; the gate of the pull-up thin film transistor is connected to the second node, the source of the pull-up thin film transistor is connected to the drain of the fifth thin film transistor, and the The drain of the pull-up thin film transistor is connected to the first output terminal;
  • a voltage stabilizing unit for eliminating the influence of the threshold voltage of the pull-up thin film transistor on the potential of the first output terminal; the voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal;
  • a pull-down module for pulling down the potentials of the first node, the second node and the first output terminal
  • the pull-down maintenance module is used to maintain the potential of the first node when the first node is at a low potential, where m ⁇ n ⁇ 1.
  • the present invention provides a display panel including the GOA circuit described above.
  • the present invention provides a display device including the above-mentioned display panel.
  • the potential of the first output terminal is independent of the threshold voltage of the pull-up thin film transistor, and the deviation of the threshold voltage is prevented from affecting the output
  • the signal affects, so as to avoid distortion of the output signal.
  • Figure 1 is a schematic diagram of the structure of an existing GOA circuit
  • Figure 2 is a waveform diagram of the output signal of the existing GOA circuit
  • FIG. 3 is a schematic diagram of the structure of the GOA circuit of the present invention.
  • Fig. 6 is a waveform comparison diagram between M point and the first output terminal of the present invention.
  • the existing GOA circuit includes m cascaded GOA units, and the n-th level GOA unit includes: a pull-up control module 100, a first pull-up module 200, a second pull-up module 300', a pull-down module 400.
  • the pull-down maintenance module 500 further includes a storage capacitor C. Where m ⁇ n ⁇ 1.
  • the pull-up control module 100 is used to pull up the potential of the first node Q; that is, to charge the Q point.
  • the first pull-up module 200 is used to pull up the potential of the n-th stage transmission signal Cout(n), that is, to raise the potential of the n-th stage transmission signal Cout(n), and the second pull-up module 300' is used for When the potential of the first output terminal is pulled up, even if the potential of the output signal Out(n) rises, the first output terminal is connected to the scan line.
  • the function of the pull-down module 400 is to pull down the potential of the first node Q point, the second node M point and the first output terminal, that is, pull down the potential of the M point and the output signal Out(n).
  • the pull-down sustaining module 500 is used to maintain the potential of the Q point when the potential of the Q point is at a low potential, where the potential of the Q point and the QB point are opposite.
  • the storage capacitor C is used to store the potential input by the pull-up control module 100 in the storage capacitor.
  • the disadvantage of the traditional GOA circuit is that the thin film transistor T21 is affected by the DC stress of Vds, and the Vth is prone to forward bias, which will cause serious distortion of the output signal.
  • the Vth of T21 does not shift, Out(n)
  • the high level of the signal is 18V (the highest level), as shown in the waveform 101
  • the Vth of T21 is positively biased by 10V
  • the high level of the Out(n) signal is 8V (the highest level), as shown in the waveform 102, That is, the level of the Out(n) signal drops, and the visible signal is distorted.
  • the GOA circuit of the present invention includes m cascaded GOA units, and the n-th level GOA unit includes: a pull-up control module 100, a first pull-up module 200, a second pull-up module 300, and a pull-down module 400 , Pull-down maintenance module 500 and storage capacitor C1.
  • the second pull-up module 300 is used to pull up the potential of the first output terminal.
  • the second pull-up module 300 includes: a pull-up unit 31 and a voltage stabilizing unit; the pull-up unit 31 includes a pull-up thin film transistor T21; the pull-up thin film transistor The gate of T21 is connected to the second node M, the source of the pull-up thin film transistor T21 is connected to the drain of the fifth thin film transistor T65, and the drain of the pull-up thin film transistor T21 is connected to the The first output terminal is connected.
  • the voltage stabilizing unit is used to eliminate the influence of the threshold voltage of the pull-up thin film transistor T21 on the potential of the first output terminal.
  • the voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal.
  • the voltage stabilizing unit includes a first thin film transistor T61, a second thin film transistor T62, a third thin film transistor T63, a fourth thin film transistor T64, and a fifth thin film transistor T65.
  • the gate of the first thin film transistor T61 is connected to the n-1th level transmission signal Cout(n-1); the drain of the first thin film transistor T61 is connected to the second node M;
  • the gate of the second thin film transistor T62 is connected to the n-2th level transmission signal Cout(n-2), the source of the second thin film transistor T62 is connected to the high potential signal VDD, and the second thin film transistor The drain of T62 is connected to the second node M;
  • the gate of the third thin film transistor T63 is connected to the n-2th level transmission signal Cout(n-2), and the drain of the third thin film transistor T63 is connected to the second node M through the first capacitor C3 , The source of the third thin film transistor T63 is connected to the low potential signal VGL.
  • the gate of the fourth thin film transistor T64 is connected to the n-1th level transmission signal Cout(n-1), the drain of the fourth thin film transistor T64 and the first output terminal (for outputting Out(n) Signal) connection, the source of the fourth thin film transistor T64 is connected to the low potential signal VGL.
  • the gate of the fifth thin film transistor T65 is connected to the high potential signal VDD, and the source of the fifth thin film transistor T65 is connected to the n-1th stage reverse signal QB(n-1); the fifth thin film transistor The drain of T65 is connected to the source of the first thin film transistor T61.
  • the voltage stabilizing unit further includes a second capacitor C2, one end of the second capacitor C2 is connected to the drain of the second thin film transistor T62, and the other end of the second capacitor C2 is connected to the second output terminal, The second output terminal is used to output a Cout(n) signal.
  • the pull-down module 400 further includes a seventh thin film transistor T51, an eighth thin film transistor T52, a ninth thin film transistor T53, and a tenth thin film transistor T54;
  • the gate of the seventh thin film transistor T51, the gate of the eighth thin film transistor T52, the gate of the ninth thin film transistor T53, and the gate of the tenth thin film transistor T54 are all connected to the n+1th stage Transmission signal Cout(n+1), the source of the seventh thin film transistor T51, the source of the eighth thin film transistor T52, the source of the ninth thin film transistor T53, and the source of the tenth thin film transistor T54 Both are connected to the low potential signal VGL.
  • the drain of the seventh thin film transistor T51 is connected to the first output terminal, the drain of the eighth thin film transistor T52 is electrically connected to the second node M, and the drain of the ninth thin film transistor T53 is connected to the second node M.
  • the output terminal is connected, and the drain of the tenth thin film transistor T54 is connected to the first node Q point.
  • the first pull-up module 200 includes an eleventh thin film transistor T22, the gate of the eleventh thin film transistor T22 is connected to the first node Q, and the source of the eleventh thin film transistor T22 is connected to the second Clock signal CK2; the drain of the eleventh thin film transistor T22 is connected to the second output terminal.
  • the second output terminal is used to output a Cout(n) signal.
  • the pull-down sustain module 500 includes a twelfth thin film transistor T31 and a thirteenth thin film transistor T32.
  • the gate and source of the twelfth thin film transistor T31 are both connected to a high-level signal VDD, and the drain of the twelfth thin film transistor T31 and the drain of the thirteenth thin film transistor T32 are both connected to the third
  • the node (used to output the nth stage reverse signal QR(n)) is connected, the gate of the thirteenth thin film transistor T32 is connected to the first node Q, and the source of the thirteenth thin film transistor T32 is connected to Low level signal VGL.
  • the pull-down maintenance module 500 further includes a fourteenth thin film transistor T4, the gate of the fourteenth thin film transistor T4 is connected to the third node, and the source of the fourteenth thin film transistor T4 is connected to a low level Signal VGL, the drain of the fourteenth thin film transistor T4 is connected to the first node Q point.
  • the pull-up control module 100 includes a fifteenth thin film transistor T1, the gate of the fifteenth thin film transistor T1 is connected to the first clock signal CK1, and the source of the fifteenth thin film transistor T1 is connected to the n-th The first-level transmission signal Cout(n-1), the drain of the fifteenth thin film transistor T1 is connected to the first node Q point.
  • One end of the storage capacitor C1 is connected to the first node Q, and the other end of the storage capacitor C1 is connected to the second output terminal.
  • Q(n) is the signal of the nth level Q point
  • Q(n-1) is the signal of the n-1th level Q point
  • Cout(n-1), Cout(n-2) The maximum voltage of Cout(n+2), CK1, CK2, CK3, CK4 is 20V, the minimum voltage is -10V, VDD is for example 20V, and VGL is for example -10v.
  • CK1 and CK2 are a set of clock signals
  • Cout(n-2) is the Cout(n) signal connected to the previous two stages
  • Cout(n-1) is the Cout(n) signal connected to the previous stage
  • Cout(n+1) Connect the Cout(n) output signal of the next stage, where Cout(n-2) and Cout(n-1) of the GOA circuit of the first stage of the GOA circuit are connected to the STV1 and STV2 signals respectively.
  • the STV signal is the start of the GOA circuit
  • the signals, STV1 and STV2 correspond to the left STV and the right STV respectively.
  • the GOA circuit circulates with 2 basic units as the minimum repeating unit.
  • the nth level GOA unit and the n+2 level GOA unit can jointly form a GOA repeating unit.
  • the display panel can also use the 8CK architecture, and the GOA circuit circulates with 4 basic units as the minimum repeating unit.
  • QB(n-1) is the n-1 level reverse signal, that is, the signal of the QB point of the n-1 level GOA unit
  • M(n) is the M point of the nth level GOA unit signal.
  • Period t1 Cout(n-1), CK1, and CK2 are all low potentials, and point Q is low, that is, Q(n) is low, so T22 and T32 are turned off.
  • QB(n) is high and T4 is open.
  • CK2 is also low, the level transfer signal Cout(n) is low and Cout(n-2) is high, making T62 open and the potential at point M reset to 20V, and T63 is turned on at the same time, pulling down the potential at point M, that is, M(n) is a low potential, T21 is turned on, and QB(n-1) is a low potential, and T65 is turned off.
  • Cout(n-2) is high, T63 is turned on, and the output signal Out(n) is low.
  • Time period t2 Cout(n-1) and CK1 are high, T1 is open, Q(n) is raised to high, T22 and T32 are open, QB(n) is pulled down to low, making T4 closed. Since CK2 is low potential, the level transmission signal Cout(n) is low potential, Cout(n-1) is high potential, T61 is open, point M is connected to point N, T21 forms a diode connection, T64 is open, Out(n) The low potential VGL is output, and the potential at point M is VGL+Vth.
  • Phase t3 CK1 and Cout(n-1) fall to low potential, T1 is closed, and CK2 rises to high potential. Due to the existence of storage capacitor C1, the potential of point Q is coupled to a higher potential, and T22 is turned on.
  • the level-by-level transmission signal Cout(n) output potential rises from VGL to VGH. Therefore, the potential increase value of Cout(n) is (VGH-VGL). At this time, the n-th stage transmission signal Cout(n) is high.
  • V1 (VGH-VGL)+(VGL+Vth)+ ⁇ V;
  • V2 has nothing to do with Vth, that is, the potential of the first output terminal has nothing to do with the threshold voltage of T21.
  • point M that is, M(n) is high, so T21 is turned on and Cout(n-1) is low.
  • T61 is closed, QB(n-1) is high, and T65 is open, therefore, the output signal Out(n) is high
  • 201 represents the waveform diagram at point M when the potential is negatively biased by 10V
  • 202 represents the waveform diagram at point M when the potential is not biased
  • 203 represents the waveform diagram at point M when the potential is positively biased by 10V
  • 301 represents the waveform of Out(n) when the potential is negatively biased by 10V
  • 302 represents the waveform of Out(n) when the potential is not biased
  • 303 represents the waveform of Out(n) when the potential is positively biased by 10V.
  • the present invention also provides a display panel, which includes any of the aforementioned GOA circuits.
  • the present invention also provides a display device, which includes any of the above-mentioned display panels.
  • the potential of the first output terminal is independent of the threshold voltage of the pull-up thin film transistor, and the deviation of the threshold voltage is prevented from affecting the output
  • the signal affects, so as to avoid distortion of the output signal.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un circuit GOA, un panneau d'affichage et un dispositif d'affichage. Le circuit GOA comprend m unités GOA montées en cascade, une unité GOA de Nième étage comprenant : un module de commande d'excursion haute (100) servant à élever le potentiel d'un premier noeud (Q) ; un premier module d'excursion haute (200) servant à élever le potentiel d'un signal de transfert d'étage de nième étage (Cout(n)) ; un second module d'excursion haute (300) servant à élever le potentiel d'une première extrémité de sortie (Out(n)), le second module d'excursion haute comprenant : une unité d'excursion haute (31) comprenant un transistor d'excursion haute à couches minces (T21), et une unité de stabilisation de tension servant à éliminer l'influence de la tension de seuil du transistor d'excursion haute à couches minces (T21) sur le potentiel de la première extrémité de sortie (Out(n)), l'unité de stabilisation de tension étant connectée au transistor d'excursion haute à couches minces (T21) et à la première extrémité de sortie (Out(n)) ; un module d'excursion basse (400) servant à abaisser le potentiel du premier noeud (Q), d'un deuxième noeud (M) et de la première extrémité de sortie (Out(n)) ; et un module de maintien d'excursion basse (500) servant à maintenir le potentiel du premier noeud (Q) lorsque le premier noeud (Q) est à un potentiel bas. Selon le circuit GOA, le panneau d'affichage et le dispositif d'affichage, la distorsion d'un signal de sortie peut être évitée.
PCT/CN2019/121003 2019-05-08 2019-11-26 Circuit goa, panneau d'affichage et dispositif d'affichage Ceased WO2020224240A1 (fr)

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CN201910378279.X 2019-05-08
CN201910378279.XA CN110148382B (zh) 2019-05-08 2019-05-08 一种goa电路、显示面板及显示装置

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115188345A (zh) * 2022-07-27 2022-10-14 福建华佳彩有限公司 一种gip驱动电路
CN115602094A (zh) * 2022-10-24 2023-01-13 重庆邮电大学（Cn） 一种goa电路、goa单元及驱动方法、阵列基板

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110148382B (zh) * 2019-05-08 2020-08-04 深圳市华星光电半导体显示技术有限公司 一种goa电路、显示面板及显示装置
CN111081190B (zh) 2019-12-18 2021-08-24 深圳市华星光电半导体显示技术有限公司 Goa电路、显示面板及薄膜晶体管的阈值电压补偿方法
CN111243543B (zh) * 2020-03-05 2021-07-23 苏州华星光电技术有限公司 Goa电路、tft基板、显示装置及电子设备
CN113241040B (zh) 2021-07-09 2021-09-24 北京京东方技术开发有限公司 显示基板及显示装置
CN114944124B (zh) * 2022-05-25 2025-01-24 Tcl华星光电技术有限公司 Goa电路及显示面板

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CN107993627A (zh) * 2017-12-25 2018-05-04 深圳市华星光电技术有限公司 一种goa电路
KR20180066375A (ko) * 2016-12-08 2018-06-19 엘지디스플레이 주식회사 시프트 레지스터 및 이를 이용한 표시장치
CN110148382A (zh) * 2019-05-08 2019-08-20 深圳市华星光电半导体显示技术有限公司 一种goa电路、显示面板及显示装置

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US20110227505A1 (en) * 2010-03-17 2011-09-22 Kyong-Tae Park Organic light emitting display device
CN104167192A (zh) * 2014-07-22 2014-11-26 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN105845183A (zh) * 2016-03-21 2016-08-10 京东方科技集团股份有限公司 移位寄存器电路、阵列基板和显示装置
CN105957487A (zh) * 2016-07-08 2016-09-21 深圳市华星光电技术有限公司 一种goa电路
KR20180066375A (ko) * 2016-12-08 2018-06-19 엘지디스플레이 주식회사 시프트 레지스터 및 이를 이용한 표시장치
CN107993627A (zh) * 2017-12-25 2018-05-04 深圳市华星光电技术有限公司 一种goa电路
CN110148382A (zh) * 2019-05-08 2019-08-20 深圳市华星光电半导体显示技术有限公司 一种goa电路、显示面板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115188345A (zh) * 2022-07-27 2022-10-14 福建华佳彩有限公司 一种gip驱动电路
CN115602094A (zh) * 2022-10-24 2023-01-13 重庆邮电大学（Cn） 一种goa电路、goa单元及驱动方法、阵列基板

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CN110148382A (zh) 2019-08-20

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