WO2020215277A1 - Driver circuit - Google Patents

Abstract

A driver circuit, comprising a boost converter and M charge pumps, where M is an integer greater than or equal to 1. The boost converter is connected to the first charge pump in the M charge pumps; the i-th charge pump in the M charge pumps is connected to the (i-1)-th charge pump in the M charge pumps, wherein i=2, 3, ..., M; the boost converter is used for boosting a first voltage input to the boost converter to a second voltage; the J-th charge pump is used for boosting a voltage input to the J-th charge pump by the second voltage, and the J-th charge pump is any one of the M charge pumps. The embodiments of the present invention can improve the conversion efficiency.

Description

A drive circuit Technical field

The embodiment of the present invention relates to the technical field of electronic circuits, in particular to a driving circuit.

Background technique

White light emitting diodes (WLEDs) are increasingly used in display backlighting, lighting and other industries due to their long service life, high luminous brightness, and high luminous efficiency. The WLED drive circuit can be boosted by a direct current to direct current (DC-DC) converter to raise the battery voltage to the turn-on voltage of the WLED. At present, the mainstream drive circuit adopts a single-stage asynchronous boost structure, which mainly includes inductors, Schottky diodes and integrated laterally diffused metal oxide semiconductor (LDMOS) tubes, which can be modulated by pulse width modulation. (pulse width modulation, PWM) duty cycle to realize the dimming of WLED. However, as the number of WLEDs that need to be driven increases, the output voltage of the drive circuit also needs to increase. As the output voltage of the drive circuit increases, it is necessary to use high-voltage LDMOS transistors and inductors, which increases the parasitic capacitance of the switching node and the impedance of the inductor. In addition, the swing of the switching node increases as the output voltage of the driving circuit increases, so that the crossover loss and switching loss are increased. Therefore, the system power conversion efficiency is reduced.

Summary of the invention

The embodiment of the invention discloses a drive circuit for improving conversion efficiency.

The first aspect discloses a driving circuit, which may include a boost converter and M charge pumps, the boost converter is connected to the first charge pump of the M charge pumps, and the i-th charge pump of the M charge pumps is connected to the M charge pumps. The i-1th charge pump in the charge pump, the boost converter boosts the first voltage input to the boost converter to the second voltage, and the J-th charge pump boosts the voltage input to the J-th charge pump by the second voltage. M is an integer greater than or equal to 1, i=2, 3,..., M, and the J-th charge pump is any one of the M voltage pumps. Since the device withstand voltage of the boost converter and M charge pumps is 1 part of M+1 of the drive voltage, M can be set to an appropriate value so that the output voltage of the drive circuit is increased without increasing the withstand voltage of the device. At the same time, the voltage swing is also 1/M+1 of the final output voltage, which can improve the system power conversion efficiency.

As a possible implementation, the boost converter has a variable voltage boost ratio. Therefore, under the condition that the input voltage of the drive circuit remains unchanged, the drive circuit can be adjusted by adjusting the voltage boost ratio of the boost converter. The output voltage can increase the voltage range.

As a possible implementation manner, the driving circuit may further include a bias circuit, the bias circuit is respectively connected to the boost converter and M charge pumps, and the bias circuit may provide bias voltages for the boost converter and the M charge pumps. . The bias circuit can make the boost converter and M charge pumps work in a proper working state.

As a possible implementation, the boost converter may include an inductor, a first metal oxide semiconductor (MOS) tube, a second MOS tube, and a first capacitor. One end of the inductor is the input terminal of the drive circuit, and the inductor The other end is connected to the drain of the first MOS tube, the source of the second MOS tube, and the first end of the first charge pump among the M charge pumps. The source of the first MOS tube and one end of the first capacitor are used respectively At the ground terminal, the drain of the second MOS tube is connected to the other terminal of the first capacitor and the second terminal of the first one of the M charge pumps, the gate of the first MOS tube and the gate of the second MOS tube. The poles are respectively connected to the bias circuit.

As a possible implementation manner, the boost converter includes an inductor, a first MOS transistor, a second MOS transistor, and a first capacitor. One end of the inductor is the input end of the driving circuit, and the other end of the inductor is respectively connected to the first MOS transistor. The source, the drain of the second MOS tube, and the first end of the first charge pump, the drain of the first MOS tube and one end of the first capacitor are used to connect to the ground, and the source of the second MOS tube is connected to the ground. The other end of the first capacitor and the second end of the first charge pump, the gate of the first MOS tube and the gate of the second MOS tube are respectively connected to the bias circuit.

As a possible implementation manner, the jth charge pump in the M charge pumps includes a 2j+1th MOS tube, a 2j+2MOS tube, a 2jth capacitor, and a 2j+1th capacitor, and the source of the 2k+1th MOS tube is connected The drain of the 2kMOS transistor, one end of the 2k capacitor is connected to the source of the 2kMOS transistor, the drain of the 2k+1 MOS transistor is connected to the other end of the 2k capacitor, the source of the 2k+2MOS transistor and the 2k+2 One end of the capacitor, the drain of the 2k+2 MOS transistor is connected to the source of the 2k+3 MOS transistor and one end of the 2k+1 capacitor, and the drain of the 2M+1 MOS transistor is connected to the other end of the 2M capacitor and the 2M capacitor. The source of the +2MOS transistor, the drain of the 2M+2MOS transistor is connected to one end of the 2M+1 capacitor, the other end of the 2k+1 capacitor and the other end of the 2M+1 capacitor are respectively used to connect to the ground, the 2M The drain of the +2MOS transistor is the output terminal of the drive circuit, the gate of the 2j+1th MOS transistor and the gate of the 2j+2th MOS transistor are respectively connected to the bias circuit, j=1, 2, 3,...,M, k=2 ,3,...,M-1.

As a possible implementation manner, the jth charge pump of the M charge pumps includes a 2j+1th MOS tube, a 2j+2MOS tube, a 2jth capacitor, and a 2j+1th capacitor, and the drain of the 2k+1th MOS tube is connected The source of the 2kMOS transistor, one end of the 2k capacitor is connected to the drain of the 2kMOS transistor, and the source of the 2k+1 MOS transistor is respectively connected to the other end of the 2k capacitor, the drain of the 2k+2MOS transistor and the 2k+2 One end of the capacitor and the source of the 2k+2 MOS transistor are respectively connected to the drain of the 2k+3 MOS transistor and one end of the 2k+1 capacitor. The source of the 2M+1 MOS transistor is respectively connected to the other end of the 2M capacitor and the 2M capacitor. The drain of the +2MOS transistor, the source of the 2M+2MOS transistor is connected to one end of the 2M+1 capacitor, the other end of the 2k+1 capacitor and the other end of the 2M+1 capacitor are respectively used to connect to the ground, the 2M The source of the +2MOS tube is the output terminal of the drive circuit, the gate of the 2j+1th MOS tube and the gate of the 2j+2th MOS tube are respectively connected to the bias circuit, j=1, 2, 3,...,M, k=2 ,3,...,M-1.

As a possible implementation manner, the bias circuit may include 2M+2 bias voltage circuits, and the Lth bias voltage circuit may provide a bias voltage for the gate of the LMOS transistor, L=1, 2,...,2M +2.

As a possible implementation manner, the L-th bias voltage circuit includes an L-th XOR gate, an L-th AND gate, an L-th buffer, and an L-th delayer, and the p-th bias voltage circuit further includes a p-1th low voltage For the high-voltage converter and the p-1th high-voltage and low-voltage converter, the input end of the first exclusive OR gate is connected to the output end of the p-th delayer, and the input end of the first AND gate is connected to the output end of the first exclusive OR gate and Pulse low level, the input terminal of the first buffer is connected to the output terminal of the first AND gate, and the output terminal of the first buffer is respectively connected to the input terminal of the first delayer and the gate of the first MOS transistor. The input terminal of the OR gate is connected to the output terminal of the odd delayer in the 2M+2 delayers, and the input terminal of the qth AND gate is connected to the output terminal of the qth exclusive OR gate and the pulse high level respectively. 1 The input of the low-voltage and high-voltage converter is connected to the output of the qth AND gate, the input of the qth buffer is connected to the output of the q-1th low-voltage and high-voltage converter, and the output of the qth buffer is respectively connected to the qMOS tube The gate and the input terminal of the q-1th high-voltage and low-voltage converter, the input terminal of the q-th delayer is connected to the output terminal of the q-1th high-voltage and low-voltage converter, and the input terminal of the r-th XOR gate is respectively connected to 2M+2 The output terminal of the even-numbered delayer in the delayer, the input terminal of the r-th AND gate are respectively connected to the output terminal of the r-th XOR gate, the pulse low level and the output terminal of the first delayer, the r-1th low voltage and high voltage The input end of the converter is connected to the output end of the rth AND gate, the input end of the rth buffer is connected to the output end of the r-1th low-voltage and high-voltage converter, and the output end of the rth buffer is connected to the gate and the rMOS tube respectively. The input terminal of the r-1th high-voltage and low-voltage converter, and the input terminal of the r-th delayer is connected to the output terminal of the r-1th high-voltage and low-voltage converter. p=2,3,...,2M+2, q=2,4,...,2M+2, r=3,5,...,2M+1.

As a possible implementation, the driving circuit may also include a WLED circuit, the WLED circuit may include N WLED light strings, the first WLED light string may include H WLEDs, and the H WLEDs are connected in series, and The anode of the first WLED is connected to the M-th charge pump among the M charge pumps, and the cathode of the H-th WLED among the H WLEDs is used to connect to the ground terminal. N and H are integers greater than 1, and the first WLED light string is any WLED light string among the N WLED light strings.

As a possible implementation manner, the first WLED light string may further include a MOS tube, the drain of the MOS tube is connected to the negative electrode of the H-th WLED, and the source of the MOS tube is used to connect the drain terminal. Connecting a MOS tube in series with the WLED light string can adjust the current flowing in the WLED light string.

Description of the drawings

FIG. 1 is a schematic structural diagram of a driving circuit disclosed in an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of another driving circuit disclosed in an embodiment of the present invention;

3 is a schematic structural diagram of another driving circuit disclosed in an embodiment of the present invention;

4 is an equivalent schematic diagram of a driving circuit disclosed in an embodiment of the present invention;

FIG. 5 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention;

FIG. 6 is an equivalent schematic diagram of yet another driving circuit disclosed in an embodiment of the present invention;

FIG. 7 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention;

FIG. 8 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention;

FIG. 9 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention;

Figure 10 is a schematic diagram of a waveform disclosed in an embodiment of the present invention;

Fig. 11 is a schematic diagram of another waveform disclosed in an embodiment of the present invention.

Detailed ways

The embodiment of the invention discloses a drive circuit for improving conversion efficiency. The detailed description is given below.

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a driving circuit disclosed in an embodiment of the present invention. As shown in Figure 1, the drive circuit may include a boost converter and M charge pumps, where M is an integer greater than or equal to 1, where:

The boost converter is connected to the first charge pump among the M charge pumps, and the i-th charge pump among the M charge pumps is connected to the i-1th charge pump among the M charge pumps, i=2,3,...,M;

The boost converter is used to boost the first voltage input to the boost converter to the second voltage;

The J-th charge pump is used to increase the voltage input to the J-th charge pump by the second voltage, and the J-th charge pump is any one of the M voltage pumps.

In this embodiment, the boost converter can boost the first voltage input to the boost converter to the second voltage. The first voltage is the input voltage of the drive circuit and also the input voltage of the boost converter, and the second voltage is The output voltage of the boost converter, the second voltage is greater than the first voltage. The J-th charge pump is used to increase the voltage input to the J-th charge pump by the second voltage. The J-th charge pump is any one of the M voltage pumps, that is, each of the M charge pumps is used to separate the voltage The second voltage is boosted, that is, the output voltage of the j-th charge pump in the M charge pumps is equal to the second voltage that is j+1 times, that is, the boosted voltage of each charge pump in the M charge pumps is the second voltage. The output voltage of the driving circuit is M+1 times the second voltage, that is, the output voltage of the driving circuit is M+1 times the output voltage of the boost converter.

Please refer to FIG. 2. FIG. 2 is a schematic structural diagram of another driving circuit disclosed in an embodiment of the present invention. Among them, the driving circuit shown in FIG. 2 is optimized from the driving circuit shown in FIG. 1. among them:

The boost converter has a variable voltage boost ratio.

In this embodiment, the boost converter has a variable voltage boost ratio, that is, the ratio of the second voltage to the first voltage is variable, that is, the ratio of the second voltage to the first voltage is adjustable.

In an embodiment, the driving circuit may further include a bias circuit, wherein:

The bias circuit is respectively connected to the boost converter and M charge pumps;

The bias circuit is used to provide bias voltages for the boost converter and M charge pumps.

In one embodiment, the boost converter includes an inductor L, a first MOS transistor Q1, a second MOS transistor Q2, and a first capacitor C1, where:

One end of the inductor L is the input terminal Vin of the drive circuit, and the other end of the inductor L is respectively connected to the drain of the first MOS transistor Q1, the source of the second MOS transistor Q2, and the first of the first charge pump among the M charge pumps. The source of the first MOS transistor Q1 and one end of the first capacitor C1 are respectively used to connect to the ground, and the drain of the second MOS transistor Q2 is connected to the other end of the first capacitor C1 and the first of the M charge pumps. The second end of the charge pump, the gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2 are respectively connected to a bias circuit.

In this embodiment, the first MOS transistor Q1 and the second MOS transistor Q2 are N-type MOS transistors. When the first MOS transistor Q1 is turned on and the second MOS transistor Q2 is turned off, the inductor L is magnetized. When the first MOS transistor Q1 is off and the second MOS transistor Q2 is on, the inductor L is demagnetized. The voltage boost ratio of the boost converter can be adjusted by adjusting the length of the magnetizing time. The longer the magnetizing time, the higher the voltage boost ratio of the boost converter.

In an embodiment, the jth charge pump of the M charge pumps may include 2j+1th MOS transistor Q2j+1, 2j+2th MOS transistor Q2j+2, 2jth capacitor C2j, and 2j+1th capacitor C2j+1, j=1,2,3,...,M, where:

The source of the 2k+1 MOS transistor Q2k+1 is connected to the drain of the 2k MOS transistor Q2k, one end of the 2k capacitor C2k is connected to the source of the 2k MOS transistor Q2k, and the drain of the 2k+1 MOS transistor Q2k+1 is respectively connected to the 2k The other end of the capacitor C2k, the source of the 2k+2 MOS transistor Q2k+2 and one end of the 2k+2 capacitor C2k+2, and the drain of the 2k+2 MOS transistor Q2k+2 are respectively connected to the 2k+3 MOS transistor Q2k+3 The source of the 2k+1 capacitor C2k+1, the drain of the 2M+1 MOS transistor Q2M+1 is connected to the other end of the 2M capacitor C2M and the source of the 2M+2 MOS transistor Q2M+2, respectively. The drain of the +2MOS transistor Q2M+2 is connected to one end of the 2M+1 capacitor C2M+1, the other end of the 2k+1 capacitor C2k+1 and the other end of the 2M+1 capacitor C2M+1 are respectively connected to the ground , The drain of the 2M+2MOS transistor Q2M+2 is the output terminal of the drive circuit, the gate of the 2j+1 MOS transistor Q2j+1 and the gate of the 2j+2MOS transistor Q2j+2 are respectively connected to the bias circuit, k=2 ,3,...,M-1.

In this embodiment, all MOS tubes in the charge pump are N-type MOS tubes, and each charge pump includes two MOS tubes and two capacitors. Among them, one capacitor is a voltage stabilizing capacitor, which is used to set between the output terminal of the charge pump and the ground terminal, and the other capacitor is a flying jump (FLY) capacitor, which is used to bridge two charge pumps, or between the charge pump and the ground. Voltage converter.

In an embodiment, the bias circuit may include 2M+2 bias voltage circuits, where:

The Lth bias voltage circuit is used to provide a bias voltage for the gate of the LMOS tube, L=1, 2,...,2M+2.

In an embodiment, the L-th bias voltage circuit includes an L-th XOR gate XL, an L-th AND gate YL, an L-th buffer BL, and an L-th delayer DL, and the p-th bias voltage circuit may also include a p-th -1 low-voltage high-voltage converter Up-1 and the p-1th high-voltage low-voltage converter Vp-1, p=2,3,...,2M+2, where:

The input terminal of the first exclusive OR gate X1 is connected to the output terminal of the p-th time delay, and the input terminal of the first AND gate Y1 is connected to the output terminal of the first exclusive OR gate X1 and the pulse low level PWM_L respectively. The first buffer The input terminal of B1 is connected to the output terminal of the first AND gate Y1, the output terminal Q1_G of the first buffer B1 is respectively connected to the input terminal of the first delayer D1 and the gate of the first MOS transistor Q1, and the qth exclusive OR gate Xq The input terminals of the 2M+2 delayers are respectively connected to the output terminal of the odd-numbered delayer, the input terminal of the qth AND gate Yq is respectively connected to the output terminal of the qth exclusive OR gate Xq and the pulse high level PWM_H, the qth -1 The input terminal of the low-voltage high-voltage converter Uq-1 is connected to the output terminal of the qth AND gate Yq, the input terminal of the qth buffer Bq is connected to the output terminal of the q-1th low-voltage and high-voltage converter Uq-1, and the qth buffer The output terminal Qq_G of Bq is respectively connected to the gate of the q-th MOS transistor Qq and the input terminal of the q-1th high-voltage and low-voltage converter Vq-1, and the input terminal of the q-th delayer Dq is connected to the q-1th high-voltage and low-voltage converter Vq- The output terminal of 1, the input terminal of the r-th exclusive OR gate Xr is connected to the output terminal of the even-numbered delayer in the 2M+2 delayers, and the input terminal of the r-th AND gate Yr is connected to the r-th exclusive OR gate Xr. The output terminal, pulse low level PWM_L and the output terminal of the first delayer D1, the input terminal of the r-1th low-voltage and high-voltage converter Ur-1 is connected to the output terminal of the rth AND gate Yr, and the input of the rth buffer Br The terminal is connected to the output terminal of the r-1th low-voltage and high-voltage converter Ur-1, and the output terminal Qr_G of the r-th buffer Br is connected to the gate of the rMOS transistor Qr and the input terminal of the r-1th high-voltage and low-voltage converter Vr-1, respectively , The input terminal of the r-th delayer Dr is connected to the output terminal of the r-1th high-voltage and low-voltage converter Vr-1, q=2,4,...,2M+2, r=3,5,...,2M+1.

Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of another driving circuit disclosed in an embodiment of the present invention. As shown in Figure 3, the drive circuit can include a boost converter, two charge pumps, a bias circuit and a WLED circuit. The boost converter can include an inductor L, MOS transistors Q1-Q2 and a capacitor C1. The first charge The pump can include MOS tubes Q3-Q4 and capacitors C2-C3, the second charge pump can include MOS tubes Q5-Q6 and capacitors C4-C5, the bias circuit includes 6 bias voltage circuits, and the first bias voltage circuit can Including exclusive OR gate X1, AND gate Y1, buffer B1 and time delay D1, the second bias voltage circuit may include exclusive OR gate X2, AND gate Y2, low voltage and high voltage converter U1, buffer B2, high voltage and low voltage converter V1 and delayer D2. The third bias voltage circuit may include exclusive OR gate X3, AND gate Y3, low-voltage and high-voltage converter U2, buffer B3, high-voltage and low-voltage converter V2 and delayer D3, fourth bias voltage The circuit may include exclusive OR gate X4, AND gate Y4, low voltage and high voltage converter U3, buffer B4, high voltage and low voltage converter V3, and time delay D4, and the fifth bias voltage circuit may include exclusive OR gate X5, AND gate Y5, Low voltage and high voltage converter U4, buffer B5, high voltage and low voltage converter V4 and time delay D5, the sixth bias voltage circuit may include exclusive OR gate X6, AND gate Y6, low voltage and high voltage converter U5, buffer B6, high voltage and low voltage Converter V5 and delayer D6, the WLED circuit includes N WLED light strings, among the N WLED light strings, the g-th WLED light string includes H WLEDs and MOS tubes Mg, g=1, 2,...,H, where :

One end of L is the input terminal Vin of the drive circuit, the other end of L is connected to the drain of Q1, the source of Q2 and one end of C2, the drain of Q2 is connected to one end of C1 and the source of Q3, and the drain of Q3 The electrodes are connected to the other end of C2, the source of Q4 and one end of C4. The drain of Q4 is connected to one end of C3 and the source of Q5. The drain of Q5 is connected to the other end of C4 and the source of Q6. The drain is respectively connected to one end of C5 and the anode of the first WLED included in each WLED string of N WLED light strings, and the H WLEDs included in each WLED string of N WLED light strings are connected in series, Mg The drain of is connected to the negative electrode of the H-th WLED included in the g-th WLED string, the source of Q1, the other end of C1, the other end of C3, the other end of C5, the source of M1,..., the source of MH The poles are respectively used to connect to the ground terminal, the input terminal of X1 is connected to the output terminal Q2_DE of D2, the output terminal Q3_DE of D3, the output terminal Q4_DE of D4, the output terminal Q5_DE of D5 and the output terminal Q6_DE of D6, and the input terminal of Y1 is respectively connected The output terminal of X1 and pulse low level PWM_L, the input terminal of B1 is connected to the output terminal of Y1, the output terminal Q1_G of B1 is connected to the gate of Q1 and the input terminal of D1 respectively, and the input terminal of X2 is connected to the output terminal Q1_DE, The output terminal Q3_DE of D3 and the output terminal Q5_DE of D5, the input terminal of Y2 is connected to the output terminal of X2 and the pulse high level PWM_H respectively, the input terminal of U1 is connected to the output terminal of Y2, the input terminal of B2 is connected to the output terminal of U1, B2 The output terminal Q2_G is connected to the gate of Q2 and the input terminal of V1, the input terminal of D2 is connected to the output terminal of V1, the input terminal of X3 is connected to the output terminal Q2_DE of D2, the output terminal Q4_DE of D4 and the output terminal Q6_DE of D6, The input terminal of Y3 is connected to the output terminal of X3, the output terminal Q1_DE of D1 and the pulse low level PWM_L, the input terminal of U2 is connected to the output terminal of Y3, the input terminal of B3 is connected to the output terminal of U2, and the output terminal Q3_G of B3 is connected respectively The gate of Q3 and the input of V2. The input of D3 is connected to the output of V2. The input of X4 is connected to the output Q1_DE of D1, the output Q3_DE of D3 and the output Q5_DE of D5, and the input of Y4 is connected respectively. The output terminal of X4 and pulse high level PWM_H, the input terminal of U3 is connected to the output terminal of Y4, the input terminal of B4 is connected to the output terminal of U3, the output terminal Q4_G of B4 is connected to the gate of Q4 and the input terminal of V3, respectively, and the input terminal of D4 The input terminal is connected to the output terminal of V3, the input terminal of X5 is connected to the output terminal Q2_DE of D2, the output terminal Q4_DE of D4 and the output terminal Q6_DE of D6, and the input terminal of Y5 is connected to the output terminal of X5, the output terminal Q1_DE and pulse of D1 respectively. Low level PWM_L, the input of U4 is connected to the output of Y5, and the input of B5 is connected to the output of U4 The output terminal, the output terminal Q5_G of B5 is connected to the gate of Q5 and the input terminal of V4, the input terminal of D5 is connected to the output terminal of V4, and the input terminal of X6 is connected to the output terminal Q1_DE of D1, the output terminal Q3_DE of D3 and the output terminal of D5. The output terminals Q5_DE and the input terminals of Y6 are respectively connected to the output terminal of X6 and the pulse high level PWM_H, the input terminal of U5 is connected to the output terminal of Y6, the input terminal of B6 is connected to the output terminal of U5, and the output terminal Q6_G of B6 is connected to the output terminal of Q6 respectively. The gate is connected to the input terminal of V5, and the input terminal of D6 is connected to the output terminal of V5.

In this embodiment, the driving circuit shown in FIG. 3 is a driving circuit obtained by M=2 in the driving circuit shown in FIG. 2. Therefore, the working principle of the driving circuit shown in FIG. 3 can be used to illustrate the driving circuit shown in FIG. The working principle of the drive circuit. The driving circuit shown in Figure 3 adopts the BOOST+ charge pump (charge pump, CP) architecture, which is formed by cascading three-stage DC-DC converters. The first-stage DC-DC converter consists of inductor L, power switch Q1, and The power switch Q2 and the stabilized capacitor C1 form a boost converter, the power switch Q1 is turned on, Q2 is turned off, the input voltage Vin magnetizes the inductor L through the Q1 path, the power switch Q2 is turned on, Q1 is turned off, and the input voltage Vin passes The Q2 path demagnetizes the inductor L, and the output voltage V _{OUT1 is} used as the input voltage of the second-stage DC-DC converter. The second-stage DC-DC converter is composed of FLY capacitor C2, power switch Q3, power switch Q4, and stabilizing capacitor C3. The first-stage charge pump is formed. Power switches Q1 and Q3 are turned on, Q4 is turned off, and the input voltage V _OUT1 passes through Q3. -The Q1 channel charges the FLY capacitor C2, the power switch Q4 is turned on, Q1 and Q3 are disconnected, the FLY capacitor C2 discharges the second stage output capacitor C3 through the Q4 channel, and the output voltage V _{OUT2 is} used as the third stage DC-DC converter Input voltage. The third-stage DC-DC converter is composed of FLY capacitor C4, power switch Q5, power switch Q6, and stabilized capacitor C5 to form a second-stage charge pump. Power switches Q1 and Q5 are turned on, Q6 is turned off, and input voltage V _OUT2 passes through Q5. -The Q1 path charges the FLY capacitor C2, the power switch Q6 is turned on, Q1 and Q5 are disconnected, the FLY capacitor C4 discharges the third stage output capacitor C5 through the Q6 path, and the output voltage V _{OUT3 is} used as the output voltage of the drive circuit.

From the charge and discharge balance relationship of FLY capacitor C2, we can get:

From the FLY capacitor C4 charge and discharge balance relationship, we can get:

According to the above FLY capacitor charge and discharge balance relationship formula, the output voltage V _OUT2 of the second-stage DC-DC converter is twice the output voltage V _OUT1 of the first-stage DC-DC converter, and the third-stage DC-DC conversion The output voltage V _OUT3 of the converter is three times the output voltage V _OUT1 of the first-stage DC-DC converter. The operating voltage range of power devices Q1 and Q2 is zero to one-third of the highest output voltage V _OUT3 ; the operating voltage range of power devices Q3 and Q4 is one-third of the highest output voltage V _OUT3 to two-thirds of the highest output voltage V _OUT3 ; The operating voltage range of power devices Q5 and Q6 is two-thirds of the highest output voltage V _OUT3 to the highest output voltage V _OUT3 .

Power devices Q1-Q6 device type LDMOS power device may be selected highest output voltage V _OUT3 third voltage requirements, the other may be selected to meet the maximum output voltage of the third MOS transistor breakdown voltage V _OUT3 requirements. The inverse withstand voltage requirement of the inductor L is one third of the highest output voltage V _OUT3 , the capacitor C1 withstand voltage requirement is one third of the highest output voltage V _OUT3 , and the capacitor C3 withstand voltage requirement is one third of the highest output voltage V _OUT3 Second, the withstand voltage of the capacitor C5 is required to be the highest output voltage V _OUT3 , the withstand voltage of the capacitor C2 is required to be one third of the maximum output voltage V _OUT3 , and the withstand voltage of the capacitor C4 is required to be one third of the maximum output voltage V _OUT3 .

In order to prevent the risk of collusion during the switching process of the power tube, the BOOST+CP architecture includes six stages in the driving logic relationship. Please refer to FIG. 4, which is an equivalent schematic diagram of a driving circuit disclosed in an embodiment of the present invention. As shown in Figure 4, in phase t1, the power switch Q1 is turned on, Q2-Q6 is turned off, the input voltage Vin magnetizes the inductor L, the voltage of the switch node LX1 is clamped to the power ground by the power switch Q1, and the switch node LX2 The voltage of the power switch is clamped to V _OUT1 -VD by the parasitic diode of the power switch Q3, and the voltage of the switch node LX3 is clamped to V _OUT2 -VD by the parasitic diode of the power switch Q5. VD is the turn-on voltage of the parasitic diode of the power switch. Please refer to FIG. 5. FIG. 5 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention. As shown in Figure 5, in phase t2, power switches Q1, Q3, and Q5 are turned on, power switches Q2, Q4, and Q6 are turned off, the input voltage Vin magnetizes the inductor L, and the first-stage output voltage V _OUT1 pairs the FLY capacitor C2 is charged, the second-stage output power supply V _OUT2 charges the FLY capacitor C4, the voltage of the switch node LX1 is clamped to the power ground by the power switch Q1, the voltage of the switch node LX2 is clamped to V _OUT1 by the power switch Q3, and the voltage of the switch node LX3 The voltage is clamped at V _OUT2 by the power switch Q5. Please refer to FIG. 6. FIG. 6 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention. As shown in Figure 6, in phase t3, the power switch Q1 is turned on, Q2-Q6 is turned off, the input voltage Vin magnetizes the inductor L, the voltage of the switch node LX1 is clamped to the power ground by the power switch Q1, and the switch node LX2 The voltage of the power switch Q3 is clamped to V _OUT1 -VD by the parasitic diode of the power switch Q3, and the voltage of the switch node LX3 is clamped to V _OUT2 -VD by the parasitic diode of the power switch Q5. Please refer to FIG. 7. FIG. 7 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention. As shown in Figure 7, in stage t4, the power switches Q1-Q6 are all disconnected, and the first demagnetization path of the inductor L: the first stage output capacitor C1 is discharged through the parasitic diode of the power switch Q2, and the voltage of the switch node LX1 is Clamped at V _OUT1 +VD; the second demagnetization path of the inductor L: discharges the second-stage output capacitor C3 through the FLY capacitor C2 and the parasitic diode of the power switch Q4, and the voltage of the switch node LX2 is clamped at V _OUT2 +VD; The third demagnetization path of the inductor L: The third-stage output capacitor C5 is discharged through the FLY capacitor 2, C4 and the parasitic diode of the power switch Q6, and the voltage of the switch node LX3 is clamped at V _OUT3 +VD. Please refer to FIG. 8. FIG. 8 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention. As shown in Figure 8, in stage t5, power switches Q1, Q3, and Q5 are turned off, Q2, Q4, and Q6 are turned on, and the first demagnetization path of inductor L: discharges first-stage output capacitor 1 through power switch Q2, The voltage of the switch node LX1 is clamped at V _OUT1 ; the second demagnetization path of the inductor L: the second-stage output capacitor C3 is discharged through the FLY capacitor C2 and the power switch Q4, and the voltage of the switch node LX2 is clamped at V _OUT2 ; The third demagnetization path of L: The third-stage output capacitor C5 is discharged through the FLY capacitor 2, C4 and the power switch Q6, and the voltage of the switch node LX3 is clamped at V _OUT3 . Please refer to FIG. 9. FIG. 9 is an equivalent schematic diagram of another driving circuit disclosed in an embodiment of the present invention. As shown in Figure 9, in stage t6, the power switches Q1-Q6 are all disconnected, and the first demagnetization path of the inductor L: the first stage output capacitor C1 is discharged through the parasitic diode of the power switch Q2, and the voltage of the switch node LX1 is Clamped at V _OUT1 +VD; the second demagnetization path of the inductor L: discharges the second-stage output capacitor C3 through the FLY capacitor C2 and the parasitic diode of the power switch Q4, and the voltage of the switch node LX2 is clamped at V _OUT2 +VD; The third demagnetization path of the inductor L: the third-stage output capacitor COUT3 is discharged through the FLY capacitors C2, C4 and the parasitic diode of the power switch Q6, and the voltage of the switch node LX3 is clamped at V _OUT3 +VD.

Please refer to FIG. 10, which is a schematic diagram of a waveform disclosed in an embodiment of the present invention. FIG 10 is a case where the inductance _L L of the continuous current I, power switches Q1-Q6 and the switching node of the waveform LX1-LX3. Please refer to FIG. 11. FIG. 11 is another waveform diagram disclosed in an embodiment of the present invention. FIG 11 is the inductor current I _L L interrupted, the power switches Q1-Q6 and the switching node of the waveform LX1-LX3.

The driving logic of the power tube Q1 is generated by the signal Q2_DE-Q6_DE phase “NOR” and the PWM_L phase “AND” and then generated by B1, the signal Q2_DE-Q6_DE respectively represents the falling edge delay signal of the output signal of B2-B6, and PWM_L represents low Terminal PWM logic, the power and ground of B1 are respectively connected to the input power and power ground, and the output signal of B1 generates a falling edge delay signal Q1_DE after passing through D1. The driving logic of the power tube Q2 is generated by the signals Q1_DE, Q3_DE and Q5_DE phase "NOR" and PWM_H phase "AND" and then through the low-voltage high-voltage converter and buffer to generate, PWM_H represents the high-end PWM logic, B2 power supply and ground are connected separately VBOOT1, LX1, and VBOOT1 are generated by the bootstrap circuit 1 related to LX1, and are characterized by a floating power supply with a constant difference from LX1. The output signal of B2 passes through a high-voltage and low-voltage converter and D2 to produce a falling edge delay signal Q2_DE. The driving logic of the power tube Q3 is generated by the signals Q2_DE, Q4_DE and Q6_DE phase "NOR" and PWM_L, Q1_DE phase "and" and then through the low-voltage high-voltage converter and buffer, the power and ground of B3 are connected to VCP1 and V _OUT1 respectively , VCP1 is generated by the first charge pump circuit, which is characterized by a power supply with a constant difference from V _OUT1 . The output signal of B3 passes through a high-voltage and low-voltage converter and D3 to produce a falling edge delay signal Q3_DE. The driving logic of the power tube Q4 is generated by the signals Q1_DE, Q3_DE and Q5_DE phase "NOR" and PWM_H phase "AND" and then through the low-voltage high-voltage converter and buffer, B4 power supply and ground are connected to VBOOT2 and LX2, VBOOT2 by The bootstrap circuit 2 related to LX2 is produced, which is characterized by a floating power supply with a constant difference from LX2, the output signal of B4 is a high-voltage and low-voltage converter and D4 generates a falling edge delay signal Q4_DE. The driving logic of the power tube Q5 is generated by the signals Q2_DE, Q4_DE and Q6_DE phase "NOR" and the signals PWM_L, Q1_DE phase "and" and then through the low-voltage high-voltage converter and buffer, the power and ground of B5 are connected to VCP2 and V respectively _OUT2 and VCP2 are generated by the second charge pump circuit, which are characterized by a power supply with a constant difference from V _OUT2 . The output signal of B5 passes through a high-voltage and low-voltage converter and D5 to produce a falling edge delay signal Q5_DE. The driving logic of the power tube Q6 is generated by the signals Q1_DE, Q3_DE and Q5_DE phase "NOR" and the signal PWM_H phase "AND" and then through the low-voltage high-voltage converter and buffer, B6 power and ground are connected to VBOOT3 and LX3, VBOOT3 Produced by the bootstrap circuit 3 related to LX3, which is characterized by a floating power supply with a constant difference with LX3, the output signal of B6 is a high voltage and low voltage converter and D6 generates a falling edge delay signal Q6_DE.

Similarly, the BOOST+CP architecture shown in Figure 2 is formed by cascading M+1-stage DC-DC converters. The first stage is a synchronous rectification DC-DC boost converter, and the second stage to the M+1th stage The stage is a charge pump. The relationship between the output voltage V _OUT1 of the first stage, the output voltage V _{OUT2 of the} second stage,..., the output voltage V _{OUTM+1 of} the M+1 stage can be expressed as:

Therefore, the constraints of the BOOST+CP architecture formed by cascading M+1 DC-DC converters are:

The BOOST+CP architecture formed by cascading M+1-level DC-DC converters includes: an inductor, 2(M+1) MOS high-voltage devices, M+1 voltage-regulating capacitors, and M FLY capacitors. The withstand voltage requirements of MOS high voltage devices should not be lower than V _OUT(M+1) /(M+1). One end of the inductor is connected to the input voltage Vin, and the other end of the inductor is connected to the switching node of the first-stage DC-DC converter; the stabilized capacitor C1 is connected to the output of the first-stage DC-DC converter, and the stabilized capacitor C3 is connected to the second-stage DC- The output terminal of the DC converter,..., the stabilized capacitor C2M+1 is connected to the output terminal of the M+1th stage DC-DC converter. One end of the FLY capacitor C2 is connected to the switch node of the first-stage DC-DC converter, the other end of the FLY capacitor C2 is connected to the switch node of the second-stage DC-DC converter, and one end of the FLY capacitor C4 is connected to the second-stage DC-DC converter The other end of the FLY capacitor C4 is connected to the switching node of the third-stage DC-DC converter,..., one end of the FLY capacitor C2M is connected to the switching node of the M-th DC-DC converter, and the other end of the FLY capacitor C2M is connected to the M-th Switch node of +1 level DC-DC converter.

In one embodiment, the power device included in the boost converter may also be a P-type MOS tube. In this case, the boost converter includes an inductor, a first MOS tube, a second MOS tube, and a first capacitor, where:

One end of the inductor is the input end of the drive circuit, the other end of the inductor is connected to the source of the first MOS transistor, the drain of the second MOS transistor and the first end of the first charge pump, the drain of the first MOS transistor and One end of the first capacitor is respectively used to connect to the ground, the source of the second MOS transistor is respectively connected to the other end of the first capacitor and the second end of the first charge pump, the gate of the first MOS transistor and the second MOS transistor The gates are respectively connected to the bias circuit.

In an embodiment, the power devices included in the M charge pumps may also be P-type MOS tubes. In this case, the jth charge pump in the M charge pumps includes the 2j+1th MOS tube, the 2j+2th MOS tube, and the 2jth MOS tube. The capacitance and the 2j+1th capacitance, j=1, 2, 3,...,M, where:

The drain of the 2k+1 MOS transistor is connected to the source of the 2kMOS transistor, one end of the 2k capacitor is connected to the drain of the 2kMOS transistor, and the source of the 2k+1 MOS transistor is respectively connected to the other end of the 2k capacitor and the 2k+2MOS. The drain of the tube and one end of the 2k+2 capacitor, the source of the 2k+2 MOS tube are respectively connected to the drain of the 2k+3 MOS tube and one end of the 2k+1 capacitor, and the source of the 2M+1 MOS tube is connected respectively The other end of the 2M capacitor and the drain of the 2M+2MOS transistor, the source of the 2M+2MOS transistor is connected to one end of the 2M+1 capacitor, the other end of the 2k+1 capacitor and the other end of the 2M+1 capacitor They are used to connect the ground terminal, the source of the 2M+2MOS transistor is the output terminal of the drive circuit, the gate of the 2j+1 MOS transistor and the gate of the 2j+2MOS transistor are respectively connected to the bias circuit, k=2,3, …, M-1.

It can be seen that when the power devices included in the boost converter and the M charge pumps are P-type MOS tubes, the MOS tubes in Figures 2 and 3 can be replaced by N-type MOS tubes with P-type MOS tubes. Its working principle The same, I won't repeat it here. In addition, the output end of the drive circuit in Figures 2 and 3 is connected to the input end of the WLED circuit. The drive circuit is only an application scenario for the WLED circuit. The drive circuit can also be applied to other applications that need to increase the voltage for driving. Scenes.

In addition, when the drive circuit structure is the same, the power conversion efficiency of the system using the N-type MOS tube is higher than that of the system using the P-type MOS tube.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in further detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. The protection scope, any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of the present invention shall be included in the protection scope of the present invention.

Claims (11)

A driving circuit, characterized by comprising a boost converter and M charge pumps, where M is an integer greater than or equal to 1, wherein: The boost converter is connected to the first charge pump among the M charge pumps, and the i-th charge pump among the M charge pumps is connected to the i-1th charge pump among the M charge pumps, i= 2,3,…,M; The boost converter is used to boost the first voltage input to the boost converter to a second voltage; The J-th charge pump is used to increase the voltage input to the J-th charge pump to the second voltage, and the J-th charge pump is any one of the M voltage pumps. 3. The driving circuit of claim 1, wherein the boost converter has a variable voltage boost ratio. The drive circuit according to claim 1 or 2, wherein the drive circuit further comprises a bias circuit, wherein: The bias circuit is respectively connected to the boost converter and the M charge pumps; The bias circuit is used to provide bias voltages for the boost converter and the M charge pumps. The driving circuit according to claim 3, wherein the boost converter comprises an inductor, a first metal oxide semiconductor MOS tube, a second MOS tube and a first capacitor, wherein: One end of the inductor is the input end of the drive circuit, and the other end of the inductor is respectively connected to the drain of the first MOS transistor, the source of the second MOS transistor, and the first charge pump. At the first end, the source of the first MOS transistor and one end of the first capacitor are respectively used to connect to the ground, and the drain of the second MOS transistor is respectively connected to the other end of the first capacitor and the The second end of the first charge pump, the gate of the first MOS tube and the gate of the second MOS tube are respectively connected to the bias circuit. The driving circuit according to claim 3, wherein the boost converter comprises an inductor, a first MOS tube, a second MOS tube and a first capacitor, wherein: One end of the inductor is the input end of the driving circuit, and the other end of the inductor is respectively connected to the source of the first MOS transistor, the drain of the second MOS transistor and the first charge pump. At the first end, the drain of the first MOS transistor and one end of the first capacitor are respectively used to connect to the ground, and the source of the second MOS transistor is respectively connected to the other end of the first capacitor and the The second end of the first charge pump, the gate of the first MOS tube and the gate of the second MOS tube are respectively connected to the bias circuit. The driving circuit of claim 4, wherein the jth charge pump in the M charge pumps includes a 2j+1th MOS tube, a 2j+2th MOS tube, a 2jth capacitor, and a 2j+1th capacitor, j =1,2,3,...,M, where: The source of the 2k+1 MOS transistor is connected to the drain of the 2k MOS transistor, one end of the 2k capacitor is connected to the source of the 2k MOS transistor, and the drain of the 2k+1 MOS transistor is respectively connected to the other of the 2k capacitor. One end, the source of the 2k+2 MOS transistor and one end of the 2k+2 capacitor, the drain of the 2k+2 MOS transistor is connected to the source of the 2k+3 MOS transistor and one end of the 2k+1 capacitor, respectively. The drain of the +1 MOS transistor is connected to the other end of the 2M capacitor and the source of the 2M+2 MOS transistor. The drain of the 2M+2 MOS transistor is connected to one end of the 2M+1 capacitor. The 2k+1 capacitor The other end of the 2M+1 capacitor and the other end of the 2M+1 capacitor are respectively used to connect to the ground, the drain of the 2M+2MOS transistor is the output terminal of the drive circuit, and the gate of the 2j+1 MOS transistor is The gates of the 2j+2th MOS transistors are respectively connected to the bias circuit, k=2, 3,..., M-1. The driving circuit according to claim 5, wherein the j-th charge pump in the M charge pumps includes a 2j+1th MOS tube, a 2j+2th MOS tube, a 2jth capacitor, and a 2j+1th capacitor. =1,2,3,...,M, where: The drain of the 2k+1 MOS transistor is connected to the source of the 2k MOS transistor, one end of the 2k capacitor is connected to the drain of the 2k MOS transistor, and the source of the 2k+1 MOS transistor is respectively connected to the other of the 2k capacitor. One end, the drain of the 2k+2 MOS transistor and one end of the 2k+2 capacitor, the source of the 2k+2 MOS transistor is connected to the drain of the 2k+3 MOS transistor and one end of the 2k+1 capacitor, respectively. The source of the +1 MOS transistor is respectively connected to the other end of the 2M capacitor and the drain of the 2M+2 MOS transistor. The source of the 2M+2 MOS transistor is connected to one end of the 2M+1 capacitor. The 2k+1 capacitor The other end of the 2M+1 capacitor and the other end of the 2M+1 capacitor are respectively used to connect to the ground, the source of the 2M+2MOS transistor is the output terminal of the driving circuit, the gate of the 2j+1 MOS transistor and The gates of the 2j+2th MOS transistor are respectively connected to the bias circuit, k=2, 3,..., M-1. The driving circuit according to claim 6 or 7, wherein the bias circuit comprises 2M+2 bias voltage circuits, wherein: The Lth bias voltage circuit is used to provide a bias voltage for the gate of the LMOS tube, L=1, 2,...,2M+2. 8. The driving circuit according to claim 8, wherein the L-th bias voltage circuit comprises an L-th XOR gate, an L-th AND gate, an L-th buffer, and an L-th delayer, and the p-th bias voltage The circuit also includes the p-1th low-voltage high-voltage converter and the p-1th high-voltage low-voltage converter, p=2,3,...,2M+2, where: The input terminal of the first exclusive OR gate is respectively connected to the output terminal of the p-th delayer, the input terminal of the first AND gate is connected to the output terminal of the first exclusive OR gate and the pulse low level respectively, and the input of the first buffer Terminal is connected to the output terminal of the first AND gate, the output terminal of the first buffer is respectively connected to the input terminal of the first delayer and the gate of the first MOS transistor, and the input terminal of the qth exclusive OR gate is respectively connected to The output terminal of the odd-numbered delayer among the 2M+2 delayers, the input terminal of the qth AND gate is respectively connected to the output terminal of the qth exclusive OR gate and the pulse high level, and the q-1th low voltage and high voltage The input end of the converter is connected to the output end of the qth AND gate, the input end of the qth buffer is connected to the output end of the q-1th low voltage and high voltage converter, and the output ends of the qth buffer are respectively connected to the first The gate of the qMOS tube and the input terminal of the q-1th high-voltage and low-voltage converter, the input terminal of the q-th delayer is connected to the output terminal of the q-1th high-voltage and low-voltage converter, and the input terminals of the r-th XOR gate respectively Connect the output terminal of the even-numbered delayer among the 2M+2 delayers, and the input terminal of the r-th AND gate is respectively connected to the output terminal of the r-th XOR gate, the pulse low level and the first delay The output terminal of the r-1th low-voltage and high-voltage converter is connected to the output terminal of the r-th AND gate, and the input terminal of the r-th buffer is connected to the output terminal of the r-1th low-voltage and high-voltage converter , The output end of the r-th buffer is connected to the gate of the r-th MOS tube and the input end of the r-1th high-voltage and low-voltage converter respectively, and the input end of the r-th delayer is connected to the r-1th high-voltage and low-voltage converter The output terminal of q=2,4,...,2M+2, r=3,5,...,2M+1. The drive circuit according to any one of claims 1-9, wherein the drive circuit further comprises a WLED circuit, the WLED circuit comprises N WLED light strings, the first WLED light string comprises H WLEDs, so The first WLED light string is any one of the N WLED light strings, and the N and the H are integers greater than 1, where: The H WLEDs are connected in series, the anode of the first WLED of the H WLEDs is connected to the M-th charge pump of the M charge pumps, and the cathode of the H-th WLED of the H WLEDs Used to connect to the ground. The driving circuit of claim 10, wherein the first WLED light string further comprises a MOS tube, wherein: The drain of the MOS tube is connected to the cathode of the H th WLED, and the source of the MOS tube is used to connect to the drain.

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