[go: up one dir, main page]

WO2020111422A1 - Substrat en semiconducteur transparent incolore et son procédé de fabrication - Google Patents

Substrat en semiconducteur transparent incolore et son procédé de fabrication Download PDF

Info

Publication number
WO2020111422A1
WO2020111422A1 PCT/KR2019/007221 KR2019007221W WO2020111422A1 WO 2020111422 A1 WO2020111422 A1 WO 2020111422A1 KR 2019007221 W KR2019007221 W KR 2019007221W WO 2020111422 A1 WO2020111422 A1 WO 2020111422A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
hole
transparent semiconductor
light
transparent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2019/007221
Other languages
English (en)
Korean (ko)
Inventor
서관용
이강민
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UNIST Academy Industry Research Corp
Original Assignee
UNIST Academy Industry Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020190049829A external-priority patent/KR102253547B1/ko
Application filed by UNIST Academy Industry Research Corp filed Critical UNIST Academy Industry Research Corp
Priority to US17/267,031 priority Critical patent/US11894476B2/en
Publication of WO2020111422A1 publication Critical patent/WO2020111422A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/10—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising photovoltaic cells in arrays in a single semiconductor substrate, the photovoltaic cells having vertical junctions or V-groove junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention was made with the funding of the Ministry of Trade, Industry and Energy under the task identification number 20183010013900 entitled “Development of Translucent Crystalline Silicon Solar Cell Element Technology for Various Colors”.
  • the present invention relates to a colorless transparent semiconductor substrate and a method for manufacturing the same.
  • semiconductor substrates including various semiconductor materials (for example, crystalline silicon, germanium, gallium arsenide (GaAs), and gallium arsenide (GaAsP)) are used.
  • a semiconductor substrate for example, a wafer
  • a semiconductor substrate made of these semiconductor materials is essentially opaque because it does not transmit the visible region.
  • crystalline silicon has been used as a material for solar cells and various electronic devices due to the richness and high stability of raw materials.
  • next-generation devices such as transparent electronic devices (e.g. transparent semiconductors, transparent displays).
  • transparent electronic devices e.g. transparent semiconductors, transparent displays
  • existing crystalline silicon-based semiconductor devices have limitations in constructing transparent electronic devices due to the opacity of crystalline silicon.
  • An embodiment of the present invention provides a colorless transparent semiconductor substrate that transmits all light in the visible light region, exhibits colorless transparency, and has an improved viewing angle.
  • a semiconductor substrate including a first surface and a second surface opposite to the first surface;
  • a transparent semiconductor substrate is provided that includes a through hole penetrating the semiconductor substrate, the through hole including an inclined portion inclined with respect to the first surface and the second surface.
  • the diameter of the through hole increases from the first surface to the second surface.
  • the cross section in the longitudinal direction of the through hole has a trapezoidal shape.
  • the inclined portion is configured to form an acute angle with respect to the first surface.
  • the diameter of the through hole in the first surface is 1 um or more
  • the diameter of the through hole in the first surface is defined such that the haze value calculated by Equation 1 below is less than 1%:
  • T d is the diffusion transmittance
  • T t is the total transmittance
  • the spacing S 1 of the through holes in the first surface is calculated by Equation 2 below:
  • L is the distance between the substrate and the observer.
  • the transparent semiconductor substrate further includes a light-reflecting layer.
  • the transparent semiconductor substrate further includes a light-reflecting layer disposed on the first surface, the inclined portion, and the second surface.
  • the transparent semiconductor substrate further includes a light-reflection layer.
  • the transparent semiconductor substrate further includes a light-reflection prevention layer disposed on the first surface, the inclined portion, and the second surface.
  • the semiconductor substrate includes crystalline silicon (c-Si), germanium (Ge), gallium arsenide (GaAs), gallium arsenide (GaAsP), amorphous silicon (a-Si), or a combination thereof. do.
  • the transparent semiconductor substrate further includes a passivation layer disposed on the first surface, the second surface, and the inclined portion.
  • the transparent semiconductor substrate further includes a passivation layer disposed to directly contact the first surface, the second surface, and the inclined portion.
  • the passivation layer includes an oxide, carbide, or nitride of one or more elements selected from metals, transition metals, and metalloids.
  • the total area of the through-holes in the first surface is 5% to 95% of the area of the semiconductor substrate, and the total area of the through-holes in the second surface is 6% to 96% of the area of the semiconductor substrate. It is formed, the total area of the through hole in the first surface is smaller than the total area of the through hole in the second surface.
  • the inclined portion is formed to form an acute angle with respect to the first surface.
  • the step of forming the through hole further comprising the step of forming a passivation layer.
  • the step of forming the passivation layer further comprising the step of forming a light-reflection layer or light-reflection layer.
  • a transparent semiconductor substrate includes a semiconductor substrate including a first surface and a second surface opposite to the first surface; By including a through hole penetrating the semiconductor substrate, the through hole includes an inclined portion inclined with respect to the first surface and the second surface, so that the viewing angle is widened, and a certain transparency can be maintained even at various viewing angles. .
  • FIG. 1 is a perspective view of a colorless transparent semiconductor substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the colorless transparent semiconductor substrate of FIG. 1 taken along line I-I'.
  • 3 is a perspective view showing the arrangement of through holes on the surface of the colorless transparent semiconductor substrate.
  • FIG. 4 is a view showing a correlation between the distance between the through holes on the surface of the colorless transparent semiconductor substrate and the distance between the observer and the substrate.
  • 5A and 5B are views showing a viewing angle of a substrate having a cylindrical through hole.
  • FIG. 6(a) and (b) are views showing a viewing angle of a substrate having a through hole having an inclined portion on an inner surface.
  • FIG. 7 is a perspective view of a colorless transparent semiconductor substrate according to another exemplary embodiment.
  • FIG. 8 is a graph showing a change in transmittance according to an etching time of a semiconductor substrate according to an embodiment.
  • FIG. 9 is a perspective view of a colorless transparent semiconductor substrate according to another exemplary embodiment.
  • FIG. 10 is a perspective view of a colorless transparent semiconductor substrate according to another exemplary embodiment.
  • FIG. 11 is a plan view schematically illustrating a solar cell manufactured by employing a colorless transparent semiconductor substrate according to an embodiment.
  • FIG. 12 is a cross-sectional view schematically showing a cross-section I-I' of FIG. 11.
  • Colorless means no color. For example, a color day corresponding to (0.2905, 0.2999), (0.3028, 0.3163), (0.3127, 0.3290), (0.3134, 0.3313), or (0.3324, 0.3474) as (x, y) coordinates in the CIE 1931 chromaticity diagram. Can be.
  • FIG. 1 is a plan view showing a colorless transparent semiconductor substrate according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view schematically showing a cross-section taken along line I-I' of FIG. 1.
  • a colorless transparent semiconductor substrate 10 includes a first surface 12 and a second surface 13, and between the first surface and the second surface
  • the thickness of the silicon substrate 10 includes a first surface 12, a second surface 13 and a plurality of through holes 11 penetrating through the thickness between the first surface and the second surface.
  • the through holes 11 may form an arbitrary pattern, but are not limited thereto.
  • the through holes 11 may be formed on the substrate while maintaining the same distance from each other.
  • the total area of the through-holes on the first surface 12 may be 5% to 95% of the total area of the semiconductor substrate, and the total area of the through-holes on the second surface 13 is 6 of the total area of the semiconductor substrate. % To 96%.
  • the total area of the through-holes on the first surface is smaller than the area of the through-holes on the second surface.
  • the through hole 11 has a side wall extending from the first surface 22 to the second surface 23 through the thickness of the substrate.
  • the side wall may include a first inclined portion 24 and a second inclined portion 25.
  • the first inclined portion 24 and the second inclined portion 25 may be configured to extend in a direction away from each other, but are not limited thereto, and may be configured to extend in parallel directions to each other.
  • the first inclined portion 24 may be configured to form an acute angle ⁇ 1 with respect to the first surface 22, and the second inclined portion 25 may be acute angle ⁇ with respect to the first surface 22. 2 ).
  • the acute angle ( ⁇ 1 ) and the acute angle ( ⁇ 2 ) may be the same or different from each other.
  • the viewing angle may be improved according to the size of the acute angle ⁇ 1 and the acute angle ⁇ 2 .
  • the cross section of the through hole 21 may have a pyramid shape, but is not limited thereto, and may have a parallelogram shape according to the size of the acute angle ⁇ 1 and the acute angle ⁇ 2 . Further, the plurality of through holes may have the same or different cross-sectional shape. When a plurality of through holes have the same cross-sectional shape, a constant viewing angle may be secured. When a plurality of through-holes have different cross-sectional shapes, it is possible to have different viewing angles depending on the viewing angle, and thus it is easy to adjust the transparency according to the viewing angles.
  • the through holes 21 have different diameters (a 1 ) and diameters (b 1 ) at the first and second surfaces.
  • the diameter a 1 may be smaller than the diameter b 1 .
  • the semiconductor substrate may include a plurality of through holes 21, the diameters (a 1 ) and (a 2 ) of the through holes may be different from each other, and the diameters (b 1 ) and (b 2 ) may be different from each other.
  • the diameters (a 1 ) and (a 2 ) are the same and the diameters (b 1 ) and (b 2 ) are the same from the viewpoint of securing an equal level of viewing angle according to the viewing angle. .
  • the through hole 21 may be manufactured by a method of etching a semiconductor substrate or a semiconductor deposition and growth method (for example, a polysilicon growth method).
  • the method of etching the semiconductor substrate may include dry etching or wet etching.
  • the through-hole 11 patterns a portion to be etched using a photolithography process on the first surface 12 of the semiconductor substrate 10. Thereafter, a metal mask layer is formed on the remaining first surface 12 that is not patterned through a metal mask deposition process, and the photoresist is removed. Thereafter, a plurality of through holes 11 are fabricated on the semiconductor substrate 10 by bringing SF 6 and C 4 F 8 gases into contact with the substrate. At this time, by adjusting the flow rates of the SF 6 and C 4 F 8 gas, the inclination of the inner surface of the through hole is adjusted.
  • the through hole 11 is patterned on the first surface 12 of the semiconductor substrate 10 using a photolithography process. Thereafter, a plurality of through holes are formed by immersing the semiconductor substrate in a basic etching solution or an acid etching solution.
  • a through hole is formed using the basic etching solution
  • a plurality of through holes are produced by immersing the substrate in a basic etching solution (eg, KOH) after the photolithography process.
  • a through hole is manufactured using the acidic etching solution (for example, a hydrofluoric acid/hydrogen peroxide solution or a nitric acid/hydrofluoric acid mixed solution)
  • the acidic etching solution for example, a hydrofluoric acid/hydrogen peroxide solution or a nitric acid/hydrofluoric acid mixed solution
  • metal is selectively selected from the first surface 12 to be etched.
  • a plurality of through holes are formed by immersing the substrate in an acidic etching solution.
  • the inclination of the inner surface of the through hole is adjusted according to the crystal structure of the semiconductor substrate and the concentration of the etching solution.
  • the diameter of the through hole is controlled by adjusting the immersion time of the substrate in the etching solution.
  • the diameter of the through hole on the first side is 113 seconds after 30 seconds. It is about 10% wider by ⁇ m.
  • the diameter of the through-hole becomes wide, the distance between the through-holes is relatively reduced, and as a result, light transmittance can be improved.
  • the change in the diameter of the through-hole and the change in the light transmittance according to the etching time were measured, and the results are shown graphically in FIG. 8. Referring to FIG. 8, it can be seen that as the etching time increases, the diameter of the through-hole increases, and as a result, the light transmittance increases.
  • the interval between scale the SiO 2 beads by; (RIE Reactive ion etch) to SiO 2 beads semiconductor deposition and growth method for example, placing a SiO 2 beads (beads) to a substrate, and a reactive ion etching After adjusting, depositing a semiconductor between SiO 2 beads by depositing a semiconductor material on the substrate, and removing the SiO 2 beads and the substrate, a semiconductor substrate having a through hole can be manufactured.
  • RIE Reactive ion etch reactive ion etch
  • FIG. 3 is a top view of the first surface of the semiconductor substrate viewed from a vertical direction with respect to the first surface.
  • the semiconductor substrate 30 includes a plurality of through holes 31, and the through holes 31 are disposed spaced apart from each other at regular intervals d 2 .
  • the through-holes 31 may be circular holes, as shown in FIG. 3, but are not limited thereto, and may be polygonal holes (not shown).
  • the size of each of the plurality of through-holes 31 may be formed to be 1 ⁇ m or more and 20 cm or less so that at least all light in the visible light region passes and can be manufactured by a photolithography process.
  • the diameter (d 1 ) of the through-hole 31 means the largest of the diameters of the circles or, in the case of polygons, line segments connecting two vertices. By configuring the diameter of the through hole 31 to be 1 ⁇ m or more, all visible light can be passed through.
  • the diameter (d 1) of the through-hole 31 may be greater than 100 ⁇ m, not less than the diameter (d 1) of the through-hole 31 100 ⁇ m, visible without the light-scattering and light-diffusing Since all the substrates can be transmitted, the transparency of the substrate 30 is improved.
  • the diameter d1 of the through hole 31 is 100 ⁇ m
  • the haze value calculated by the following Equation 1 is 0.95%, and it is confirmed that the haze value of the known glass is very close to the haze value of 0.85%. Therefore, it can be seen that when the diameter d1 of the through hole 31 is 100 ⁇ m or more, a transparent substrate such as glass can be obtained.
  • T d is the diffusion transmittance
  • T t is the total transmittance
  • the semiconductor substrate may have a colorless and transparent property because a specific color is not expressed.
  • the through hole 41 disposed in the semiconductor substrate should not be visually recognized. Specifically, if the distance S 1 between the through holes 41 satisfies Equation 2 below, the through holes are not visually recognized.
  • L is the distance between the observer and the substrate
  • S 1 is the distance between the through holes.
  • a colorless transparent semiconductor substrate can be obtained without depending on the thickness of the semiconductor substrate.
  • the gap S 1 of the through hole may be formed to be 200 ⁇ m or less, but is not limited thereto.
  • FIG 5 and 6 are views showing a difference in viewing angles between a conventional semiconductor substrate 50 having a cylindrical through hole and a semiconductor substrate 60 having a through hole according to an embodiment of the present invention.
  • the viewing angle is limited. That is, as shown in Fig. 5 (a), the viewing angle ⁇ 1 in the semiconductor substrate 50 having a conventional cylindrical through hole is limited. In addition, in order to widen the viewing angle, it is important not to recognize the thickness portion of the through hole 51 in the field of view, so the thickness of the semiconductor substrate 50 must be reduced.
  • the viewing angle ⁇ 2 is shown in FIG. 5(a).
  • the viewing angle ( ⁇ 1 ) Compared to the viewing angle ( ⁇ 1 ).
  • FIG. 7 is a perspective view of a colorless transparent semiconductor substrate according to another exemplary embodiment.
  • a colorless transparent semiconductor substrate 70 includes a first surface 72 and a second surface 73, and a thickness 74 between the first surface and the second surface
  • the silicon substrate 70 includes a first surface 72, a second surface 73, and a plurality of through holes 71 penetrating the thickness between the first surface and the second surface.
  • the light-reflection layer may reduce the reflectance of light reflected by the surface of the silicon substrate among the incident light.
  • the light-reflective layer for example, a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, MgF 2, ZnS, TiO 2, and at least any one of a single layer or two groups selected from the group consisting of CeO 2 It may have a multilayer film structure in which the films are combined.
  • the coating layer 75 for example, the anti-reflection layer is formed to cover the first surface 72, the inner surface of the plurality of through holes 71, and the second surface 73, so that the first surface and the second In addition to reducing the light reflection from the surface, it also reduces the reflection of light passing through the through-hole 71.
  • the light-reflection layer may include a surface structure of various irregularities such as a pyramid, a square, and a triangle on the surface.
  • the surface structure may be formed by a method of increasing the surface roughness of the light-reflecting layer by various methods such as dry/wet etching.
  • the transparency of the silicon crystalline substrate is improved from the introduction of such a light-reflecting layer.
  • the light-reflecting layer may increase reflectance of light incident on the semiconductor substrate.
  • the light-reflecting layer may include a metal coating or metal flake having high surface reflectivity.
  • the metal includes all metals that can reflect light such as Al, Ag, and Au.
  • the light-reflecting layer can be formed by polishing the surface of the semiconductor substrate.
  • the light-reflection layer and the light-reflection layer are sputtering, e-beam evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic Chemical vapor deposition (MOCVD; metal-organic chemical vapor deposition), molecular beam epitaxy (MBE; molecular beam epitaxy), and may be formed by a method such as atomic layer deposition (Atomic Layer Deposition), but is not limited thereto.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • MOCVD metal organic Chemical vapor deposition
  • MBE molecular beam epitaxy
  • Atomic Layer Deposition atomic layer deposition
  • FIG. 9 is a perspective view of a colorless transparent semiconductor substrate according to another exemplary embodiment.
  • the colorless transparent semiconductor substrate 90 includes a first surface 92 and a second surface 93, has a thickness 94 between the first surface and the second surface, and the silicon
  • the substrate 90 includes a first surface 92, a second surface 93, and a plurality of through holes 91 penetrating the thickness between the first surface and the second surface. It further includes a coating layer 95' covering the inner surface of the plurality of through holes 91 penetrating through the second surface and the thickness 94 between the first and second surfaces.
  • the coating layer 95' may include a passivation layer.
  • the passivation layer may passivate defects present on the surface of the substrate and reduce reflectance of incident sunlight. When the defect present on the substrate surface is immobilized, the surface can be stabilized, thereby increasing the implied open voltage (Implied Voc). For example, when the passivation layer was not applied to the same semiconductor substrate surface, the implicit open voltage was 517 mV, but when the passivation layer was applied, the implicit open voltage was increased to 536 mV.
  • the solar reflectance is reduced and the amount of light reaching the PN junction is increased to increase the short circuit current of the solar cell, and as a result, the photoelectric conversion efficiency of the solar cell may be improved.
  • the passivation layer is sputtering, e-beam evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD) metal- organic chemical vapor deposition (MBE), molecular beam epitaxy (MBE), and atomic layer deposition (Atomic Layer Deposition).
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MBE metal- organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • atomic layer deposition Atomic Layer Deposition
  • FIG. 10 is a perspective view of a colorless transparent semiconductor substrate according to another exemplary embodiment.
  • the colorless transparent semiconductor substrate 100 includes a first surface 102 and a second surface 103, has a thickness 104 between the first surface and the second surface, and the silicon
  • the substrate 100 includes a first surface 102, a second surface 103, and a plurality of through holes 101 penetrating the thickness between the first surface and the second surface. It further includes a first coating layer 105 and a second coating layer 106 covering the inner surfaces of the plurality of through holes 101 penetrating the second surface and the thickness 104 between the first surface and the second surface.
  • the first coating layer and the second coating layer may be disposed to contact each other, and the first coating layer may be disposed to directly contact the first surface, the second surface, and the inner surface of the through hole.
  • the second coating layer may be disposed on the first coating layer.
  • the first coating layer 105 is a passivation layer
  • the second coating layer 106 may be a light-reflection prevention layer or a light-reflection layer.
  • the passivation layer, the light-reflection prevention layer, and the light-reflection layer refer to the foregoing.
  • the above-described transparent semiconductor substrate is a variety of electronic devices using a semiconductor substrate, for example, a memory semiconductor, a non-memory semiconductor, a device including an electronic circuit, a solar cell, an organic light emitting device, a light emitting device (LED ), lighting devices, etc.
  • a semiconductor substrate for example, a memory semiconductor, a non-memory semiconductor, a device including an electronic circuit, a solar cell, an organic light emitting device, a light emitting device (LED ), lighting devices, etc.
  • FIG. 11 is a perspective view of a solar cell manufactured using a colorless transparent semiconductor substrate according to an embodiment.
  • the solar cell 1100 includes a colorless transparent semiconductor substrate 110, a first layer 120 positioned on a first surface S1 of the semiconductor substrate 110, and a first surface ( The second layer 130 positioned on the second surface S2 of the semiconductor substrate 110 opposite to S1), the first electrode positioned on the first layer 120 and connected to the first layer 120 A portion 140 and a second electrode portion 150 positioned on the second layer 130 and connected to the second layer 130 may be included.
  • the solar cell 100 may further include an anti-reflection film 160 and a protective film 170 positioned on the first layer 120.
  • the colorless transparent semiconductor substrate may be an N-type or P-type crystalline silicon semiconductor substrate.
  • the crystalline silicon semiconductor substrate may be doped with Group 5 elements P, As, Sb, etc. as N-type impurities.
  • the crystalline silicon semiconductor substrate may be implemented as a P-type by doping B, Ga, In, etc., a group 3 element as a P-type impurity.
  • the light receiving surface of the semiconductor substrate may include various types of uneven structures (not shown) such as a pyramid, a square, and a triangle.
  • the uneven structure reduces the reflectance of light incident on the semiconductor substrate, so that the photoelectric change efficiency of the solar cell 1100 can be improved.
  • the first layer 120 may form a P-N junction with the semiconductor substrate 110.
  • the first layer 120 may be an emitter layer formed by doping impurities having a second conductivity type on the semiconductor substrate 110. Therefore, the first surface S1 of the semiconductor substrate 110 is not a clearly divided region, and may be understood as a region where P-N bonding is performed.
  • the first layer 120 when the semiconductor substrate 110 is doped with an N-type impurity, the first layer 120 may be doped with a P-type impurity. Conversely, when the semiconductor substrate 110 is doped with a P-type impurity, the first The first layer 120 may be doped with N-type impurities. As described above, when the first layer 120, which is an emitter layer, and the crystalline silicon semiconductor substrate 110 have opposite conductivity types, a PN junction is formed at the interface between the semiconductor substrate 110 and the first layer 120. When the light is irradiated to the PN junction, photovoltaic power may be generated by the photoelectric effect.
  • the second layer 130 may be, for example, a back surface layer (BSF) formed by doping impurities having a first conductivity type on the semiconductor substrate 110. Therefore, the second surface S2 of the semiconductor substrate 110 is not a clearly distinguished region, and may be understood as a region partitioning the rear electric field layer BSF from the semiconductor substrate 110.
  • BSF back surface layer
  • the second layer 130 which is a back surface layer (BSF) can prevent carriers from moving to the rear surface of the semiconductor substrate 110 and recombining, thereby increasing the open voltage (Voc) of the solar cell 1100.
  • the efficiency of the solar cell 1100 may be improved.
  • the first electrode unit 140 and the second electrode unit 150 collect carriers generated by irradiation of light, and serve as a movement path through which the carrier moves to an external electronic device electrically connected to the solar cell 1100.
  • the first electrode unit 140 may be located on the light-receiving surface of the solar cell 1100, wherein the first electrode unit 140 may have a micro grid pattern.
  • the line width of the micro grid pattern may be 5 ⁇ m to 1 mm, whereby the aperture ratio of the first electrode unit 140 may be formed to be 90% or more. Therefore, it is possible to minimize the phenomenon that the light incident by the first electrode unit 140 is obscured.
  • the second electrode unit 150 has the same shape as the second surface S2 of the crystalline silicon semiconductor substrate 110 and may be formed on the entire bottom surface of the solar cell 1100.
  • the semiconductor substrate 110 may include a plurality of through holes H penetrating the semiconductor substrate 110 from the first surface S1 to the second surface S2.
  • the plurality of through holes H may extend to penetrate at least the first layer 120, the second layer 130, and the second electrode unit 150.
  • the first electrode part 140 having the micro grid pattern may be positioned between the plurality of through holes H. Accordingly, some of the light incident on the solar cell 1100 passes through the plurality of through holes H, so that the solar cell 1100 may have light transmittance.
  • the solar cell 1100 according to an embodiment of the present invention can control the transparency, that is, the brightness of the solar cell 1100 by adjusting the filling fraction.
  • Filling Fraction refers to a value obtained by subtracting the total area of the plurality of through holes H from the area of the semiconductor substrate 110 divided by the area of the crystalline silicon semiconductor substrate 110.
  • the solar cell 1100 according to an embodiment of the present invention decreases in transmittance.
  • the solar cell 1100 may gradually have dark properties.
  • the solar cell 1100 according to an embodiment of the present invention can adjust the transmittance, that is, the transparency according to various environments to which the solar cell 1100 is applied.
  • the transparency of the solar cell 1100 may be set differently when the solar cell 1100 according to the embodiment of the present invention is applied to a sunroof of an automobile and when applied to a window of a building.
  • Table 1 below shows the photoelectric conversion efficiency of the solar cell 1100 according to the total area of the plurality of through-holes H, where the total area of the plurality of through-holes H can be expressed as a filling fraction.
  • the efficiency of the solar cell 1100 improves.
  • the transmittance of the solar cell 1100 decreases, so that the filling fraction can be reduced to increase the transparency of the solar cell 1100.
  • the efficiency of the solar cell 1100 becomes less than 5%, which is not preferable.
  • the Filling Fraction is 95% or more, it is difficult for the solar cell 1100 to maintain transmittance.
  • the total area of the plurality of through holes H may be formed to be greater than 5% to 60% or less of the area of the semiconductor substrate 110, and preferably 20 in consideration of the efficiency and transmittance of the solar cell 1100. % Or more and 50% or less.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

La présente invention concerne un substrat en semiconducteur transparent et son procédé de fabrication, le substrat en semiconducteur transparent comprenant : un substrat en semiconducteur qui comporte une première surface et une deuxième surface opposée à la première surface ; et un trou traversant qui pénètre dans le substrat en semiconducteur. Le trou traversant comprend une portion inclinée par rapport à la première surface et à la deuxième surface, et la présente invention réalise un semiconducteur transparent incolore qui transmet toute la lumière dans une région de lumière visible de façon à avoir une transparence incolore et un angle de vue amélioré.
PCT/KR2019/007221 2018-11-29 2019-06-14 Substrat en semiconducteur transparent incolore et son procédé de fabrication Ceased WO2020111422A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/267,031 US11894476B2 (en) 2018-11-29 2019-06-14 Colorless transparent semiconductor substrate and method for manufacturing same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20180150847 2018-11-29
KR10-2018-0150847 2018-11-29
KR10-2019-0049829 2019-04-29
KR1020190049829A KR102253547B1 (ko) 2018-11-29 2019-04-29 무색 투명 반도체 기판 및 이의 제조방법

Publications (1)

Publication Number Publication Date
WO2020111422A1 true WO2020111422A1 (fr) 2020-06-04

Family

ID=70854082

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2019/007221 Ceased WO2020111422A1 (fr) 2018-11-29 2019-06-14 Substrat en semiconducteur transparent incolore et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2020111422A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230207399A1 (en) * 2020-05-11 2023-06-29 Shin-Etsu Handotai Co., Ltd. Method for dry-etching semiconductor substrate and method for dry-etching silicon oxide film

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020000813A (ko) * 2000-03-22 2002-01-05 마치오 나카지마 구멍 구조체 및 구멍 구조체의 제조 방법
US20050099577A1 (en) * 2002-08-21 2005-05-12 Samsung Electronics Co., Ltd. Substrate, liquid crystal display device, and method of manufacturing the same
KR20090031232A (ko) * 2007-09-21 2009-03-25 가부시끼가이샤 도시바 극미세 구조를 갖는 광투과형 금속 전극 및 그의 제조 방법
US20100194091A1 (en) * 2006-10-24 2010-08-05 Giesecke & Devrient Gmbh See-through security element with microstructures
KR20100097150A (ko) * 2007-12-14 2010-09-02 선파워 코포레이션 후면 접촉 태양 전지를 위한 높은 광 흡수 층을 갖는 반사 방지 코팅

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020000813A (ko) * 2000-03-22 2002-01-05 마치오 나카지마 구멍 구조체 및 구멍 구조체의 제조 방법
US20050099577A1 (en) * 2002-08-21 2005-05-12 Samsung Electronics Co., Ltd. Substrate, liquid crystal display device, and method of manufacturing the same
US20100194091A1 (en) * 2006-10-24 2010-08-05 Giesecke & Devrient Gmbh See-through security element with microstructures
KR20090031232A (ko) * 2007-09-21 2009-03-25 가부시끼가이샤 도시바 극미세 구조를 갖는 광투과형 금속 전극 및 그의 제조 방법
KR20100097150A (ko) * 2007-12-14 2010-09-02 선파워 코포레이션 후면 접촉 태양 전지를 위한 높은 광 흡수 층을 갖는 반사 방지 코팅

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230207399A1 (en) * 2020-05-11 2023-06-29 Shin-Etsu Handotai Co., Ltd. Method for dry-etching semiconductor substrate and method for dry-etching silicon oxide film

Similar Documents

Publication Publication Date Title
AU2006242030B2 (en) Solar cell manufacturing method, solar cell, and semiconductor device manufacturing method
WO2010013972A2 (fr) Pile solaire et procédé de fabrication correspondant
WO2010104340A2 (fr) Cellule solaire et son procédé de fabrication, et procédé de formation de région d'impureté
WO2010093177A2 (fr) Cellule solaire et procédé de fabrication associé
WO2010147260A1 (fr) Pile solaire et procédé de fabrication associé
EP0334330A2 (fr) Elément de conversion opto-électrique et méthode de fabrication
WO2009104899A2 (fr) Procédés d'attaque de tranche asymétrique, photopile comprenant la tranche ainsi attaquée et procédé de fabrication correspondant
WO2011136488A2 (fr) Cellule solaire
WO2011122853A2 (fr) Dispositif photovoltaïque solaire et son procédé de production
CN101443893A (zh) 背面触点太阳能电池及制造方法
WO2015041470A1 (fr) Cellule solaire
WO2015041467A1 (fr) Cellule solaire et son procédé de fabrication
WO2010114314A2 (fr) Appareil de génération d'énergie à photopiles et son procédé de fabrication
WO2015046845A1 (fr) Cellule solaire
WO2012093845A2 (fr) Photopiles et leur procédé de fabrication
WO2011129503A1 (fr) Cellule solaire et procédé de fabrication associé
KR102253547B1 (ko) 무색 투명 반도체 기판 및 이의 제조방법
WO2015102409A1 (fr) Dispositif pour fabriquer une cellule solaire à couche mince intégrée
KR100994924B1 (ko) 태양전지 및 그 제조방법
WO2020111422A1 (fr) Substrat en semiconducteur transparent incolore et son procédé de fabrication
WO2011002130A1 (fr) Cellule solaire et son procédé de fabrication
WO2014204182A1 (fr) Cellule solaire
KR102509612B1 (ko) 양면 투광성 향상을 위한 투명 반도체 기판 및 그 제조방법
JP2000261009A (ja) 集積型光起電力装置
WO2019102073A1 (fr) Structure semi-conductrice photovoltaïque

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19888458

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19888458

Country of ref document: EP

Kind code of ref document: A1