WO2020195757A1 - Display device - Google Patents

Abstract

The present invention provides a display device that makes it possible to visually recognize an image displayed using a light source from one surface of a display panel, together with a background on the other surface on the reverse side, and reduce light leakage from a switching element. This display device is provided with: a liquid crystal layer having polymer dispersed liquid crystal filled between an array substrate and an opposite substrate; and a light source disposed such that light enters a side surface of the array substrate or a side surface of the opposite substrate. In a region surrounded by scanning lines and signal lines, a region having an organic insulating layer with a smaller thickness than that of the organic insulating layer overlapping the scanning line and the signal line in plan view is present. A first inclined surface of the organic insulating layer, which is located closer to the light source than the switching element in plan view, is covered with a metallic layer. A second inclined surface of the organic insulating layer, which is located farther from the light source than the switching element, is covered with a metallic layer.

Description

Display device

This disclosure relates to a display device.

Patent Document 1 describes a first translucent substrate, a second translucent substrate arranged so as to face the first translucent substrate, a first translucent substrate, and a second translucent substrate. A display including a liquid crystal layer having a polymer-dispersed liquid crystal enclosed between them, and at least one light emitting portion arranged so as to face at least one side surface of the first translucent substrate and the second translucent substrate. The device is described.

Japanese Unexamined Patent Publication No. 2018-021974

In the display device described in Patent Document 1, the background on the other side of the display panel can be visually recognized from one side of the display panel. Since the light source is arranged to face at least one side surface of the first translucent substrate and the second translucent substrate, it is necessary to reduce the light leakage of the switching element due to the light source.

An object of the present invention is to provide a display device capable of visually recognizing an image displayed by using a light source from one surface of a display panel together with a background on the other surface side of the opposite side and reducing optical leakage of a switching element. To do.

The display device according to one aspect is arranged so that light enters the array substrate, the opposing substrate, the liquid crystal layer between the array substrate and the opposing substrate, and the side surface of the array substrate or the side surface of the opposing substrate. The array substrate includes a plurality of signal lines arranged at intervals in the first direction, a plurality of scanning lines arranged at intervals in the second direction, and the scanning lines and the signal lines. It has a switching element connected to, at least an organic insulating layer covering the switching element, and a metal layer provided so as to be superimposed on the organic insulating layer, and is surrounded by the scanning line and the signal line. In the region, there is a region in which the thickness of the organic insulating layer is smaller than the thickness of the organic insulating layer overlapping the scanning line and the signal line in a plan view, and is closer to the light source than the switching element. The first slope of the organic insulating layer is covered with the metal layer, and the second slope of the organic insulating layer on the side farther from the light source than the switching element is covered with the metal layer.

FIG. 1 is a perspective view showing an example of a display device according to the present embodiment. FIG. 2 is a block diagram showing the display device of the first embodiment. FIG. 3 is a timing chart illustrating the timing at which the light source emits light in the field sequential method of the first embodiment. FIG. 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrodes and the scattering state of the pixels. FIG. 5 is a cross-sectional view showing an example of a cross section of the display device of FIG. FIG. 6 is a plan view showing a plane of the display device of FIG. FIG. 7 is an enlarged cross-sectional view of the liquid crystal layer portion of FIG. FIG. 8 is a cross-sectional view for explaining a non-scattering state in the liquid crystal layer. FIG. 9 is a cross-sectional view for explaining a scattering state in the liquid crystal layer. FIG. 10 is a plan view showing scanning lines, signal lines, and switching elements in pixels. FIG. 11 is a plan view showing a holding capacitance layer in the pixel. FIG. 12 is a plan view showing the auxiliary metal layer and the opening region in the pixel. FIG. 13 is a plan view showing pixel electrodes in pixels. FIG. 14 is a plan view showing a light-shielding layer in the pixel. FIG. 15 is a cross-sectional view of XV-XV'of FIG. FIG. 16 is a cross-sectional view of XVI-XVI'of FIG. FIG. 17 is a cross-sectional view of XVII-XVII'of FIG. FIG. 18 is a cross-sectional view of the peripheral region. FIG. 19 is a plan view showing the pixels of the second embodiment. FIG. 20 is a plan view showing a plane of the display device of the third embodiment. FIG. 21 is a plan view showing scanning lines, signal lines, and switching elements in the pixels of the third embodiment. FIG. 22 is a cross-sectional view of XXII-XXII'of FIG.

The embodiment (embodiment) for carrying out the present disclosure will be described in detail with reference to the drawings. The disclosure is not limited by the content described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the disclosure are naturally included in the scope of the present disclosure. In addition, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present disclosure is used. It is not limited. Further, in the present specification and each of the drawings, the same elements as those described above with respect to the above-described drawings may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(Embodiment 1)
FIG. 1 is a perspective view showing an example of a display device according to the present embodiment. FIG. 2 is a block diagram showing the display device of FIG. FIG. 3 is a timing chart for explaining the timing at which the light source emits light in the field sequential method.

As shown in FIG. 1, the display device 1 includes a display panel 2, a light source 3, and a drive circuit 4. Here, one direction of the plane of the display panel 2 is the PX direction, the direction orthogonal to the PX direction is the second direction PY, and the direction orthogonal to the PX-PY plane is the third direction PZ.

The display panel 2 includes an array substrate 10, a counter substrate 20, and a liquid crystal layer 50 (see FIG. 5). The facing substrate 20 faces the direction perpendicular to the surface of the array substrate 10 (PZ direction shown in FIG. 1). In the liquid crystal layer 50 (see FIG. 5), the polymer-dispersed liquid crystal LC described later is sealed by the array substrate 10, the opposing substrate 20, and the sealing portion 18.

As shown in FIG. 1, in the display panel 2, there are a display area AA on which an image can be displayed and a peripheral area FR outside the display area AA. A plurality of pixel Pix are arranged in a matrix in the display area AA. In the present disclosure, the row means a pixel row having m pixel Pix arranged in one direction. Further, the column refers to a pixel column having n pixel Pix arranged in a direction orthogonal to the direction in which the rows are arranged. Then, the values of m and n are determined according to the display resolution in the vertical direction and the display resolution in the horizontal direction. Further, a plurality of scanning lines GL are wired for each row, and a plurality of signal lines SL are wired for each column.

The light source 3 includes a plurality of light emitting units 31. As shown in FIG. 2, the light source control unit 32 is included in the drive circuit 4. The light source control unit 32 may be a circuit different from the circuit of the drive circuit 4. The light emitting unit 31 and the light source control unit 32 are electrically connected by wiring in the array substrate 10.

As shown in FIG. 1, the drive circuit 4 is fixed to the surface of the array substrate 10. As shown in FIG. 2, the drive circuit 4 includes a signal processing circuit 41, a pixel control circuit 42, a gate drive circuit 43, a source drive circuit 44, and a common potential drive circuit 45. The array substrate 10 has a larger XY plane area than the opposing substrate 20, and a drive circuit 4 is provided on an overhanging portion of the array substrate 10 exposed from the opposing substrate 20.

An input signal (RGB signal, etc.) VS is input to the signal processing circuit 41 from the image output unit 91 of the external upper control unit 9 via the flexible board 92.

The signal processing circuit 41 includes an input signal analysis unit 411, a storage unit 412, and a signal adjustment unit 413. The input signal analysis unit 411 generates a second input signal VCS based on the first input signal VS input from the outside.

The second input signal VCS is a signal that determines what kind of gradation value is given to each pixel Pix of the display panel 2 based on the first input signal VS. In other words, the second input signal VCS is a signal including gradation information regarding the gradation value of each pixel Pix.

The signal adjustment unit 413 generates the third input signal VCSA from the second input signal VCS. The signal adjustment unit 413 sends the third input signal VCSA to the pixel control circuit 42, and sends the light source control signal LCSA to the light source control unit 32. The light source control signal LCSA is, for example, a signal including information on the amount of light of the light emitting unit 31 set according to the input gradation value to the pixel Pix. For example, when a dark image is displayed, the amount of light of the light emitting unit 31 is set small. When a bright image is displayed, the amount of light of the light emitting unit 31 is set large.

Then, the pixel control circuit 42 generates a horizontal drive signal HDS and a vertical drive signal VDS based on the third input signal VCSA. In the present embodiment, since the drive is performed in a field sequential manner, the horizontal drive signal HDS and the vertical drive signal VDS are generated for each color in which the light emitting unit 31 can emit light.

The gate drive circuit 43 sequentially selects the scan line GL of the display panel 2 within one vertical scan period based on the horizontal drive signal HDS. The order of selection of the scanning lines GL is arbitrary.

The source drive circuit 44 supplies a gradation signal corresponding to the output gradation value of each pixel Pix to each signal line SL of the display panel 2 within one horizontal scanning period based on the vertical drive signal VDS.

In the present embodiment, the display panel 2 is an active matrix type panel. Therefore, it has a signal (source) line SL extending in the second direction PY and a scanning (gate) line GL extending in the first direction PX in a plan view, and is an intersection of the signal line SL and the scanning line GL. Has a switching element Tr.

A thin film transistor is used as the switching element Tr. As an example of the thin film transistor, a bottom gate type transistor or a top gate type transistor may be used. A single-gate thin film transistor is exemplified as the switching element Tr, but a double-gate transistor may also be used. One of the source electrode and the drain electrode of the switching element Tr is connected to the signal line SL, the gate electrode is connected to the scanning line GL, and the other of the source electrode and the drain electrode is the capacitance of the polymer-dispersed liquid crystal LC described later. It is connected to one end of. One end of the capacitance of the polymer-dispersed liquid crystal LC is connected to the switching element Tr via the pixel electrode PE, and the other end is connected to the common potential wiring COML via the common electrode CE. Further, a holding capacitance HC is generated between the pixel electrode PE and the holding capacitance electrode IO electrically connected to the common potential wiring COML. The common potential wiring COML is supplied from the common potential drive circuit 45.

The light emitting unit 31 includes a first color (for example, red) light emitting body 33R, a second color (for example, green) light emitting body 33G, and a third color (for example, blue) light emitting body 33B. Based on the light source control signal LCSA, the light source control unit 32 controls each of the first color illuminant 33R, the second color illuminant 33G, and the third color illuminant 33B to emit light in a time-division manner. As described above, the first color illuminant 33R, the second color illuminant 33G, and the third color illuminant 33B are driven by the field sequential method.

As shown in FIG. 3, in the first subframe (first predetermined time) RF, the first color illuminant 33R emits light in the first color emission period RON, and is selected within one vertical scanning period GateScan. Pixel Pix scatters and displays light. In the entire display panel 2, if a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the above-mentioned signal lines SL to the pixel Pix selected in one vertical scanning period GateScan, the first Only the first color is lit during the color emission period RON.

Next, in the second subframe (second predetermined time) GF, the second color illuminant 33G emits light in the second color emission period GON, and the pixel Pix selected in one vertical scanning period GateScan emits light. Is scattered and displayed. In the entire display panel 2, if a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the above-mentioned signal lines SL to the pixel Pix selected in one vertical scanning period GateScan, the second Only the second color is lit during the color emission period GON.

Further, in the third subframe (third predetermined time) BF, the light emitting body 33B of the third color emits light in the light emitting period BON of the third color, and the pixel Pix selected in one vertical scanning period GateScan emits light. Display in a scattered manner. In the entire display panel 2, if a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the above-mentioned signal lines SL to the pixel Pix selected in one vertical scanning period GateScan, a third display panel 2 is used. Only the third color is lit during the color emission period BON.

The human eye has a time resolution limitation and an afterimage occurs, so a composite image of three colors is recognized in a period of one frame (1F). In the field sequential method, the color filter can be eliminated and the absorption loss in the color filter is reduced, so that high transmittance can be realized. In the color filter method, one pixel is created by subpixels in which the pixel Pix is divided for each of the first color, the second color, and the third color, whereas in the field sequential method, such subpixel division is not necessary. Good. It should be noted that a fourth subframe may be further provided, and a fourth color different from the first color, the second color, and the third color may be emitted.

FIG. 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrodes and the scattering state of the pixels. FIG. 5 is a cross-sectional view showing an example of a cross section of the display device of FIG. FIG. 6 is a plan view showing a plane of the display device of FIG. FIG. 5 is a VV'cross section of FIG. FIG. 7 is an enlarged cross-sectional view of the liquid crystal layer portion of FIG. FIG. 8 is a cross-sectional view for explaining a non-scattering state in the liquid crystal layer. FIG. 9 is a cross-sectional view for explaining a scattering state in the liquid crystal layer.

1 If the pixel Pix selected in the vertical scanning period GateScan is supplied with a gradation signal corresponding to the output gradation value of each pixel Pix to each of the above-mentioned signal lines SL, the pixel electrode is supplied according to the gradation signal. The voltage applied to the PE changes. When the voltage applied to the pixel electrode PE changes, the voltage between the pixel electrode PE and the common electrode CE changes. Then, as shown in FIG. 4, the scattering state of the liquid crystal layer 50 for each pixel Pix is controlled according to the voltage applied to the pixel electrode PE, and the scattering ratio in the pixel Pix changes.

As shown in FIG. 4, when the voltage applied to the pixel electrode PE is equal to or higher than the saturation voltage Vsat, the change in the scattering ratio in the pixel Pix becomes small. Therefore, the drive circuit 4 changes the voltage applied to the pixel electrode PE according to the vertical drive signal VDS in the voltage range Vdr lower than the saturation voltage Vsat.

As shown in FIGS. 5 and 6, the array substrate 10 includes a first main surface 10A, a second main surface 10B, a first side surface 10C, a second side surface 10D, a third side surface 10E, and a fourth side surface 10F. The first main surface 10A and the second main surface 10B are parallel planes. Further, the first side surface 10C and the second side surface 10D are parallel planes. The third side surface 10E and the fourth side surface 10F are parallel planes.

As shown in FIGS. 5 and 6, the facing substrate 20 includes a first main surface 20A, a second main surface 20B, a first side surface 20C, a second side surface 20D, a third side surface 20E, and a fourth side surface 20F. The first main surface 20A and the second main surface 20B are parallel planes. The first side surface 20C and the second side surface 20D are parallel planes. The third side surface 20E and the fourth side surface 20F are parallel planes.

As shown in FIGS. 5 and 6, the light source 3 faces the second side surface 20D of the facing substrate 20. The light source 3 is sometimes called a side light source. As shown in FIG. 5, the light source 3 irradiates the second side surface 20D of the facing substrate 20 with the light source light L. The second side surface 20D of the facing substrate 20 facing the light source 3 is a light incident surface.

As shown in FIG. 5, the light source light L emitted from the light source 3 is reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the opposing substrate 20, and is directed away from the second side surface 20D. Propagate in the second direction PY). When the light source light L is directed to the outside from the first main surface 10A of the array substrate 10 or the first main surface 20A of the opposing substrate 20, it travels from the medium having a large refractive index to the medium having a small refractive index. If the incident angle incident on the first main surface 10A of the array substrate 10 or the first main surface 20A of the opposing substrate 20 is larger than the critical angle, the light source light L is the first main surface 10A of the array substrate 10 or the opposing substrate 20. It is totally reflected on the first main surface 20A of.

As shown in FIG. 5, the light source light L propagating inside the array substrate 10 and the opposing substrate 20 is scattered by a pixel Pix having a scattered liquid crystal, and the incident angle of the scattered light is smaller than the critical angle. At an angle, the emitted light 68 and 68A are emitted to the outside from the first main surface 20A of the opposing substrate 20 and the first main surface 10A of the array substrate 10, respectively. The synchrotron radiation 68 and 68A emitted to the outside from the first main surface 20A of the facing substrate 20 and the first main surface 10A of the array substrate 10, respectively, are observed by the observer. Hereinafter, the polymer-dispersed liquid crystal in the scattered state and the polymer-dispersed liquid crystal in the non-scattered state will be described with reference to FIGS. 7 to 9.

As shown in FIG. 7, the array substrate 10 is provided with the first alignment film AL1. The facing substrate 20 is provided with the second alignment film AL2. The first alignment film AL1 and the second alignment film AL2 are, for example, vertical alignment films.

A solution containing a liquid crystal and a monomer is sealed between the array substrate 10 and the facing substrate 20. Next, in a state where the monomer and the liquid crystal are oriented by the first alignment film AL1 and the second alignment film AL2, the monomer is polymerized by ultraviolet rays or heat to form a bulk 51. As a result, the liquid crystal layer 50 having the reverse mode polymer-dispersed liquid crystal LC in which the liquid crystals are dispersed in the gaps of the network of the polymers formed in a network shape is formed.

As described above, the polymer-dispersed liquid crystal LC has a bulk 51 formed of the polymer and a plurality of fine particles 52 dispersed in the bulk 51. The fine particles 52 are formed of liquid crystal. The bulk 51 and the fine particles 52 each have optical anisotropy.

The orientation of the liquid crystal contained in the fine particles 52 is controlled by the voltage difference between the pixel electrode PE and the common electrode CE. The orientation of the liquid crystal changes depending on the voltage applied to the pixel electrode PE. By changing the orientation of the liquid crystal, the degree of scattering of light passing through the pixel Pix changes.

For example, as shown in FIG. 8, in a state where no voltage is applied between the pixel electrode PE and the common electrode CE, the directions of the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the fine particles 52 are equal to each other. The optical axis Ax2 of the fine particles 52 is parallel to the PZ direction of the liquid crystal layer 50. The optical axis Ax1 of the bulk 51 is parallel to the PZ direction of the liquid crystal layer 50 regardless of the presence or absence of voltage.

The normal light refractive indexes of the bulk 51 and the fine particles 52 are equal to each other. When no voltage is applied between the pixel electrode PE and the common electrode CE, the difference in refractive index between the bulk 51 and the fine particles 52 becomes zero in all directions. The liquid crystal layer 50 is in a non-scattering state in which the light source light L is not scattered. The light source light L propagates in a direction away from the light source 3 (light emitting unit 31) while being reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the opposing substrate 20. When the liquid crystal layer 50 is in a non-scattering state in which the light source light L is not scattered, the background on the first main surface 20A side of the opposing substrate 20 is visually recognized from the first main surface 10A of the array substrate 10, and the first main surface of the opposing substrate 20 is visible. The background of the array substrate 10 on the first main surface 10A side is visually recognized from the surface 20A.

As shown in FIG. 9, between the pixel electrode PE to which the voltage is applied and the common electrode CE, the optical axis Ax2 of the fine particles 52 is tilted by the electric field generated between the pixel electrode PE and the common electrode CE. Become. Since the optical axis Ax1 of the bulk 51 does not change with an electric field, the directions of the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the fine particles 52 are different from each other. The light source light L is scattered in the pixel Pix having the pixel electrode PE to which the voltage is applied. The light in which a part of the light source light L scattered as described above is radiated to the outside from the first main surface 10A of the array substrate 10 or the first main surface 20A of the opposing substrate 20 is observed by the observer.

In the pixel Pix having the pixel electrode PE to which no voltage is applied, the background on the first main surface 20A side of the opposing substrate 20 is visually recognized from the first main surface 10A of the array substrate 10, and the first main surface 20A of the opposing substrate 20 is visually recognized. The background on the first main surface 10A side of the array substrate 10 is visually recognized from the above. Then, in the display device 1 of the present embodiment, when the first input signal VS is input from the image output unit 91, a voltage is applied to the pixel electrode PE of the pixel Pix on which the image is displayed, and the voltage is applied to the third input signal VCSA. The underlying image is visible along with the background. In this way, when the polymer-dispersed liquid crystal is in a scattered state, an image is displayed in the display area.

The image displayed by the light emitted to the outside by the light source light L being scattered in the pixel Pix having the pixel electrode PE to which the voltage is applied is displayed so as to overlap the background. In other words, the display device 1 of the present embodiment displays an image superimposed on the background by combining the synchrotron radiation 68 or the synchrotron radiation 68A and the background.

In the 1 vertical scanning period GateScan shown in FIG. 3, the potentials of the written pixel electrodes PE (see FIG. 7) are the first color emission period RON and the second color emission period after each 1 vertical scanning period GateScan. It must be held in at least one of the GON and the emission period BON of the third color. The potential of each written pixel electrode PE (see FIG. 7) is at least the first color emission period RON, the second color emission period GON, and the third color emission period BON after each one vertical scanning period GateScan. If it cannot be held by one, so-called flicker is likely to occur. In other words, in order to shorten the 1 vertical scanning period GateScan, which is the selection time of the scanning lines, and to improve the visibility in driving by the so-called field sequential method, the light emitting period RON of the first color, the light emitting period GON of the second color, and There is a demand to make it easier to maintain the potential of each written pixel electrode PE (see FIG. 7) in each of the light emission periods BON of the third color.

FIG. 10 is a plan view showing scanning lines, signal lines, and switching elements in pixels. FIG. 11 is a plan view showing a holding capacitance layer in the pixel. FIG. 12 is a plan view showing the auxiliary metal layer and the opening region in the pixel. FIG. 13 is a plan view showing pixel electrodes in pixels. FIG. 14 is a plan view showing a light-shielding layer in the pixel. FIG. 15 is a cross-sectional view of XV-XV'of FIG. FIG. 16 is a cross-sectional view of XVI-XVI'of FIG. FIG. 17 is a cross-sectional view of XVII-XVII'of FIG. FIG. 18 is a cross-sectional view of the peripheral region. As shown in FIGS. 1, 2 and 10, the array substrate 10 is provided with a plurality of signal lines SL and a plurality of scanning lines GL in a grid pattern in a plan view. In other words, one surface of the array substrate 10 includes a plurality of signal lines arranged at intervals in the first direction PX, and a plurality of scanning lines arranged at intervals in the second direction PY.

As shown in FIG. 10, the area surrounded by the adjacent scanning lines GL and the adjacent signal lines SL is the pixel Pix. The pixel Pix is provided with a pixel electrode PE and a switching element Tr. In the present embodiment, the switching element Tr is a bottom gate type thin film transistor. The switching element Tr has a semiconductor layer SC that is superposed on the gate electrode GE that is electrically connected to the scanning line GL in a plan view.

As shown in FIG. 10, the scanning line GL is a wiring of a metal such as molybdenum (Mo) or aluminum (Al), a laminate thereof, or an alloy thereof. The signal line SL is a wiring made of a metal such as aluminum or an alloy.

As shown in FIG. 10, the semiconductor layer SC is provided so as not to protrude from the gate electrode GE in a plan view. As a result, the light source light L from the gate electrode GE side toward the semiconductor layer SC is reflected, and light leakage is less likely to occur in the semiconductor layer SC.

As shown in FIGS. 5 and 20, the light source light L emitted from the light source 3 comes in with the second direction PY as the incident direction. When the incident direction of the light source light L is the second direction PY, the width of the semiconductor layer SC in the first direction is smaller than the width of the semiconductor layer SC in the second direction. As a result, the width of the light source light L in the direction intersecting the incident direction is reduced, and the influence of light leakage is reduced.

As shown in FIG. 10, in the source electrode SE, the same two conductors as the signal line SL extend from the signal line SL in the same layer as the signal line SL and in the direction intersecting the signal line. As a result, the source electrode SE that is electrically connected to the signal line SL is superimposed on one end of the semiconductor layer SC in a plan view.

As shown in FIG. 10, a drain electrode DE is provided at a position between conductors of adjacent source electrodes SE in a plan view. The drain electrode DE overlaps with the semiconductor layer SC in a plan view. The portion that does not overlap with the source electrode SE and the drain electrode DE functions as a channel of the switching element Tr. As shown in FIG. 13, the contact electrode DEA electrically connected to the drain electrode DE is electrically connected to the pixel electrode PE at the contact hole CH.

As shown in FIG. 15, the array substrate 10 has a first translucent base material 19 formed of, for example, glass. The first translucent base material 19 may be a resin such as polyethylene terephthalate as long as it has translucency.

As shown in FIG. 15, a scanning line GL (see FIG. 10) and a gate electrode GE are provided on the first translucent base material 19.

As shown in FIG. 15, a first insulating layer 11 is provided so as to cover the scanning line GL and the gate electrode GE. The first insulating layer 11 is formed of a transparent inorganic insulating material such as silicon nitride.

A semiconductor layer SC is laminated on the first insulating layer 11. The semiconductor layer SC is formed of, for example, amorphous silicon, but may be formed of polysilicon or an oxide semiconductor. When viewed in the same cross section, the width Lsc of the semiconductor layer SC is smaller than the width Lge of the gate electrode GE superimposed on the semiconductor layer SC. As a result, the gate electrode GE can block the light Ld propagating in the first translucent base material 19. As a result, the switching element Tr of the first embodiment reduces optical leakage.

On the first insulating layer 11, a source electrode SE and a signal line SL covering a part of the semiconductor layer SC and a drain electrode DE covering a part of the semiconductor layer SC are provided. The drain electrode DE is made of the same material as the signal line SL. A second insulating layer 12 is provided on the semiconductor layer SC, the signal line SL, and the drain electrode DE. The second insulating layer 12 is formed of a transparent inorganic insulating material such as silicon nitride, like the first insulating layer, for example.

A third insulating layer that covers a part of the second insulating layer 12 is formed on the second insulating layer 12. The third insulating layer 13 is formed of a translucent organic insulating material such as acrylic resin. The third insulating layer 13 has a thicker film thickness than other insulating films formed of an inorganic material.

As shown in FIGS. 15, 16 and 17, there is a region with the third insulating layer 13 and a region without the third insulating layer 13. As shown in FIGS. 16 and 17, the region where the third insulating layer 13 is located is above the scanning line GL and above the signal line SL. The third insulating layer 13 has a grid pattern that covers the upper part of the scanning line GL and the signal line SL along the scanning line GL and the signal line SL. Further, as shown in FIG. 15, the region where the third insulating layer 13 is located is above the semiconductor layer SC, that is, above the switching element Tr. Therefore, the switching element Tr, the scanning line GL, and the signal line SL are relatively separated from the holding capacitance electrode ITO, so that they are less likely to be affected by the common potential from the holding capacitance electrode ITO. Further, in the array substrate 10, a region without the third insulating layer 13 is formed in the region surrounded by the scanning line GL and the signal line SL, so that the thickness of the insulating layer overlapping the signal line SL and the scanning line GL in a plan view is formed. There is a region where the thickness of the insulating layer is smaller than that. In the region surrounded by the scanning line GL and the signal line SL, the light transmittance is improved and the light transmittance is improved relative to the upper part of the scanning line GL and the upper part of the signal line SL.

As shown in FIG. 15, a holding capacitance electrode IO is provided on the third insulating layer 13. The holding capacity electrode IO is formed of a translucent conductive material such as ITO (Indium Tin Oxide). The holding capacity electrode IO is also referred to as a third translucent electrode. As shown in FIG. 11, the holding capacitance electrode IO has a region IOX in which there is no translucent conductive material in the region surrounded by the scanning line GL and the signal line SL. The holding capacitance electrode IO is provided over a plurality of pixel Pix across adjacent pixel Pix. In the holding capacitance electrode IO, the region where the translucent conductive material is present overlaps the scanning line GL or the signal line SL and extends to the adjacent pixel Pix.

The holding capacitance electrode IO has a grid pattern that covers the upper part of the scanning line GL and the signal line SL along the scanning line GL and the signal line SL. As a result, the holding capacity HC between the region IOX without the translucent conductive material and the pixel electrode PE is reduced, so that the holding capacity HC is adjusted by the size of the region IOX without the translucent conductive material.

As shown in FIG. 15, a conductive metal layer TM is provided on a part of the holding capacity electrode IO. The conductive metal layer TM is a wiring of a metal such as molybdenum (Mo) or aluminum (Al), a laminate thereof, or an alloy thereof. As shown in FIG. 12, the metal layer TM is provided in a region overlapping the signal line SL, the scanning line GL, and the switching element Tr in a plan view. As a result, the metal layer TM becomes a grid pattern, and an opening AP surrounded by the metal layer TM is formed.

As shown in FIG. 12, a switching element Tr connected to the scanning line GL and the signal line SL is provided, and at least the switching element Tr is covered with a third insulating layer 13 which is an organic insulating layer, and a third Above the insulating layer 13, there is a metal layer TM having a larger area than the switching element Tr. Thereby, the optical leakage of the switching element Tr can be suppressed.

The metal layer TM may be under the holding capacity electrode IO, and may be laminated with the holding capacity electrode IO. The metal layer TM has a smaller electrical resistance than the holding capacitance electrode IO. Therefore, the variation in the potential of the holding capacitance electrode IO depending on the position of the pixel Pix in the display area AA is suppressed.

As shown in FIG. 12, the width of the metal layer TM overlapping the signal line SL in a plan view is larger than the width of the signal line SL. As a result, the reflected light reflected at the edge of the signal line SL is suppressed from being emitted from the display panel 2. Here, the width of the metal layer TM and the width of the signal line SL are the lengths in the direction intersecting the extending direction of the signal line SL. Further, the width of the metal layer TM overlapping the scanning line GL is larger than the width of the scanning line GL. Here, the width of the metal layer TM and the width of the scanning line GL are the lengths in the direction intersecting the extending direction of the scanning line GL.

As shown in FIG. 15, a fourth insulating layer 14 is provided on the holding capacity electrode IO and the metal layer TM. The fourth insulating layer 14 is an inorganic insulating layer formed of a transparent inorganic insulating material such as silicon nitride.

As shown in FIG. 15, a pixel electrode PE is provided on the fourth insulating layer 14. The pixel electrode PE is formed of a translucent conductive material such as ITO. The pixel electrode PE is electrically connected to the contact electrode DEA via the contact hole CH provided in the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12. As shown in FIG. 13, the pixel electrode PE is partitioned for each pixel Pix. A first alignment film AL1 is provided on the pixel electrode PE.

As shown in FIG. 15, the opposed substrate 20 has a second translucent base material 29 made of, for example, glass. The second translucent base material 29 may be a resin such as polyethylene terephthalate as long as it has translucency. A common electrode CE is provided on the second translucent base material 29. The common electrode CE is formed of a translucent conductive material such as ITO. A second alignment film AL2 is provided on the surface of the common electrode CE. Further, the counter substrate 20 has a light-shielding layer LS between the second translucent base material 29 and the common electrode CE. The light-shielding layer LS is made of a black resin or metal material. Further, a spacer PS is formed between the array substrate 10 and the facing substrate 20, and the spacer PS is located between the common electrode CE and the second alignment film AL2.

As shown in FIGS. 12 and 16, in the display device of the first embodiment, the position where the light-shielding layer GS in the same layer as the scanning line GL extends along the signal line SL and overlaps a part of the signal line SL. It is provided in. The light-shielding layer GS is made of the same material as the scanning line GL. The light-shielding layer GS is not provided at a portion where the scanning line GL and the signal line SL intersect in a plan view.

As shown in FIG. 12, the light-shielding layer GS and the signal line SL are electrically connected by a contact hole CHG. As a result, the wiring resistance composed of the light-shielding layer GS and the signal line SL is lower than the wiring resistance of only the signal line SL. As a result, the delay of the gradation signal supplied to the signal line SL is suppressed. It is not necessary that there is no contact hole CHG and the light shielding layer GS and the signal line SL are not connected.

As shown in FIG. 16, the light-shielding layer GS is provided on the side opposite to the metal layer TM with respect to the signal line SL. The width of the light-shielding layer GS is larger than the width of the signal line SL and smaller than the width of the metal layer TM. The width of the light-shielding layer GS, the width of the metal layer TM, and the width of the signal line SL are the lengths in the direction intersecting the extending direction of the signal line SL. As described above, since the light-shielding layer GS is wider than the signal line SL, it suppresses the emission of the reflected light reflected at the edge of the signal line SL from the display panel 2. As a result, the visibility of the image is improved in the display device 1.

As shown in FIGS. 14 and 15, the facing substrate 20 is provided with a light-shielding layer LS. The light-shielding layer LS is provided in a region overlapping the signal line SL, the scanning line GL, and the switching element Tr in a plan view.

As shown in FIGS. 14, 15, 16 and 17, the light-shielding layer LS has a width larger than that of the metal layer TM. As a result, the reflected light reflected at the edges of the signal line SL, the scanning line GL, and the metal layer TM is suppressed from being emitted from the display panel 2. As a result, the visibility of the image is improved in the display device 1.

The contact hole CH and the contact hole CHG are likely to be diffusely reflected when exposed to the light source light L. Therefore, the light-shielding layer LS is provided in a region overlapping the contact hole CH and the contact hole CHG in a plan view.

As shown in FIG. 15, a spacer SP is arranged between the array substrate 10 and the opposing substrate 20 to improve the uniformity of the distance between the array substrate 10 and the opposing substrate 20.

As shown in FIG. 18, the common potential wiring COML is routed in the peripheral region FR. The common potential wiring COML includes, for example, a first common potential wiring COML1 and a second common potential wiring COML2. The first common potential wiring COML1 is electrically connected to the common electrode CE of the facing substrate 20 via the conductive conductive member CP. The conductive member CP may be a conductive injection (pillar), or may be a sealing material containing conductive particles such as Au particles.

As shown in FIG. 18, in the peripheral region FR, the holding capacitance electrode IO is electrically connected to the second common potential wiring COML2. The metal layer TM is arranged in the display area AA.

As described above, the display device 1 includes an array substrate 10, a counter substrate 20, a liquid crystal layer 50, and a light source 3. The array substrate 10 has a plurality of pixel electrode PEs which are first translucent electrodes arranged for each pixel Pix. The array substrate 10 is provided with a plurality of signal lines SL arranged at intervals in the first direction PX and a plurality of scanning lines GL arranged at intervals in the second direction PY. The facing substrate 20 has a common electrode CE, which is a second translucent electrode, at a position where it overlaps with the pixel electrode PE in a plan view. The liquid crystal layer 50 has a polymer-dispersed liquid crystal LC enclosed between the array substrate 10 and the opposing substrate 20. The light emitting unit 31 of the light source 3 emits light in the second direction PY with respect to the side surface of the opposing substrate 20. The incident direction of the light propagating through the array substrate 10 and the opposing substrate 20 is the second direction. The light emitting unit 31 may emit light propagating through the array substrate 10 and the opposing substrate 20 toward the side surface of the array substrate 10.

The array substrate 10 is provided with at least a third insulating layer 13 which is an organic insulating layer covering the switching element Tr and a metal layer TM which is superposed on the third insulating layer 13 and has a larger area than the switching element Tr. There is. In the region surrounded by the scanning line GL and the signal line SL, there is a region having a thickness smaller than the thickness of the third insulating layer 13 overlapping the scanning line GL and the signal line SL in a plan view. Therefore, it is a slope in which the thickness of the third insulating layer 13 on the side closer to the light source 3 than the switching element Tr in a plan view changes, and as shown in FIG. 15, the third insulating layer 13 is superimposed on the switching element Tr. The first slope 13t1 of the above is covered with a metal layer TMt. Here, the metal layer TMt is a tapered portion formed of the same material as the metal layer TM and extending the metal layer TM.

As shown in FIGS. 5 and 20, the light source light L emitted from the light source 3 comes in with the second direction PY as the incident direction. As shown in FIG. 15, the light Lu arrives. The light Lu is a part of the light source light L that arrives from the side closer to the light source 3 than the switching element Tr. Here, since the metal layer TMt blocks light Lu, light leakage is reduced.

It should be noted that the metal layer TM may not be provided on the slopes in which the thickness of the third insulating layer 13 changes and the slopes other than the first slope of the third insulating layer 13 superimposed on the switching element Tr.

(Embodiment 2)
FIG. 19 is a plan view showing the pixels of the second embodiment. The same components as those described in the present embodiment described above are designated by the same reference numerals, and duplicate description will be omitted.

As shown in FIG. 19, the configuration of the pixel Pix of the second embodiment is different from the configuration of the pixel Pix of the first embodiment, and there are two signal lines SL between adjacent pixel Pix. One signal line SL is electrically connected to the switching element Tr1 at the intersection of every other pixel Pix with the scanning line GL. The other signal line SL is electrically connected to the switching element Tr2 at the intersection of the switching element Tr1 with the scanning line GL of every other pixel Pix except for the pixel Pix.

Thereby, the gate drive circuit 43 can simultaneously select two adjacent scanning lines GL. As a result, the 1 vertical scanning time GateScan shown in FIG. 3 is shortened. When each one vertical scanning period GateScan becomes shorter, the first color emission period RON, the second color emission period GON, and the third color emission period BON after each one vertical scanning period GateScan may become relatively longer. it can.

(Embodiment 3)
FIG. 20 is a plan view showing a plane of the display device of the third embodiment. FIG. 21 is a plan view showing scanning lines, signal lines, and switching elements in the pixels of the third embodiment. FIG. 22 is a cross-sectional view of XXII-XXII'of FIG. The same components as those described in the present embodiment described above are designated by the same reference numerals, and duplicate description will be omitted.

As shown in FIG. 20, the light source 3 faces the third side surface 10E of the array substrate 10 or the third side surface 20E of the facing substrate 20. For example, as shown in FIG. 20, the light source 3 irradiates the third side surface 10E of the facing substrate 20 with the light source light L. The third side surface 10E of the facing substrate 20 facing the light source 3 is a light incident surface. The light source light L emitted from the light source 3 is reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the opposing substrate 20, while being reflected by the third side surface 10E of the array substrate 10 or the third surface of the opposing substrate 20. It propagates in the direction away from the side surface 20E (first direction PX).

As shown in FIG. 21, the configuration of the pixel Pix of the third embodiment is different from the configuration of the pixel Pix of the first embodiment, and there are two signal lines SL between adjacent pixel Pix. One signal line SL is electrically connected to the switching element Tr1 at the intersection of every other pixel Pix with the scanning line GL. The other signal line SL is electrically connected to the switching element Tr2 at the intersection of the switching element Tr1 with the scanning line GL of every other pixel Pix except for the pixel Pix.

Thereby, the gate drive circuit 43 can simultaneously select two adjacent scanning lines GL. As a result, the 1 vertical scanning time GateScan shown in FIG. 3 is shortened. When the one vertical scanning period GateScan shown in FIG. 3 becomes short, the first color emission period RON, the second color emission period GON, and the third color emission period BON after each one vertical scanning period GateScan become relatively long. can do.

As shown in FIGS. 21 and 22, the light source light L propagates along the first direction PX. Since the light entering direction is along the first direction PX, as shown in FIG. 20, the light blocking structure SGS is located in the light entering direction on the side where the light emitting portion 31 of the light source 3 is located from the switching element Tr1. is there. In the second direction PY intersecting the light entering direction, the length of the light-shielding structure SGS is larger than the length of the semiconductor layer SC. As a result, the light-shielding structure SGS can block the optical path propagating to the switching element Tr and suppress the light leakage of the switching element Tr1.

In the light-shielding structure SGS, the light-shielding layer GS of the same layer as the scanning line GL is extended, and the first light-shielding layer SM formed of the conductive material of the same layer as the signal line SL is laminated on the conductive material of the light-shielding layer GS. Has been done. As described above, the light-shielding structure SGS is on the extension line of the signal line SL.

As shown in FIGS. 21 and 22, the switching element Tr is covered with a third insulating layer 13 which is an organic insulating layer, and the first slope 13t1 of the third insulating layer 13 in the incident direction is a metal layer TMt. It is covered. As a result, the metal layer TMt can block the optical path propagating to the switching element Tr1 and suppress the optical leakage of the switching element Tr1.

As shown in FIG. 22, the array substrate 10 is provided with at least a third insulating layer 13 which is an organic insulating layer covering the switching element Tr1 and is provided above the third insulating layer 13, and is more than the switching element Tr1. There is a metal layer TM with a large area. In the region surrounded by the scanning line GL and the signal line SL, there is a region having a thickness smaller than the thickness of the third insulating layer 13 overlapping the scanning line GL and the signal line SL in a plan view. Therefore, the first slope 13t1 of the third insulating layer 13 superimposed on the switching element Tr1 is a slope on which the thickness of the third insulating layer 13 on the side closer to the light source 3 than the switching element Tr1 changes in a plan view. It is covered with a metal layer TMt. Here, the metal layer TMt is a tapered portion formed of the same material as the metal layer TM and extending the metal layer TM.

As shown in FIG. 21, it is a slope on which the thickness of the third insulating layer 13 on the side farther from the light source 3 than the switching element Tr1 changes in a plan view, and the third insulating layer 13 superimposed on the switching element Tr1. Two slopes 13t2 are covered with a metal layer TMt. This reduces light leakage.

The light-shielding structure SGS is covered with a third insulating layer 13, a metal layer TM, and a metal layer TMt. As a result, the light-shielding structure SGS blocks the light Lu that has passed through the metal layer TMt.

As described above, there is a light-shielding structure SGS between the first slope 13t1 and the switching element Tr1. As a result, the metal layer TMt and the light-shielding structure SGS make it more difficult for the optical Lu to reach the switching element Tr1.

(Modification example)
Although the switching element Tr has been described as having a bottom gate type in the first to third embodiments, the switching element Tr is not limited to the bottom gate structure and may be a top gate type as described above. If the switching element Tr is a top gate type, the semiconductor layer SC is arranged between the first translucent base material 19 and the first insulating layer, and the gate electrode GE is described with reference to the insulating film laminated structure of FIG. It is arranged between the first insulating layer 11 and the second insulating layer 12, and the source electrode SE and the contact electrode DEA have a structure formed between the second insulating layer 12 and the third insulating layer 13.

Further, regarding the common potential, a DC voltage may be supplied, that is, a constant common potential, or an AC voltage may be shared, that is, a common potential having two upper and lower limits. Good. A common potential is supplied to the holding capacity electrode IO and the common electrode CE regardless of whether the common potential is direct current or alternating current.

Further, with respect to the third insulating layer 13 which is a lattice-shaped organic insulating film, the third insulating layer 13 inside the lattice is completely removed to expose the lower second insulating layer 12 and the holding capacity electrode IO. It is disclosed, but it is not limited to this. For example, the inside of the grid-like region surrounded by the plurality of signal lines SL and the plurality of scanning lines GL may have a structure in which a part of the film thickness of the third insulating layer 13 is left thin by halftone exposure. As a result, the third insulating layer 13 has a thinner film thickness inside the grid-like region than the grid-like region surrounded by the plurality of signal lines SL and the plurality of scanning lines GL.

Although the preferred embodiment has been described above, the present disclosure is not limited to such an embodiment. The content disclosed in the embodiment is merely an example, and various changes can be made without departing from the spirit of the present disclosure. Appropriate changes made to the extent that they do not deviate from the gist of this disclosure also naturally fall within the technical scope of this disclosure.

1 Display device 2 Display panel 3 Light source 4 Drive circuit 9 Upper control unit 10 Array substrate 11 1st insulation layer 12 2nd insulation layer 13 3rd insulation layer 14 4th insulation layer 20 Opposite substrate 31 Light emitting unit 41 Signal processing circuit 42 pixels Control circuit 43 Gate drive circuit 44 Source drive circuit 45 Common potential drive circuit 50 Liquid crystal layer AP Opening CE Common electrode CH Contact hole COML Common potential wiring CP Conductive member DE Drain electrode DEA Contact electrode FR Peripheral region GE Gate electrode GL Scan line GON Light emission period GS Light-shielding layer HC Retention capacity HDS Horizontal drive signal IO Retention capacity Electrode IOX Region without translucent conductive material LC Polymer dispersion liquid crystal LS Light-shielding layer PE Pixel electrode SC Semiconductor layer SE Source electrode SGS Light-shielding structure TM, TMt Metal layer Tr, Tr1, Tr2 switching element

Claims (10)

With the array board
With the opposite board
The liquid crystal layer between the array substrate and the facing substrate,
A light source is provided so as to allow light to enter the side surface of the array substrate or the side surface of the facing substrate.
The array substrate is
Multiple signal lines lined up at intervals in the first direction,
Multiple scanning lines that are spaced apart in the second direction,
A switching element connected to the scanning line and the signal line,
At least an organic insulating layer covering the switching element,
It has a metal layer that is superposed on the organic insulating layer and is provided.
In the region surrounded by the scanning line and the signal line, there is a region in which the thickness of the organic insulating layer is smaller than the thickness of the organic insulating layer overlapping the scanning line and the signal line in a plan view.
The first slope of the organic insulating layer on the side closer to the light source than the switching element is covered with the metal layer.
A display device in which a second slope of the organic insulating layer on the side farther from the light source than the switching element is covered with the metal layer. The display device according to claim 1, wherein the metal layer overlaps the plurality of signal lines and the plurality of scanning lines in a plan view, and is arranged in a grid pattern on the organic insulating layer. The second aspect of the present invention, wherein the width of the metal layer overlapping the signal line is larger than the width of the signal line and the width of the metal layer overlapping the scanning line is larger than the width of the scanning line in a plan view. Display device. The array substrate has a plurality of first translucent electrodes arranged for each pixel.
The facing substrate has a second translucent electrode at a position where it overlaps with the first translucent electrode.
The array substrate further includes a third translucent electrode in which at least a part of the first translucent electrode is overlapped with the first translucent electrode in a plan view, and the metal layer is the third translucent electrode. The display device according to any one of claims 1 to 3, which is laminated on the optical electrode. The display device according to any one of claims 1 to 4, wherein there is a light-shielding structure between the first slope and the switching element. The display device according to claim 5, wherein the light-shielding structure is laminated with the same conductive material as the scanning line and the same conductive material as the signal line. The display device according to claim 5 or 6, wherein the two signal lines are arranged between two pixels adjacent to each other in the first direction, and the light-shielding structure is provided on an extension line of the signal lines. .. The display device according to any one of claims 5 to 7, wherein the light-shielding structure is covered with the organic insulating layer and the metal layer. Any one of claims 1 to 8, wherein the length of the semiconductor layer of the switching element in the direction intersecting the incident direction of the light incident on the light source is smaller than the length of the semiconductor layer of the switching element in the incident direction. The display device described in the section. The liquid crystal layer is a polymer-dispersed liquid crystal, and is
The display device according to any one of claims 1 to 9, wherein the background of the facing substrate is visually recognized from the array substrate, and the background of the array substrate is visually recognized from the facing substrate.

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