[go: up one dir, main page]

WO2020193553A1 - Photodiode et circuit de lecture pour photodiode - Google Patents

Photodiode et circuit de lecture pour photodiode Download PDF

Info

Publication number
WO2020193553A1
WO2020193553A1 PCT/EP2020/058162 EP2020058162W WO2020193553A1 WO 2020193553 A1 WO2020193553 A1 WO 2020193553A1 EP 2020058162 W EP2020058162 W EP 2020058162W WO 2020193553 A1 WO2020193553 A1 WO 2020193553A1
Authority
WO
WIPO (PCT)
Prior art keywords
photodiode
region
area
conductivity type
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2020/058162
Other languages
German (de)
English (en)
Inventor
Daniel Dietze
Massimo Cataldo Mazzillo
Tim Boescke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of WO2020193553A1 publication Critical patent/WO2020193553A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/223—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/95—Circuit arrangements
    • H10F77/953—Circuit arrangements for devices having potential barriers

Definitions

  • German patent application No. 10 2019 107 895.4 which was filed with the German Patent and Trademark Office on March 27, 2019.
  • the disclosure content of German patent application No. 10 2019 107 895.4 is hereby incorporated into the disclosure content of the present application.
  • the present invention relates to a photodiode, a method for operating a photodiode and a readout circuit for a photodiode.
  • Photodiodes are used, for example, in VR (virtual reality) applications and AR (augmented reality) applications, such as VR or AR position tracking, a set.
  • Other applications of photodiodes can be found in optical communication systems, such as for the communication of battery cells in vehicles, or in smoke detectors.
  • optical communication systems such as for the communication of battery cells in vehicles, or in smoke detectors.
  • Such systems require integrated optical detectors with high photon detection efficiency and speed in the vicinity Infrared (near infrared, or NIR for short) work in order to be able to detect very fast light signals in a wide dynamic range with possibly only very low light intensity.
  • Infrared near infrared, or NIR for short
  • the present invention is based, inter alia, on the task of creating a photodiode which allows signals with low noise and low capacitive coupling to be read out. Furthermore, a method for operating the photodiode and a readout circuit for the photodiode are to be specified.
  • One object of the invention is achieved by a photodiode with the features of claim 1. Further objects of the invention are achieved by a method for operating the photodiode with the features of independent claim 13 and a readout circuit with the features of independent claim 14. Preferred embodiments and developments of the invention are specified in the dependent claims.
  • a photodiode comprises a semiconductor substrate and a semiconductor layer arranged on the semiconductor substrate.
  • the semiconductor layer has a photosensitive area, which can also be referred to as an optically active area.
  • charge carriers or electron / hole pairs can be generated by incident light.
  • the photosensitive area in particular adjoins a main surface of the semiconductor layer or the photo diode.
  • the semiconductor substrate and the overlying semiconductor layer are of a first conductivity type.
  • a first region of a second conductivity type and a second region of the first conductivity type are integrated into the photosensitive region of the semiconductor layer.
  • the first and the second areas are laterally offset from one another and in particular arranged at a distance from one another. Laterally offset means that they are offset from one another in a direction parallel to the main surface of the semiconductor layer.
  • the second conductivity type is opposite to the first conductivity type.
  • One of the two first and second areas represents the anode of the photodiode and the other area the cathode of the photodiode.
  • the different conductivity types can ren by doping, d. H. by the introduction of foreign atoms into the semiconductor material have been generated.
  • the first conductivity type can be a p-conductivity type and the second conductivity type can be an n-conductivity type.
  • Opposite doping is also conceivable.
  • the semiconductor substrate, the semiconductor layer, the first area and the second area can be doped to different degrees.
  • the semiconductor substrate can be more heavily doped than the semiconductor layer and the first and second regions can each be more heavily doped than the semiconductor substrate.
  • the semiconductor substrate can be heavily doped, the semiconductor layer can be weakly doped and the first and second regions can each be very heavily or heavily doped.
  • the photodiode converts light in the visible range, ultraviolet (UV) light and / or infrared (IR) light into an electrical current through an internal photoelectric effect in the light-sensitive area.
  • UV ultraviolet
  • IR infrared
  • the photodiode can have a pin (positive-intrinsic-negative, English: positive intrinsic negative) structure.
  • a pin photodiode is similar to a pn photodiode, with the difference that there is an additional weakly doped or undoped area between the first area and the second area, ie between the n- and p-doped areas.
  • This area is therefore only intrinsically conductive and is therefore referred to as the i-area.
  • the i-region can be formed by the weakly doped semiconductor layer.
  • the first and second areas are therefore not in direct contact with one another, and when a reverse voltage is applied, a larger space charge zone is formed than with a pn photodiode. Since the i-area contains only a few free charge carriers, it is high-resistance.
  • the lateral structure of the photodiode reduces the total capacitance and in particular the influence of the capacitance on the vertical transition between the cathode and the semiconductor substrate by significantly reducing both capacitive couplings and noise-amplification effects, especially at high frequencies will. As a result, the achievable signal-to-noise ratio is increased, while the efficiency of the photon detection is retained due to the possibility of using large-area detectors without significantly increasing the capacity parameters.
  • the new photodiode structure also improves the reliability and reproducibility of the measurement results.
  • the first conductivity type is a p-conductivity type and the second conductivity type is an n-conductivity type.
  • the first area forms the cathode and the second area forms the anode of the photodiode.
  • the semiconductor substrate is p + -doped, ie heavily p-doped, and the semiconductor layer above it is p-doped, ie weakly p-doped.
  • the first region is n + or n ++ - doped, ie heavily or very heavily n-doped, and the second Area is p + - or p ++ -doped, ie heavily or very heavily p- doped.
  • the photodiode can be a CMOS photodiode and consequently be produced by means of the CMOS (complementary metal-oxide-semiconductor) technology.
  • CMOS complementary metal-oxide-semiconductor
  • the photodiode described in the present application is fully compatible with standard CMOS processes.
  • the photodiode can therefore be integrated into a large number of integrated circuits (ICs for short), the production costs of the integrated circuits being able to be reduced and the footprint of the sensors being minimized.
  • the semiconductor layer arranged over the semiconductor substrate can be an epitaxial layer, i. H. an epitaxially grown semiconductor layer.
  • the lateral distance between the first area, which is in particular n + - or n ++ -doped and forms the cathode of the photodiode, and the second area, which is in particular p + - or p ++ - doped and forms the anode of the photodiode, can be comparatively low and, for example, be at most 20 ⁇ m. Alternatively, this distance can be at most 19 pm or 18 pm or 17 pm or 16 pm or 15 pm or 14 pm or 13 pm or 12 pm or 11 pm or 10 pm.
  • the area of the first area on the main surface of the semiconductor layer ie the lateral extent of the first area, can be in the pm 2 range and therefore be significantly smaller than in a conventional photodiode with a vertical structure in which the cathode has a lateral extent in the mm 2 range.
  • the area of the first region on the main surface of the semiconductor layer can be at most 100 pm 2 or 50 pm 2 or 10 pm 2 or 5 pm 2 or 2 pm 2 or 1 pm 2 .
  • the electrical resistance between the second region and the semiconductor substrate is greatly reduced compared to conventional photodiodes with a vertical structure and, according to one embodiment, is at most 200 W or 180 W or 160 W or 140 W or 120 W or 100 W.
  • the semiconductor layer can have a well of the first conductivity type, in which the second region is integrated or embedded.
  • the well is in particular more heavily doped than the semiconductor layer and, for example, p + -doped.
  • the distance between the well and the semiconductor substrate can be at most 15 pm or 14 pm or 13 pm or 12 pm or 11 pm or 10 pm.
  • the small distance between the well and the semiconductor substrate contributes to the low electrical resistance between the second region and the semiconductor substrate.
  • a first contact element can be applied to the first area and a second contact element can be applied to the second area.
  • the two contact elements can be made from a suitable metal or a suitable metal alloy.
  • a polysilicon gate layer which is p-doped, in particular p + -doped, for example, can be applied to the semiconductor layer.
  • the polysilicon gate layer can be applied to the lateral pin structure between the first region and the second region, and in particular the area surrounding the lateral pin structure.
  • a field oxide layer in particular made of SiO 2 , can be located between the polysilicon gate layer and the semiconductor layer.
  • the first region and the second region can be recessed from the field oxide layer and the polysilicon gate layer.
  • the fat the field oxide layer can be at most 300 nm, for example.
  • the polysilicon gate layer can be short-circuited with the second region, ie in particular with the anode, or alternatively a predetermined electrical, in particular negative potential can be applied via an independent connection.
  • a layer of a transparent, electrically conductive oxide (English: transparent conducting oxide, TCO), such as indium tin oxide (English: indium tin oxide, ITO), on the semiconductor layer and in particular the field oxide layer above the lateral be applied pin structure.
  • the layer made of the transparent, electrically conductive oxide can, for example, have a thickness of at most 120 nm or 110 nm or 100 nm or 90 nm or 80 nm.
  • Another alternative is to replace the polysilicon gate layer together with the field oxide layer by a thin dielectric layer with a constant, especially negative charge, which is applied to the semiconductor layer and in particular the lateral pin structure and / or its surroundings - is brought.
  • This layer can for example consist of Al2O3 and prevents the accumulation of electrons in the p-doped semiconductor layer.
  • the dielectric layer can be applied directly to the main surface of the semiconductor layer.
  • one or more dielectric layers, each having a fixed charge can be applied to the semiconductor layer and in particular the lateral pin structure between the first region and the second region and / or their surroundings.
  • the fixed charges of the dielectric layers prevent the accumulation of minority carriers on the surface of the p-doped semiconductor layer.
  • such layers can have a positive charge and consist of SX 3 N 4 or Si0 2 if the above-described doping of the layers is inverted and the semiconductor layer or epitaxial layer has a low n-doping.
  • the lower limit for a surface charge concentration of the dielectric layer is, for example, 10 11 cm 2 .
  • a method for operating a photodiode according to one of the configurations described above provides that a first electrical potential is applied to the first area, i.e. H. in particular to the cathode, and a second electrical potential to the second area, d. H. especially to the anode.
  • the second electrical potential can be a reference potential, in particular a ground potential.
  • the second potential is greater than the first potential.
  • a readout circuit can comprise a photodiode according to one of the configurations described above and furthermore have a transimpedance amplifier connected downstream of the photodiode, a first high-pass filter connected downstream of the transimpedance amplifier and a first comparator connected downstream of the high-pass filter. It should be noted that further components can be switched between the components described above.
  • the readout circuit Due to the photodiode used with the lateral structure described above, the readout circuit has a high performance and sensitivity as well as an improved signal-to-noise ratio.
  • the developed photodiode structure creates the electrical potentials at the anode and the cathode changed equally during operation, whereby an additional current flow through the photodiode is prevented and the output signal of the transimpedance amplifier is not influenced.
  • the read-out circuit is suitable for reading out fast light signals, particularly in the near infrared, over a wide dynamic range, with possibly only very low light intensity. Both capacitive couplings and parasitic noise-amplification effects caused by undesired coupling with the electronics can be largely prevented by using the lateral photodiode structure, which increases the measurement accuracy.
  • one or more amplifier stages are connected downstream of the first high-pass filter.
  • One or more second high-pass filters can also be connected downstream of the amplifier stage or stages.
  • a rectifier can be connected downstream of the first high-pass filter or the amplifier stage or stages or the second high-pass filter or filters. Furthermore, a low-pass filter is connected downstream of the rectifier.
  • the readout circuit can have a first circuit branch and a second circuit branch.
  • the first circuit branch can contain the components of the configurations described above.
  • the second circuit branch branches off, for example, downstream of the first high-pass filter and contains at least one second comparison.
  • the first circuit branch delivers as an output signal an envelope signal, while the second circuit branch provides a digital output signal.
  • the photodiode and / or the read-out circuit described in the present application are particularly suitable for use in VR and / or AR applications, such as sensors, devices or systems for VR or AR - Position tracking.
  • the photodiode and / or the readout circuit can be used in other sensors, devices or systems that have, in particular, similar requirements as in VR or AR position tracking.
  • the photodiode and / or the read-out circuit can be used in optical communication systems, such as for the communication of battery cells in vehicles, or in smoke detectors.
  • FIG. 1 is an illustration of a photodiode with a vertical structure
  • FIG. 2 is an illustration of an electrical model of the photodiode of FIG. 1;
  • FIG. 3 shows an illustration of an embodiment of a photodiode with a lateral struc ture
  • Figure 4 is an illustration of an electrical model of the photodiode of Figure 3;
  • Fig. 5 shows an illustration of a front-end circuit for a photodiode with a vertical structure;
  • Fig. 6 shows a representation of a front-end circuit for a photodiode with a lateral structure;
  • Fig. 7 shows an illustration of a further exemplary embodiment of a photodiode with a lateral structure
  • Fig. 8 shows a representation of different photodiode capacitances against the cathode blocking voltage
  • Fig. 9 shows the spectral sensitivity for various photodiode parameters versus the wavelength
  • 10 shows a representation of various photodiode capacitances versus the polysilicon gate voltage
  • 11 shows an illustration of a parasitic feedback in a readout circuit for a photodiode
  • FIG. 12 shows an illustration of the effect of capacitive coupling in a readout circuit for a photodiode with a vertical structure
  • Fig. 14 shows an illustration of the noise spectral density versus frequency for photodiodes with a vertical structure and different photodiode capacitances
  • 16A to 16E representations of various exemplary embodiments of readout circuits for photodiodes with a lateral structure.
  • Fig. 1 shows a CMOS photodiode 1 with a vertical struc ture, which is also referred to below as a VPIN structure. It should be pointed out that the representations in FIG. 1 and all other figures are not true to scale.
  • the photodiode 1 is integrated in an integrated circuit and comprises a p + -doped semiconductor substrate 2 and a p -doped epitaxial layer 3 arranged above it.
  • the epitaxial layer 3 comprises a photosensitive region 4, the lateral extent of which is shown in FIG. 1 by a dashed line Line is shown.
  • An n ++ doped area 5 is integrated into the photosensitive area 4.
  • a p ++ -doped area 6 is embedded in a p + -doped well 7, which is located in the epitaxial layer 3.
  • the photodiode 1 has a pin structure and is identified by a circuit symbol labeled PD in FIG. 1.
  • the n ++ -doped area 5 and the p + -doped semiconductor substrate 2 represent the cathode CAT and the anode of the photodiode 1.
  • the p ++ -doped area 6 is connected to a ground potential VSS.
  • FIG. 1 An electrical model of the photodiode PD of FIG. 1 is shown in FIG.
  • the photodiode PD is connected between the cathode CAT or the n ++ -doped area 5 and the semiconductor substrate 2 designed as an anode.
  • the disadvantage of this structure is that the semiconductor substrate 2 cannot be contacted directly, but rather has to be contacted via the p ++ -doped region 6 through the only weakly doped and therefore high-resistance epitaxial layer 3.
  • the electrical resistance R SU B caused by the epitaxial layer 3 is typically approximately 1 k ⁇ .
  • Fig. 3 shows a CMOS photodiode 10 with a lateral struc- ture, which is also referred to below as an LPIN structure.
  • the photodiode 10 comprises a p + -doped semiconductor substrate 11 and a semiconductor layer located on the semiconductor substrate 11 in the form of a p -doped epitaxial layer 12.
  • the epitaxial layer 12 comprises a main surface 13 and a photosensitive area 14 adjacent to the main surface 13 In region 14, charge carriers or electron / hole pairs can be generated by incident light.
  • a first area in the form of an n ++ -doped diffusion area 15 and a second area in the form of a p ++ -doped diffusion area 16 are integrated into the photosensitive area 14 of the epitaxial layer 12.
  • the p ++ -doped region 16 is also embedded in a p + -doped well 17.
  • the n ++ -doped area 15 and the p ++ -doped area 16 are laterally offset from one another and arranged at a distance from one another. Laterally offset means that they are offset from one another in a direction 21 which runs parallel to the main surface 13 of the epitaxial layer 12 and which is indicated by an arrow in FIG. 3.
  • the distance between the n ++ -doped region 15 and the p ++ -doped region 16 is identified in FIG. 3 by the reference symbol 23.
  • both the n ++ -doped area 15 and the p ++ -doped area 16 are integrated in the photosensitive area 14 of the epitaxial layer 12. Furthermore, the distance 23 between the n ++ doped region 15 and the p ++ - doped region 16 significantly lower in the photodiode 10 as in the photodiode 1, and is, for example not more than 20 pm. Furthermore, the extension of the n ++ -doped region 15 in the lateral direction in the photodiode 10 is smaller than the extension of the n ++ -doped region 5 in the lateral direction in the photodiode 1.
  • the photodiode 10 has an area in the pm 2 range on the main surface 13, while the n ++ -doped area 5 of the photodiode 1 has an area in the mm 2 range.
  • the vertical pin junction between the n ++ -doped region 15 and the p + -doped semiconductor substrate 11 forms a photodiode labeled PD1 in FIG. 3. Further, the lateral pin junction between the n ++ doped region 15 and the p ++ forms - doped region 16 of a designated photodiode PD2, which is the dominant photodiode compared to the photo diode PD1.
  • the n ++ -type region 15, the cathode and the p ++ - doped region 16, the anode of the photodiode 10 is.
  • FIG. 4 shows an electrical model of the photodiode 10 from FIG. 3 with the two photodiodes PD1 and PD2.
  • the anode ANO of the overall circuit is connected to the anode of the photodiode PD1 via the comparatively small resistor R SU B.
  • the lateral photodiode 10 allows a circuit design that is closer to a differential configuration than a single-ended configuration.
  • FIG. 5 shows an exemplary front-end circuit for the photodiode 1 from FIG. 1.
  • the capacitance shown in FIG C D corresponds to the capacitance of the photodiode PD.
  • the capacitances C cat and C Sub are parasitic capacitances.
  • the photodiode PD is connected to a transimpedance amplifier which generates an output signal out at its output.
  • Fig. 6 shows an exemplary front-end circuit for the photodiode 10 from FIG. 3.
  • the capacitances C Di and C D2 correspond to the capacitances of the photodiodes PD1 and PD2.
  • the capacitances C cat , C ano and C sub are parasitic capacitances.
  • FIG. 7 shows the CMOS photodiode 10 with the LPIN structure from FIG. 3, with a field oxide layer 25 being deposited on the main surface 13 of the epitaxial layer 12 in FIG. 7.
  • the Areas 15 and 16 which are n + and p + doped in the configuration shown in FIG. 7 are recessed from the field oxide layer 25 and hen with metal contact elements 26 and 27, respectively.
  • a p + -doped polysilicon gate layer 28 is applied to the field oxide layer 25.
  • the p + -doped region 16 and the p + -doped semiconductor substrate 11 are at a ground potential.
  • the polysilicon gate layer 28 is electrically connected to the p + -doped region 16.
  • the n + -doped region 15 is positive
  • the minimum width of the n + -doped area 15 is 0.7 pm and the minimum width of the p + -doped area 16 is 1.4 pm.
  • the distance 23 between the areas 15 and 16 is between 10 pm and 15 pm and is comparable to the thickness of the epitaxial layer 12.
  • the width of the p + -doped well 17 is in the range from 2 pm to 10 pm.
  • the cathode-anode capacitance, the cathode-substrate capacitance and the total capacitance for a photodiode with an LPIN structure and the total capacitance of a Photodi ode with a VPIN structure are plotted against the cathode blocking voltage.
  • the LPIN structure allows the total capacitance of the photodiode to be reduced by a factor of approximately 4.5, while at the same time the contribution of the cathode-substrate transition to the total capacitance is minimized .
  • the effect can be lead back to the doped by use of a p + Be Reich 16 and the p + -doped region 16 surrounding p + to the lateral boundary of the depleted region at the surfaces of cathode contact - resulting doped well 17th
  • the spectral sensitivity which is abbreviated to "Resp” in the legend of FIG. 9, is at an irradiance of 1 mi / cm 2 versus the wavelength for photodiodes with an LPIN or a VPIN structure and Cathode voltages of 0 V, 0.7 V or 3 V.
  • the very low doping of the epitaxial layer combined with the interlocking surface contact design allows a good optical response of the Photodiode with the LPIN structure both in the visible range and in the near infrared with very low blocking voltages. If the optical response is simulated under the same experimental conditions, the optical response of LPIN photodiodes is comparable to that of VPIN photodiodes.
  • the surface charge effects can be reduced in that the p + -doped polysilicon gate layer is biased with a negative voltage in the range between -5V and 0V.
  • the polysilicon gate layer is electrically decoupled from the anode and the desired potential is applied via a separate connection (structure with 4 connections).
  • the cathode-anode capacitance, the cathode-substrate capacitance, the cathode-gate capacitance and the total polysilicon gate capacitance are plotted against the polysilicon gate voltage to illustrate the above embodiments gen.
  • the use of the p + -doped well is designed to reduce the bulk contact resistance. This resistance has proven to be a critical parameter in view of the very low doping of the epitaxial layer.
  • the beschrie in the present application bene design is compatible gate oxide layer nm with a thin with a thickness of, for example, 7 or 14, which replaces the field oxide S chicht.
  • a suitably biased polysilicon gate layer is advantageous in order to improve the reproducibility of the electro-optical properties and the reliability of the photodiode despite the influence of surface charges.
  • the metal layers and the surface polysilicon layers can be suitably passivated by a stack of dielectric layers.
  • the LPIN structure is distinguished from the VPIN structure by:
  • a capacitive coupling between bond wires, which are used for the electrical connection with the photodiode's rule, and the active surface of the photodiode can lead to a parasitic feedback between the driver output and the input of the impedance amplifier, as is illustrated in FIG. 11. This can cause signal distortion, false positives, pulse skipping and
  • FIG. 14 shows by way of example for a photodiode with a VPIN structure, which reduces the achievable signal-to-noise ratio.
  • the LPIN structure allows a considerable reduction in the total capacitance of the photodiode, ie the capacitances C Di and C D 2 shown in FIG. 6, whereas the entire active area and the spectral sensitivity are retained. Furthermore, with the LPIN structure, the capacity is split into two capacities, with only the vertical capacity contributing to the noise peak. In Fig. 15, noise spectral densities for VPIN and LPIN structures are plotted against frequency.
  • 16A to 16E show differently configured readout circuits 51 to 55 for a photodiode 10 with an LPIN structure as described above.
  • the read-out circuit 51 shown in FIG. 16A has an optical input 60 at which an optical signal is received which is converted by the photodiode 10 into a photocurrent becomes.
  • the photodiode 10 can, for example, have a large area in the range from 1 mm 2 to 2 mm 2 , a high IR sensitivity of, for example, 0.4 A / W for light with a wavelength of 850 nm and a high bandwidth of greater than 10 MHz .
  • the photodiode 10 is a transimpedance amplifier 61 switched downstream, which converts the photodiode 10 provided photo current into a voltage.
  • the transimpedance amplifier 61 requires both a high speed and a large gain.
  • the transimpedance amplifier 61 has a bandwidth of greater than 10 MHz and a gain of 10 k ⁇ .
  • a high-pass filter 62 connected downstream of the transimpedance amplifier 61 removes low-frequency background signals.
  • the cut-off frequency of the high-pass filter 62 is less than 1 MHz.
  • a comparator 63 which is designed as a Schmitt trigger, for example, is arranged behind the high-pass filter 62.
  • the comparator 63 converts the analog signal into a digital signal and requires a high response speed.
  • a digital output driver 64 feeds the digital output signal to electronics connected to the read-out circuit 61, for example a microcontroller or an FPGA (field programmable gate array).
  • the digital output driver 64 should be able to provide typical logic levels such as 1.8V, 3.3V or 5V.
  • the structure of the in Fig. 16B is largely identical to the readout circuit 51 shown in FIG. 16A.
  • the read-out circuit 52 additionally has one or more voltage amplification stages 65 which are connected after the high-pass filter 62.
  • the in Fig. Readout circuit 53 shown in FIG. 16C is based on readout circuit 52 from FIG. 16B.
  • the readout circuit 53 additionally contains one or more high-pass filter stages 66, which are connected downstream of the voltage amplification stages 65.
  • the read-out circuit 54 shown in FIG. 16D is based on one of the read-out circuits 51, 52 and 53.
  • a rectifier 67 and a low-pass filter 68 are connected upstream of the comparator 63.
  • the digital output driver 64 supplies an envelope signal as an output signal.
  • the readout circuit 55 shown in FIG. 16E comprises a first circuit branch which corresponds to the readout circuit 54 from FIG. 16D. Furthermore, the read-out circuit 54 comprises a second circuit branch which is connected downstream of the high-pass filter 62. The second circuit branch comprises a comparator 69 and a digital output driver 70. The digital output driver 64 provides an envelope signal at its output, while the digital output driver 70 supplies a digital signal as an output signal.

Landscapes

  • Light Receiving Elements (AREA)

Abstract

Photodiode (10) comprenant un substrat semi-conducteur (11) d'un premier type de conductivité, une couche semi-conductrice (12) disposée sur le substrat semi-conducteur (11) comprenant une zone photosensible (14), une première zone (15) d'un deuxième type de conductivité, qui est intégrée dans la zone photosensible (14), et une deuxième zone (16) du premier type de conductivité, qui est intégrée dans la zone photosensible (14) et est décalée latéralement par rapport à la première zone (15), une des première et deuxième zones (15, 16) formant l'anode et l'autre zone formant la cathode de la photodiode (10).
PCT/EP2020/058162 2019-03-27 2020-03-24 Photodiode et circuit de lecture pour photodiode Ceased WO2020193553A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102019107895.4 2019-03-27
DE102019107895.4A DE102019107895A1 (de) 2019-03-27 2019-03-27 Photodiode und Ausleseschaltung für Photodiode

Publications (1)

Publication Number Publication Date
WO2020193553A1 true WO2020193553A1 (fr) 2020-10-01

Family

ID=70008503

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2020/058162 Ceased WO2020193553A1 (fr) 2019-03-27 2020-03-24 Photodiode et circuit de lecture pour photodiode

Country Status (2)

Country Link
DE (1) DE102019107895A1 (fr)
WO (1) WO2020193553A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4236069A (en) * 1978-10-16 1980-11-25 Varo, Inc. Avalanche photodiode gain control system
US20050092896A1 (en) * 2003-09-19 2005-05-05 Moriyasu Ichino Light-receiving method of an avalanche photodiode and a bias control circuit of the same
US20070018268A1 (en) * 2002-11-12 2007-01-25 X-Fab Semiconductor Foundries Ag Monolithically integrated vertical pin photodiode used in bicmos technology
WO2018191497A2 (fr) * 2017-04-13 2018-10-18 Captl Llc Comptage et spectroscopie de photons

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7423302B2 (en) * 2005-11-21 2008-09-09 Digital Imaging Systems Gmbh Pinned photodiode (PPD) pixel with high shutter rejection ratio for snapshot operating CMOS sensor
US9728565B2 (en) * 2013-06-11 2017-08-08 Trustees Of Dartmouth College Low full-well capacity image sensor with high sensitivity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4236069A (en) * 1978-10-16 1980-11-25 Varo, Inc. Avalanche photodiode gain control system
US20070018268A1 (en) * 2002-11-12 2007-01-25 X-Fab Semiconductor Foundries Ag Monolithically integrated vertical pin photodiode used in bicmos technology
US20050092896A1 (en) * 2003-09-19 2005-05-05 Moriyasu Ichino Light-receiving method of an avalanche photodiode and a bias control circuit of the same
WO2018191497A2 (fr) * 2017-04-13 2018-10-18 Captl Llc Comptage et spectroscopie de photons

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KOLKA Z ET AL: "Adaptive voltage source for avalanche photodiodes", RADIOELEKTRONIKA, 2009. RADIOELEKTRONIKA '09. 19TH INTERNATIONAL CONFERENCE, IEEE, PISCATAWAY, NJ, USA, 22 April 2009 (2009-04-22), pages 207 - 210, XP031485801, ISBN: 978-1-4244-3537-1 *
MAMUN KHANDAKER A AL ET AL: "A 10.6[mu]m x 10.6[mu]m CMOS SPAD with integrated readout", 2013 IEEE SENSORS, IEEE, 3 November 2013 (2013-11-03), pages 1 - 4, XP032532526, ISSN: 1930-0395, [retrieved on 20131218], DOI: 10.1109/ICSENS.2013.6688553 *

Also Published As

Publication number Publication date
DE102019107895A1 (de) 2020-10-01

Similar Documents

Publication Publication Date Title
DE112018002674B4 (de) Festkörper-Bildsensor und Abbildungsvorrichtung
EP3948951B1 (fr) Réseau de photodiodes à avalanche
EP2174355A1 (fr) Photodiode à avalanche
DE102020104561B4 (de) Optoelektronische Komponente mit drei Anschlüssen und verbesserter Anpassung des elektrischen Feldes und der Photostromdichte
DE102011076635B3 (de) Detektor zur Detektion elektromagnetischer Strahlung mit Transfersteuerelektrode und Abflusssteuerelektrode
DE3135462A1 (de) Monolithische eingangsstufe eines optischen empfaengers
EP2549536B1 (fr) Structure semi-conductrice pour la détection de photons
DE3345239A1 (de) Festkoerper-bildsensor
WO2004025739A2 (fr) Procede de production d'une diode pin integree et circuit associe
DE3706251C2 (fr)
WO2020193553A1 (fr) Photodiode et circuit de lecture pour photodiode
DE102021200828A1 (de) Fotodiode mit orthogonalem Schichtaufbau
DE112018005789T5 (de) Esd-geschützter halbleiter-photomultiplikator
EP1837918A2 (fr) Dispositif de photodétecteurs, dispositif de mesure doté d'un dispositif de photodétecteurs et procédé de fonctionnement d'un dispositif de mesure
DE60116169T2 (de) Polaritätsunabhängiger optischer Empfänger und Verfahren zu dessen Herstellung
DE68921738T2 (de) Integrierte Lichtempfänger-Halbleiterschaltung.
DE112009004341B4 (de) Halbleiter-Geigermodus-Mikrozellenphotodioden
DE112020007122T5 (de) Fotodiode und verfahren zum betrieb einer fotodiode
DE112021003907T5 (de) Fotodetektionsvorrichtung
DE112021005507T5 (de) Optischer Sensor
DE10230225B4 (de) Photomischdetektor und Verfahren zu seinem Betrieb und zu seiner Herstellung
DE102006013461B3 (de) Photodetektoranordnung, Messanordnung mit einer Photodetektoranordnung und Verfahren zum Betrieb einer Messanordnung
DE112021006393T5 (de) Fotodiodenvorrichtung mit verbesserten Eigenschaften
DE112021002675T5 (de) Optischer Sensor
DE112021000488T5 (de) Verbesserungen der lichtdetektion mit halbleiter-fotodioden

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20714537

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20714537

Country of ref document: EP

Kind code of ref document: A1