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WO2020191628A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2020191628A1
WO2020191628A1 PCT/CN2019/079740 CN2019079740W WO2020191628A1 WO 2020191628 A1 WO2020191628 A1 WO 2020191628A1 CN 2019079740 W CN2019079740 W CN 2019079740W WO 2020191628 A1 WO2020191628 A1 WO 2020191628A1
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semiconductor layer
gan
semiconductor
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French (fr)
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程凯
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Enkris Semiconductor Inc
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Enkris Semiconductor Inc
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Priority to PCT/CN2019/079740 priority Critical patent/WO2020191628A1/zh
Priority to CN201980094459.3A priority patent/CN113892186B/zh
Publication of WO2020191628A1 publication Critical patent/WO2020191628A1/zh
Priority to US17/086,709 priority patent/US12080786B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8171—Doping structures, e.g. doping superlattices or nipi superlattices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching

Definitions

  • the present invention relates to microelectronic technology, in particular to a semiconductor structure and a method of manufacturing the semiconductor structure.
  • High Electron Mobility Transistor is a kind of heterojunction field effect transistor.
  • AlGaN/GaN heterostructure due to the strong two-dimensional electron gas in AlGaN/GaN heterostructure, Generally, AlGaN/GaN HEMTs are depletion-mode devices, making enhancement-mode devices difficult to implement.
  • the application of depletion-type devices has certain limitations. For example, in the application of power switching devices, enhanced (normally-off) switching devices are required.
  • Enhanced GaN switching devices are mainly used in high-frequency devices, power switching devices and digital circuits, and its research has very important significance.
  • the p-type semiconductor material is set in the gate area, and it is necessary to selectively etch the p-type semiconductor in other areas other than the gate.
  • the precise process control of the etching thickness in the epitaxial direction is very difficult, and it is very easy to over-etch the p-type semiconductor.
  • the semiconductor material etched below it, and the defects caused by the etching will cause serious current collapse effects, which will also affect the stability and reliability of the device.
  • the present invention provides a semiconductor structure and a manufacturing method thereof, which solves the problems of complicated manufacturing process and poor stability and reliability of the existing semiconductor structure.
  • the present invention provides a method for manufacturing a semiconductor structure, which includes the following steps: preparing a channel layer, a barrier layer, and a semiconductor layer sequentially stacked on a substrate, wherein the semiconductor layer is a GaN-based material, and the semiconductor layer The upper surface of is a Ga surface; and a P-type GaN-based semiconductor layer with an upper surface of an N surface is prepared above the semiconductor layer.
  • the GaN-based material described in the embodiments of the present invention refers to a semiconductor material based on Ga element and N element, and may be, for example, AlGaN, AlInGaN, GaN, etc.
  • preparing the p-type semiconductor layer of the GaN-based material with the upper surface of the N-face on the semiconductor layer includes: preparing the p-type Ga-face GaN-based material on the semiconductor layer, The p-type Ga-plane GaN-based material is doped with a polarity inversion element, so that the p-type Ga-plane GaN-based material is inverted into a P-type GaN-based semiconductor layer whose upper surface is an N-plane.
  • the polarity inversion element includes Mg.
  • preparing the p-type semiconductor layer of the GaN-based material with the upper surface of the N-face above the semiconductor layer includes: making the p-type Ga-face GaN-based material polarized by the polarity inversion layer Inverted to a P-type GaN-based semiconductor layer whose upper surface is an N-face.
  • preparing a P-type GaN-based semiconductor layer with an N-face upper surface over the semiconductor layer includes: directly bonding a P-type GaN-based semiconductor layer with an N-face upper surface to the semiconductor layer. Layer up.
  • the manufacturing method of the semiconductor structure further includes: selectively etching the p-type semiconductor, leaving only the gate region.
  • the method for manufacturing the semiconductor structure further includes: preparing a gate electrode on the p-type semiconductor, preparing a source electrode in the source region of the barrier layer, and forming a source electrode on the barrier layer. Drain electrode is prepared in the drain region.
  • the manufacturing method of the semiconductor structure is characterized in that it further comprises: before forming the channel layer, sequentially forming a nucleation layer and a buffer layer on the substrate.
  • the present invention provides a semiconductor structure, which is characterized by comprising:
  • the semiconductor structure further includes: a gate electrode disposed above the p-type semiconductor layer; a source electrode disposed in the source region of the barrier layer; and a source electrode disposed on the barrier layer The drain electrode of the drain region of the layer.
  • the semiconductor structure further includes: a nucleation layer between the channel layer and the substrate; and a buffer layer between the nucleation layer and the channel layer.
  • a P-type GaN-based semiconductor layer with an N-face on the upper surface is formed in the gate region to achieve the purpose of pinching off the n-type conductive layer under the gate to realize the semiconductor structure.
  • the etching process is easy to control, which reduces the process difficulty of selective etching of the p-type semiconductor material in the gate region, and improves the stability and stability of the device. reliability.
  • a high-quality Schottky gate can be achieved by using different metals and adjusting the work function; in addition, it is also possible to achieve high doping concentration of Mg doping on the surface of the n-face p-type GaN of the gate. Realize ohmic contact.
  • Figures 1a, 2, 3a, 3b, 4a, 4b, 4c, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 8b, 9a, 9b, and 10 are respectively the preparation process of the semiconductor structure provided by an embodiment of the present invention
  • Figure 1b shows a schematic diagram of the atomic structure of Ga-plane GaN
  • Figure 1c shows a schematic diagram of the atomic structure of N-plane GaN.
  • Step 601 As shown in FIG. 1a, a channel layer 23, a barrier layer 24, and a semiconductor layer 3 are prepared sequentially on the substrate 1, wherein the semiconductor layer 3 is a GaN-based material, and the upper surface of the semiconductor layer 3 (away from the substrate) The bottom surface) is the Ga surface.
  • the GaN-based material described in the embodiments of the present invention refers to a semiconductor material based on Ga element and N element, and may be, for example, AlGaN, AlInGaN, GaN, etc.
  • Figure 1b shows a schematic diagram of the atomic structure of Ga-plane GaN
  • Figure 1c shows a schematic diagram of the atomic structure of N-plane GaN.
  • Ga-plane GaN taking Ga-N bonds parallel to the C-axis as a reference, the Ga atoms in each Ga-N bond are closer to the substrate 1, which is Ga-plane GaN. Conversely, if the N atoms in each Ga-N bond are closer to the substrate 1, it is N-plane GaN.
  • the Ga-plane GaN in Figure 1b is inverted to obtain N-plane GaN, the side far from the substrate shown in Figure 1b is defined as the Ga side, and the side far away from the substrate shown in Figure 1c is defined It is the N plane, and the Ga plane corresponds to the N plane. Since Ga-plane GaN and N-plane GaN have different atomic arrangements on the side away from the substrate, their characteristics are also different.
  • the barrier layer 24 and the channel layer 23 may also be GaN-based materials. Further, the barrier layer 24 and the channel layer 23 may also be Ga-plane GaN materials.
  • the substrate 1 can be selected from semiconductor materials, ceramic materials, or polymer materials.
  • the substrate 1 is preferably selected from sapphire, diamond, silicon carbide, silicon, lithium niobate, silicon on insulator (SOI), gallium nitride, or aluminum nitride.
  • the channel layer 23 and the barrier layer 24 may be semiconductor materials that can form two-dimensional electron gas.
  • the channel layer 23 may be GaN
  • the barrier layer 24 may be AlGaN
  • the channel layer 23 and the barrier layer 24 form a heterogeneous structure to form a two-dimensional electron gas.
  • a nucleation layer 21 and a buffer layer 22 may be grown on the substrate 1 in sequence.
  • the nucleation layer 21 can reduce dislocation density and defect density, and improve crystal quality.
  • the nucleation layer 21 may be one or more of AlN, AlGaN and GaN.
  • the buffer layer 22 can buffer the stress in the epitaxial structure above the substrate and prevent the epitaxial structure from cracking.
  • the buffer layer 22 may include one or more of GaN, AlGaN, and AlInGaN.
  • the semiconductor layer 3 can protect the underlying semiconductor structure, so that it is not necessary to strictly control the etching depth when the P-type N-face GaN-based material layer 5 is selectively etched, even if there is a part of the epitaxial layer above the barrier layer 24 It does not matter if it is etched away.
  • the semiconductor layer 3 can be grown in situ, or can be grown by atomic layer deposition (ALD, Atomic Layer Deposition), or Chemical Vapor Deposition (CVD, Chemical Vapor Deposition), or Molecular Beam Epitaxy (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal-Organic Chemical Vapor Deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), Or a combination thereof.
  • ALD Atomic Layer Deposition
  • CVD Chemical Vapor Deposition
  • MBE Molecular Beam Epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • Step 602 As shown in FIG. 3a, a p-type GaN-based semiconductor layer 5 is prepared above the semiconductor layer 3, and the upper surface of the p-type GaN-based semiconductor layer 5 is an N-face.
  • preparing the P-type GaN-based semiconductor layer 5 with the upper surface of the N-face on the semiconductor layer 3 may include various methods.
  • a P-type GaN-based semiconductor layer 5 with an N-face upper surface is prepared on the semiconductor layer 3, and a p-type Ga-face GaN-based material can be epitaxially grown first, and a polarity inversion element is added during the epitaxial growth.
  • the polarity reversal element may be, for example, Mg, etc., so that the GaN-based material on the Ga side becomes the GaN-based material on the N side.
  • continuous epitaxial growth is possible.
  • the GaN-based material can be made from the Ga side Inverted to N face.
  • the process of changing the Ga surface to the N surface by adding a polarity reversal element may have a transition process, so the lower surface of the p-type semiconductor layer 5 close to the semiconductor layer 3 may be a Ga surface, but the p-type semiconductor
  • the thickness of the Ga-plane GaN contained in the layer 5 does not exceed 120 nm, preferably it can be controlled below 40 nm, and even more preferably it can be less than 15 nm.
  • a P-type GaN-based semiconductor layer 5 with an N-face upper surface is prepared on the semiconductor layer 3, as shown in FIG. 3b, during the epitaxial growth process, a polar pattern is prepared on the Ga-face GaN-based material.
  • the reversal layer 31 thus realizes polarity reversal and realizes the preparation of N-face GaN-based materials. Specifically, during the preparation of the semiconductor layer 3 and the p-type semiconductor layer 5, continuous epitaxial growth is possible. After the barrier layer 24 on the Ga surface is prepared, the polarity inversion layer 31 can be prepared to make the GaN-based material from the Ga surface Inverted to N face.
  • the lower surface of the p-type semiconductor layer 5 close to the barrier layer may also be an N surface.
  • the polarity reversal layer 31 may be Al 2 O 3, for example.
  • the polarity inversion layer 31 is Al 2 O 3 , it can also prevent etching. When the p-type semiconductor layer 5 is etched, the etching is stopped on the polarity inversion layer.
  • a P-type GaN-based semiconductor layer 5 with an N-face upper surface is prepared above the semiconductor layer 3, and the N-face P-type semiconductor layer 5 can be directly bonded on the semiconductor layer 3.
  • the material of the p-type semiconductor layer 5 may be selected from, for example, one or a combination of the following materials: p-type AlGaN, p-type GaN, and p-type InGaN.
  • the lower surface of the p-type GaN-based semiconductor layer 5 close to the semiconductor layer 3 can be a Ga surface, the remaining Ga-surface GaN that is not etched away will not have a significant impact on the overall performance of the device due to its thin thickness.
  • Step 603 As shown in FIG. 4a, the p-type semiconductor layer 5 is selectively etched, leaving only the gate region.
  • the gate area in the present invention is the area used to prepare the gate. Those skilled in the art should understand that the gate area can be defined and determined according to the design and process of the relevant device.
  • the selective etching process performed on the p-type semiconductor layer 5 may be a wet etching process, for example, a wet etching process using KOH.
  • N-face GaN-based materials are easily etched, while Ga-face GaN-based materials are not easily etched. Therefore, in the process of etching the N-face GaN-based material, the etching process can be easily controlled to avoid damage to the Ga-face GaN-based material under the N-face GaN-based material.
  • the etching process can be easily controlled to avoid etching the p-type semiconductor layer 5 In the process, damage to the barrier layer is caused.
  • the selective etching of the p-type GaN-based semiconductor layer 5 can be specifically shown in Figures 4b-4c.
  • a mask layer 41 is deposited on the p-type GaN-based semiconductor layer 5.
  • the mask layer 41 may be a dielectric layer such as SiN. SiO2, which can also be metals such as TiN, Ni, etc.; then, selective etching is performed to retain only the p-type GaN-based semiconductor layer 5 and the mask layer 41 in the gate region.
  • the mask layer 41 can play a good role in protecting the p-type GaN-based semiconductor layer 5 during the etching process.
  • the etching can be either wet etching or a combination of wet etching and dry etching to avoid excessive lateral etching reactions in the gate area during wet etching.
  • Step 604 As shown in FIG. 5a, prepare the gate electrode 51, the source electrode 6, and the drain electrode 7.
  • a gate electrode 51 is prepared above the p-type semiconductor 5
  • a source electrode 6 is prepared in the source region of the barrier layer 24, and a drain electrode 7 is prepared in the drain region of the barrier layer 24.
  • the source region and the drain region in the present invention are similar to the gate region in the present invention, that is, the region used to prepare the source and drain. Those skilled in the art should understand that they can be performed according to the design and process of related devices. Define and confirm.
  • the source electrode 6, the drain electrode 7, and the electrode material 51 on the p-type semiconductor layer 5 can be made of a metal material such as a nickel alloy, or can be made of a metal oxide or a semiconductor material. 6.
  • the specific preparation materials of the drain electrode 7 and the electrode material 51 on the p-type semiconductor layer 5 are not limited.
  • a passivation layer 8 can be formed on the surface of the exposed barrier layer 24 first. Then, an electrode material 51 is prepared on the P-type semiconductor material 5, as shown in FIG. 5b.
  • the passivation layer 8 can be, for example, Al 2 O 3 , SiO 2 , SiN, or the like.
  • the p-type semiconductor layer 5 can also be prepared.
  • a groove 4 was provided in the gate region of the semiconductor layer 3, and the groove 4 completely penetrates the semiconductor layer 3 and stops on the barrier layer 24.
  • the groove 4 may also extend to the barrier layer 24 and partially penetrate the barrier layer 24.
  • the p-type semiconductor layer 5 is selectively etched , Only the p-type semiconductor layer 5 in the gate region is preserved; as shown in FIGS. 9a and 9b, the gate electrode 51, the source electrode 6, and the drain electrode 7 are continuously prepared.
  • the barrier layer 24 may adopt a sandwich structure.
  • the barrier layer 24 includes a first outer interlayer 241: AlGaN, an intermediate layer 242: GaN, and a second outer interlayer 243: AlGaN.
  • the groove 4 can penetrate to the second outer interlayer 243 of the sandwich structure of the barrier layer 24.
  • the intermediate layer 242 can function as a stop layer in the local etching process for forming the groove 4 to protect
  • the first outer interlayer 241 on the surface of the channel layer 23 is not damaged by the local etching process.
  • the present invention does not strictly limit the preparation depth of the groove 4, as long as the p-type semiconductor layer 5 inside the groove 4 can pinch off the n-type conductive layer under the gate to achieve a semiconductor structure.
  • An embodiment of the present invention also provides a semiconductor structure, as shown in FIG. 5a.
  • the semiconductor structure includes: a channel layer 23, a barrier layer 24, and a semiconductor layer 3 sequentially superimposed on a substrate 1; and a p-type semiconductor layer 5 formed on a gate region above the semiconductor layer 3.
  • the semiconductor layer 3 is a GaN-based material
  • the upper surface of the semiconductor layer 3 is a Ga surface.
  • the P-type semiconductor layer 5 is a GaN-based material whose upper surface is an N-face.
  • the substrate 1 may preferably be selected from sapphire, diamond, silicon carbide, silicon, lithium niobate, silicon insulator 1 (SOI), gallium nitride, or aluminum nitride.
  • the channel layer 23 and the barrier layer 24 may be semiconductor materials that can form two-dimensional electron gas.
  • the channel layer 23 can be GaN
  • the barrier layer 24 can be AlGaN or GaN
  • the channel layer 23 and the barrier layer 24 form a heterogeneous structure to form a two-dimensional electron gas.
  • the material of the p-type semiconductor layer 5 may be selected from, for example, one or a combination of more of the following materials: p-type AlGaN, p-type GaN, p-type InGaN, and p-type GaN/AlGaN .
  • the semiconductor structure may further include a nucleation layer 21 and a buffer layer 22 disposed under the channel layer 23.
  • a nucleation layer 21 prepared above the substrate 1.
  • the nucleation layer 21 may be One or more of AlN, AlGaN and GaN.
  • the GaN-based semiconductor structure may further include a buffer layer 22 prepared above the nucleation layer 21, and the buffer layer 22 may include GaN, AlGaN, and AlInGaN. One or more of.
  • the semiconductor structure further includes a source electrode 6 provided in the source region of the barrier layer 24, a drain electrode 7 provided in the drain region of the barrier layer 24, and The gate electrode 51 above the p-type semiconductor layer.
  • the source electrode 6, the drain electrode 7, and the gate electrode 51 can be made of conductive metal materials such as nickel alloys, or can be made of metal oxide or semiconductor materials.
  • the present invention relates to the source electrode 6, the drain electrode 7 and the p-type semiconductor layer. 5
  • the specific preparation material of the electrode material 51 above is not limited.
  • the semiconductor structure may further include The groove 4 in the gate region of the semiconductor layer 3 can completely penetrate the semiconductor layer 3 and stop on the barrier layer 24. As shown in FIG. 9b, the groove 4 can also extend to the barrier layer 24 In, part of the barrier layer 24 penetrates.
  • the semiconductor structure may not include the groove 4 and the p-type semiconductor layer 5 It can be directly prepared in the gate area, and the groove 4 may partially penetrate the semiconductor layer 3.
  • the barrier layer 24 may also adopt a sandwich structure including a first outer interlayer prepared on the surface of the channel layer 23 241.
  • An intermediate layer 242 sandwiched between the first outer interlayer 241 and the second outer interlayer 243 and the second outer interlayer 243.
  • the materials of the first outer interlayer 241, the intermediate layer 242, and the second outer interlayer 243 can be adjusted according to the material of the channel layer 23.
  • the first outer interlayer 241 and the second outer interlayer 243 can be made of AlGaN
  • the intermediate layer 242 can be made of GaN.
  • the present invention does not specifically limit the materials of the first outer interlayer 241, the intermediate layer 242, and the second outer interlayer 243.

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Abstract

一种半导体结构及其制造方法，解决了现有半导体结构的制造工艺复杂以及稳定性和可靠性差的问题。该半导体结构，包括衬底（1）；所述衬底（1）上依次叠加的沟道层（23）、势垒层（24）及半导体层（3），其中所述半导体层（3）为GaN基材料，且所述半导体层（3）的上表面为Ga面；以及形成于所述半导体层（3）的栅极区域的上表面为N面的p型GaN基半导体层（5）。

Description

一种半导体结构及其制造方法 技术领域
本发明涉及微电子技术，具体涉及一种半导体结构，以及制造该半导体结构的方法。
背景技术
高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)是一种异质结场效应晶体管，以AlGaN/GaN异质结构为例，由于AlGaN/GaN异质结构中存在较强的二维电子气，通常AlGaN/GaN HEMT是耗尽型器件，使得增强型器件不易实现。而在许多地方耗尽型器件的应用又具有一定的局限性，比如在功率开关器件的应用中，就需要增强型(常关型)开关器件。增强型氮化镓开关器件主要用于高频器件、功率开关器件和数字电路等，它的研究具有十分重要的意义。
实现增强型氮化镓开关器件，需要找到合适的方法来降低零栅压时栅极下方的沟道载流子浓度，例如通过在栅极区域设置p型半导体材料。但是发明人发现该方法至少有如下缺陷：
栅极区域设置p型半导体材料，需要选择性刻蚀栅极以外的其他区域的p型半导体，而在外延方向上刻蚀厚度的精确工艺控制是非常难的，非常容易对p型半导体过刻而刻蚀到其下方的半导体材料，而且刻蚀中带来的缺陷，会引起严重的电流崩塌效应，同样会影响到器件的稳定性和可靠性。
发明内容
有鉴于此，本发明提供一种半导体结构及其制造方法，解决了现有半导体结构的制造工艺复杂以及稳定性和可靠性差的问题。
本发明提供了一种半导体结构的制造方法，包括以下步骤：在衬底上制备依次叠加的沟道层、势垒层及半导体层，其中所述半导体层为GaN基材料，且所述半导体层的上表面为Ga面；以及在所述半导体层上方制备上表面为N面的P型 GaN基半导体层。
本发明实施例中所描述的GaN基材料是指以Ga元素和N元素为基础构成的半导体材料，例如可为AlGaN、AlInGaN、GaN等。
在本发明的一实施例中，在所述半导体层上方制备上表面为N面的GaN基材料的所述p型半导体层包括：在所述半导体层的上方制备p型Ga面GaN基材料，在所述p型Ga面GaN基材料中掺杂极性反转元素，以使得p型Ga面GaN基材料极性反转为上表面为N面的P型GaN基半导体层。
在本发明的一实施例中，所述极性反转元素包括Mg。
在本发明的一实施例中，在所述半导体层上方制备上表面为N面的GaN基材料的所述p型半导体层包括：通过极性反转层使p型Ga面GaN基材料极性反转为上表面为N面的P型GaN基半导体层。
在本发明的一实施例中，在所述半导体层上方制备上表面为N面的P型GaN基半导体层包括：将上表面为N面的P型GaN基半导体层直接键合在所述半导体层上。
在本发明的一实施例中，该半导体结构的制造方法，还包括：选择性刻蚀所述p型半导体，仅保留栅极区域部分。
在本发明的一实施例中，该半导体结构的制造方法，还包括：在所述p型半导体上制备栅电极，在所述势垒层的源极区域制备源电极，在所述势垒层的漏极区域制备漏电极。
在本发明的一实施例中，该半导体结构的制造方法，其特征在于，进一步包括：在形成所述沟道层之前，依次形成于所述衬底上的成核层和缓冲层。
本发明提供了一种半导体结构，其特征在于，包括：
衬底；所述衬底上依次叠加的沟道层、势垒层以及半导体层，其中所述势垒层为GaN基材料，且所述势垒层的上表面为Ga面；以及形成于所述势垒层的栅极区域的p型半导体层，其中所述p型半导体层为GaN基材料，且所述p型半导体层的上表面为N面。
在本发明的一实施例中，该半导体结构，进一步包括：设置于所述p型半导体层上方的栅电极；设置于所述势垒层的源极区域的源电极；设置于所述势垒层的漏极区域的漏电极。
在本发明的一实施例中，该半导体结构进一步包括：所述沟道层与所述衬底之间的成核层；以及所述成核层与所述沟道层之间的缓冲层。
本发明实施例所提供的半导体结构及其制造方法，在栅极区域形成上表面为N面的P型GaN基半导体层，即可达到夹断栅极下方n型导电层的目的，以实现半导体结构。更重要的是，由于N面GaN基材料具有易于腐蚀的特点，刻蚀过程易于控制，降低了对于栅极区域p型半导体材料进行选择性刻蚀的工艺难度，同时提高了器件的稳定性和可靠性。在栅极区域，可以通过采用不同的金属、调整功函数，实现高质量的肖特基栅极；另外，也可以在栅极N面p型GaN的表面实现高掺杂浓度的Mg掺杂，实现欧姆接触。
附图简要说明
图1a、2、3a、3b、4a、4b、4c、5a、5b、6a、6b、7a、7b、8a、8b、9a、9b和10分别为本发明一实施例提供的半导体结构在制备过程中的分解示意图。
图1b所示为Ga面GaN的原子结构示意图，图1c所示为N面GaN的原子结构示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例和/或结构之间具有任何关联性。
本发明一实施例提供的一种半导体结构的制备方法包括如下步骤：
步骤601：如图1a所示，衬底1上制备依次叠加的沟道层23、势垒层24以及半导体层3，其中半导体层3为GaN基材料，且半导体层3的上表面(远离衬底的表面)为Ga面。
本发明实施例中所描述的GaN基材料是指以Ga元素和N元素为基础构成的半导体材料，例如可为AlGaN、AlInGaN、GaN等。
图1b所示为Ga面GaN的原子结构示意图，图1c所示为N面GaN的原子结构示意图。关于Ga面GaN，以平行于C轴的Ga-N键为参照，每一个Ga-N键中的Ga原子更靠近衬底1，即为Ga面GaN。反之，如果每一个Ga-N键中的N原子更靠近衬底1，即为N面GaN。对于同一GaN基半导体层，将图1b中的Ga面GaN倒转即得到N面GaN，把图1b中所示的远离衬底的一面定义为Ga面，而图1c所示的远离衬底一面定义为N面，Ga面与N面相对应。由于Ga面GaN和N面GaN各自远离衬底的一面原子排列不同，因此其特性也存在差异。
在本发明一实施例中，势垒层24和沟道层23也可为GaN基材料，进一步地，势垒层24及沟道层23也可为Ga面的GaN材料。
衬底1可选自半导体材料、陶瓷材料或高分子材料等。例如，衬底1优选自蓝宝石、金刚石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓或氮化铝。
沟道层23和势垒层24为可形成二维电子气的半导体材料即可。例如，以GaN基材料为例，沟道层23可采用GaN，势垒层24可采用AlGaN，沟道层23和势垒层24构成异质结构以形成二维电子气。
在本发明一实施例中，如图2所示，在生长沟道层23之前，还可在衬底1上依次生长成核层21和缓冲层22。以GaN基半导体结构为例，成核层21可降低位错密度和缺陷密度，提升晶体质量。该成核层21可为AlN、AlGaN和GaN中的一种或多种。缓冲层22可缓冲衬底上方外延结构中的应力，避免外延结构开裂。该缓冲层22可包括GaN、AlGaN、AlInGaN中的一种或多种。
半导体层3可对下层半导体结构起到保护作用，使得在后续对P型N面 GaN基材料层5进行选择性刻蚀时不必严格控制刻蚀深度，即使有部分势垒层24上方的外延层被刻蚀掉也没关系。半导体层3可以通过原位生长，也可以是通过原子层沉积(ALD,Atomic layer deposition)、或化学气相沉积(CVD，Chemical Vapor Deposition)、或分子束外延生长(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式制得。应该理解，这里描述形成半导体层3的方法只是进行举例，本发明可以通过本领域的技术人员公知的任何方法形成势垒层24上方的半导体层3。
步骤602：如图3a所示，在半导体层3上方制备p型GaN基半导体层5，且所述p型GaN基半导体层5的上表面为N面。其中，上述步骤中，在半导体层3上方制备上表面为N面的P型GaN基半导体层5可包括多种方法。
在一实施例中，在半导体层3上方制备上表面为N面的P型GaN基半导体层5，可首先外延生长p型Ga面的GaN基材料，在外延生长的同时添加极性反转元素，极性反转元素可例如为Mg等，从而使Ga面的GaN基材料变成N面的GaN基材料。更进一步地，在制备半导体层3及p型半导体层5时，可连续外延生长，在Ga面的半导体层3制备完成后，通过添加极性反转元素，就可使GaN基材料从Ga面反转为N面。在该实施例中，通过添加极性反转元素使有Ga面变为N面的过程可以有过渡过程，因此p型半导体层5靠近半导体层3的下表面可为Ga面，但p型半导体层5中包含的Ga面GaN的厚度不超过120nm，较优的可控制在40nm以下，再优选的可小于15nm。
在一实施例中，在半导体层3上方制备上表面为N面的P型GaN基半导体层5，如图3b所示，在外延生长的过程中，在Ga面的GaN基材料上方制备极性反转层31从而实现极性反转，实现N面的GaN基材料的制备。具体地，在制备半导体层3及p型半导体层5时，可连续外延生长，在Ga面的势垒层 24制备完成后，制备极性反转层31，就可以使GaN基材料从Ga面反转为N面。在该实施例中，p型半导体层5靠近势垒层的下表面也可为N面。该极性反转层31可例如为Al 2O 3。此外，当该极性反转层31为Al 2O 3时，其还可以有阻止刻蚀的作用，当刻蚀p型半导体层5时，使刻蚀停止在该极性反转层上。
在一实施例中，在半导体层3上方制备上表面为N面的P型GaN基半导体层5，可直接在半导体层3上方键合N面的P型半导体层5。
本发明一实施例中，p型半导体层5的材质可例如选自以下几种材料中的一种或多种的组合：p型AlGaN、p型GaN和p型InGaN。当p型GaN基半导体层5靠近半导体层3的下表面可为Ga面时，未刻蚀掉而残留的Ga面GaN由于厚度较薄，对器件整体性能不会造成明显影响。
步骤603：如图4a所示，对p型半导体层5进行选择性刻蚀，仅保留栅极区域的部分。
本发明中的栅极区域，即用于制备栅极的区域，本领域人员应当理解，栅极区域可根据相关器件的设计和工艺而进行定义和确定。
在本发明一实施例中，该对p型半导体层5进行的选择性刻蚀过程可为湿法刻蚀过程，例如采用KOH进行的湿法刻蚀过程。
在湿法刻蚀中，N面GaN基材料极易被刻蚀，而Ga面GaN基材料不易被刻蚀。因此，刻蚀N面GaN基材料的过程中，可轻易控制刻蚀进程，避免对N面GaN基材料下方的Ga面GaN基材料造成损伤。
由于p型半导体层5为上表面为N面的GaN基材料，而半导体层3为上表面为Ga面的GaN基材料，因此可轻易控制刻蚀过程，避免在刻蚀p型半导体层5的过程中，对势垒层造成损伤。
其中对p型GaN基半导体层5进行选择性刻蚀可具体如图4b-4c所示，先在p型GaN基半导体层5上沉积掩膜层41，掩膜层41可以是介质层如SiN、SiO2，也可以是金属如TiN、Ni等；然后进行选择性刻蚀，仅保留栅极区域的p型GaN基半导体层5及掩膜层41。掩膜层41在刻蚀过程中可以对p型GaN 基半导体层5起到很好的保护作用。在该实施例中，刻蚀，既可以是湿法刻蚀，也可以是湿法刻蚀与干法刻蚀相互结合，避免栅极区域在湿法刻蚀中过多的横向刻蚀反应。
步骤604：如图5a所示，制备栅电极51，源电极6，漏电极7。
在p型半导体5上方制备栅电极51，在势垒层24的源极区域制备源电极6，以及在势垒层24的漏极区域制备漏电极7。
本发明中源极区域和漏极区域，类似于本发明中的栅极区域，即用于制备源极和漏极的区域，本领域人员应当理解，其可根据相关器件的设计和工艺而进行定义和确定。
还应当理解，源电极6、漏电极7以及p型半导体层5上面的电极材料51可采用例如镍合金的金属材料制成，也可采用金属氧化物或半导体材料制成，本发明对源电极6、漏电极7以及p型半导体层5上面的电极材料51的具体制备材料不做限定。
在本发明一实施例中，如图5b所示，当要在P型半导体材料5上面制作电极材料51用作栅电极时，可先在暴露的势垒层24表面制备钝化层8。然后再在P型半导体材料5上方制备电极材料51，如图5b所示。钝化层8可例如为Al 2O 3、SiO 2、SiN等。
在本发明一实施例中，为了进一步提高该半导体结构的性能，进一步降低栅极区域下方沟道层23中的二维电子气密度，如图6a所示，还可在制备p型半导体层5之前，在半导体层3的栅极区域设置凹槽4，该凹槽4完全贯穿半导体层3并停止于势垒层24之上。在本发明另一实施例中，如图6b所示，该凹槽4也可延伸至势垒层24，部分贯穿势垒层24。在形成凹槽4后，如图7a及7b所示，再在势垒层24上方制备p型半导体层5；然后如图8a及8b所示，再对p型半导体层5进行选择性刻蚀，仅保栅极区域的p型半导体层5；再如图9a及9b所示，继续制备栅电极51、源电极6、漏电极7。
在本发明一实施例中，势垒层24可采用三明治结构，例如图10所示，势 垒层24包括第一外夹层241：AlGaN，中间层242：GaN，第二外夹层243：AlGaN，凹槽4就可贯穿至该势垒层24的三明治结构的第二外夹层243，此时该中间层242可在形成凹槽4的局部刻蚀工艺中起到停止层的作用，以保护位于沟道层23表面的该第一外夹层241不被该局部刻蚀工艺损坏。然而本发明对凹槽4的制备深度不做严格限定，只要凹槽4内部的p型半导体层5能够夹断栅极下方n型导电层以实现半导体结构即可。
本发明的一实施例还提供了一种半导体结构，如图5a所示。该半导体结构包括：衬底1上依次叠加的沟道层23、势垒层24及半导体层3；形成于半导体层3的上方的栅极区域的p型半导体层5。其中，半导体层3为GaN基材料，且半导体层3的上表面为Ga面。P型半导体层5为上表面为N面的GaN基材料。
衬底1可优选自蓝宝石、金刚石、碳化硅、硅、铌酸锂、绝缘衬底1硅(SOI)、氮化镓或氮化铝。
沟道层23和势垒层24为可形成二维电子气的半导体材料即可。例如，以GaN基材料为例，沟道层23可采用GaN，势垒层24可采用AlGaN或GaN，沟道层23和势垒层24构成异质结构以形成二维电子气。
在本发明一实施例中，p型半导体层5的材质可例如选自以下几种材料中的一种或多种的组合：p型AlGaN、p型GaN、p型InGaN和p型GaN/AlGaN。
在本发明一进一步实施例中，如图5a所示，为了提高器件性能，满足相关技术需求，该半导体结构可进一步包括设置沟道层23下方的成核层21和缓冲层22。以GaN基半导体结构为例，为降低位错密度和缺陷密度，防止回熔，提升晶体质量等技术需求，可进一步包括制备于衬底1上方的成核层21，该成核层21可为AlN、AlGaN和GaN中的一种或多种。此外，为了缓冲衬底上方外延结构中的应力，避免外延结构开裂，该GaN基半导体结构还可进一步包括制备于成核层21上方的缓冲层22，该缓冲层22可包括GaN、AlGaN、AlInGaN中的一种或多种。
在本发明一实施例中，如图5a所示，该半导体结构还包括设置于势垒层24的源极区域的源电极6、设置于势垒层24的漏极区域的漏电极7和设置于p型半导体层上方的栅电极51。源电极6、漏电极7以及栅电极51可采用例如镍合金的导电金属材料制成，也可采用金属氧化物或半导体材料制成，本发明对源电极6、漏电极7以及p型半导体层5上面的电极材料51的具体制备材料不做限定。
在本发明一实施例中，为了进一步提高该半导体结构的性能，进一步降低栅极区域下方沟道层23中的二维电子气密度，如图9a所示，该半导体结构还可进一步包括设置于半导体层3栅极区域的凹槽4，该凹槽4可完全贯穿半导体层3，停止于势垒层24之上，又如图9b所示，该凹槽4还可延伸至势垒层24中，部分贯穿势垒层24。然而应当理解，考虑到只要栅极区域制备有p型半导体层5就可达到夹断栅极下方n型导电层的目的，该半导体结构也可并不包括该凹槽4，p型半导体层5直接制备于栅极区域即可，该凹槽4也可部分贯穿半导体层3。
在本发明一实施例中，当该半导体结构包括凹槽4时，如图10所示，势垒层24还可采用三明治结构，该三明治结构包括制备于沟道层23表面的第一外夹层241、夹在该第一外夹层241和第二外夹层243之间的中间层242以及第二外夹层243。应当理解，该第一外夹层241、中间层242以及第二外夹层243的材料可根据沟道层23的材料而调整。例如，以GaN基材料为例，当沟道层23采用GaN时，该第一外夹层241和第二外夹层243可采用AlGaN制成，该中间层242可采用GaN制成。然而，本发明对该第一外夹层241、中间层242以及第二外夹层243的材料不做具体限定。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的 具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种半导体结构，其特征在于，包括：
    衬底；
    所述衬底上依次叠加的沟道层、势垒层及半导体层，其中所述半导体层为GaN基材料，且所述半导体层的上表面为Ga面；以及
    形成于所述半导体层的栅极区域的上表面为N面的P型GaN基半导体层。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构进一步包括：
    设置于所述p型半导体层上方的栅电极；
    设置于所述势垒层的源极区域的源电极；
    设置于所述势垒层的漏极区域的漏电极。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构进一步包括：
    所述沟道层与所述衬底之间的成核层；以及
    所述成核层与所述沟道层之间的缓冲层。
  4. 根据权利要求1所述的半导体结构，其特征在于：
    所述p型GaN基半导体层包括p型AlGaN、p型GaN、p型InGaN中的一种或多种组成的多层结构或超晶格结构。
  5. 根据权利要求1所述的半导体结构，其特征在于，还包括设置于所述势垒层栅极区域的凹槽，所述凹槽贯穿所述势垒层停留在所述沟道层上或部分贯穿所述势垒层停留在所述势垒层中。
  6. 一种半导体结构的制造方法，其特征在于，包括以下步骤：
    在衬底上制备依次叠加的沟道层、势垒层及半导体层，其中所述半导体层为GaN基材料，且所述半导体层的上表面为Ga面；以及
    在所述半导体层上方制备上表面为N面的P型GaN基半导体层。
  7. 根据权利要求6所述的半导体结构的制造方法，其特征在于，在所述半导 体层上方制备上表面为N面的GaN基材料的所述p型半导体层包括：
    在所述半导体层的上方制备p型Ga面GaN基材料，在所述p型Ga面GaN基材料中掺杂极性反转元素，以使得p型Ga面GaN基材料极性反转为上表面为N面的P型GaN基半导体层。
  8. 根据权利要求7所述的半导体结构的制造方法，其特征在于，所述极性反转元素包括Mg。
  9. 根据权利要求6所述的半导体结构的制造方法，其特征在于，在所述半导体层上方制备上表面为N面的GaN基材料的所述p型半导体层包括：
    通过极性反转层使p型Ga面GaN基材料极性反转为上表面为N面的p型GaN基半导体层。
  10. 根据权利要求6所述的半导体结构的制造方法，其特征在于，在所述半导体层上方制备上表面为N面的p型GaN基半导体层包括：
    将上表面为N面的p型GaN基半导体层直接键合在所述半导体层上。
  11. 根据权利要求6所述的半导体结构的制造方法，其特征在于，还包括：
    选择性刻蚀所述p型半导体，仅保留栅极区域部分。
  12. 根据权利要求6所述的半导体结构的制造方法，其特征在于，还包括：
    在所述p型半导体层上制备栅电极，在所述势垒层的源极区域制备源电极，在所述势垒层的漏极区域制备漏电极。
  13. 根据权利要求6所述的半导体结构的制造方法，其特征在于，进一步包括：
    在形成所述沟道层之前，依次形成于所述衬底上的成核层和缓冲层。
  14. 根据权利要求6所述的半导体结构的制造方法，其特征在于，进一步包括：先在所述势垒层栅极区域制备凹槽，再在所述势垒层上方制备上表面为N面的p型GaN基半导体层，所述凹槽贯穿所述势垒层停留在所述沟道层上或部分贯穿所述势垒层停留在所述势垒层中。
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