WO2020188167A1 - Procede de transfert d'une couche utile sur un substrat support - Google Patents
Procede de transfert d'une couche utile sur un substrat support Download PDFInfo
- Publication number
- WO2020188167A1 WO2020188167A1 PCT/FR2020/050367 FR2020050367W WO2020188167A1 WO 2020188167 A1 WO2020188167 A1 WO 2020188167A1 FR 2020050367 W FR2020050367 W FR 2020050367W WO 2020188167 A1 WO2020188167 A1 WO 2020188167A1
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- WIPO (PCT)
- Prior art keywords
- buried
- plane
- annealing
- transfer method
- support substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- TITLE PROCESS FOR TRANSFERRING A USEFUL LAYER ON A
- the present invention relates to the field of microelectronics. It relates in particular to a method of transferring a useful layer onto a support substrate.
- a method of transferring a useful layer 3 onto a support substrate 4, shown in FIG. 1, is known from the state of the art; this process described in particular in documents WO2005043615 and WO2005043616 comprises the following steps:
- the species implanted at the level of the buried fragile plane 2 are at the origin of the development of microcavities.
- the thermal embrittlement treatment has the effect of promoting the growth and pressurization of these microcavities.
- additional external forces energy pulse
- the initiation of a fracture wave in the buried fragile plane 2 is operated, which wave propagates in a self-sustaining manner, leading the transfer of the useful layer 3 by detachment at the level of the buried fragile plane 2.
- This process can be used for the manufacture of silicon on insulator substrates (SOI - “Silicon on insulator”).
- the donor substrate 1 and the support substrate 4 are each formed from a silicon wafer, the standardized diameter of which is typically 200mm, 300mm, or even 450 mm for the next generations.
- One and / or the other of the donor substrate 1 and of the support substrate 4 are oxidized at the surface.
- SOI substrates must meet very precise specifications. This is particularly the case for the average thickness and the uniformity of thickness of the useful layer 3. Compliance with these specifications is required for the proper functioning of the semiconductor devices which will be formed in and on this useful layer 3. .
- the architecture of these semiconductor devices requires the availability of SOI substrates having a very low average thickness of the useful layer 3, for example less than 50 nm, and having very good uniformity of thickness of the layer. useful 3.
- the expected thickness uniformity can be of the order of 5% at most, corresponding to variations typically ranging from +/- 0.3nm to +/- lnm over the entire surface of the useful layer 3. Even if additional finishing steps, such as etching or heat treatments for surface smoothing, are carried out after the useful layer 3 is transferred to the support substrate 4, it is important that the surface morphological properties are as favorable as possible after transfer, to guarantee that the final specifications are maintained.
- the Applicant has observed that the useful layers 3 transferred according to the aforementioned method, resulting from bonded structures prepared under similar conditions and having undergone the same heat treatment of embrittlement, did not exhibit morphological surface properties (roughness, uniformity of thickness). reproducible from plate to plate.
- the non-reproducibility of the surface morphological properties of the useful layers after transfer can impact production yields as the finishing steps do not always succeed in bringing the roughness and uniformity of thickness of all useful layers back to the required level of specification. .
- document EP2933828 proposes to put in contact with the assembly to be fractured, an absorbing element to dissipate the acoustic vibrations emitted during initiation and the self-sustaining propagation of the fracture wave.
- the present invention relates to a method of transferring a useful layer onto a support substrate.
- the method proposes an alternative solution to those of the state of the art, aiming to obtain a low surface roughness and a good uniformity of thickness of the useful layers after transfer and to improve the plate-to-plate reproducibility of the surface morphological properties of the useful layers transferred.
- the invention relates to a method of transferring a useful layer onto a support substrate, comprising the following steps:
- a donor substrate comprising a buried fragile plane, the useful layer being delimited by a front face of the donor substrate and the buried fragile plane;
- a predetermined stress is applied to the brittle plane buried during annealing step d), for a period of time, the predetermined stress being chosen so as to initiate the fracture wave when a given level of embrittlement is reached ,
- the predetermined stress causes the initiation and self-sustaining propagation of the fracture wave along said buried brittle plane, leading to the transfer of the useful layer onto the support substrate.
- the time period is between 1 minute to 5 hours;
- the period of time is a fraction of the duration of the annealing comprised between 1% and 100%;
- the transfer process is applied to the collective treatment of a plurality of bonded structures, and the predetermined stress is applied to the buried fragile plane of each of the bonded structures, so as to initiate the fracture wave when the given level of embrittlement is achieved for each bonded structure;
- step d) the annealing of step d) is carried out in heat treatment equipment of horizontal or vertical configuration, suitable for the collective treatment of a plurality of bonded structures;
- the predetermined stress is locally applied to the buried fragile plane of the bonded structure by means of a bevel positioned opposite the bonding interface and exerting a pressing force against chamfered edges of the donor and support substrates of said bonded structure, to generate a tensile stress in the buried brittle plane;
- the support force is between 0.5 N and 50 N;
- the given level of embrittlement is defined by the surface occupied by microcavities in the buried fragile plane and is chosen between 1% and 90%, preferably between 5% and 40%; -
- the annealing of step d) reaches a maximum temperature between 300 ° C and 600 ° C;
- the predetermined stress is applied from the start of the annealing of step d);
- the donor substrate and the support substrate are made of monocrystalline silicon, and in which the buried fragile plane is formed by ion implantation of light species in the donor substrate, said light species being chosen from hydrogen and helium or a combination hydrogen and helium.
- FIG. 1 shows a method of transferring a thin film according to the state of the art
- FIG. 2 presents a transfer method according to the invention
- FIG. 3 shows an example of collective processing of a plurality of structures, in a transfer method according to the invention.
- the invention relates to a method of transferring a useful layer 3 onto a support substrate 4.
- the useful layer 3 is so named because it is intended to be used for the manufacture of components in the fields of microelectronics or microsystems.
- the useful layer and the support substrate can be of various types depending on the type of component and the intended application. Since silicon is the semiconductor material most used at present, the useful layer and the support substrate can in particular be made of monocrystalline silicon but are of course not limited to this material.
- the transfer method according to the invention first of all comprises a step a) of supplying a donor substrate 1, from which the useful layer 3 will be obtained.
- the donor substrate 1 comprises a buried fragile plane 2 (FIG. 2 - a). ).
- the latter is advantageously formed by ion implantation of light species in the donor substrate 1, at a defined depth.
- the light species are preferably chosen from hydrogen and helium, or a combination of hydrogen and helium, because these species are favorable to the formation of microcavities around the defined depth of implantation, giving rise to the fragile plane.
- the useful layer 3 is delimited by a front face 1a of the donor substrate 1 and the buried fragile plane 2.
- the donor substrate 1 can be formed by at least one material chosen from among silicon, germanium, silicon carbide, compound semiconductors IV-IV, III-V or II-VI, piezoelectric materials (for example, LiNb03 , LiTa03, ...), etc. It may also include one or more surface layers arranged on its front face 1a and / or on its rear face 1b, of all kinds, for example dielectric (s).
- the transfer process also comprises a step b) of providing a support substrate 4 (FIG. 2 - b)).
- the support substrate can for example be formed by at least one material chosen from among silicon, silicon carbide, glass, sapphire, aluminum nitride, or any other material capable of being available in the form of a substrate. It can also include one or more surface layer (s) of all types, for example dielectric (s).
- the transfer method according to the invention is the manufacture of SOI substrates.
- the donor substrate 1 and the support substrate 4 are made of monocrystalline silicon, and one and / or the other of said substrates comprises a surface layer of silicon oxide 6 on its front face.
- the transfer method then comprises a step c) of assembling, according to a bonding interface 7, of the donor substrate 1 at its front face 1a, and of the support substrate 4, to form a bonded structure 5 (FIG. 2 - c )).
- the assembly can be carried out by any known method, in particular by direct bonding by molecular adhesion, or by thermocompression, or even by electrostatic bonding. These techniques, which are well known from the state of the art, will not be described in detail here. It is nevertheless recalled that, previously on assembly, the donor 1 and support 4 substrates will have undergone cleaning and / or surface activation sequences, so as to guarantee the quality of the bonding interface 7 in terms of defectivity and bonding energy .
- a step d) of annealing the bonded structure 5 is then carried out, in order to increase the level of embrittlement of the buried fragile plane 2.
- the temperature range in which the annealing can be carried out for this weakening of the buried plane 2 depends essentially on the type of bonded structure 5 (homo-structure or hetero-structure) and on the nature of the donor substrate 1.
- the annealing of step d) reaches a maximum temperature typically between 200 ° C and 600 ° C, advantageously between 300 and 500 ° C, and even more preferably between 350 ° C and 450 ° C.
- Annealing may include a temperature rise ramp (typically between 200 ° C. and the maximum temperature) and a plateau at the maximum temperature. In general, such an annealing will have a duration of between a few tens of minutes and several hours, depending on the maximum temperature of the annealing.
- the time / temperature pair determines the thermal budget applied to the bonded structure 5 during annealing.
- the level of embrittlement of the buried brittle plane 2 is defined by the surface occupied by the microcavities present in the buried brittle plane 2. In the case of a donor substrate 1 made of silicon, the characterization of this surface occupied by the microcavities can be perform by infrared microscopy.
- the level of embrittlement can increase from a low level ( ⁇ 1%, below the detection threshold of the characterization instruments) to more than 80%, depending on the thermal budget applied to the bonded structure 5 during annealing.
- the thermal embrittlement budget is of course always maintained below the thermal fracture budget, for which the spontaneous initiation of the fracture wave is obtained in the buried fragile plane 2, during annealing.
- the bonded structure 5 is removed after the annealing step, while the buried fragile plane 2 has a certain level. weakening.
- An energy pulse is then applied to the buried fragile plane 2, to cause the initiation of the fracture wave: by propagating, the fracture wave generates the transfer of the useful layer 3 onto the support substrate 4.
- the Applicant has identified problems of reproducibility of the surface morphological properties of the useful layers 3 after transfer, even though the process steps were carried out under identical conditions.
- the transfer method according to the present invention provides that, during annealing step d), a predetermined stress is applied to the buried brittle plane 2, for a period of time (figure 2 - d). ).
- predetermined stress is meant a stress of defined and constant amplitude.
- the predetermined stress can be applied in particular by exerting a mechanical stress checked on the bonded structure 5, as will be described in more detail below.
- the predetermined stress is chosen so as to initiate a fracture wave whose propagation is self-sustaining, when a given level of embrittlement is reached in the buried fragile plane 2.
- a self-sustaining propagation reflects the fact that once initiated, the fracture wave propagates by itself, without application of additional stress and over the entire extent of the buried fragile plane 2, so as to completely detach the useful layer 3 from the donor substrate 1 and to transfer it to the support substrate 4.
- the period of time during which the predetermined stress is applied to the buried brittle plane 2 is typically greater than 1 min. In particular, it is between 1 minute and 5 hours. In other words, the time period is a fraction of the annealing time between 1% and 100%.
- the predetermined stress then causes the initiation and self-sustaining propagation of the fracture wave along the buried brittle plane 2, leading to the transfer of the layer useful 3 on the support substrate 4 (figure 2 - e)).
- the initiation of the fracture wave in the buried fragile plane 2 is not concomitant with the application of the predetermined stress to said plane 2.
- the mechanical stress n ' is not suitable for causing the initiation and propagation of the fracture wave at the time of its application, regardless of the level of weakening of the buried fragile plane 2.
- the predetermined mechanical stress according to the invention does not allow initiation and the propagation of the fracture wave at the time of its application; the initiation of the fracture wave is only caused by the predetermined stress when the buried brittle plane reaches the given level of embrittlement, after a period of time following the application of the constraint.
- the predetermined stress is applied to the buried brittle plane 2 from the start of annealing step d): the period of time (during which the predetermined stress is applied to the buried brittle plane 2) therefore extends from the start of annealing (or potentially before) until the given level of embrittlement is reached, when the fracture wave is initiated.
- the predetermined stress is applied after a determined period of annealing, without interrupting said annealing.
- This variant can promote consolidation of the bonding interface 7 of the bonded structure 5 at the start of annealing, prior to the application of the predetermined stress to the buried fragile plane 2.
- the period of time extends in this case from an intermediate moment during the annealing until the given level of embrittlement is reached, when the fracture wave is initiated.
- the predetermined stress is chosen as a function of the level of embrittlement for which it is desired that the fracture wave propagates.
- a high stress will make it possible to initiate the fracture wave for a low level of embrittlement of the buried fragile plane 2; a lower stress will initiate the fracture wave for a greater level of embrittlement of the buried brittle plane 2.
- the given level of brittleness is defined by the area occupied by microcavities in the buried brittle plane 2 and can be chosen between 1% and 90%, preferably between 5% and 40%.
- Relatively low levels of embrittlement, for example less than 25%, are favorable to a reduced surface roughness after transfer and to a good uniformity of thickness of the useful layers 3 transferred.
- the transfer method is applied to the collective treatment of a plurality of bonded structures 5, in which the predetermined stress is applied to the buried fragile plane 2 of each of the bonded structures 5, so as to initiate the fracture wave when the given level of embrittlement is reached for each bonded structure 5.
- the annealing of step d) can be carried out in a heat treatment equipment of horizontal or vertical configuration, suitable for the collective treatment of a plurality of structures. glued 5.
- the time period during which the predetermined stress is applied to the buried fragile plane 2 and at the end of which the fracture wave will be initiated may be more or less long for each of the bonded structures 5: in fact, the buried fragile planes 2 will not reach not all at the same time the given level of embrittlement for which the predetermined stress applied will cause initiation.
- the duration of the annealing is defined to take these variabilities into account and allow initiation and self-sustaining propagation in the buried fragile plane 2 for all the bonded structures 5.
- Each bonded structure 5 will then have seen its buried fragile plane 2 fracture to the given level of embrittlement, ie at a constant and reproducible level.
- the transfer method according to the invention allows the choice of the level of embrittlement at which the fracture wave will propagate and ensures initiation of said wave at a constant level of embrittlement for all the bonded structures 5: this makes it possible to obtain properties favorable surface morphologies (low roughness, good uniformity and reproducibility from plate to plate) for the useful layers 3 transferred.
- the predetermined stress is applied to the fragile buried plane 2 locally, by exerting a point mechanical stress on the bonded structure 5, by means of a bevel 10.
- the bevel 10 is positioned opposite. -vis the bonding interface 7 and exerts a pressing force against chamfered edges of the donor substrates 1 and support 4 of the bonded structure 5. This has the effect of generating a tensile stress in the buried fragile plane 2.
- the support force has a predetermined and constant amplitude.
- the support force can be between 0.5 N and 50 N.
- the transfer method according to the invention can be used for the manufacture of SOI substrates in which the useful layer 3 is very thin, in particular between a few nanometers and 50 nm.
- donor 1 and support 4 substrates in monocrystalline silicon each in the form of a wafer 300 mm in diameter.
- the donor substrate 1 is covered with a layer of silicon oxide 50 nm thick.
- the buried fragile plane 2 is formed in the donor substrate 1 by co-implantation of hydrogen and helium ions under the following conditions:
- He implantation energy 25 keV, dose 1E16 He / cm2.
- the buried fragile plane 2 is located at a depth of approximately 290 nm, from the surface of the donor substrate 1. It delimits, with the oxide layer 6, a useful layer 3 of approximately 240 nm.
- the assembly of the donor substrate 1 and the support substrate 4 is made by direct bonding by molecular adhesion, to form the bonded structure 5.
- the donor 1 and support 4 substrates Prior to assembly, will have undergone cleaning and / or sequences. known surface activation, so as to guarantee the quality of the bonding interface 7 in terms of defectivity and bonding energy.
- a furnace 20 of horizontal configuration is used to collectively perform the annealing of a plurality of bonded structures such as that described above.
- This type of heat treatment equipment 20 comprises a loading shovel 21 which supports nacelles 22 in which the bonded structures 5 are positioned (FIG. 3).
- the loading shovel 21 is moves between a retracted position, in which the bonded structures 5 are inside the oven 20, and an extended position, in which they are outside the oven 20.
- a system of bevels 10 is positioned on each nacelle 22, below or above the bonded structures 5, so as to exert a constant point pressing force against the chamfered edges of the assembled substrates of each bonded structure.
- the weight of each bonded structure may constitute said support force.
- an additional device 11 can be provided to apply an additional support force, locally at the edge and above the bonded structures 5.
- This mechanical stress exerted by the bevel system 10 (with or without the additional device 11) on the bonded structures 5 generates a predetermined stress, local and in tension at the level of the buried fragile plane 2.
- the mechanical stress can be exerted from the start. annealing or after a fixed period. This determined duration is always much less than the duration necessary to reach the given level of embrittlement for which the predetermined stress will induce the initiation of the fracture wave.
- the SOI substrate is obtained after transfer (transferred assembly 5a) and the remainder 5b of the donor substrate.
- the finishing steps applied to the transferred sets 5a include chemical cleanings and at least one high temperature smoothing heat treatment.
- the SOI substrates comprise a useful layer 3 with a thickness of 50 nm, the non-uniformity of which is less than 2% and having a surface roughness less than 0.3 nm RMS.
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Abstract
Description
Claims
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/436,532 US12142517B2 (en) | 2019-03-15 | 2020-02-26 | Method for transferring a useful layer from a donor substrate onto a support substrate by applying a predetermined stress |
| EP20713728.2A EP3939076A1 (fr) | 2019-03-15 | 2020-02-26 | Procede de transfert d'une couche utile sur un substrat support |
| KR1020217032705A KR20210138051A (ko) | 2019-03-15 | 2020-02-26 | 유용 층을 캐리어 기판에 전사하는 공정 |
| SG11202109798U SG11202109798UA (en) | 2019-03-15 | 2020-02-26 | Process for transferring a useful layer to a carrier substrate |
| JP2021555272A JP7605748B2 (ja) | 2019-03-15 | 2020-02-26 | キャリア基板へ有用層を移転するためのプロセス |
| CN202080016649.6A CN113574654A (zh) | 2019-03-15 | 2020-02-26 | 将有用层转移到载体衬底的方法 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1902668A FR3093858B1 (fr) | 2019-03-15 | 2019-03-15 | Procédé de transfert d’une couche utile sur un substrat support |
| FR1902668 | 2019-03-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2020188167A1 true WO2020188167A1 (fr) | 2020-09-24 |
Family
ID=67384006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/FR2020/050367 Ceased WO2020188167A1 (fr) | 2019-03-15 | 2020-02-26 | Procede de transfert d'une couche utile sur un substrat support |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US12142517B2 (fr) |
| EP (1) | EP3939076A1 (fr) |
| JP (1) | JP7605748B2 (fr) |
| KR (1) | KR20210138051A (fr) |
| CN (1) | CN113574654A (fr) |
| FR (1) | FR3093858B1 (fr) |
| SG (1) | SG11202109798UA (fr) |
| TW (1) | TWI811528B (fr) |
| WO (1) | WO2020188167A1 (fr) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005043615A1 (fr) | 2003-10-28 | 2005-05-12 | S.O.I.Tec Silicon On Insulator Technologies | Procede de transfert autoentretenu d'une couche fine par impulsion apres implantation ou co-implantation |
| EP2802001A1 (fr) * | 2012-01-06 | 2014-11-12 | Shin-Etsu Handotai Co., Ltd. | Procédé de fabrication de tranche de silicium sur isolant (soi) fixée |
| EP2933828A1 (fr) | 2014-04-16 | 2015-10-21 | Soitec | Procédé de transfert d'une couche utile |
| US9914233B2 (en) * | 2012-09-07 | 2018-03-13 | Soitec | Device for separating two substrates |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223683A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 複合部材及びその分離方法、貼り合わせ基板及びその分離方法、移設層の移設方法、並びにsoi基板の製造方法 |
| EP1777735A3 (fr) * | 2005-10-18 | 2009-08-19 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de recyclage d'une plaquette donneuse épitaxiée |
| FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
| JP5703853B2 (ja) | 2011-03-04 | 2015-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| US8845859B2 (en) * | 2011-03-15 | 2014-09-30 | Sunedison Semiconductor Limited (Uen201334164H) | Systems and methods for cleaving a bonded wafer pair |
| KR101316053B1 (ko) | 2011-04-26 | 2013-10-11 | 국립대학법인 울산과학기술대학교 산학협력단 | 리튬 이차 전지용 양극 활물질, 이의 제조 방법 및 이를 포함하는 리튬 이차 전지 |
| FR2982071B1 (fr) | 2011-10-27 | 2014-05-16 | Commissariat Energie Atomique | Procede de lissage d'une surface par traitement thermique |
| WO2013066758A1 (fr) * | 2011-10-31 | 2013-05-10 | Memc Electronic Materials, Inc. | Appareil de serrage permettant de cliver une structure de plaquette soudée et procédés de clivage |
| JP6396852B2 (ja) * | 2015-06-02 | 2018-09-26 | 信越化学工業株式会社 | 酸化物単結晶薄膜を備えた複合ウェーハの製造方法 |
| WO2017142849A1 (fr) * | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | Structure de semi-conducteur sur isolant comprenant une couche enfouie à haute résistivité |
-
2019
- 2019-03-15 FR FR1902668A patent/FR3093858B1/fr active Active
-
2020
- 2020-02-24 TW TW109105909A patent/TWI811528B/zh active
- 2020-02-26 KR KR1020217032705A patent/KR20210138051A/ko not_active Ceased
- 2020-02-26 US US17/436,532 patent/US12142517B2/en active Active
- 2020-02-26 SG SG11202109798U patent/SG11202109798UA/en unknown
- 2020-02-26 EP EP20713728.2A patent/EP3939076A1/fr active Pending
- 2020-02-26 CN CN202080016649.6A patent/CN113574654A/zh active Pending
- 2020-02-26 JP JP2021555272A patent/JP7605748B2/ja active Active
- 2020-02-26 WO PCT/FR2020/050367 patent/WO2020188167A1/fr not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005043615A1 (fr) | 2003-10-28 | 2005-05-12 | S.O.I.Tec Silicon On Insulator Technologies | Procede de transfert autoentretenu d'une couche fine par impulsion apres implantation ou co-implantation |
| WO2005043616A1 (fr) | 2003-10-28 | 2005-05-12 | S.O.I. Tec Silicon On Insulator Technologies | Procede de transfert catastrophique d'une couche fine apres co-implantation |
| EP2802001A1 (fr) * | 2012-01-06 | 2014-11-12 | Shin-Etsu Handotai Co., Ltd. | Procédé de fabrication de tranche de silicium sur isolant (soi) fixée |
| US9914233B2 (en) * | 2012-09-07 | 2018-03-13 | Soitec | Device for separating two substrates |
| EP2933828A1 (fr) | 2014-04-16 | 2015-10-21 | Soitec | Procédé de transfert d'une couche utile |
Non-Patent Citations (1)
| Title |
|---|
| MASSY D ET AL: "Fracture dynamics in implanted silicon", APPLIED PHYSICS LETTERS, A I P PUBLISHING LLC, US, vol. 107, no. 9, 31 August 2015 (2015-08-31), XP012200151, ISSN: 0003-6951, [retrieved on 19010101], DOI: 10.1063/1.4930016 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2022526250A (ja) | 2022-05-24 |
| TWI811528B (zh) | 2023-08-11 |
| KR20210138051A (ko) | 2021-11-18 |
| TW202036782A (zh) | 2020-10-01 |
| JP7605748B2 (ja) | 2024-12-24 |
| CN113574654A (zh) | 2021-10-29 |
| EP3939076A1 (fr) | 2022-01-19 |
| FR3093858B1 (fr) | 2021-03-05 |
| US20220172983A1 (en) | 2022-06-02 |
| FR3093858A1 (fr) | 2020-09-18 |
| SG11202109798UA (en) | 2021-10-28 |
| US12142517B2 (en) | 2024-11-12 |
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