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WO2020173293A1 - Composant d'attaque de grille, procédé d'attaque de grille, circuit d'attaque de grille et dispositif d'affichage - Google Patents

Composant d'attaque de grille, procédé d'attaque de grille, circuit d'attaque de grille et dispositif d'affichage Download PDF

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Publication number
WO2020173293A1
WO2020173293A1 PCT/CN2020/074587 CN2020074587W WO2020173293A1 WO 2020173293 A1 WO2020173293 A1 WO 2020173293A1 CN 2020074587 W CN2020074587 W CN 2020074587W WO 2020173293 A1 WO2020173293 A1 WO 2020173293A1
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WO
WIPO (PCT)
Prior art keywords
pull
node
control
down node
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/074587
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English (en)
Chinese (zh)
Inventor
许卓
白雅杰
王孝林
付鹏程
张手强
袁剑峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chongqing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2020173293A1 publication Critical patent/WO2020173293A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a gate driving component, a gate driving method, a gate driving circuit, and a display device.
  • Background technique
  • a pull-up node control transistor is used to charge the pull-up node, and the pull-up node controls the gate and source of the transistor Are connected to the input terminal, the drain of the pull-up node control transistor is connected to the pull-up node, and the pull-up node control transistor is equivalent to a diode o
  • the pull-down node control circuit controls the potential of the pull-down node under the control of the DC control signal and the potential of the pull-up node, and the potential of the pull-down node is controlled by DC.
  • the related art gate drive components use gate drive signals for cascading, so that the drive capability of the gate drive output terminal is weak.
  • the present disclosure provides a gate drive assembly, including a pull-up node control circuit, a pull-down node control circuit, a carry signal output terminal, and a carry signal output circuit;
  • the pull-up node control circuit is configured to control the connection between the pull-up node and the input terminal under the control of the first clock signal input from the first clock signal input terminal;
  • the pull-down node control circuit is used to control the potential of the pull-down node under the control of the AC control signal input from the AC control signal terminal and the potential of the pull-up node;
  • the carry signal generating circuit is used to control the carry signal output terminal to output a carry signal under the control of the potential of the pull-up node and the potential of the pull-down node;
  • the input terminal is connected to the adjacent previous carry signal output terminal.
  • the pull-up node control circuit includes a pull-up node control transistor
  • the control electrode of the pull-up node control transistor is connected to the first clock signal input terminal, the first electrode of the pull-up node control transistor is connected to the pull-up node, and the second electrode of the pull-up node controls the transistor.
  • the pole is connected to the input terminal.
  • the AC control signal terminal is a second clock signal input terminal.
  • the pull-down node control circuit includes a first pull-down node control transistor and a second pull-down node control transistor;
  • the control electrode of the first pull-down node control transistor and the first electrode of the first pull-down node control transistor are both connected to the second clock signal input terminal, and the second pull-down node control transistor Pole is connected to the pull-down node;
  • the first pole of the pull-down node control transistor is connected to the pull-down node, and the second pole of the second pull-down node control transistor is connected to the first level terminal.
  • the AC control signal terminal includes a first control voltage terminal and a second control voltage terminal;
  • the pull-down node control circuit includes a first pull-down control circuit and a second pull-down control circuit;
  • the pull-down node includes a first Drop-down node and second drop-down node;
  • the first pull-down control circuit is configured to control the potential of the first pull-down node under the control of the first control voltage input from the first control voltage terminal and the potential of the pull-up node;
  • the second pull-down control circuit is configured to control the potential of the second pull-down node under the control of the second control voltage input from the second control voltage terminal and the potential of the pull-up node.
  • the first pull-down control circuit is respectively connected to a first control voltage terminal, the pull-up node, and the first pull-down node, and is used for the first control voltage and the first control voltage input at the first control voltage terminal. Controlling the potential of the first pull-down node under the control of the potential of the pull-up node;
  • the second pull-down control circuit is respectively connected to a second control voltage terminal, the pull-up node, and the second pull-down node, and is used for the second control voltage input at the second control voltage terminal and the pull-up node Controlling the potential of the second pull-down node under the control of the potential;
  • the carry signal output circuit is respectively connected to the first pull-down node, the second pull-down node, the pull-up node, and the carry signal output terminal, and is used for setting the potential of the first pull-down node and the Under the control of the potential of the second pull-down node and the potential of the pull-up node, the carry signal output terminal is controlled to output a carry signal.
  • the first pull-down node control circuit includes a first pull-down node control transistor and a second pull-down node control transistor
  • the second pull-down node control circuit includes a third pull-down node control transistor and a fourth pull-down node control transistor.
  • the control electrode of the first pull-down node control transistor and the first electrode of the first pull-down node control transistor are both connected to the first control voltage terminal, and the first pull-down node controls the second electrode of the transistor Connected to the first drop-down node;
  • the first pole of the pull-down node control transistor is connected to the first pull-down node, and the second pole of the second pull-down node control transistor is connected to the second level terminal;
  • control electrode of the third pull-down node control transistor and the first electrode of the third pull-down node control transistor are both connected to the second control voltage terminal, and the second electrode of the third pull-down node control transistor is connected to the The second drop-down node connection;
  • the control electrode of the fourth pull-down node control transistor is connected to the pull-up node
  • the first electrode of the fourth pull-down node control transistor is connected to the second pull-down node
  • the second pull-down node controls the first electrode of the transistor.
  • the two poles are connected to the second level terminal.
  • the gate drive assembly further includes a pull-up node denoising circuit, a blank area reset circuit, and a pull-down node denoising circuit, where
  • the pull-up node denoising circuit is used to denoise the pull-up node under the control of the reset signal input from the reset terminal;
  • the blank area reset circuit is used to reset the potential of the pull-up node under the control of the blank area reset signal input from the blank area reset terminal;
  • the pull-down node denoising circuit is used to denoise the pull-down node under the control of the input signal.
  • the pull-up node denoising circuit is respectively connected to the reset terminal and the pull-up node, and is configured to denoise the pull-up node under the control of a reset signal input from the reset terminal.
  • the blank area reset circuit is respectively connected to the blank area reset terminal and the pull-up node, and is used to reset the potential of the pull-up node under the control of the blank area reset signal input from the blank area reset terminal ;
  • the pull-down node denoising circuit is respectively connected to the input terminal and the pull-down node, and is configured to denoise the pull-down node under the control of an input signal.
  • the gate drive assembly further includes a gate drive signal output terminal, a tank circuit and a gate drive signal output circuit;
  • the tank circuit is connected to the pull-up node and is used to maintain the potential of the pull-up node; the gate drive signal output circuit is used to set the potential of the pull-up node, the potential of the pull-down node, and Under the control of the reset signal input from the reset terminal, the gate drive signal output terminal is controlled to output a gate drive signal.
  • the gate drive assembly further includes: a gate drive signal output terminal, an energy storage circuit, and a gate drive signal output circuit;
  • the pull-up node control circuit includes a pull-up node control transistor
  • the gate of the pull-up node control transistor is connected to the first clock signal, the drain of the pull-up node control transistor is connected to the input terminal, and the source of the pull-up node controls the transistor and the pull-up node connection.
  • the pull-down node control circuit includes a first pull-down node control transistor and a second pull-down node control transistor;
  • the gate of the first pull-down node control transistor and the drain of the first pull-down node control transistor are both connected to a second clock signal, and the first pull-down node controls the source of the transistor and the pull-down node Connect
  • the gate of the second pull-down node control transistor is connected to the pull-up node, the drain of the second pull-down node control transistor is connected to the pull-down node, and the second pull-down node controls the source of the transistor and the second pull-down node.
  • a low-level terminal is connected; the first low-level terminal is used to input a first low level; the energy storage circuit includes a storage capacitor;
  • a first end of the storage capacitor is connected to the pull-up node, and a second end of the storage capacitor is connected to the gate drive signal output end;
  • the gate drive signal output circuit includes a first gate drive signal output transistor, a second gate drive signal output transistor, and a third gate drive signal output transistor;
  • the gate of the first gate drive signal output transistor is connected to the pull-up node, the drain of the first gate drive signal output transistor is connected to a second clock signal, and the first gate drive signal output The source and connection of the transistor;
  • the gate of the second gate drive signal output transistor is connected to the pull-down node, the drain of the second gate drive signal output transistor is connected to the gate drive signal output terminal, and the second gate drive signal The source of the output transistor is connected to the first low level;
  • the gate of the third gate drive signal output transistor is connected to the reset terminal, the drain of the third gate drive signal output transistor is connected to the gate drive signal output terminal, and the second gate drive signal The source of the output transistor is connected to the first low level.
  • the present disclosure also provides a gate driving method, which is applied to the above-mentioned gate driving circuit, and the gate driving method includes:
  • the pull-up node control circuit controls the charging of the pull-up node through the input signal under the control of the first clock signal to control the potential of the pull-up node as an effective voltage;
  • the pull-down node control circuit is Under the control of the AC control signal input from the AC control signal terminal and the potential of the pull-up node, the potential of the pull-down node is controlled to be an invalid voltage;
  • the pull-up node control circuit controls the pull-up node to denoise under the control of the first clock signal
  • the pull-down node control circuit controls the potential of the pull-down node to be an effective voltage under the control of the AC control signal and the potential of the pull-up node;
  • the carry signal generating circuit is used to control the carry signal output terminal to output a carry signal under the control of the potential of the pull-up node and the potential of the pull-down node.
  • the gate driving method further includes:
  • bootstrap pulls up the potential of the pull-up node, so that the potential of PU is maintained at an effective voltage.
  • the present disclosure also provides a gate drive circuit, which includes multiple stages of gate drive components as described above.
  • the carry signal output end of each stage of gate drive component is connected to the adjacent one.
  • the input terminal of the gate drive component is connected;
  • the carry signal output terminal of each stage of gate drive components is connected to the reset terminal of the adjacent next stage of gate drive components.
  • the present disclosure also provides a display device including the gate driving circuit described above. Description of the drawings
  • FIG. 1 is a structural diagram of a gate driving component of some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of a gate driving component according to some embodiments of the present disclosure
  • FIG. 3 is a structural diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 5 is a structural diagram of a gate driving component of some embodiments of the present disclosure.
  • Fig. 6 is a structural diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 9 is a circuit diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 10 is a working timing diagram of the gate driving component of some embodiments of the present disclosure.
  • FIG. 11 is a circuit diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 12 is a working timing diagram of the gate driving component of some embodiments of the present disclosure.
  • FIG. 13 is a circuit diagram of a gate driving component of some embodiments of the present disclosure.
  • FIG. 14 is a working timing diagram of the gate driving component of some embodiments of the present disclosure.
  • FIG. 15 is a circuit diagram of a gate driving component of some embodiments of the present disclosure. detailed description
  • a pull-up node control transistor is used to charge the pull-up node, and the gate and source of the pull-up node control transistor are both connected to the input terminal, and the pull-up node controls the drain of the transistor and The pull-up node is connected.
  • the pull-up node control transistor is equivalent to a diode.
  • the pull-down node is used to denoise the pull-up node.
  • the pull-up node's ability to pull the pull-down node When the pull-up node's ability to pull the pull-down node is weakened, the potential of the pull-down node will be further pulled down by the pull-down node.
  • the attenuated input signal will be continuously amplified and attenuated when it is transmitted to the next-stage gate drive component, and eventually the G0A cannot be started.
  • the pull-down node control circuit controls the potential of the pull-down node under the control of the DC control signal and the potential of the pull-up node.
  • the potential of the pull-down node is controlled by DC, and there is a risk of DC bias.
  • the threshold voltage of the transistor whose gate is connected to the DC control signal in the pull-down node control circuit has a greater drift.
  • the related art gate drive components use gate drive signals for cascading, so that the drive capability of the gate drive output terminal is weak.
  • the main purpose of the present disclosure is to provide a gate driving component, a gate driving method, a gate driving circuit, and a display device, so as to solve the insufficiency of the related technology of the gate driving component in charging and releasing noise on the pull-up node, and pull down the node
  • the threshold voltage of the transistor whose gate is connected to the DC control signal in the control circuit has a large drift, and the driving capability of the gate driving signal output terminal of the related-art gate driving component is weak.
  • the transistors used in all embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics.
  • one of the poles is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the gate drive assembly of some embodiments of the present disclosure includes a pull-up node control circuit 10, a pull-down node control circuit 11, a carry signal output terminal Out_C, and a carry signal output circuit 12;
  • the pull-up node control circuit 10 are respectively connected to the first clock signal input terminal, the pull-up node PU and the input terminal I nput, and are used to control the pull-up node PU and the input terminal under the control of the first clock signal GLK input from the first clock signal input terminal. Connect between terminals I nput;
  • the pull-down node control circuit 11 is respectively connected with the pull-up node PU, the pull-down node PD and the AC control
  • the signal terminal AGS is connected, and is used to control the potential of the pull-down node PD under the control of the AC control signal input by the AC control signal terminal AGS and the potential of the pull-up node PU;
  • the carry signal generating circuit 12 is respectively connected to the pull-up node PU, the pull-down node PD, and the carry signal output terminal Out_C, and is used for controlling the potential of the pull-up node PU and the potential of the pull-down node PD Next, control the carry signal output terminal 0ut_C to output a carry signal;
  • the input terminal I nput is connected to the adjacent previous carry signal output terminal.
  • the AC control signal terminal may be a clock signal terminal, or the AC control signal terminal may also include a first control voltage terminal and a second control voltage terminal, and the first control voltage terminal input A control voltage and the second control voltage input from the second control voltage terminal are AC signals; but it is not limited to this.
  • the display period when the gate driving component shown in FIG. 1 is in operation, the display period includes an input phase, an output phase, a reset phase, and an output cut-off hold phase that are sequentially arranged;
  • the pull-up node control circuit 10 controls the connection between PU and I nput, and the effective voltage input by I nput charges the pull-up node PU to control the potential of PU as Effective voltage;
  • the pull-down node control circuit 11 controls the potential of the pull-down node PD to be an invalid voltage under the control of the AC control signal input from the AC control signal terminal ACS and the potential of the pull-up node PU;
  • the potential of PU is pulled up by bootstrap, so that the potential of PU is maintained as an effective voltage; in the reset phase and the output cut-off hold phase, under the control of the first clock signal CLKB, the pull-up node control circuit 1 0 Control the PU to connect to I nput, and I nput inputs an invalid voltage to control the potential of the PU as an invalid voltage;
  • the pull-down node control circuit 11 controls the potential of the pull-down node PD to be an effective voltage under the control of the AC control signal and the potential of the pull-up node PU; in the display period
  • the carry signal generating circuit 12 is used to control the carry signal output terminal Out_C to output a carry signal under the control of the potential of the pull-up node PU and the potential of the pull-down node PD.
  • the effective voltage is a voltage that can control the conduction of a transistor whose gate is connected to the effective voltage.
  • the effective voltage may be a high voltage; when the transistor is In the case of a p-type transistor, the effective voltage can be a low voltage; but not Limit
  • the invalid voltage is a voltage capable of controlling the cut-off of a transistor whose gate is connected to the invalid voltage.
  • the invalid voltage may be a low voltage; when the transistor is a P-type transistor, The invalid voltage can be a high voltage; but it is not limited to this.
  • the pull-up node control circuit 10 in the gate drive assembly of some embodiments of the present disclosure charges the pull-up node PU through the input signal under the control of CLKB in the input phase, and passes the first
  • the clock signal CLKB is used to denoise the pull-up node PU, instead of denoising the pull-up node PU through the pull-down node, so that the pull-up node PU is charged without loss in the input stage, and it has strong denoising ability and has Strong input signal transmission ability, so that GOA (Gate On Ar ray, gate drive circuit provided on the array substrate) still has an ideal output after the reliability evaluation is completed when the TFT (thin film transistor) is degraded; and,
  • the pull-down node control circuit 11 controls the pull-down node PD under the control of the AC control signal and the potential of the pull-up node PU The potential of the pull-down node PD is controlled by an
  • Some embodiments of the present disclosure adopt the carry signal output circuit 12. Control the output of the carry signal through the carry signal output terminal 0ut_C for cascading to improve the driving capability of the gate drive output terminal and increase the VGH Marg in (high voltage variable range) for low temperature startup.
  • the gate driving component of some embodiments of the present disclosure adopts a pull-down node control circuit 11 to control the potential of the pull-down node PD, and the pull-down node PD is used to control the resetting of the gate drive signal and the carry signal.
  • Some embodiments of the present disclosure are applicable to Oxide (oxide) TFT panels with poor TFT stability, or LTPS (Low Temperature Polysilicon) TFT panels with poor uniformity. Suitable for aSi (amorphous silicon) TFT panels, but not limited to this.
  • Some embodiments of the present disclosure propose an improved gate drive component based on the G0A model of the related technology, which realizes a more reliable G0A signal output by changing the charging method and denoising method of the pull-up node PU.
  • the pull-down node no longer pulls down the potential of the pull-up node PU, and the denoising use of the pull-up node PU is the same as the second clock signal CLK (CLK is used for the gate
  • CLK is used for the gate
  • the second clock signal output by the driving signal is implemented by inverted CLKB, which can not only improve the charging capability of the pull-up node PU, but also ensure a strong denoising capability of the pull-up node PU.
  • the pull-up node control circuit may include a pull-up node control transistor; the control electrode of the pull-up node control transistor is connected to the first clock signal input terminal, and the pull-up node control transistor has a first electrode. Connected to the pull-up node, and the second pole of the pull-up node control transistor is connected to the input terminal.
  • the pull-up node control circuit 10 may include a pull-up node control transistor M1;
  • M1 is an n-type thin film transistor, but it is not limited to this.
  • nput can be connected to the gate drive signal output terminal of the adjacent upper-level gate drive component, and optionally, it can also be connected to the carry signal output end of the adjacent upper-level gate drive component .
  • the AC control signal terminal is a second clock signal input terminal;
  • the pull-down node control circuit is connected to the pull-down node, the second clock signal input terminal, and the pull-up node, respectively, and is used to Under the control of the second clock signal input from the second clock signal input terminal and the potential of the pull-up node, the potential of the pull-down node is controlled.
  • the pull-down node control circuit controls the pull-down node through the second clock signal, and the potential of the pull-down node is controlled by an AC signal, which reduces the risk of DC bias and improves the threshold voltage of the pull-down node control transistor drift.
  • the AC control signal terminal is a second clock signal input terminal for inputting a second clock signal CLK;
  • the pull-down node control circuit 11 is configured to control the potential of the pull-down node PD under the control of the second clock signal CLK and the potential of the pull-up node PU.
  • the pull-down node control circuit 11 controls the potential of the PD under the control of the potential of the PU and the CLK.
  • the pull-down node control circuit may include a first pull-down node control transistor and a second pull-down node control transistor;
  • the control electrode of the first pull-down node control transistor and the first pull-down node control transistor The first poles of are all connected to the second clock signal input terminal, and the second pole of the first pull-down node control transistor is connected to the pull-down node;
  • the control electrode of the second pull-down node control transistor is connected to the pull-up node
  • the first electrode of the second pull-down node control transistor is connected to the pull-down node
  • the second pull-down node controls the second electrode of the transistor Connect with the first level terminal.
  • the pull-down node control circuit 11 may include a first pull-down node control transistor M5 and a second pull-down node control transistor. M6;
  • the gate of the first pull-down node control transistor M5 and the drain of the first pull-down node control transistor M5 are both connected to the second clock signal CLK, and the source of the first pull-down node control transistor M5 is connected to The drop-down node PD is connected;
  • the gate of the second pull-down node control transistor M6 is connected to the pull-up node PU, the drain of the second pull-down node control transistor M6 is connected to the pull-down node PD, and the second pull-down node control transistor M6
  • the source is connected to the first low level terminal; the first low level terminal is used to input the first low level VGL o
  • the first level terminal is the first low level terminal, but it is not limited to this.
  • both M5 and M6 are n-type thin film transistors, but not limited to this.
  • the AC control signal terminal may include a first control voltage terminal and a second control voltage terminal;
  • the pull-down node control circuit may include a first pull-down control circuit and a second pull-down control circuit;
  • the drop-down node includes a first drop-down node and a second drop-down node;
  • the first pull-down control circuit is configured to control the potential of the first pull-down node under the control of the first control voltage input from the first control voltage terminal and the potential of the pull-up node;
  • the second pull-down control circuit is configured to control the potential of the second pull-down node under the control of the second control voltage input from the second control voltage terminal and the potential of the pull-up node.
  • the first pull-down control circuit included in the pull-down node control circuit controls the potential of the first pull-down node under the control of the first control voltage and the potential of the pull-up node, and the pull-down node
  • the control circuit includes a second pull-down control circuit at the second control voltage and the pull-up node Under the control of the potential of, the potential of the second pull-down node is controlled.
  • the display time may include multiple voltage supply time periods, and each voltage supply time period includes a first voltage supply stage and a second voltage supply stage that are sequentially set;
  • the first control voltage is an effective voltage
  • the second control voltage is an invalid voltage
  • the first control voltage is an invalid voltage
  • the second control voltage is an effective voltage
  • the first control voltage and the second control voltage are AC voltages, and the interval between the first control voltage and the second control voltage is an effective voltage, so that the gate of the first pull-down control circuit
  • the transistor whose pole is connected to the first control voltage and the transistor whose gate is connected to the second control voltage included in the second pull-down control circuit are opened at intervals, and the potential of the pull-down node is controlled by AC, reducing the risk of DC bias, thereby improving the performance of the above transistor Threshold voltage drift.
  • the first pull-down node control circuit may include a first pull-down node control transistor and a second pull-down node control transistor
  • the second pull-down node control circuit may include a third pull-down node control transistor and a fourth pull-down node Control transistor
  • the control electrode of the first pull-down node control transistor and the first electrode of the first pull-down node control transistor are both connected to the first control voltage terminal, and the first pull-down node controls the second electrode of the transistor Connected to the first drop-down node;
  • the control electrode of the second pull-down node control transistor is connected to the pull-up node, the first electrode of the second pull-down node control transistor is connected to the first pull-down node, and the second pull-down node controls the transistor
  • the second pole is connected to the second level terminal
  • control electrode of the third pull-down node control transistor and the first electrode of the third pull-down node control transistor are both connected to the second control voltage terminal, and the second electrode of the third pull-down node control transistor is connected to the The second drop-down node connection;
  • the control electrode of the fourth pull-down node control transistor is connected to the pull-up node
  • the first electrode of the fourth pull-down node control transistor is connected to the second pull-down node
  • the second pull-down node controls the first electrode of the transistor.
  • the two poles are connected to the second level terminal.
  • the pull-down node control circuit includes a first pull-down control circuit 1 1 1 and a second pull-down control circuit 1 1 2; Narrate The pull node includes a first pull-down node PD1 and a second pull-down node PD2;
  • the first pull-down control circuit 11 1 is connected to a first control voltage terminal, the pull-up node PU, and the first pull-down node PD1, respectively, and is used for the first control voltage input at the first control voltage terminal Controlling the potential of the first pull-down node PD1 under the control of VDDo and the potential of the pull-up node PU;
  • the second pull-down control circuit 112 is respectively connected to a second control voltage terminal, the pull-up node PU and the second pull-down node PD2, and is used for the second control voltage VDDe input at the second control voltage terminal and the Controlling the potential of the second pull-down node PD2 under the control of the potential of the pull-up node PU;
  • the carry signal output circuit 11 is connected to the first pull-down node PD1, the second pull-down node PD2, the pull-up node PU, and the carry signal output terminal Out_C, respectively, and is used for setting the potential of PD1 and the potential of PD2. Under the control of the potential and the potential of the PU, 0ut_C is controlled to output a carry signal.
  • the first pull-down node control circuit 11 1 includes a first pull-down node control transistor M5A and a second pull-down node control transistor M5A.
  • Transistor M6A the second pull-down node control circuit 112 includes a third pull-down node control transistor M5B and a fourth pull-down node control transistor M6B;
  • the gate of the first pull-down node control transistor M5A and the drain of the first pull-down node control transistor M5A are both connected to the first control voltage terminal, and the first pull-down node controls the source of the transistor M5A Pole is connected to the first pull-down node PD1;
  • the gate of the second pull-down node control transistor M6A is connected to the pull-up node PU, the drain of the second pull-down node control transistor M6A is connected to the first pull-down node PD1, and the second pull-down node
  • the source of the control transistor M6A is connected to the second low level terminal; the second low level terminal is used to input the second low level LVGL;
  • the gate of the third pull-down node control transistor M5B and the drain of the third pull-down node control transistor M5B are both connected to the second control voltage terminal, and the source of the third pull-down node control transistor M5B is connected to the The second pull-down node PD2 is connected;
  • the gate of the fourth pull-down node control transistor M6B is connected to the pull-up node PU, the drain of the fourth pull-down node control transistor M6B is connected to the second pull-down node PD2, and the second pull-down node controls The source of the transistor M6B is connected to the second low level terminal.
  • the second level terminal is the second low level terminal, but it is not limited to this.
  • M5A, M6A, M5B, and M6B are all n-type thin film transistors, but not limited to this.
  • the first control voltage VDDo is a high voltage
  • the second control voltage VDDe is a low voltage
  • M5A is turned on
  • M5B is turned off
  • PD1 is connected to VDDo;
  • the potential of PD2 is a low voltage
  • the first control voltage VDDo is a low voltage
  • the second control voltage VDDe is a high voltage
  • M5A is turned off
  • M5B is turned on
  • PD2 is connected to VDDe
  • the potential of PD1 is a low voltage.
  • the gate driving component of some embodiments of the present disclosure may further include a pull-up node denoising circuit, a blank area reset circuit, and a pull-down node denoising circuit, where
  • the pull-up node denoising circuit is used to denoise the pull-up node under the control of the reset signal input from the reset terminal;
  • the blank area reset circuit is used to reset the potential of the pull-up node under the control of the blank area reset signal input from the blank area reset terminal;
  • the pull-down node denoising circuit is used to denoise the pull-down node under the control of the input signal.
  • the gate driving component of some embodiments of the present disclosure further includes a pull-up node denoising circuit 13, a blank area reset circuit 14 and a pull-down Node denoising circuit 15, where
  • the pull-up node denoising circuit 13 is respectively connected to the reset terminal Reset and the pull-up node PU, and is configured to denoise the pull-up node PU under the control of the reset signal input from the reset terminal Reset;
  • the blank area The reset circuit 14 is respectively connected to the blank area reset terminal T_RST and the pull-up node PU, and is used to reset the potential of the pull-up node PU under the control of the blank area reset signal input from the blank area reset terminal T_RST;
  • the pull-down node denoising circuit 15 is respectively connected to the input terminal I nput and the pull-down node PD, and is used to denoise the pull-down node PD under the control of the input signal.
  • the gate drive assembly of some embodiments of the present disclosure may include a pull-up node to The noise circuit 13, the blank area reset circuit 14, and the pull-down node denoising circuit 15.
  • the reset signal is an effective voltage
  • the pull-up node denoising circuit 13 denoises the pull-up node PU; displayed on two frames
  • the blank area reset signal T_RST is an effective voltage
  • the blank area reset circuit 14 resets the potential of the pull-up node PU to prevent AD (Abnormal Display) from occurring and not continuing to the next Frame picture display time
  • AD Abnormal Display
  • the input signal is an effective voltage
  • the pull-down node denoising circuit 15 denoises the pull-down node PD.
  • the gate driving component of some embodiments of the present disclosure may further include a gate driving signal output terminal, a tank circuit, and a gate driving signal output circuit;
  • the tank circuit is connected to the pull-up node and is used to maintain the potential of the pull-up node; the gate drive signal output circuit is used to set the potential of the pull-up node, the potential of the pull-down node, and Under the control of the reset signal input from the reset terminal, the gate drive signal output terminal is controlled to output a gate drive signal.
  • the gate driving component of some embodiments of the present disclosure further includes a gate driving signal output terminal Gout, a storage circuit 16 and a gate Drive signal output circuit 17;
  • the tank circuit 16 is connected to the pull-up node PU, and is used to maintain the potential of the pull-up node PU;
  • the gate drive signal output circuit 17 is respectively connected to the pull-up node PU, the pull-down node PD, the reset terminal Reset and the gate drive signal output terminal Gout, and is used to pull up the potential of the node PU. Under the control of the potential of the pull-down node PD and the reset signal input from the reset terminal Reset, the gate drive signal output terminal Gout is controlled to output a gate drive signal.
  • the gate drive component of some embodiments of the present disclosure includes a pull-up node control circuit 10, a pull-down node control circuit 11, a gate drive signal output terminal Gout, a tank circuit 16, and a gate drive signal output circuit 17. ;
  • the pull-up node control circuit 10 includes a pull-up node control transistor M1;
  • the gate of M1 is connected to CLKB, the drain of M1 is connected to Input, and the source of M1 is connected to PU.
  • the pull-down node control circuit 11 includes a first pull-down node control transistor M5 and a second pull-down node control transistor M6; The gate of the first pull-down node control transistor M5 and the drain of the first pull-down node control transistor M5 are both connected to the second clock signal CLK, and the source of the first pull-down node control transistor M5 is connected to The drop-down node PD is connected;
  • the gate of the second pull-down node control transistor M6 is connected to the pull-up node PU, the drain of the second pull-down node control transistor M6 is connected to the pull-down node PD, and the second pull-down node control transistor M6
  • the source is connected to the first low-level terminal; the first low-level terminal is used to input the first low-level VGL;
  • the storage circuit 16 includes a storage capacitor Cst;
  • a first end of the storage capacitor Cst is connected to the pull-up node PU, and a second end of the storage capacitor Cst is connected to the gate drive signal output terminal Gout;
  • the gate drive signal output circuit 17 includes a first gate drive signal output transistor M3, a second gate drive signal output transistor M13, and a third gate drive signal output transistor M4;
  • the gate of M3 is connected to PU, the drain of M3 is connected to CLK, and the source of M3 is connected to Gout;
  • the gate of M13 is connected to PD, the drain of M13 is connected to Gout, and the source of M13 is connected to VGL;
  • the gate of M4 is connected to Reset, the drain of M4 is connected to Gout, and the source of M13 is connected to VGL.
  • the gate drive assembly shown in FIG. 9 of the present disclosure may further include a carry signal output circuit (not shown in FIG. 9) and a carry signal output terminal (not shown in FIG. 9); the carry signal output circuit is used for Under the potential of the pull-up node PU and the potential of the pull-down node PD, the carry signal output terminal is controlled to output a carry signal, which can be cascaded through the carry signal output terminal.
  • all transistors are n-type thin film transistors, but not limited to this.
  • the gate drive assembly shown in FIG. 9 of the present disclosure can improve the charging ability of the pull-up node PU and ensure a strong denoising ability for the pull-up node PU, and reduce the number of transistors used. Reduce the G0A frame, and PU and PD are both AC control, and the risk of DC bias is reduced;
  • the display period includes an input phase T1, an output phase T2, a reset phase T3, and an output cut-off holding phase T4 that are sequentially set;
  • the gate drive component of some embodiments of the present disclosure includes a pull-up node control circuit 10, a pull-down node control circuit 11, a gate drive signal output terminal Gout, a tank circuit 16 and a gate drive Signal output circuit 1 7, carry signal output terminal 0ut_G, carry signal output circuit 1 2, pull-up node denoising circuit 13, blank area reset circuit 14 and pull-down node denoising circuit 15;
  • the pull-up node control circuit 10 includes a pull-up node control transistor M1;
  • the gate of M1 is connected to CLKB, the drain of M1 is connected to I nput, and the source of M1 is connected to PU.
  • the pull-down node control circuit 11 includes a first pull-down node control transistor M5 and a second pull-down node control transistor M6;
  • the gate of the first pull-down node control transistor M5 and the drain of the first pull-down node control transistor M5 are both connected to the second clock signal CLK, and the source of the first pull-down node control transistor M5 is connected to The drop-down node PD is connected;
  • the gate of the second pull-down node control transistor M6 is connected to the pull-up node PU, the drain of the second pull-down node control transistor M6 is connected to the pull-down node PD, and the second pull-down node control transistor M6
  • the source is connected to the first low-level terminal; the first low-level terminal is used to input the first low-level VGL;
  • the storage circuit 16 includes a storage capacitor Cst;
  • the gate drive signal output circuit 17 includes a first gate drive signal output transistor M3, a second gate drive signal output transistor M13, and a third gate drive signal output transistor M4;
  • the gate of M3 is connected to PU, the drain of M3 is connected to CLK, and the source of M3 is connected to Gout;
  • the gate of M13 is connected to PD, the drain of M13 is connected to Gout, the source of M13 is connected to VGL; the gate of M4 is connected to Reset, the drain of M4 is connected to Gout, and the source of M13 is connected to VGL;
  • the carry signal output circuit 12 includes a first carry signal output transistor M11, a second carry signal output transistor M12, and a carry signal denoising transistor M120;
  • the gate of M11 is connected to PU, the drain of M11 is connected to CLK, the source of M11 is connected to 0ut_C; the gate of M12 is connected to PD, the drain of M12 is connected to 0ut_C, and the source of M12 is connected to the second low voltage LVGL;
  • the gate of M120 is connected to Reset, the drain of M120 is connected to 0ut_C, and the source of M120 is connected to the second low voltage LVGL;
  • the pull-up node denoising circuit 13 includes a pull-up node drive transistor M2;
  • the gate of M2 is connected to the reset terminal Reset, the drain of M2 is connected to PU, and the source of M2 is connected to LVGL;
  • the blank area reset circuit 14 includes a blank area reset transistor M15;
  • M15 is connected to the blank area reset terminal T_RST, the drain of M15 is connected to PU, and the source of M15 is connected to LVGL;
  • the pull-down node denoising circuit 15 includes a pull-down node denoising transistor M7;
  • the gate of M7 is connected to the input terminal Input, the drain of M7 is connected to PD, and the source of M7 is connected to LVGL.
  • all transistors are n-type thin film transistors, but not limited to this; and Input is connected to the carry signal output terminal of the adjacent upper stage, and Reset is connected to the adjacent next stage.
  • the carry signal output terminal of the stage gate drive component is connected.
  • the display period includes an input phase T1, an output phase T2, a reset phase T3, and an output cut-off holding phase T4 that are sequentially set;
  • In the input stage T1 Input inputs high level, CLK is low level, CLKB is high level, Reset inputs low level, M1 opens, and Cst is charged with the high level input through Input, so that the potential of PU is high Level, M3 and M11 are turned on, Gout and 0ut_C output low level; M7 is turned on to control PD access to LVGL;
  • I nput inputs low level In the reset phase T3, I nput inputs low level, CLK is low level, CLKB is high level, Reset inputs high level, and M1 is turned on, so that PU is connected to I nput, and PU is denoised, so that the potential of PU is Is low level; M2 is turned on to control the PU to access LVGL; M4 is turned on to make Gout output low level, and M120 is turned on to make 0ut_G output low level;
  • T_RST inputs high level and M15 is turned on to control PU access to LVGL.
  • M1 is controlled by AC, it is not easy to cause deterioration of characteristics due to DC bias, and the potential of the pull-up node PU is not controlled by the pull-down node PD, and is controlled by CLKB M1 denoises the PU, which is conducive to charging the PU, and the PD is AC controlled by CLK, and is simultaneously pulled down by nput and PU to ensure normal output.
  • the gate driving component of some embodiments of the present disclosure includes a pull-up node control circuit 10, a pull-down node control circuit, a carry signal output terminal Out_C, a carry signal output circuit 12, a pull-up node denoising circuit 13, and a blank Zone reset circuit 14, pull-down node denoising circuit 15, gate drive signal output terminal Gout, tank circuit 16, and gate drive signal output circuit 17;
  • the pull-up node control circuit 10 includes a pull-up node control transistor M1;
  • the gate of M1 is connected to CLKB, the drain of M1 is connected to I nput, and the source of M1 is connected to PU;
  • the pull-down node control circuit includes a first pull-down control circuit 11 and a second pull-down control circuit
  • the first pull-down node control circuit 111 includes a first pull-down node control transistor M5A and a second pull-down node control transistor M6A
  • the second pull-down node control circuit 112 includes a third pull-down node control transistor M5B and a second pull-down node control transistor M5B.
  • the gate of the first pull-down node control transistor M5A and the drain of the first pull-down node control transistor M5A are both connected to the first control voltage terminal, and the first pull-down node control transistor
  • the source of M5A is connected to the first pull-down node PD1;
  • the gate of the second pull-down node control transistor M6A is connected to the pull-up node PU, the drain of the second pull-down node control transistor M6A is connected to the first pull-down node PD1, and the second pull-down node
  • the source of the control transistor M6A is connected to the second low level terminal; the second low level terminal is used to input the second low level LVGL;
  • the gate of the third pull-down node control transistor M5B and the drain of the third pull-down node control transistor M5B are both connected to the second control voltage terminal, and the source of the third pull-down node control transistor M5B is connected to the second control voltage terminal.
  • the gate of the fourth pull-down node control transistor M6B is connected to the pull-up node PU, the drain of the fourth pull-down node control transistor M6B is connected to the second pull-down node PD2, and the second pull-down node controls The source of the transistor M6B is connected to the second low level terminal;
  • the storage circuit 16 includes a storage capacitor Cst;
  • a first end of the storage capacitor Cst is connected to the pull-up node PU, and a second end of the storage capacitor Cst is connected to the gate drive signal output terminal Gout;
  • the carry signal output circuit 12 includes a first carry signal output transistor M1 1, a second carry signal output transistor M12A and a second carry signal output transistor M12B;
  • the gate of M1 1 is connected to PU, the drain of M1 1 is connected to CLK, and the source of M1 1 is connected to 0ut_C;
  • the gate of M12A is connected to PD1, the drain of M12A is connected to 0ut_C, and the source of M12A is connected to the second low voltage LVGL;
  • the gate of M12B is connected to PD2, the drain of M12B is connected to 0ut_C, and the source of M12B is connected to the second low voltage LVGL;
  • the pull-up node denoising circuit 13 includes a pull-up node drive transistor M2;
  • the gate of M2 is connected to the reset terminal Reset, the drain of M2 is connected to PU, and the source of M2 is connected to LVGL;
  • the blank area reset circuit 14 includes a blank area reset transistor M15;
  • M15 is connected to the blank area reset terminal T_RST, the drain of M15 is connected to PU, and the source of M15 is connected to LVGL;
  • the pull-down node denoising circuit 15 includes a first pull-down node denoising transistor M7A and a second pull-down node denoising transistor M7B;
  • the gate of M7A is connected to the input terminal I nput, the drain of M7A is connected to PD1, and the source of M7A is connected Enter LVGL;
  • the gate of M7B is connected to the input terminal Input, the drain of M7B is connected to PD2, and the source of M7B is connected to LVGL;
  • the gate drive signal output circuit 17 includes a first gate drive signal output transistor M3, a second gate drive signal output transistor M13A, a third gate drive signal output transistor M13B, and a fourth gate drive signal output transistor M4;
  • the gate of M3 is connected to PU, the drain of M3 is connected to CLK, and the source of M3 is connected to Gout;
  • the gate of M13A is connected to PD1, the drain of M13A is connected to Gout, and the source of M13A is connected to VGL;
  • the gate of M13B is connected to PD2, the drain of M13B is connected to Gout, and the source of M13B is connected to VGL;
  • the gate of M4 is connected to Reset, the drain of M4 is connected to Gout, and the source of M13 is connected to VGL.
  • all transistors are n-type thin film transistors, but not limited to this; and Input is connected to the carry signal output terminal of the adjacent upper stage, and Reset is connected to the adjacent next stage.
  • the carry signal output terminal of the stage gate drive component is connected.
  • the display period includes an input phase T1, an output phase T2, a reset phase T3, and an output cut-off holding phase T4 that are sequentially set;
  • VDDo is a high voltage and VDDe is a low voltage.
  • VDDo is switched from high voltage to low voltage
  • VDDe is switched from low voltage to high voltage
  • T_RST is input high voltage
  • In the input phase T1 Input inputs high level, CLK is low level, CLKB is high level, Reset inputs low level, M1 opens, and Cst is charged with the high level input through Input, so that the potential of PU is high Level, M3 and M11 are turned on, Gout and 0ut_C output low level; M7A and M7B are turned on to control both PD1 and PD2 to access LVGL;
  • In the output stage T2 Input inputs low level, CLK is high level, CLKB is low level, Reset inputs low level, M1 turns off, the potential of PU is raised by Cst bootstrap, M3 and M11 turn on, Gout and 0ut_C outputs low level;
  • T_RST inputs high level and M15 is turned on to control PU access to LVGL.
  • the interval between VDDo and VDDe is at a high level, so that the interval between M5A and M5B is opened, and the potential of the pull-down node is controlled by AC, which reduces the risk of DC bias, thereby Improve the threshold voltage drift of the above transistor.
  • the gate drive assembly pull-up node control circuit 10 of some embodiments of the present disclosure further includes a pull-up control transistor M16;
  • the gate of M16 and the drain of M16 are both connected to the input terminal I nput, and the source of M16 is connected to the pull-up node PU;
  • M16 is an n-type thin film transistor, but it is not limited to this.
  • the gate driving component shown in FIG. 15 of the present disclosure uses M1 and M16 together to charge the pull-up node PU in the input phase.
  • the gate drive assembly described in the present disclosure uses the pull-up node control circuit in the input phase, under the control of the first clock signal, to charge the pull-up node through the input signal, and in the reset phase and the output is turned off.
  • the first clock signal is used to denoise the pull-up node, instead of the pull-down node to denoise the pull-up node, so that the pull-up node is charged without loss in the input phase, and it has a strong denoising ability.
  • the pull-down node control circuit controls the potential of the pull-down node under the control of the AC control signal and the potential of the pull-up node.
  • the potential of the pull-down node is controlled by the AC signal, reducing the risk of DC bias and improving the pull-down node
  • the pull-down node in the control circuit controls the threshold voltage drift of the transistor.
  • the present disclosure uses a carry signal to output the voltage.
  • the path control outputs a carry signal through the carry signal output terminal for cascading to improve the driving capability of the gate drive output terminal.
  • the gate driving method of some embodiments of the present disclosure is applied to the above-mentioned gate driving circuit, and the gate driving method includes:
  • the pull-up node control circuit controls the charging of the pull-up node through the input signal under the control of the first clock signal to control the potential of the pull-up node as an effective voltage;
  • the pull-down node control circuit is Under the control of the AC control signal input from the AC control signal terminal and the potential of the pull-up node, the potential of the pull-down node is controlled to be an invalid voltage;
  • the pull-up node control circuit controls the pull-up node to denoise under the control of the first clock signal
  • the pull-down node control circuit controls the potential of the pull-down node to be an effective voltage under the control of the AC control signal and the potential of the pull-up node;
  • the carry signal generating circuit is used to control the carry signal output terminal to output a carry signal under the control of the potential of the pull-up node and the potential of the pull-down node.
  • the pull-up node control circuit charges the pull-up node through the input signal under the control of the first clock signal in the input phase, and in the reset phase and the output cut-off holding phase,
  • the first clock signal is used to denoise the pull-up node, instead of the pull-down node to denoise the pull-up node, so that the pull-up node is charged without loss in the input stage, and it has strong denoising ability and strong
  • the input signal transmission capability of the GOA Gate On Ar ray, the gate drive circuit provided on the array substrate
  • the gate drive circuit provided on the array substrate still has an ideal output even when the TFT (thin film transistor) is deteriorated after the reliability evaluation is completed.
  • the pull-down node control circuit controls the potential of the pull-down node under the control of the AC control signal and the potential of the pull-up node, and the potential of the pull-down node is controlled by the AC signal to reduce the DC bias. To improve the threshold voltage drift of the pull-down node control transistor in the pull-down node control circuit.
  • the gate drive circuit of some embodiments of the present disclosure includes multiple stages of the above-mentioned gate drive components; in addition to the first stage of gate drive components, the carry signal output terminal of each stage of the gate drive component is connected to the adjacent upper stage gate drive component.
  • the display device of some embodiments of the present disclosure includes the above-mentioned gate driving circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

L'invention concerne une unité d'attaque de grille, un procédé d'attaque de grille, un circuit d'attaque de grille et un dispositif d'affichage. L'unité d'attaque de grille comprend un circuit de commande de nœud d'excursion haute (10), un circuit de commande de nœud d'excursion basse (11), une extrémité de sortie de signal porteur (Sortie_C), et un circuit de sortie de signal porteur (12) ; le circuit de commande de nœud d'excursion haute (10) est utilisé pour commander la communication entre un nœud d'excursion haute et une extrémité d'entrée (ENTRÉE) sous la commande d'un premier signal d'horloge (CLKB) entré par une première extrémité d'entrée de signal d'horloge ; le circuit de commande de nœud d'excursion basse (11) est utilisé pour commander le potentiel d'un nœud d'excursion basse (PD) sous la commande d'un signal de commande de courant alternatif entré par une extrémité de signal de commande de courant alternatif (ACS) et le potentiel du nœud d'excursion haute (PU) ; un circuit de génération de signal porteur (12) est utilisé pour commander l'extrémité de sortie de signal porteur (Sortie_C) pour délivrer en sortie un signal porteur sous la commande du potentiel du nœud d'excursion haute (PU) et du potentiel du nœud d'excursion basse (PD) ; et l'extrémité d'entrée (ENTRÉE) est connectée à l'extrémité de sortie de signal porteur (Sortie_C) d'étage supérieur adjacente.
PCT/CN2020/074587 2019-02-28 2020-02-10 Composant d'attaque de grille, procédé d'attaque de grille, circuit d'attaque de grille et dispositif d'affichage Ceased WO2020173293A1 (fr)

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CN114495782A (zh) * 2020-10-27 2022-05-13 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路和显示装置
CN114495783A (zh) * 2020-10-27 2022-05-13 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置
CN112562566B (zh) * 2020-12-10 2023-03-10 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法和显示装置
CN112927645B (zh) * 2021-03-26 2024-04-05 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN113990233B (zh) * 2021-10-21 2024-06-18 福州京东方光电科技有限公司 驱动电路、驱动模组和显示装置
WO2024221296A1 (fr) * 2023-04-26 2024-10-31 京东方科技集团股份有限公司 Circuit d'attaque et substrat d'affichage
CN117746766A (zh) 2023-12-29 2024-03-22 厦门天马光电子有限公司 栅极驱动单元及其驱动方法、移位寄存电路和显示装置

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