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WO2020039493A1 - Dispositif, procédé et programme d'optimisation de calcul - Google Patents

Dispositif, procédé et programme d'optimisation de calcul Download PDF

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Publication number
WO2020039493A1
WO2020039493A1 PCT/JP2018/030769 JP2018030769W WO2020039493A1 WO 2020039493 A1 WO2020039493 A1 WO 2020039493A1 JP 2018030769 W JP2018030769 W JP 2018030769W WO 2020039493 A1 WO2020039493 A1 WO 2020039493A1
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WO
WIPO (PCT)
Prior art keywords
value
arithmetic
explanatory variable
objective function
accuracy
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Ceased
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PCT/JP2018/030769
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English (en)
Japanese (ja)
Inventor
芙美代 鷹野
竹中　崇
誠也 柴田
浩明 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
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NEC Corp
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Publication date
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Priority to JP2020537921A priority Critical patent/JP6973651B2/ja
Priority to PCT/JP2018/030769 priority patent/WO2020039493A1/fr
Publication of WO2020039493A1 publication Critical patent/WO2020039493A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Definitions

  • the operation optimization device of the present invention determines the operation accuracy of each layer in a discrimination model in which a plurality of layers each composed of one or more units are combined.
  • a discrimination model is a neural network.
  • the discrimination model is not limited to the neural network.
  • FIG. 3 is a schematic diagram showing an example of the above processing apparatus.
  • the processing device 18 includes, for example, a low-precision arithmetic circuit 5, a high-precision arithmetic circuit 6, a first memory 7, a second memory 8, and a third memory 9.
  • the low-precision arithmetic circuit 5, the high-precision arithmetic circuit 6, the first memory 7, the second memory 8, and the third memory 9 are connected via, for example, a bus 10.
  • the explanatory variable value acquiring unit 23 acquires the values of the explanatory variables (in this example, “inference accuracy” and “processing speed”).
  • the explanatory variable value obtaining unit 23 causes the actually existing processing device 18 (see FIG. 3) to execute the inference process, and obtains the values of “inference accuracy” and “processing speed” by actual measurement. It is.
  • the second mode is a mode in which the explanatory variable value obtaining unit 23 obtains the values of “inference accuracy” and “processing speed” by simulation. That is, the first mode is a mode in which the value of the explanatory variable is obtained by actual measurement, and the second mode is a mode in which the value of the explanatory variable is obtained by simulation.
  • the explanatory variable value acquisition unit 23 processes the number of the arithmetic units, the memory access amount derived based on the selected applied pattern, and the data transfer amount between the low precision arithmetic circuit 5 and the high precision arithmetic circuit 6.
  • the value of the processing speed may be calculated by substituting the value into the speed function. As a result, the explanatory variable value acquisition unit 23 can acquire the value of the processing speed based on the simulation.
  • the explanatory variable value acquiring unit 23 may acquire the value of the explanatory variable by actual measurement or by simulation. In any case, the explanatory variable value acquiring unit 23 acquires the values of the explanatory variables (in this example, “inference accuracy” and “processing speed”) for each application pattern.
  • the arithmetic accuracy of each layer of the neural network is determined by the first arithmetic accuracy (for example, It is possible to determine whether to use an 8-bit integer operation by the low-precision operation circuit 5 or to use the second operation accuracy (for example, a 32-bit floating-point operation by the high-precision operation circuit 6).
  • the explanatory variable value acquisition unit 23, the objective function calculation unit 25, and the application pattern determination unit 27 are realized by, for example, a CPU (Central Processing Unit) of a computer that operates according to an operation optimization program.
  • the CPU reads the operation optimization program from a program recording medium such as a program storage device. Then, the CPU may operate as the explanatory variable value acquisition unit 23, the objective function calculation unit 25, and the applied pattern determination unit 27 according to the operation optimization program.
  • a CPU Central Processing Unit
  • the explanatory variable value acquisition unit 23 also acquires a value of “circuit scale” in addition to “inference accuracy” and “processing speed”.
  • the design information stored in the design information storage unit 19 includes a design value of the number of arithmetic units included in the low-precision arithmetic circuit 5 and a design value of the number of arithmetic units included in the high-precision arithmetic circuit 6.
  • the design information stored in the design information storage unit 19 includes a design value of the number of arithmetic units included in the low-precision arithmetic circuit 5 and a design value of the number of arithmetic units included in the high-precision arithmetic circuit 6.
  • What is necessary is just to include a value and a design value of how many arithmetic units included in the low-precision arithmetic circuit 5 correspond to one arithmetic unit included in the high-precision arithmetic circuit 6.
  • one arithmetic unit included in the high-precision arithmetic circuit 6 will be described as equivalent to J arithmetic units included in the low-precision arithmetic circuit 5.
  • ⁇ is a coefficient of “power consumption” and is determined in advance.
  • ⁇ is defined as a positive value.
  • FIG. 12 is a schematic block diagram showing a configuration example of a computer according to the embodiment of the present invention or its modification.
  • the computer 1000 includes a CPU 1001, a main storage device 1002, an auxiliary storage device 1003, and an interface 1004.
  • the plurality of information processing devices, circuits, and the like may be centrally arranged or may be distributed.
  • the information processing device, the circuit, and the like may be realized as a form in which each is connected via a communication network, such as a client and server system or a cloud computing system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Neurology (AREA)
  • Image Analysis (AREA)

Abstract

Un moyen d'acquisition de valeur variable explicative 73 réalise un calcul à l'aide d'un modèle de discrimination obtenu par combinaison de multiples couches composées chacune d'une ou de plusieurs unités, pour acquérir une certaine valeur variable explicative pour chaque modèle de modèles d'application qui sont des informations spécifiant une couche à laquelle doit être appliqué un premier circuit de calcul pour réaliser un calcul avec une première précision de calcul, et une couche à laquelle doit être appliqué un second circuit de calcul pour réaliser un calcul avec une seconde précision de calcul plus élevée que la première précision de calcul. Un moyen de calcul de fonction objectif 75 calcule, pour le modèle d'application, la valeur d'une fonction objectif exprimée avec la certaine variable explicative. Un moyen de détermination de modèle d'application 77 détermine un tel modèle d'application pour lequel la valeur de la fonction objectif devient minimale parmi les modèles d'application.
PCT/JP2018/030769 2018-08-21 2018-08-21 Dispositif, procédé et programme d'optimisation de calcul Ceased WO2020039493A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2020537921A JP6973651B2 (ja) 2018-08-21 2018-08-21 演算最適化装置、方法およびプログラム
PCT/JP2018/030769 WO2020039493A1 (fr) 2018-08-21 2018-08-21 Dispositif, procédé et programme d'optimisation de calcul

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/030769 WO2020039493A1 (fr) 2018-08-21 2018-08-21 Dispositif, procédé et programme d'optimisation de calcul

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WO2020039493A1 true WO2020039493A1 (fr) 2020-02-27

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114004968A (zh) * 2020-07-28 2022-02-01 富泰华工业（深圳）有限公司 图像处理方法、装置、电子设备及存储介质
JP2022034897A (ja) * 2020-08-19 2022-03-04 富士通株式会社 情報処理装置、機械学習方法及び機械学習プログラム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018010618A (ja) * 2016-05-03 2018-01-18 イマジネイション テクノロジーズ リミテッド 畳み込みニューラルネットワークハードウエア構成

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10621486B2 (en) * 2016-08-12 2020-04-14 Beijing Deephi Intelligent Technology Co., Ltd. Method for optimizing an artificial neural network (ANN)

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018010618A (ja) * 2016-05-03 2018-01-18 イマジネイション テクノロジーズ リミテッド 畳み込みニューラルネットワークハードウエア構成

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIN, DARRYL D. ET AL.: "Fixed Point Quantization of Deep Convolutional Networks", ARXIV, 2 June 2016 (2016-06-02), XP055561866, Retrieved from the Internet <URL:https://arxiv.org/abs/1511.06393v3> [retrieved on 20180831] *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114004968A (zh) * 2020-07-28 2022-02-01 富泰华工业（深圳）有限公司 图像处理方法、装置、电子设备及存储介质
CN114004968B (zh) * 2020-07-28 2025-07-04 富泰华工业（深圳）有限公司 图像处理方法、装置、电子设备及存储介质
US12475374B2 (en) 2020-07-28 2025-11-18 Hon Hai Precision Industry Co., Ltd. Image processing method, electronic device and storage medium
JP2022034897A (ja) * 2020-08-19 2022-03-04 富士通株式会社 情報処理装置、機械学習方法及び機械学習プログラム
JP7524667B2 (ja) 2020-08-19 2024-07-30 富士通株式会社 情報処理装置、機械学習方法及び機械学習プログラム

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JPWO2020039493A1 (ja) 2021-04-30

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