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WO2020024228A1 - Condensateur et son procédé de fabrication - Google Patents

Condensateur et son procédé de fabrication Download PDF

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Publication number
WO2020024228A1
WO2020024228A1 PCT/CN2018/098370 CN2018098370W WO2020024228A1 WO 2020024228 A1 WO2020024228 A1 WO 2020024228A1 CN 2018098370 W CN2018098370 W CN 2018098370W WO 2020024228 A1 WO2020024228 A1 WO 2020024228A1
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WIPO (PCT)
Prior art keywords
semiconductor layer
layer
capacitor
deep hole
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/098370
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English (en)
Chinese (zh)
Inventor
陆斌
沈健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Weitongbo Technology Co Ltd
Original Assignee
Shenzhen Weitongbo Technology Co Ltd
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Priority to CN201880001016.0A priority Critical patent/CN110998856B/zh
Priority to PCT/CN2018/098370 priority patent/WO2020024228A1/fr
Publication of WO2020024228A1 publication Critical patent/WO2020024228A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present application relates to the field of capacitors, and more particularly, to capacitors and methods of making the same.
  • Capacitors can play a role of bypassing, filtering and decoupling in the circuit, which is an indispensable part to ensure the normal operation of the circuit.
  • MLCC multilayer ceramic capacitors
  • the present application provides a capacitor and a manufacturing method thereof.
  • the capacitor can achieve a smaller package volume and a higher capacity, and the manufacturing method of the capacitor has the advantages of simple process flow and low manufacturing cost.
  • a capacitor comprising:
  • a first insulator layer disposed between the first semiconductor layer and the second semiconductor layer
  • At least one conductive structure that penetrates the first semiconductor layer and the first insulator layer in a first direction and is electrically connected to the second semiconductor layer, the conductive structure and the first semiconductor layer An insulating sidewall is provided therebetween, which electrically isolates the conductive structure from the first semiconductor layer;
  • a first electrode layer electrically connected to the first semiconductor layer and electrically isolated from the at least one conductive structure
  • the second electrode layer is electrically connected to the second semiconductor layer.
  • the capacitor provided in the embodiment of the present application is a wafer-level 3D silicon capacitor, which has the characteristics of small size and high capacity.
  • the electrode of the capacitor can have a larger welding area, thereby reducing or solving the problem of the ultra-micro capacitor due to the pad. Too small, it is difficult to align when the circuit is connected.
  • the capacitor described in the embodiments of the present application has excellent performance and stability, and has a high capacitance density. At the same time, the capacitors described in the embodiments of the present application can play a role of bypassing, filtering, and decoupling in the circuit.
  • the first semiconductor layer, the first insulator layer, and the second semiconductor layer constitute a Silicon On Insulator (SOI) substrate.
  • SOI Silicon On Insulator
  • an included angle between the first direction and a direction perpendicular to the first semiconductor layer is smaller than a preset value.
  • a second insulator layer is disposed between the first semiconductor layer and the first electrode layer, and at least one window is opened on the second insulator layer, and the first electrode layer passes through The at least one window is electrically connected to the first semiconductor layer.
  • the first electrode layer covers the second insulator layer.
  • the insulating sidewall penetrates the first semiconductor layer along the first direction and is connected to the first insulator layer.
  • the insulating sidewall penetrates the first semiconductor layer and the first insulator layer along the first direction, and is connected to the second semiconductor layer.
  • the first cross section of the conductive structure and the second cross section have the same shape or different shapes, wherein the first cross section is perpendicular to the first direction and is far from the second semiconductor layer.
  • the second cross section is a cross section perpendicular to the first direction and close to the second semiconductor layer.
  • the first cross-section or the second cross-section is one of a polygon or a rounded polygon such as a circle, a circle, a triangle, a rectangle, a trapezoid, or a hexagon, or the shape of the above figure. combination.
  • the first cross section or the second cross section is a curve or a polyline segment with a line width greater than a first threshold.
  • the conductive structure is a structure formed by filling a conductive material in a Deep Via (TSV) structure.
  • TSV Deep Via
  • the conductive structure is a structure formed by filling a conductive material in a trench structure.
  • the first insulator layer includes at least one of the following: a silicon dioxide layer, an aluminum oxide layer, a zirconia layer, a hafnium oxide layer, and lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) layer and copper calcium titanate (CaCu 3 Ti 4 O 12 , CCTO) layer.
  • the first insulator layer may be a stack of a material containing a high dielectric constant such as silicon dioxide / alumina / silicon dioxide (SiO 2 / Al 2 O 3 / SiO 2 ).
  • the first insulator layer may be bonded by a material with a high relative permittivity or a dielectric constant.
  • the first insulator layer described in the embodiment of the present application may be a material with high dielectric constant bonding, so that the capacitor described in the embodiment of the present application has a larger capacitance density.
  • a method for manufacturing a capacitor including:
  • a semiconductor-on-insulator (SOI) substrate is provided.
  • the SOI substrate includes a first semiconductor layer, a second semiconductor layer, and a first insulator layer.
  • the first insulator layer is located between the first semiconductor layer and the semiconductor layer. Said between the second semiconductor layers;
  • a conductive material is deposited on a lower surface of the second semiconductor layer to form a second electrode layer.
  • the manufacturing method of the capacitor has the advantages of simple process flow and low manufacturing cost.
  • photolithography is not required for patterning when manufacturing the first electrode layer and the second electrode layer, thereby further simplifying the manufacturing process of the capacitor and reducing the manufacturing cost.
  • the method before the conductive material is deposited on the lower surface of the second semiconductor layer, the method further includes:
  • the second semiconductor layer is thinned.
  • removing the insulating material deposited at the bottom of the at least one deep hole or trench structure includes:
  • the first-direction enhanced plasma etching or dry etching combined with wet etching is used to remove the insulating material deposited at the bottom of the at least one deep hole or trench structure.
  • the opening is slightly smaller than the opening of the deep hole or trench structure, so that the influence on the insulating material deposited on the sidewall of the deep hole or trench structure can be avoided.
  • removing the insulating material deposited at the bottom of the at least one deep hole or trench structure includes:
  • the second direction is perpendicular to the first direction;
  • the protective material may be silicon nitride.
  • the etching the SOI substrate includes:
  • the SOI substrate is etched by Deep Reactive Ion Etch (DRIE).
  • DRIE Deep Reactive Ion Etch
  • FIG. 1 is a schematic structural diagram of a capacitor according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an extending direction of a conductive structure of a capacitor according to an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of a conductive structure of a capacitor according to an embodiment of the present application.
  • FIG. 4 is another schematic cross-sectional view of a conductive structure of a capacitor according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • 10a to 10o are schematic diagrams of a method for manufacturing a capacitor according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a deep hole or trench structure formed by etching in the method of manufacturing a capacitor according to an embodiment of the present application.
  • the capacitor in the embodiment of the present application can play a role of bypassing, filtering, and decoupling in a circuit.
  • the capacitor described in the embodiment of the present application may be a 3D silicon capacitor, which is a new type of capacitor based on semiconductor wafer processing technology. Compared with traditional MLCC (multilayer ceramic capacitors), 3D silicon capacitors have the advantages of small size, high accuracy, high stability, long life and so on.
  • the basic processing flow needs to first process 3D structures such as deep holes, trenches, columns, and walls on the wafer or substrate, and then deposit insulating films and low-resistivity conductive materials on the 3D structure surface in order. Capacitor's lower electrode, dielectric layer and upper electrode.
  • FIG. 1 to FIG. 8 are schematic diagrams of the capacitors in the embodiments of the present application, showing that the capacitors in the embodiments of the present application include two conductive structures, but the two conductive structures are merely examples. Include other numbers of conductive structures, for example, one conductive structure, three conductive structures, or even more conductive structures.
  • the first direction is described by taking the direction perpendicular to the first semiconductor layer (wafer) as an example. In the embodiment of the present application, the first direction may be some other directions. The directions of, for example, satisfy all directions whose angles with the direction perpendicular to the first semiconductor layer (wafer) are smaller than a preset value.
  • FIG. 1 is a possible structural diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 includes a first semiconductor layer 110, a first insulator layer 120, a second semiconductor layer 130, at least one conductive structure 140, an insulating sidewall 150, a first electrode layer 160, and a second electrode layer 170.
  • the first insulator layer 120 is disposed below the first semiconductor layer 110; the second semiconductor layer 130 is disposed below the first insulator layer 120; and the conductive structure 140 penetrates the first in a first direction.
  • the semiconductor layer 110 and the first insulator layer 120 are electrically connected to the second semiconductor layer 130.
  • An insulating sidewall 150 is provided between the conductive structure 140 and the first semiconductor layer 110, and the insulating sidewall 150 is electrically isolated.
  • the conductive structure 140 and the first semiconductor layer 110; the first electrode layer 160 is electrically connected to the first semiconductor layer 110, and is electrically isolated from the at least one conductive structure 140; and the second electrode layer 170 and the second The semiconductor layer 130 is electrically connected.
  • the first semiconductor layer 110, the first insulator layer 120, and the second semiconductor layer 130 may constitute The capacitor A (capacitor C1), the conductive structure 140, the insulating sidewall 150, and the first semiconductor layer 110 may constitute a capacitor B (capacitor C2).
  • the capacitor A is in parallel with the capacitor B. Therefore, the capacitor 100
  • each conductive structure 140 in the capacitor 100 may form a capacitor B with the insulating sidewall 150 and the first semiconductor layer 110.
  • an included angle between the first direction and a direction perpendicular to the first semiconductor layer 110 is smaller than a preset value.
  • the corresponding first directions of different conductive structures may be the same or different.
  • different conductive structures may have the same extending direction or different extending directions.
  • the capacitor 100 includes a conductive structure 10 and a conductive structure 20.
  • the angle between the corresponding first direction A and the direction perpendicular to the first semiconductor layer 110 is 0 °.
  • the included angle between the corresponding first direction B and the direction perpendicular to the first semiconductor layer 110 is 5 °.
  • the above preset value may be determined according to the manufacturing process of the actual capacitor, for example, the preset value is ⁇ 10 °.
  • the first semiconductor layer 110, the first insulator layer 120, and the second semiconductor layer 130 constitute an SOI substrate.
  • the first semiconductor layer and the second semiconductor layer are low-resistance silicon and have good conductivity.
  • the first semiconductor layer and the second semiconductor layer are P-type heavily doped single crystal silicon ( Resistivity: 1m ⁇ .cm).
  • the first insulator layer 120 may be formed by bonding one or more materials with a high dielectric constant or dielectric constant.
  • the first insulator layer 120 includes at least one of the following: a silicon dioxide layer, an aluminum oxide layer, a zirconia layer, a hafnium oxide layer, and lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT ) Layer, and a copper calcium titanate (CaCu 3 Ti 4 O 12 , CCTO) layer.
  • the first insulator layer 120 may further include some other material layers with high dielectric constant characteristics, which is not limited in the embodiment of the present application.
  • the first insulator layer may be a stack of a material containing a high dielectric constant such as silicon dioxide / alumina / silicon dioxide (SiO 2 / Al 2 O 3 / SiO 2 ).
  • the first insulator layer described in the embodiment of the present application may be a material with high dielectric constant bonding, so that the capacitor described in the embodiment of the present application has a larger capacitance density.
  • the conductive structure 140 is a structure formed by filling a conductive material in a Through Hole (TSV) structure, or a structure formed by filling a conductive material in a trench structure.
  • TSV Through Hole
  • deep holes and trenches are two types of structures.
  • an xy plane formed by the upper surface of the first semiconductor layer 110 as the x-axis and the y-axis is established with the depth direction of the deep hole or the trench as the z-axis
  • the difference in the dimensions of the deep hole in the x-axis and y-axis directions is small, while the dimensions of the groove in the x-axis and y-axis directions have a large gap.
  • the conductive structure 140 when the conductive structure 140 is a structure formed by filling a conductive material in a deep hole structure, the conductive structure 140 may present a figure as shown in FIG. 3 on a cross section perpendicular to the first direction. It should be noted that FIG. 3 is a collection of figures that the conductive structure 140 may present on a cross section perpendicular to the first direction. In practice, the conductive structure 140 may present a cross section that is perpendicular to the first direction. A variety of patterns, or multiple patterns, and the number of the conductive structures 140 are also determined according to the actual manufacturing process. In other words, FIG. 3 does not limit the number of the conductive structures 140 in the capacitor 100 in a cross section perpendicular to the first direction and the number of the conductive structures 140.
  • the conductive structure 140 when the conductive structure 140 is a structure formed by filling a conductive material in a trench structure, the conductive structure 140 may present a pattern as shown in FIG. 4 on a cross section perpendicular to the first direction.
  • FIG. 4 is a collection of figures that the conductive structure 140 may present on a cross section perpendicular to the first direction.
  • the conductive structure 140 may present a cross section that is perpendicular to the first direction.
  • a variety of patterns, or multiple patterns, and the number of the conductive structures 140 are also determined according to the actual manufacturing process. In other words, FIG. 4 does not limit the number of the conductive structures 140 in the capacitor 100 in a cross section perpendicular to the first direction and the number of the conductive structures 140.
  • the conductive structure 140 when the conductive structure 140 is a structure formed by filling a conductive material in a deep hole, the conductive structure 140 may be circular, circular, triangular, rectangular, trapezoidal, One of polygons such as hexagons or rounded polygons, or a combination of the above graphics.
  • the conductive structure 140 when the conductive structure 140 is a structure formed by filling a trench with a conductive material, the conductive structure 140 may be a curved line segment or a broken line segment having a line width greater than a first threshold on a cross section perpendicular to the first direction. .
  • the first threshold value may be determined according to a manufacturing process of the capacitor 100, for example, the first threshold value is 0.2 micrometers.
  • the shapes of the first cross section and the second cross section of the conductive structure 140 are the same or different, wherein the first cross section and the second cross section may be the conductive structure at two different positions along the first direction. section.
  • the first cross section is a cross section perpendicular to the first direction and away from the second semiconductor layer
  • the second cross section is a cross section perpendicular to the first direction and close to the second semiconductor layer.
  • the material of the conductive structure 140 may be heavily doped polysilicon, a carbon-based material, or various metals such as aluminum, tungsten, and copper, or a low-resistivity compound such as titanium nitride, or the above. A combination of several conductive materials.
  • the aspect ratio of the conductive structure 140 can be set flexibly, for example, it can be between 1 and 500.
  • the width of the conductive structure 140 can be defined as: the average width of the conductive structure 140 in a cross section perpendicular to the first direction, for example, the conductive structure 140 appears in a cross section perpendicular to the first direction In a circle, the width of the conductive structure 140 is the radius of the circle.
  • the width of the conductive structure 140 can also be defined as: the maximum width of the conductive structure 140 in a cross section perpendicular to the first direction, for example, in the cross section of the conductive structure 140 perpendicular to the first direction
  • the width of the conductive structure 140 is the diameter of the circle.
  • the insulating sidewall 150 may be a thin film of insulating material.
  • the material of the insulating sidewall 150 may be silicon oxide, silicon nitride, metal oxide, metal nitride, and the like, such as silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride. , Hafnium oxide, zirconia, zinc oxide, titanium dioxide, lead zirconate titanate, etc.
  • the insulating material may be one layer, or two or more layers. The specific material and layer thickness can be adjusted according to the capacitor's capacitance value, frequency characteristics, and losses.
  • the material of the first electrode layer 160 and the second electrode layer 170 may be heavily doped polysilicon, a carbon-based material, or various metals such as aluminum, tungsten, and copper, and may also be a low nitride or the like. Resistivity compounds, or a combination of the aforementioned conductive materials.
  • first electrode layer 160 and the second electrode layer 170 may be a full-surface electrode design, thereby increasing the electrode area, which is helpful to alleviate or solve the problem of ultra-small capacitors, because the pads are too small, during circuit connection, Difficult alignment issues.
  • a second insulator layer 180 and a second insulator layer are provided between the first semiconductor layer 110 and the first electrode layer 160. At least one window is opened on 180, and the first electrode layer 160 is electrically connected to the first semiconductor layer 110 through the at least one window.
  • the first electrode layer 160 covers the second insulator layer 180. In other words, the first electrode layer 160 also covers the at least one window opened on the second insulator layer 180.
  • the material of the second insulator layer 180 may be a nitride of silicon, an oxide of silicon, such as silicon nitride, which is grown by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • the insulating material may be one or more layers.
  • the shape and number of windows provided on the second insulator layer 180 may be specifically determined according to the manufacturing process of the capacitor 100, which is not limited in the embodiment of the present application.
  • the insulating sidewall 150 penetrates the first semiconductor layer 110 and the first insulator layer 120 along the first direction, and is connected to the second semiconductor layer 130. .
  • the insulating sidewall 150 penetrates the first semiconductor layer 110 in the first direction and is connected to the first insulator layer 120. At this time, the conductive structure 140 is directly connected to the first The insulator layers 120 are connected.
  • the conductive structure 140 may further extend into the second semiconductor layer 130 so as to realize the connection with the The second semiconductor layer 130 is electrically connected.
  • the conductive structure 140 extends into the second semiconductor layer 130, but does not penetrate through the second semiconductor layer 130.
  • the shapes of the third cross section and the fourth cross section of the conductive structure 140 are approximately the same, but of course they may be different. It should be understood that the third cross section may be a cross section of the conductive structure 140 in the section of the first semiconductor layer 110 along the first direction, and the fourth cross section may be the conductive structure 140 in the first insulator layer 120 along the first direction. Inside the section.
  • the shapes of the third cross section 101 and the fourth cross section 102 of the conductive structure 140 are approximately the same.
  • the shapes of the third cross section and the fourth cross section are approximately the same, and are not shown in the drawings.
  • the shapes of the third cross section 101 and the fourth cross section 102 of the conductive structure 140 are different.
  • the cross-section of the conductive structure 140 perpendicular to the first direction along the first direction may have a constant area, for example, as shown in FIGS. 1, 2, 5, 6, and 7. It may also start at a specific position along the first direction (for example, from the extension of the conductive structure 140 into the first insulator layer 120), and the area of the cross-section of the conductive structure 140 perpendicular to the first direction increases. Large, and then gradually reduced, for example, as shown in Figure 8.
  • the capacitor provided in the embodiment of the present application is a 3D silicon capacitor, which has the characteristics of small size and high capacity.
  • the electrode of the capacitor can have a larger welding area, so that the ultra-small capacitor can be alleviated or solved because the pad is too small. Difficult to align when connecting circuits.
  • FIG. 9 to FIG. 11 are schematic flowcharts of a method for manufacturing a capacitor according to an embodiment of the present application, but these steps or operations are merely examples.
  • the embodiments of the present application may also perform other operations or the operations in FIGS. 9 to 11 Variations of each operation.
  • FIG. 9 shows a schematic flowchart of a capacitor manufacturing method 200 according to an embodiment of the present application.
  • the manufacturing method 200 of the capacitor includes:
  • an SOI substrate is provided.
  • the SOI substrate includes a first semiconductor layer 110, a second semiconductor layer 130, and a first insulator layer 120.
  • the first insulator 120 layer is disposed between the first semiconductor layer 110 and the substrate.
  • the second semiconductor layer 130 is described.
  • an SOI substrate is provided as shown in FIG. 10a.
  • Step 220 Etching the SOI substrate to form at least one deep hole or trench structure in the SOI substrate, wherein the deep hole or trench structure runs through the first direction in a first direction.
  • an included angle between the first direction and a direction perpendicular to the first semiconductor layer 110 is smaller than a preset value.
  • the SOI substrate may be etched according to deep reactive ion etching.
  • a layer of photoresist 201 is spin-coated on the upper surface of the SOI substrate, and exposed and developed to form an etch that does not cover the photoresist 201.
  • Graphic window as shown in Figure 10b.
  • deep reactive ion etching is used to etch through the first semiconductor layer 110 in the SOI substrate in a first direction to form at least one deep hole or trench structure, as shown in FIG. 10c; Reactive ion etching etches through the first semiconductor layer 110 and the first insulator layer 120 in a first direction in an SOI substrate, as shown in FIG. 10d.
  • the photoresist 201 is removed.
  • an included angle between the first direction and a direction perpendicular to the first semiconductor layer 110 is smaller than a preset value.
  • step 230 an insulating material 204 is deposited on the surface of the at least one deep hole or trench structure, and the insulating material 204 deposited on the bottom of the at least one deep hole or trench structure is removed to expose the second semiconductor layer 130.
  • the insulating sidewall 150 can be formed by depositing and partially removing the insulating material 204.
  • the deep hole or trench structure penetrates the first semiconductor layer 110 and the first insulator layer 120 along the first direction as an example. That is, in the structure shown in FIG. 10d, first, at least one An insulating material 204 (eg, a thin film of insulating material) is deposited in the deep hole or trench structure, as shown in FIG. 10e, and then the insulating material 204 deposited on the bottom of at least one deep hole or trench structure is removed to expose the second semiconductor layer 130, as shown in Figure 10f.
  • An insulating material 204 eg, a thin film of insulating material
  • the following two methods may be selected to remove the insulating material 204 deposited on the bottom of the at least one deep hole or trench structure.
  • Method 1 First, a photosensitive dry film 202 is covered on the insulating material 204 on the upper surface of the first semiconductor layer 110, as shown in FIG. 10j, and then, at the position of the at least one deep hole or trench structure An opening is opened on the photosensitive dry film 202, and the opening is slightly smaller than the opening of the deep hole or groove structure, as shown in FIG. 10h. Finally, at the position of the opened opening, the first opening is used.
  • One-way enhanced plasma etching or dry etching combined with wet etching removes the insulating material 204 deposited on the bottom of the at least one deep hole or trench structure, exposes the second semiconductor layer 130, and removes the photosensitive dry film 202 , As shown in Figure 10f.
  • the entire dry photosensitive film 202 is covered on the insulating material 204 on the upper surface of the first semiconductor layer 110. At this time, the photosensitive dry film 202 does not Into the at least one deep hole or trench structure.
  • the opening is slightly smaller than the opening of the deep hole or trench structure, which can avoid plasma etching or dry etching combined with wet etching on the side of the bottom of the deep hole or trench structure. Damage to insulating materials on walls.
  • Method 2 First, a protective material 203 is deposited on the surface of the at least one deep hole or trench structure on which a thin film-shaped insulating material 204 is deposited, as shown in FIG. 10i, and then, the first direction enhanced plasma etching is used. Removing the protective material 203 in the second direction, and removing the insulating material 204 and the protective material 203 at the bottom of the at least one deep hole or trench structure, while partially retaining the protective material 203 in the first direction, the first Two directions are perpendicular to the first direction, as shown in FIG. 10g. Finally, the protective material 203 in the first direction is removed, as shown in FIG. 10f.
  • the energy of the plasma will be lost, that is, as shown in FIG. 10g, in the first direction, as the etching depth increases, the energy of the plasma will be lost.
  • the etching effect of the protective material on the sidewall of the at least one deep hole or trench structure is getting worse and worse, and even disappears, which shows that the sidewall of the at least one deep hole or trench structure (first direction) More and more protective materials remain.
  • the protective material can prevent the plasma etching from damaging the insulating material on the sidewall of the bottom of the deep hole or trench structure.
  • a method for depositing an insulating material on the surface of the at least one deep hole or trench structure includes direct thermal oxidation to grow silicon dioxide, and atomic layer deposition (ALD), physical vapor deposition (PVD) can also be used. ), Chemical vapor deposition (CVD) or spin coating, spraying and other methods.
  • Insulating materials include silicon oxide, silicon nitride, metal oxide, metal nitride, etc., such as silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconia, zinc oxide, titanium dioxide , Lead zirconate titanate and so on.
  • the insulating material may be one layer, or two or more layers. The specific material and layer thickness can be adjusted according to the capacitor's capacitance value, frequency characteristics, and losses.
  • a conductive material 205 is deposited in the at least one deep hole or trench structure in which the insulating material 204 is deposited to form at least one conductive structure 140 in the SOI structure.
  • a conductive material 205 is deposited in the at least one deep hole or trench structure, as shown in FIG. 10k, and then, the material deposited above the upper surface of the first semiconductor layer is removed.
  • the conductive material 205 and the insulating material 204 are shown in FIG. 10l.
  • the method for depositing the conductive material includes ALD, PVD, organic metal chemical vapor deposition, evaporation, electroplating, and the like.
  • the conductive material may be heavily doped polysilicon, carbon-based materials, or various metals such as aluminum, tungsten, and copper, or a low-resistivity compound such as titanium nitride, or a combination of the above-mentioned conductive materials.
  • the method of mechanical grinding and polishing, chemical mechanical planarization (CMP), wet etching or dry etching, or a combination of the above methods can be used to remove the deposited conductive material on the first semiconductor layer and Insulation Materials.
  • a second insulator layer 180 is deposited on the upper surface of the first semiconductor layer 110, and at least one window is opened on the second insulator layer 180 to expose the first semiconductor layer 110.
  • a second insulator layer 180 is deposited on the upper surface of the first semiconductor layer 110, and at least one window is opened / formed on the second insulator layer 180 to expose The first semiconductor layer 110 is shown in FIG. 10m.
  • the second insulator layer may be silicon nitride or silicon oxide grown by PVD or CVD, such as USG or TEOS, etc., or various types of polymers by spray coating or spin coating, such as Polyimide (PI), Parylene, benzocyclobutene (BCB), etc.
  • the insulating material may be one or more layers. After deposition, a window partially exposed by the first semiconductor layer is opened by photolithography.
  • step 260 a conductive material is deposited on the upper surface of the second insulator layer 180 to form a first electrode layer 160.
  • a conductive material is deposited on the upper surface of the second insulator layer 180 to form a first electrode layer 160, and the first electrode layer 160 covers the exposed first semiconductor layer 110.
  • the upper surface is used to achieve the connection between the first electrode layer 160 and the first semiconductor layer 110, as shown in FIG. 10n.
  • a method of depositing a conductive material to form the first electrode layer 160 includes ALD, PVD, organic metal chemical vapor deposition, evaporation, electroplating, and the like.
  • the conductive material can be heavily doped polysilicon, carbon-based materials, or various metals such as aluminum, tungsten, and copper, or a low-resistivity compound such as titanium nitride, or a combination of the foregoing conductive materials.
  • step 270 a conductive material is deposited on the lower surface of the second semiconductor layer 130 to form a second electrode layer 170.
  • a conductive material is deposited on the lower surface of the second semiconductor layer 130 to form a second electrode layer 170, as shown in FIG. 10o.
  • a method for depositing a conductive material to form the second electrode layer 170 includes ALD, PVD, organic metal chemical vapor deposition, evaporation, plating, and the like.
  • the conductive material can be heavily doped polysilicon, carbon-based materials, or various metals such as aluminum, tungsten, and copper, or a low-resistivity compound such as titanium nitride, or a combination of the above-mentioned conductive materials.
  • the method 200 further includes: performing a thinning process on the second semiconductor layer 130.
  • the second semiconductor layer 130 is first thinned to a proper thickness by grinding and polishing the back surface, and then a conductive material is deposited to form the second electrode layer 170.
  • the capacitor shown in FIG. 8 may also be manufactured by using the capacitor manufacturing method 200.
  • an SOI substrate is etched to be processed in the SOI substrate.
  • step 220 the first semiconductor layer 110 is first etched by DRIE, and then the first insulator layer 120 is etched by a wet method to form a structure as shown in FIG.
  • the wet etching rate is generally isotropic in the first insulator layer 120 (silicon dioxide), after the etching is completed, the shape will be approximately an inverted trapezoid with a large size and a small size.
  • the manufacturing method of the capacitor has the advantages of simple process flow and low manufacturing cost.
  • photolithography is not required for patterning when manufacturing the first electrode layer and the second electrode layer, thereby further simplifying the manufacturing process of the capacitor and reducing the manufacturing cost.
  • the manufacturing method of the capacitor of the present application is further described below with a specific example.
  • the number of etched deep holes in this example is two.
  • Step 1 Use a SOI wafer with a diameter of 300mm and two layers of P-type heavily doped single crystal silicon (resistivity 1m ⁇ .cm) as the substrate.
  • the thickness of the upper silicon layer of the SOI wafer is 10 microns, and the middle layer of silicon dioxide The thickness is 2 microns, and the thickness of the underlying silicon is 800 microns.
  • a layer of photoresist is spin-coated on the surface of the silicon layer on the SOI wafer, and two circular holes with a diameter of 1 micron are opened after exposure and development.
  • a 12-micron deep hole is etched by the DRIE process. The bottom of the deep hole exposes the underlying silicon of the SOI wafer.
  • Step 2 An ALD process is used to deposit 20 nanometers of alumina as the dielectric layer of the capacitor on the upper surface and the deep hole surface of the SOI wafer.
  • Step 3 First cover the top surface of the SOI substrate with a photosensitive dry film, then expose and develop, and open a circular hole window with a diameter of 0.8 microns at the deep hole.
  • the insulating material at the bottom of the deep hole is removed by plasma etching.
  • Step 4 Place the wafer in the furnace tube, and deposit low-density chemically deposited heavy-doped polysilicon with a resistivity of 1m ⁇ .cm in deep holes.
  • Step 5 The polysilicon and aluminum oxide deposited on the upper surface of the SOI wafer are removed by grinding and polishing to expose the upper silicon of the SOI wafer.
  • Step 6 spin-coat a layer of PI with a thickness of 2 micrometers on the top surface of the SOI wafer, and then expose and develop. Open several windows to expose the upper layer of silicon on the SOI and cover the polysilicon deposited in the deep holes.
  • Step 7 Using PVD, deposit a layer of aluminum with a thickness of 3 micrometers, a layer of nickel with a thickness of 200 nanometers, and a layer of gold with a thickness of 100 nanometers as a pad for the upper electrode.
  • Step 8 Temporarily bond the SOI wafer to the slide, and then grind and polish the backside of the SOI wafer to a thickness of 80 microns. Next, a layer of 1 micron thick aluminum, 200 nanometers of nickel, and 100 nanometers of gold was deposited on the lower surface of the SOI wafer by PVD as the pad of the lower electrode.
  • Step 9 After debonding, the wafer is pasted on the blue film with a steel ring, and the capacitor chips are obtained by dicing along the scribe line.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

Des modes de réalisation de la présente invention concernent un condensateur et son procédé de fabrication, le condensateur ayant un petit volume de boîtier et une capacité élevée, et le procédé de fabrication d'un condensateur ayant les avantages d'être simple dans un écoulement de traitement et d'un faible coût de fabrication. Le condensateur comprend : une première couche semi-conductrice ; une seconde couche semi-conductrice; une première couche isolante, disposée entre la première couche semi-conductrice et la seconde couche semi-conductrice ; au moins une structure conductrice, la structure conductrice passant à travers la première couche semi-conductrice et la première couche isolante dans une première direction et étant électriquement connectée à la seconde couche semi-conductrice, une paroi latérale isolante étant disposée entre la structure conductrice et la première couche semi-conductrice, la paroi latérale isolante isolant électriquement la structure conductrice de la première couche semi-conductrice ; une première couche d'électrode, électriquement connectée à la première couche semi-conductrice et électriquement isolée de la ou des structures conductrices ; et une seconde couche d'électrode, connectée électriquement à la seconde couche semi-conductrice.
PCT/CN2018/098370 2018-08-02 2018-08-02 Condensateur et son procédé de fabrication Ceased WO2020024228A1 (fr)

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CN102782827A (zh) * 2009-12-30 2012-11-14 速力斯公司 用于薄晶片的可移动静电载具
JP2012248604A (ja) * 2011-05-26 2012-12-13 Denso Corp 半導体装置およびその製造方法
CN106449355A (zh) * 2015-08-06 2017-02-22 北大方正集团有限公司 一种沟槽电容及其制备方法

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US7718503B2 (en) * 2006-07-21 2010-05-18 Globalfoundries Inc. SOI device and method for its fabrication
US7808028B2 (en) * 2007-04-18 2010-10-05 International Business Machines Corporation Trench structure and method of forming trench structure
KR101017809B1 (ko) * 2008-03-13 2011-02-28 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
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CN102782827A (zh) * 2009-12-30 2012-11-14 速力斯公司 用于薄晶片的可移动静电载具
CN102376780A (zh) * 2010-08-16 2012-03-14 众智光电科技股份有限公司 具有嵌入式高密度电容的硅基座
JP2012248604A (ja) * 2011-05-26 2012-12-13 Denso Corp 半導体装置およびその製造方法
CN106449355A (zh) * 2015-08-06 2017-02-22 北大方正集团有限公司 一种沟槽电容及其制备方法

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