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WO2020000435A1 - Integrated circuit and interconnection structure thereof - Google Patents

Integrated circuit and interconnection structure thereof Download PDF

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Publication number
WO2020000435A1
WO2020000435A1 PCT/CN2018/093839 CN2018093839W WO2020000435A1 WO 2020000435 A1 WO2020000435 A1 WO 2020000435A1 CN 2018093839 W CN2018093839 W CN 2018093839W WO 2020000435 A1 WO2020000435 A1 WO 2020000435A1
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WO
WIPO (PCT)
Prior art keywords
auxiliary
integrated circuit
wiring
traces
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/093839
Other languages
French (fr)
Chinese (zh)
Inventor
杨雯
刘燕翔
曾秋玲
陈赞锋
夏禹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201880095115.XA priority Critical patent/CN112400220B/en
Priority to PCT/CN2018/093839 priority patent/WO2020000435A1/en
Publication of WO2020000435A1 publication Critical patent/WO2020000435A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Definitions

  • the present application relates to integrated circuits, and in particular, to an integrated circuit interconnect structure that is not prone to crack defects.
  • connection structure is more likely to crack, and the cracks generated by the crack are easy to extend, thereby affecting the quality of the integrated circuit interconnection structure.
  • the present application provides an integrated circuit and an interconnection structure thereof that are not prone to cracking, and the cracks generated by cracking are not easy to extend.
  • the integrated circuit interconnection structure includes an interconnect structure and a first reinforcement structure.
  • the interconnect structure includes three or more layers of wiring layers stacked on top of each other and a dielectric layer provided between two adjacent wiring layers. The dielectric layer is used to carry out the two adjacent wiring layers. Insulation; each layer of the wiring layer includes a plurality of spaced-apart metal traces and an insulating medium provided between the spaced-apart metal traces.
  • the first reinforcement structure includes a plurality of auxiliary traces and a plurality of auxiliary through holes, and the plurality of auxiliary traces are distributed in three or more adjacent wiring layers, and are in the same wiring layer.
  • the auxiliary traces are insulated from the metal traces, and the auxiliary traces extend in the same direction as the metal traces; a plurality of the auxiliary vias are distributed in at least two adjacent layers of the A dielectric layer; the auxiliary vias on each dielectric layer are connected to the auxiliary traces on the wiring layer on both sides of the dielectric layer; the auxiliary vias on adjacent dielectric layers are in Aligned or partially aligned in a direction perpendicular to the wiring layer.
  • the auxiliary wiring is not electrically connected to any structure and does not have any signal transmission function; the auxiliary through-hole is only used to connect the auxiliary wiring and has no signal transmission function.
  • the strength of the integrated circuit is enhanced, and the generation and extension of cracks in the integrated circuit interconnection structure are avoided.
  • the auxiliary traces of the first reinforcement structure and the metal traces of the interconnect structure are disposed on the same layer and spaced apart, that is, the areas where the metal traces are not arranged in the wiring layer are provided.
  • the auxiliary wiring is equivalent to inserting the auxiliary wiring with high strength into the insulating medium of the integrated circuit, thereby enhancing the strength of the insulating medium and reducing the occurrence of cracks in the insulating medium.
  • the auxiliary trace into the insulating medium, it is possible to block the crack from extending.
  • the auxiliary through hole is provided in the dielectric layer to increase the strength of the dielectric layer, so that the dielectric layer is not prone to cracks, thereby further increasing the strength of the integrated circuit.
  • crack propagation can be blocked by the auxiliary through hole.
  • Connecting the auxiliary vias on each dielectric layer to the auxiliary traces on the wiring layer on both sides of the dielectric layer, so that the auxiliary traces and auxiliary vias of the first reinforcement structure are formed It is integrated and spans multiple wiring layers, so that the first enhancement can further improve the mechanical strength and reliability of the integrated circuit interconnect structure.
  • the auxiliary through-holes located in adjacent dielectric layers are aligned or partially aligned, thereby avoiding the extension of the crack from the misaligned positions of the auxiliary through-holes between the different wiring layers and the dielectric layer.
  • the extending directions of the auxiliary traces in the two adjacent wiring layers intersect with each other, and the auxiliary vias are located in the auxiliary traces of the two adjacent wiring layers overlapping. s position.
  • the auxiliary traces in the same wiring layer and the metal traces extend in the same direction.
  • the extension directions of the auxiliary traces in two adjacent wiring layers of the present application are perpendicular to each other, and the extension directions of the metal traces in the two adjacent wiring layers are also perpendicular to each other.
  • the extension directions of the auxiliary traces and the metal traces in two adjacent wiring layers are the same, so that the metal traces and the auxiliary traces in each of the wiring layers are located.
  • the environment of the metal trace is as much as possible, which can improve the uniformity of the process in the manufacturing process of the metal trace and the auxiliary trace, and reduce the difference in electrical performance of the metal trace due to the different surrounding environments. Further, the extending directions of the metal traces and the auxiliary traces in two adjacent wiring layers are perpendicular, so that the traces in the interconnection structure of the integrated circuit can meet the micro-connections in the integrated circuit. Demand for electronic structures.
  • the integrated circuit interconnection structure further includes a second reinforcement structure
  • the second reinforcement structure includes the second reinforcement structure including auxiliary traces separated from two adjacent wiring layers, and located at a phase opposite to each other.
  • An auxiliary through hole of a dielectric layer between two adjacent wiring layers, the auxiliary through hole connecting two adjacent auxiliary wirings in the wiring layer, and the auxiliary wiring of the third reinforcing structure and the auxiliary wiring The metal traces in the wiring layer and the auxiliary traces of the first reinforcement structure are insulated.
  • the density of the auxiliary traces in the wiring layer and the density of the auxiliary through-holes of the dielectric layer are further increased, thereby further enhancing the Describes the strength of the integrated circuit interconnect structure and prevents crack propagation.
  • the integrated circuit interconnection structure further includes a third enhanced structure, and the third enhanced structure is an independent auxiliary wiring.
  • the independent auxiliary trace is located on the wiring layer and is spaced from and insulated from the metal trace in the wiring layer and the auxiliary trace of the first reinforcement structure.
  • the auxiliary through hole is filled with a filling material.
  • a filling material of the auxiliary through hole is the same as a material of the auxiliary trace connected thereto.
  • the filling material in the auxiliary through hole is the same as the material of the auxiliary trace connected to it, and the auxiliary trace and the filling material can be formed at the same time in some manufacturing processes, thereby simplifying the manufacturing process.
  • the filling material of the auxiliary through hole is the same as the material of the auxiliary wiring connected to it, so that the combining effect between the auxiliary through hole and the auxiliary wiring is better, so as to obtain a more stable first reinforcement. structure.
  • an inner wall of the auxiliary through hole is provided with a diffusion barrier layer. This prevents the filling material in the auxiliary through hole from diffusing into the dielectric layer and causes leakage and circuit failure, thereby ensuring the quality of the integrated circuit.
  • materials of the metal traces and the auxiliary traces located in the same wiring layer may be the same or different.
  • the metal wiring and the auxiliary wiring in the same wiring layer can be obtained through the same process, and the manufacturing process is simple;
  • a material with better conductivity can be used for the metal traces, and a mechanical can be selected for the auxiliary traces.
  • a material with better performance to take into account both the electrical and mechanical properties of the integrated circuit interconnect structure.
  • the dielectric layer includes an etch barrier layer, and the etch barrier layer is located on a side where the dielectric layer and the wiring layer are bonded.
  • the etch barrier layer Through the etch barrier layer, the processing accuracy of the integrated circuit interconnect structure can be guaranteed, so that the integrated circuit has better quality.
  • a surface of the metal wiring and the auxiliary wiring is provided with a diffusion barrier layer.
  • a material for forming the dielectric layer and a material for the insulating medium in the wiring layer include a low dielectric constant material, an ultra-low dielectric constant material, or an extremely low dielectric constant material.
  • the low dielectric constant material is a material with a dielectric constant less than 3.9
  • the ultra low dielectric constant material is with a dielectric constant less than 2.9
  • the very low dielectric constant material is a material with a dielectric constant less than 2.6 .
  • the material of each of the dielectric layers may be the same or different.
  • the use of a low-dielectric constant material or an ultra-low-dielectric constant material or an extremely low-dielectric constant material as the material of the dielectric layer can reduce the parasitic capacitance between metal traces and between metal traces and auxiliary traces.
  • the purpose of reducing the delay of the circuit interconnection line is achieved. It can be understood that, according to different thicknesses of different dielectric layers, distances between vias located in the dielectric layer, and distances between metal traces located in the wiring layer, etc., the dielectric layer
  • the material of the insulating medium in the wiring layer may be different.
  • an insulating dielectric material with a lower dielectric constant may be used, thereby reducing the parasitic capacitance between the metal traces;
  • an insulating dielectric material with a higher dielectric constant may be used.
  • the size of the auxiliary trace in each of the wiring layers and the gap between the auxiliary trace and the metal trace or the auxiliary trace adjacent to the auxiliary trace meet the requirements of the design rule.
  • the integrated circuit includes a substrate and the integrated circuit interconnection structure formed on the substrate. Because the integrated circuit interconnect structure is not easy to crack and the cracks generated by the crack are not easy to extend, the integrated circuit interconnect structure has better mechanical strength and reliability. The integrated circuit interconnection structure is a part of the integrated circuit, so that the integrated circuit has better mechanical strength and reliability.
  • the substrate has a plurality of microelectronic structures, and the integrated circuit interconnection structure is electrically connected to the plurality of microelectronic structures, so as to electrically connect the plurality of microelectronic structures to each other to form the integrated circuit. It implements one or more functions such as logic function, storage function, input / output function of the integrated circuit.
  • FIG. 1 is a schematic cross-sectional view of an integrated circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a first enhanced structure in an integrated circuit according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of another first enhanced structure in an integrated circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a second enhanced structure in an integrated circuit according to an embodiment of the present application.
  • FIG. 5 is a partially enlarged schematic diagram of an integrated circuit according to an embodiment of the present application.
  • FIG. 6 is a partially enlarged schematic diagram of an integrated circuit according to another embodiment of the present application.
  • This application provides an interconnect structure of an integrated circuit, and the integrated circuit may be one or more of a microprocessor (CPU) integrated circuit, a memory integrated circuit, and a switching power supply integrated circuit.
  • the integrated circuit may be one or more of a microprocessor (CPU) integrated circuit, a memory integrated circuit, and a switching power supply integrated circuit.
  • the integrated circuit 100 includes a substrate 10 and an integrated circuit interconnection structure formed on the substrate 10.
  • the integrated circuit interconnection structure includes an interconnect structure 20 and a first reinforcement structure 30.
  • the substrate 10 has a plurality of microelectronic structures.
  • the microelectronic structure includes various microelectronic components such as transistors, resistors, capacitors, and diodes.
  • the interconnect structure 20 is formed on the substrate 10 and is electrically connected to the plurality of microelectronic structures to electrically connect the plurality of microelectronic structures to each other to form the integrated circuit 100 to implement
  • the integrated circuit 100 has one or more functions such as a logic function, a storage function, and an input / output function.
  • the first reinforcement structure 30 and the interconnect structure 20 are nested with each other to increase the mechanical strength and reliability of the integrated circuit 100 through the first reinforcement structure 30.
  • the substrate 10 may be a semiconductor substrate.
  • the semiconductor substrate 10 may be an element type semiconductor, such as a silicon substrate, a germanium substrate, or the like; or the semiconductor substrate may be a compound type semiconductor, such as silicon carbide, arsenic, indium arsenide, and indium phosphide.
  • the semiconductor substrate 10 is a silicon substrate.
  • the microelectronic structure is formed on the substrate 10 by a process such as etching, ion implantation or epitaxial growth on the substrate 10.
  • the interconnect structure 20 includes a plurality of stacked wiring layers 21 and a dielectric layer 22 disposed between two adjacent wiring layers 21.
  • Each of the wiring layers 21 includes a plurality of spaced metal traces 211 and an insulation medium 212 filled in a gap between the plurality of metal traces 211.
  • the two metal traces 211 do not cross, the two metal traces 211 are spaced apart.
  • the two metal traces 211 are spaced apart; or when one end of two adjacent metal traces 211 are connected to each other, However, there is a gap between two positions of the two metal traces 211 except one end connected.
  • the two metal traces 211 are spaced apart.
  • the wiring layer 21 of the integrated circuit 100 has seven layers, and the seven wiring layers 21 are sequentially stacked on the substrate 10.
  • the metal trace 211 in the wiring layer 21 closest to the substrate 10 is electrically connected to the microelectronic structure in the substrate 10 through the through hole 213.
  • the metal traces 211 in each of the wiring layers are also electrically connected through vias 213, so that different microelectronic structures are electrically connected through the metal traces 211 and vias of each layer, The required integrated circuit 100 is obtained.
  • the metal trace 211 plays a role of interconnecting different microelectronic structures, that is, the metal trace 211 is an interconnection line in the integrated circuit interconnection structure.
  • the metal trace 211 and the through hole 213 may be copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), silver (Ag), gold (Au), ruthenium (Ru), nickel (Ni ) And other metals or alloys thereof. Materials of the metal wiring 211 and the through hole 213 may be the same or different.
  • the metal trace 211 is a copper wire
  • the through hole 213 is a Cu through hole.
  • the metal trace 211 is a copper wire
  • the through hole 213 is a Co through hole.
  • the insulation medium 212 is filled in a gap of the metal traces 211 disposed at intervals, so that the metal traces 211 are spaced apart.
  • the insulating medium 212 may be a common dielectric material such as SiO 2 , or a low-k material (low-k; LK) or an ultra-low-k material; ULK) or ultra-low dielectric constant material (extreme low-K; ELK) to reduce the parasitic capacitance between metal lines and the interconnection line delay of the circuit.
  • the material of the insulating medium 212 may be the same or different, so as to meet the parasitic capacitance, mechanical strength, and reliability of the circuit to the integrated circuit interconnection structure. Many requirements.
  • the ordinary dielectric constant material is a dielectric material with a dielectric constant of 3.9 or more;
  • the low dielectric constant material is a dielectric material with a dielectric constant less than 3.9;
  • the ultra-low dielectric constant material is a dielectric material A dielectric material having a constant less than 2.9;
  • the extremely low dielectric constant material is a dielectric material having a dielectric constant lower than 2.6.
  • the first reinforcing structure 30 includes a plurality of auxiliary traces 31 and a plurality of auxiliary vias 32.
  • a plurality of the auxiliary traces 31 are distributed on three or more of the wiring layers 21, and the auxiliary traces 31 in each of the wiring layers 21 and the metal traces 211 are spaced apart from each other.
  • a plurality of the auxiliary through-holes 32 are distributed in two or more adjacent dielectric layers 22.
  • the auxiliary through-holes 32 in each dielectric layer 22 are connected to the auxiliary traces 31 on the wiring layer 21 on both sides of the dielectric layer 22.
  • the auxiliary trace 31 is not electrically connected to any structure, and has no signal transmission effect.
  • the auxiliary through-hole 32 is only used to connect the auxiliary trace 31 without any signal transmission effect.
  • the auxiliary trace 31 is disposed between the gaps of the adjacent metal traces 211 in the wiring layer 21.
  • the uniformity of the process in the manufacturing process of the interconnect can be improved, and the damage caused by the different surrounding environments can be reduced
  • the electrical performance of the interconnect lines is different; on the other hand, the mechanical strength and reliability of the integrated circuit interconnect structure can also be improved by inserting the auxiliary trace 31.
  • the auxiliary through hole 32 is filled with a filling material 322.
  • the filling material 322 is a metal material.
  • the auxiliary through-holes 32 are connected to the auxiliary traces 31 in the wiring layer 21 on both sides of the dielectric layer 22.
  • the auxiliary through hole 32 is provided in the dielectric layer 22, which can increase the mechanical strength of the dielectric layer 22, so that the dielectric layer 22 is not easily cracked.
  • the auxiliary through-holes 32 can also prevent the cracks from extending, further increasing the reliability of the integrated circuit interconnect structure.
  • the first reinforcing structure 30 by connecting the auxiliary through-holes 32 in each dielectric layer 22 to the auxiliary traces 31 in the wiring layer 21 on both sides of the dielectric layer 22, the first reinforcing structure 30
  • the auxiliary wires 31 and the auxiliary through-holes 32 are integrated to ensure that the first reinforcing structure 30 can provide better mechanical strength.
  • the auxiliary wiring 31 and the filling material in the auxiliary through-hole 32 of the first reinforcement structure 30 are the same material. Therefore, in some embodiments, when the first reinforcement structure 30 is obtained, , The auxiliary trace 31 and the filling material 322 can be formed at the same time, thereby simplifying the manufacturing process.
  • the filling material 322 of the auxiliary through-hole is the same as the material of the auxiliary wiring 31 connected thereto, so that the combining effect between the auxiliary through-hole 32 and the auxiliary wiring 31 is better, so as to obtain more stability.
  • the first reinforcement structure 30 is the same as the material of the auxiliary wiring 31 connected thereto, so that the combining effect between the auxiliary through-hole 32 and the auxiliary wiring 31 is better, so as to obtain more stability.
  • the auxiliary through holes 32 located in the adjacent dielectric layers 22 are aligned or partially aligned in a direction perpendicular to the wiring layer 21.
  • the projections of the auxiliary through-holes 32 of the first reinforcement structure 30 located in different wiring layers 21 on the substrate 10 perpendicular to or in the direction of the wiring layer 21 overlap or partially overlap to prevent cracks from passing through the auxiliary through-holes.
  • the staggered positions extend between different wiring layers 21 and dielectric layers 22, thereby reducing the reliability risk of the interconnection structure of the integrated circuit 100.
  • the extension directions of the auxiliary traces 31 in the two adjacent wiring layers 21 are perpendicular, and the auxiliary through-holes 32 are located in the adjacent two layers of the wiring layers 21.
  • the positions where the auxiliary traces 31 overlap are described.
  • the extension directions of the auxiliary traces 31 in the two adjacent wiring layers 21 are perpendicular, and the auxiliary traces 31 and the metal located in the same wiring layer 21 are perpendicular to each other.
  • the extension direction of the trace 211 is the same.
  • the extension directions of the metal traces 211 in the adjacent wiring layers 21 are perpendicular to meet the requirements of the design rules.
  • the extension directions of the auxiliary traces 31 and the metal traces 211 in two adjacent wiring layers 21 are set to be the same, so that the The environment where the metal wiring 211 and the auxiliary wiring 31 are located is the same as much as possible, which can improve the process uniformity in the manufacturing process of the metal wiring 211 and the auxiliary wiring 31 and reduce the causes caused by the difference in the surrounding environment.
  • the electrical performance of the metal trace 31 is different.
  • the extending directions of the metal traces 211 and the auxiliary traces 31 in the two adjacent wiring layers 21 are perpendicular, so that the traces in the integrated circuit interconnection structure can meet the connection to the integrated circuit 100. The needs of microelectronic structures.
  • the plurality of auxiliary traces 31 are distributed in four adjacent wiring layers 21, and the four wiring layers 21 are respectively The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer.
  • Each of the wiring layers 21 is provided with one auxiliary trace 31.
  • the extension directions of the auxiliary traces 31 in two adjacent wiring layers 21 are perpendicular to each other.
  • the auxiliary traces extending in the same direction in different wiring layers 21 overlap or partially overlap in a direction perpendicular to the wiring layer 21.
  • the auxiliary wirings 31 in the first wiring layer and the third wiring layer overlap in a direction perpendicular to the wiring layer 21; the auxiliary wirings 31 in the second wiring layer and the fourth wiring layer 21c are at The directions perpendicular to the wiring layer 21 overlap, so that the overlapping positions of the auxiliary traces 31 of the respective wiring layers 21 overlap in the direction perpendicular to the wiring layer 21.
  • the auxiliary through-holes 32 are located in the dielectric layer between the two adjacent wiring layers 21, and are located at the overlapping positions of the auxiliary traces 31 in the adjacent two wiring layers 21, so that they are located in the adjacent dielectric layer 22.
  • the auxiliary through-holes 32 are aligned or partially aligned in the direction of the vertical wiring layer 21. .
  • the present application provides the first reinforcement structure 30 according to another embodiment, which is different from the embodiment shown in FIG. 2 in that the first wiring layer and the third wiring layer are respectively Two auxiliary traces 31 are provided, and three auxiliary traces are provided in the second wiring layer and the fourth wiring layer. As a result, the dielectric layer between each two adjacent wiring layers is provided with six auxiliary through holes 32.
  • the number of the auxiliary traces 211 in each wiring layer 21 may be changed according to an actual situation, and the number of layers of the auxiliary traces 211 of the first reinforcing structure 20 It may also be changed, and when the number and the number of layers of the auxiliary traces 211 are changed, the number of the auxiliary vias 32 may also be changed.
  • the integrated circuit 100 of the present application may further include a second enhancement structure 40.
  • the second reinforcing structure 40 includes two layers of auxiliary traces 41 and auxiliary through holes 42 connecting the two layers of auxiliary traces 41.
  • the auxiliary traces 41 of each layer are located in one layer of the wiring layer 21 and spaced from and insulated from the metal traces 211 and the auxiliary traces of the first reinforcement structure 30 in the wiring layer 21.
  • the second reinforcement structure 40 is arranged in an area of the interconnect structure of the integrated circuit 100 where the space is not sufficient to arrange the first reinforcement structure 30.
  • the second reinforcement structure 40 By arranging the second reinforcement structure 40 at a location where the first reinforcement structure 30 is not sufficient, the density of the auxiliary traces in the wiring layer 21 and the density of the auxiliary vias in the dielectric layer 22 are increased.
  • the mechanical strength of the interconnection structure of the integrated circuit 100 can be further enhanced to prevent the generation and extension of cracks.
  • the interconnect structure of the integrated circuit 100 may further include a third reinforcing structure 50, and the third reinforcing structure 50 is an independent auxiliary wiring.
  • the third reinforcing structure 50 is disposed in an area of the interconnect structure of the integrated circuit 100 where the first reinforcing structure 30 and the second reinforcing structure 40 are not sufficient.
  • the third reinforcing structure 50 is located in the wiring layer 21, and is connected to the metal wiring 211 in the wiring layer 21, the auxiliary wiring of the first reinforcing structure 30, and the auxiliary of the second reinforcing structure 40.
  • the traces are isolated from each other.
  • the third reinforcement structure 50 is disposed in the metal layer in the wiring layer 21.
  • the mechanical strength of the insulating medium 212 in the wiring layer 21 can be further enhanced, and the uniformity of the process in the manufacturing process of the interconnection line can be improved, and the interaction caused by the difference in the surrounding environment can be reduced. Difference in wiring electrical performance. .
  • materials of the auxiliary trace 31 and the metal trace 211 in the same wiring layer 21 may be the same or different.
  • the metal traces 211 and the auxiliary traces 31 in the same wiring layer 21 are made of the same material, and the metal traces 211 in the same wiring layer 21 are the same. It can be obtained through the same process as the auxiliary wiring 31, and the process is simple.
  • the specific manufacturing process of the metal trace 211 and the auxiliary trace 31 of the wiring layer 21 is the prior art, and details are not described herein.
  • the metal traces 211 and the auxiliary traces 31 in the same wiring layer 21 are made of different materials.
  • the metal wiring 211 is mainly used for signal transmission to electrically connect different microelectronic structures, a material with better electrical performance is used to form the metal wiring 211; and one of the main functions of the auxiliary wiring 31 The purpose is to enhance the mechanical strength of the interconnect structure of the integrated circuit 100. Therefore, a material with higher mechanical strength is used to form the auxiliary wiring 31.
  • the size of the metal trace 211 and the auxiliary trace 31 in each layer of the wiring layer 21, and the distance between the auxiliary trace 31 and the adjacent metal trace 211 all meet the requirements of the design rules for integrated circuit interconnects.
  • the dielectric layer 22 includes an etch barrier layer 23, and the etch barrier layer 23 is disposed on a side where the dielectric layer 22 and the wiring layer 21 are bonded.
  • the etch stop layer 23 the processing accuracy of the interconnect structure of the integrated circuit 100 can be ensured, so that the integrated circuit 100 has better quality.
  • a diffusion barrier layer 24 is deposited on the inner wall of the through hole 213 and the inner wall of the auxiliary through hole 32, so as to avoid metal materials in the through hole 213 and the auxiliary through hole 32. Diffusion into the insulating medium causes leakage and circuit failure.
  • the material of the diffusion barrier layer 24 is correspondingly disposed with respect to the metal material to obtain a better diffusion barrier effect.
  • the material of the diffusion barrier layer may be TaN / Ta, or TaN / Co, and the like; when the filled metal material is Co, the material of the diffusion barrier layer may be TiN
  • the diffusion barrier layer 24 may also be deposited on the surfaces of the metal wiring 211 and the auxiliary wiring 31, so as to prevent the metal material of the metal wiring 211 or the auxiliary wiring 31 from diffusing to the The insulation medium 212 and 22 cause leakage and circuit failure, thereby ensuring the quality of the integrated circuit 100.
  • the present application reduces the dielectric layer 22 and the insulating medium 212 of the interconnection structure of the integrated circuit 100 by providing the first reinforcement structure 30, the second reinforcement structure 40, and the third reinforcement structure 50 in the integrated circuit interconnection structure of the integrated circuit 100. Internal cracks are generated and extended to ensure the mechanical performance and reliability of the interconnect structure of the integrated circuit 100.
  • the auxiliary through-holes 32 in the first reinforcing structure 30 are aligned or partially aligned in a direction perpendicular to the wiring layer 21 to prevent cracks from extending through the misaligned auxiliary through-holes in each wiring layer 21.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The present application provides an integrated circuit and an interconnection structure thereof. The interconnection structure of the integrated circuit comprises an inner connection line structure, a first reinforcement structure, a second reinforcement structure, and a third reinforcement structure; the first reinforcement structure, the second reinforcement structure, and the third reinforcement structure are used for enhancing the mechanical strength and reliability of the interconnection structure of the integrated circuit, so as to avoid generation and extension of cracks in an insulating medium of the interconnection structure of the integrated circuit, thereby ensuring the quality of the interconnection structure of the integrated circuit as well as the quality of the integrated circuit.

Description

集成电路及其互连结构Integrated circuit and its interconnection structure 技术领域Technical field

本申请涉及集成电路，尤其涉及一种不易形成裂纹缺陷的集成电路互连结构。The present application relates to integrated circuits, and in particular, to an integrated circuit interconnect structure that is not prone to crack defects.

背景技术Background technique

集成电路制造过程中会受到各种机械应力、热应力或者其它应力的作用，使得集成电路互连结构内的介质层容易开裂。并且，由于一些集成电路互连结构的介质层采用了机械性能较差的材料，以及各介质层的材料不同而使得各介质层之间的粘附力较差等原因，使得所述集成电路互连结构会更容易开裂，且开裂产生的裂纹容易进行延伸，从而影响所述集成电路互连结构的品质。During the manufacturing process of integrated circuits, various mechanical stresses, thermal stresses, or other stresses are applied, which makes the dielectric layer in the integrated circuit interconnect structure easy to crack. In addition, because the dielectric layers of some integrated circuit interconnection structures use materials with poor mechanical properties, and the materials of each dielectric layer are different, the adhesion between the dielectric layers is poor, etc., which makes the integrated circuits mutually The connection structure is more likely to crack, and the cracks generated by the crack are easy to extend, thereby affecting the quality of the integrated circuit interconnection structure.

发明内容Summary of the invention

本申请的提供一种不容易产生开裂，且开裂产生的裂纹不易进行延伸的集成电路及其互连结构。The present application provides an integrated circuit and an interconnection structure thereof that are not prone to cracking, and the cracks generated by cracking are not easy to extend.

所述集成电路互连结构包括内连线结构及第一增强结构。所述内连线结构包括三层或三层以上层叠设置的布线层以及设于相邻两层布线层之间的介质层，所述介质层用于将所述相邻的两层布线层进行绝缘；每层所述布线层包括多条间隔设置的金属走线及设于间隔设置的所述金属走线的间隙之间的绝缘介质。所述第一增强结构，包括多条辅助走线及多个辅助通孔，多条所述辅助走线分布于相邻的三个或三个以上的所述布线层，同一所述布线层内的所述辅助走线与所述金属走线间隔绝缘设置，且所述辅助走线与所述金属走线的延伸方向相同；多个所述辅助通孔分布于至少两层相邻的所述介质层；每个介质层上的所述辅助通孔连接位于所述介质层两侧的所述布线层上的所述辅助走线；位于相邻的所述介质层的所述辅助通孔在垂直于所述布线层的方向上对齐或者部分对齐。其中，所述辅助走线不与任何结构进行电连接，不具有任何的信号传输作用；所述辅助通孔仅用于连接所述辅助走线，无任何的信号传输作用。The integrated circuit interconnection structure includes an interconnect structure and a first reinforcement structure. The interconnect structure includes three or more layers of wiring layers stacked on top of each other and a dielectric layer provided between two adjacent wiring layers. The dielectric layer is used to carry out the two adjacent wiring layers. Insulation; each layer of the wiring layer includes a plurality of spaced-apart metal traces and an insulating medium provided between the spaced-apart metal traces. The first reinforcement structure includes a plurality of auxiliary traces and a plurality of auxiliary through holes, and the plurality of auxiliary traces are distributed in three or more adjacent wiring layers, and are in the same wiring layer. The auxiliary traces are insulated from the metal traces, and the auxiliary traces extend in the same direction as the metal traces; a plurality of the auxiliary vias are distributed in at least two adjacent layers of the A dielectric layer; the auxiliary vias on each dielectric layer are connected to the auxiliary traces on the wiring layer on both sides of the dielectric layer; the auxiliary vias on adjacent dielectric layers are in Aligned or partially aligned in a direction perpendicular to the wiring layer. The auxiliary wiring is not electrically connected to any structure and does not have any signal transmission function; the auxiliary through-hole is only used to connect the auxiliary wiring and has no signal transmission function.

通过在所述集成电路互连结构中设置第一增强结构，以增强所述集成电路的强度，避免集成电路互连结构内裂纹的产生及延伸。具体的，所述第一增强结构的所述辅助走线与所述内连线结构的金属走线同层并间隔设置，即在所述布线层中未布设有所述金属走线的区域设置所述辅助走线，相当于在集成电路的所述绝缘介质中插入强度较高的所述辅助走线，从而增强所述绝缘介质的强度，减少所述绝缘介质中裂纹的产生。并且，通过在所述绝缘介质中插入所述辅助走线，能够阻挡裂纹的延伸。进一步的，通过在所述介质层设置所述辅助通孔，以增加所述介质层的强度，使得所述介质层也不容易产生裂纹，从而进一步增加所述集成电路的强度。并且，通过所述辅助通孔也能够阻挡裂纹的延伸。将每个介质层上的所述辅助通孔连接位于所述介质层两侧的所述布线层上的所述辅助走线，从而使得所述第一增强结构的辅助走线及辅助通孔形成一体，且跨越多个布线层，使得所述第一增强能够进一步提升集成电路互连结构的机械强度及可靠性。进一步的，位于相邻的介质层的所述辅助通孔对齐或者部分对齐，避免了所述裂缝从辅助通孔的错开位置在各个不同 的布线层及介质层之间的延伸。By providing a first reinforcement structure in the integrated circuit interconnection structure, the strength of the integrated circuit is enhanced, and the generation and extension of cracks in the integrated circuit interconnection structure are avoided. Specifically, the auxiliary traces of the first reinforcement structure and the metal traces of the interconnect structure are disposed on the same layer and spaced apart, that is, the areas where the metal traces are not arranged in the wiring layer are provided. The auxiliary wiring is equivalent to inserting the auxiliary wiring with high strength into the insulating medium of the integrated circuit, thereby enhancing the strength of the insulating medium and reducing the occurrence of cracks in the insulating medium. In addition, by inserting the auxiliary trace into the insulating medium, it is possible to block the crack from extending. Further, the auxiliary through hole is provided in the dielectric layer to increase the strength of the dielectric layer, so that the dielectric layer is not prone to cracks, thereby further increasing the strength of the integrated circuit. In addition, crack propagation can be blocked by the auxiliary through hole. Connecting the auxiliary vias on each dielectric layer to the auxiliary traces on the wiring layer on both sides of the dielectric layer, so that the auxiliary traces and auxiliary vias of the first reinforcement structure are formed It is integrated and spans multiple wiring layers, so that the first enhancement can further improve the mechanical strength and reliability of the integrated circuit interconnect structure. Further, the auxiliary through-holes located in adjacent dielectric layers are aligned or partially aligned, thereby avoiding the extension of the crack from the misaligned positions of the auxiliary through-holes between the different wiring layers and the dielectric layer.

本申请的一实施例中，相邻两层所述布线层内的所述辅助走线的延伸方向相互交叉，所述辅助通孔位于相邻两层所述布线层内的辅助走线交叠的位置。本申请中同一所述布线层内的辅助走线与所述金属走线的延伸方向相同。具体的，本申请的相邻的两个布线层内的所述辅助走线延伸方向相互垂直，且相邻的两个布线层内的所述金属走线的延伸方向也相互垂直。相邻的两个所述布线层内的所述辅助走线与所述金属走线的延伸方向相同，从而使得每一所述布线层内的所述金属走线与所述辅助走线所处的环境尽量相同，可以提升所述金属走线与所述辅助走线的制造过程中工艺的均匀性，降低由于周围环境的不同而导致的所述金属走线电学性能的差异。进一步的，通过将相邻的两个所述布线层内的金属走线及辅助走线的延伸方向垂直，从而使得所述集成电路的互连结构内的走线能够满足连接集成电路内的微电子结构的需求。In an embodiment of the present application, the extending directions of the auxiliary traces in the two adjacent wiring layers intersect with each other, and the auxiliary vias are located in the auxiliary traces of the two adjacent wiring layers overlapping. s position. In the present application, the auxiliary traces in the same wiring layer and the metal traces extend in the same direction. Specifically, the extension directions of the auxiliary traces in two adjacent wiring layers of the present application are perpendicular to each other, and the extension directions of the metal traces in the two adjacent wiring layers are also perpendicular to each other. The extension directions of the auxiliary traces and the metal traces in two adjacent wiring layers are the same, so that the metal traces and the auxiliary traces in each of the wiring layers are located. The environment of the metal trace is as much as possible, which can improve the uniformity of the process in the manufacturing process of the metal trace and the auxiliary trace, and reduce the difference in electrical performance of the metal trace due to the different surrounding environments. Further, the extending directions of the metal traces and the auxiliary traces in two adjacent wiring layers are perpendicular, so that the traces in the interconnection structure of the integrated circuit can meet the micro-connections in the integrated circuit. Demand for electronic structures.

进一步的，所述集成电路互连结构还包括第二增强结构，所述第二增强结构包括所述第二增强结构包括分设于相邻的两个所述布线层的辅助走线，以及位于相邻的两个布线层之间的介质层的辅助通孔，所述辅助通孔连接两个相邻的所述布线层内的辅助走线，所述第三增强结构的辅助走线与所述布线层内的金属走线以及所述第一增强结构的辅助走线绝缘。Further, the integrated circuit interconnection structure further includes a second reinforcement structure, and the second reinforcement structure includes the second reinforcement structure including auxiliary traces separated from two adjacent wiring layers, and located at a phase opposite to each other. An auxiliary through hole of a dielectric layer between two adjacent wiring layers, the auxiliary through hole connecting two adjacent auxiliary wirings in the wiring layer, and the auxiliary wiring of the third reinforcing structure and the auxiliary wiring The metal traces in the wiring layer and the auxiliary traces of the first reinforcement structure are insulated.

通过在不足够布设所述第一增强结构的位置布设所述第二增强结构，增加所述布线层内的辅助走线的密度以及所述介质层的辅助通孔的密度，从而进一步的增强所述集成电路互连结构的强度，并防止裂纹的延伸。By arranging the second reinforcement structure at a location where the first reinforcement structure is not sufficient, the density of the auxiliary traces in the wiring layer and the density of the auxiliary through-holes of the dielectric layer are further increased, thereby further enhancing the Describes the strength of the integrated circuit interconnect structure and prevents crack propagation.

进一步的，所述集成电路互连结构还包括第三增强结构，所述第三增强结构为独立的辅助走线。所述独立的辅助走线位于所述布线层并与所述布线层内的金属走线及所述第一增强结构的辅助走线间隔并绝缘。Further, the integrated circuit interconnection structure further includes a third enhanced structure, and the third enhanced structure is an independent auxiliary wiring. The independent auxiliary trace is located on the wiring layer and is spaced from and insulated from the metal trace in the wiring layer and the auxiliary trace of the first reinforcement structure.

通过在不足够布设所述第一增强结构及所述第二增强结构的位置布设所述第三增强结构，使得所述第三增强结构设置于所述布线层上的金属走线之间的空隙中，进一步增强所述布线层中的绝缘介质的强度，从而进一步的增强所述集成电路的强度。Arranging the third reinforcement structure at a place where the first reinforcement structure and the second reinforcement structure are not enough, so that the third reinforcement structure is provided in a gap between metal traces on the wiring layer , Further strengthening the strength of the insulating medium in the wiring layer, thereby further strengthening the strength of the integrated circuit.

其中，所述辅助通孔内填充有填充材料。并且，所述辅助通孔的填充材料与其连接的所述辅助走线的材料相同。Wherein, the auxiliary through hole is filled with a filling material. In addition, a filling material of the auxiliary through hole is the same as a material of the auxiliary trace connected thereto.

本申请中，将所述辅助通孔内的填充材料与其连接的辅助走线的材料相同，在一些制作过程中能够同时形成所述辅助走线以及填充所述填充材料，从而简化制程。并且，所述辅助通孔的填充材料与其连接的所述辅助走线的材料相同，使得所述辅助通孔与所述辅助走线之间的结合效果更好，以得到更加稳固的第一增强结构。In this application, the filling material in the auxiliary through hole is the same as the material of the auxiliary trace connected to it, and the auxiliary trace and the filling material can be formed at the same time in some manufacturing processes, thereby simplifying the manufacturing process. In addition, the filling material of the auxiliary through hole is the same as the material of the auxiliary wiring connected to it, so that the combining effect between the auxiliary through hole and the auxiliary wiring is better, so as to obtain a more stable first reinforcement. structure.

进一步的，所述辅助通孔的内壁设有扩散阻挡层。从而避免所述辅助通孔内的填充材料扩散至所述介质层中导致漏电及电路失效，以保证所述集成电路的品质。Further, an inner wall of the auxiliary through hole is provided with a diffusion barrier layer. This prevents the filling material in the auxiliary through hole from diffusing into the dielectric layer and causes leakage and circuit failure, thereby ensuring the quality of the integrated circuit.

进一步的，位于同一所述布线层的所述金属走线与所述辅助走线的材料可以相同，也可以不同。Further, materials of the metal traces and the auxiliary traces located in the same wiring layer may be the same or different.

当位于同一所述布线层的所述金属走线与所述辅助走线的材料相同时，同一所述布线层的所述金属走线与所述辅助走线能够通过同一制程得到，制程简单；而当位于同一所述布线层的所述金属走线与所述辅助走线的材料不相同时，对于所述金属走线能够选用导电 性能较好的材料，对于所述辅助走线能够选用机械性能较好的材料，以同时兼顾对集成电路互连结构的电学性能和机械性能方面的要求。When the materials of the metal wiring and the auxiliary wiring in the same wiring layer are the same, the metal wiring and the auxiliary wiring in the same wiring layer can be obtained through the same process, and the manufacturing process is simple; When the materials of the metal traces and the auxiliary traces in the same wiring layer are different, a material with better conductivity can be used for the metal traces, and a mechanical can be selected for the auxiliary traces. A material with better performance to take into account both the electrical and mechanical properties of the integrated circuit interconnect structure.

进一步的，所述介质层包括刻蚀阻挡层，所述刻蚀阻挡层位于所述介质层与所述布线层贴合的一面。通过所述蚀刻阻挡层，能够保证所述集成电路互连结构的加工精度，使得所述集成电路具有较好的品质。Further, the dielectric layer includes an etch barrier layer, and the etch barrier layer is located on a side where the dielectric layer and the wiring layer are bonded. Through the etch barrier layer, the processing accuracy of the integrated circuit interconnect structure can be guaranteed, so that the integrated circuit has better quality.

进一步的，所述金属走线、辅助走线的表面设有扩散阻挡层。从而防止所述金属走线、所述辅助走线的填充材料扩散至所述绝缘介质中而导致漏电及电路失效，从而保证所述集成电路的品质。Further, a surface of the metal wiring and the auxiliary wiring is provided with a diffusion barrier layer. As a result, the metal wiring and the filling material of the auxiliary wiring are prevented from diffusing into the insulating medium to cause leakage and circuit failure, thereby ensuring the quality of the integrated circuit.

进一步的，形成所述介质层的材料及所述布线层内的绝缘介质的材料包括低介电常数材料或超低介电常数材料或极低介电常数材料。其中，所述低介电常数材料为介电常数小于3.9的材料，所述超低介电常数材料的介电常数小于2.9，所述极低介电常数材料为介电常数低于2.6的材料。各个所述介质层的材料可以相同也可以不同。Further, a material for forming the dielectric layer and a material for the insulating medium in the wiring layer include a low dielectric constant material, an ultra-low dielectric constant material, or an extremely low dielectric constant material. Wherein, the low dielectric constant material is a material with a dielectric constant less than 3.9, the ultra low dielectric constant material is with a dielectric constant less than 2.9, and the very low dielectric constant material is a material with a dielectric constant less than 2.6 . The material of each of the dielectric layers may be the same or different.

将低介电常数材料或超低介电常数材料或极低介电常数材料作为所述介质层的材料，能够减小金属走线之间、金属走线与辅助走线之间的寄生电容，从而达到降低电路互连线延迟的目的。可以理解的是，根据不同的介质层的厚度、位于所述介质层内的过孔之间的距离以及位于所述布线层内的金属走线之间的距离的不同等情况，所述介质层以及所述布线层内的绝缘介质的材料也可以不同。例如，当某一布线层内的所述金属走线的密度较大，则可以使用介电常数较低的绝缘介质材料，从而减小金属走线之间的寄生电容；当某一布线层内的所述金属走线的密度较小时，则可以使用介电常数较高的绝缘介质材料。The use of a low-dielectric constant material or an ultra-low-dielectric constant material or an extremely low-dielectric constant material as the material of the dielectric layer can reduce the parasitic capacitance between metal traces and between metal traces and auxiliary traces. Thus, the purpose of reducing the delay of the circuit interconnection line is achieved. It can be understood that, according to different thicknesses of different dielectric layers, distances between vias located in the dielectric layer, and distances between metal traces located in the wiring layer, etc., the dielectric layer The material of the insulating medium in the wiring layer may be different. For example, when the density of the metal traces in a certain wiring layer is large, an insulating dielectric material with a lower dielectric constant may be used, thereby reducing the parasitic capacitance between the metal traces; When the density of the metal traces is small, an insulating dielectric material with a higher dielectric constant may be used.

其中，每层所述布线层中的所述辅助走线的尺寸，以及辅助走线与同其相邻的所述金属走线或所述辅助走线之间间隙大小均满足设计规则的要求。The size of the auxiliary trace in each of the wiring layers and the gap between the auxiliary trace and the metal trace or the auxiliary trace adjacent to the auxiliary trace meet the requirements of the design rule.

所述集成电路包括基板及形成于所述基板上的所述集成电路互连结构。由于所述集成电路互连结构不易开裂且开裂产生的裂纹不易进行延伸，使得所述集成电路互连结构具有较好的机械强度及可靠性。而所述集成电路互连结构为所述集成电路的一部分，从而使得所述集成电路具有较好的机械强度及可靠性。The integrated circuit includes a substrate and the integrated circuit interconnection structure formed on the substrate. Because the integrated circuit interconnect structure is not easy to crack and the cracks generated by the crack are not easy to extend, the integrated circuit interconnect structure has better mechanical strength and reliability. The integrated circuit interconnection structure is a part of the integrated circuit, so that the integrated circuit has better mechanical strength and reliability.

所述基板具有多个微电子结构，所述集成电路互连结构与多个所述微电子结构电连接，以将所述多个微电子结构相互之间电连接从而形成所述集成电路，以实现所述集成电路的逻辑功能、存储功能、输入/输出功能等一种或者几种功能。The substrate has a plurality of microelectronic structures, and the integrated circuit interconnection structure is electrically connected to the plurality of microelectronic structures, so as to electrically connect the plurality of microelectronic structures to each other to form the integrated circuit. It implements one or more functions such as logic function, storage function, input / output function of the integrated circuit.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without paying creative work.

图1是本申请的实施例的集成电路的截面示意图；1 is a schematic cross-sectional view of an integrated circuit according to an embodiment of the present application;

图2是本申请的实施例的集成电路中第一增强结构的结构示意图；2 is a schematic structural diagram of a first enhanced structure in an integrated circuit according to an embodiment of the present application;

图3是本申请的实施例的集成电路中另一种第一增强结构的结构示意图；3 is a schematic structural diagram of another first enhanced structure in an integrated circuit according to an embodiment of the present application;

图4是本申请的实施例的集成电路中第二增强结构的结构示意图；4 is a schematic structural diagram of a second enhanced structure in an integrated circuit according to an embodiment of the present application;

图5是本申请的一实施例的集成电路中局部放大示意图；5 is a partially enlarged schematic diagram of an integrated circuit according to an embodiment of the present application;

图6是本申请的另一实施例的集成电路中局部放大示意图。FIG. 6 is a partially enlarged schematic diagram of an integrated circuit according to another embodiment of the present application.

具体实施方式detailed description

下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

本申请提供一种集成电路的互连结构，所述集成电路可以为微处理器(CPU)集成电路、存储器集成电路、开关电源集成电路等一种或者几种。This application provides an interconnect structure of an integrated circuit, and the integrated circuit may be one or more of a microprocessor (CPU) integrated circuit, a memory integrated circuit, and a switching power supply integrated circuit.

请参阅图1，所述集成电路100包括基板10及形成于所述基板10上的集成电路互连结构。所述集成电路互连结构包括内连线结构20及第一增强结构30。所述基板10具有多个微电子结构。其中，所述微电子结构包括晶体管、电阻、电容、二极管等各种微电子元器件。所述内连线结构20形成于所述基板10上并与所述多个微电子结构电连接，以将所述多个微电子结构相互之间电连接从而形成所述集成电路100，以实现所述集成电路100的逻辑功能、存储功能、输入/输出功能等一种或者几种功能。所述第一增强结构30与所述内连线结构20相互嵌套，以通过所述第一增强结构30增加所述集成电路100的机械强度及可靠性。Referring to FIG. 1, the integrated circuit 100 includes a substrate 10 and an integrated circuit interconnection structure formed on the substrate 10. The integrated circuit interconnection structure includes an interconnect structure 20 and a first reinforcement structure 30. The substrate 10 has a plurality of microelectronic structures. The microelectronic structure includes various microelectronic components such as transistors, resistors, capacitors, and diodes. The interconnect structure 20 is formed on the substrate 10 and is electrically connected to the plurality of microelectronic structures to electrically connect the plurality of microelectronic structures to each other to form the integrated circuit 100 to implement The integrated circuit 100 has one or more functions such as a logic function, a storage function, and an input / output function. The first reinforcement structure 30 and the interconnect structure 20 are nested with each other to increase the mechanical strength and reliability of the integrated circuit 100 through the first reinforcement structure 30.

具体的，所述基板10可以为半导体基板。其中，半导体基板10又可以为元素型的半导体，如硅基板、锗基板等；或者，所述半导体基板可以为化合物型的半导体，如碳化硅、砷化稼、砷化铟以及磷化铟等。本实施例中，所述半导体基板10为硅基板。通过在对所述基板10进行刻蚀、离子注入或者外延成长等工艺在所述基板10上形成所述微电子结构。Specifically, the substrate 10 may be a semiconductor substrate. The semiconductor substrate 10 may be an element type semiconductor, such as a silicon substrate, a germanium substrate, or the like; or the semiconductor substrate may be a compound type semiconductor, such as silicon carbide, arsenic, indium arsenide, and indium phosphide. . In this embodiment, the semiconductor substrate 10 is a silicon substrate. The microelectronic structure is formed on the substrate 10 by a process such as etching, ion implantation or epitaxial growth on the substrate 10.

所述内连线结构20包括多层层叠设置的布线层21及以及设于相邻两层布线层21之间的介质层22。每层所述布线层21包括多条间隔设置的金属走线211以及填充于多条金属走线211的间隙内的绝缘介质212。需要注意是，本申请中，两条金属走线211不存在交叉时，两条金属走线211间隔设置。例如当两条金属走线211平行设置，且两条金属走线211不存在电连接，则两条金属走线211间隔设置；或者，当相邻的两条金属走线211的一端相互连接，但两条金属走线211除连接的一端外，其它位置之间均具有间隙，同样认为该两条金属走线211间隔设置。本实施例中，所述集成电路100的布线层21有七层，七层所述布线层21依次层叠于所述基板10上。其中，最靠近所述基板10的所述布线层21内的金属走线211通过通孔213与所述基板10内的微电子结构进行电连接。并且，各个所述布线层内的所述金属走线211之间也通过通孔213进行电连接，从而通过各层的所述金属走线211及通孔将不同的微电子结构进行电连接，得到所需的集成电路100。所述金属走线211起到将不同的微电子结构进行互连的作用，即所述金属走线211为所述集成电路互连结构中的互连线。所述金属走线211及通孔213可以为铜(Cu)、铝(Al)、钨(W)、钴(Co)、银(Ag)、金(Au)、钌(Ru)、镍(Ni)等各种金属或者其合金。所述金属走线211与所述通孔213的材料可以相同也可以不同。本实施例中，所述金属走线211为铜线，通孔213为Cu通孔。或者，在其它实施例中，金属走线211为铜线，通孔213为Co通孔。The interconnect structure 20 includes a plurality of stacked wiring layers 21 and a dielectric layer 22 disposed between two adjacent wiring layers 21. Each of the wiring layers 21 includes a plurality of spaced metal traces 211 and an insulation medium 212 filled in a gap between the plurality of metal traces 211. It should be noted that in the present application, when the two metal traces 211 do not cross, the two metal traces 211 are spaced apart. For example, when two metal traces 211 are arranged in parallel and there is no electrical connection between the two metal traces 211, the two metal traces 211 are spaced apart; or when one end of two adjacent metal traces 211 are connected to each other, However, there is a gap between two positions of the two metal traces 211 except one end connected. It is also considered that the two metal traces 211 are spaced apart. In this embodiment, the wiring layer 21 of the integrated circuit 100 has seven layers, and the seven wiring layers 21 are sequentially stacked on the substrate 10. The metal trace 211 in the wiring layer 21 closest to the substrate 10 is electrically connected to the microelectronic structure in the substrate 10 through the through hole 213. In addition, the metal traces 211 in each of the wiring layers are also electrically connected through vias 213, so that different microelectronic structures are electrically connected through the metal traces 211 and vias of each layer, The required integrated circuit 100 is obtained. The metal trace 211 plays a role of interconnecting different microelectronic structures, that is, the metal trace 211 is an interconnection line in the integrated circuit interconnection structure. The metal trace 211 and the through hole 213 may be copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), silver (Ag), gold (Au), ruthenium (Ru), nickel (Ni ) And other metals or alloys thereof. Materials of the metal wiring 211 and the through hole 213 may be the same or different. In this embodiment, the metal trace 211 is a copper wire, and the through hole 213 is a Cu through hole. Alternatively, in other embodiments, the metal trace 211 is a copper wire, and the through hole 213 is a Co through hole.

所述绝缘介质212填充于间隔设置的所述金属走线211的间隙内，从而将所述金属走线211间隔开。本实施例中，所述绝缘介质212可以为如SiO 2等普通介电常数材料，也可以为低介电常数材料(low-k；LK)或超低介电常数材料(ultra low-k；ULK)或极低介电常数材料(extreme low-K；ELK)，以降低金属线之间的寄生电容及电路的互连线延迟。本申请中，对于所述集成电路互连结构的不同位置，所述绝缘介质212的材料可以相同也可以不同，以满足电路对所述集成电路互连结构的寄生电容、机械强度及可靠性等多方面的要求。例如，当所述布线层21内，相邻的金属走线211之间的距离较大时，所述金属走线211之间则可以选用介电常数相对较大的绝缘介质；当相邻的金属走线211之间的距离较小时，则可选用介电常数较小的绝缘介质。其中，所述普通介电常数材料为介电常数在3.9以上的介电材料；所述低介电常数材料为介电常数小于3.9的介电材料；所述超低介电常数材料为介电常数小于2.9的介电材料；所述极低介电常数材料为介电常数低于2.6的介电材料。 The insulation medium 212 is filled in a gap of the metal traces 211 disposed at intervals, so that the metal traces 211 are spaced apart. In this embodiment, the insulating medium 212 may be a common dielectric material such as SiO 2 , or a low-k material (low-k; LK) or an ultra-low-k material; ULK) or ultra-low dielectric constant material (extreme low-K; ELK) to reduce the parasitic capacitance between metal lines and the interconnection line delay of the circuit. In this application, for different positions of the integrated circuit interconnection structure, the material of the insulating medium 212 may be the same or different, so as to meet the parasitic capacitance, mechanical strength, and reliability of the circuit to the integrated circuit interconnection structure. Many requirements. For example, when the distance between adjacent metal traces 211 in the wiring layer 21 is large, an insulation medium with a relatively large dielectric constant may be selected between the metal traces 211; When the distance between the metal traces 211 is small, an insulating medium with a small dielectric constant may be selected. Wherein, the ordinary dielectric constant material is a dielectric material with a dielectric constant of 3.9 or more; the low dielectric constant material is a dielectric material with a dielectric constant less than 3.9; the ultra-low dielectric constant material is a dielectric material A dielectric material having a constant less than 2.9; the extremely low dielectric constant material is a dielectric material having a dielectric constant lower than 2.6.

第一增强结构30包括多条辅助走线(dummy metal)31及多个辅助通孔(dummy via)32。多条所述辅助走线31分布于三个或三个以上的所述布线层21，每个所述布线层21内的所述辅助走线31与所述金属走线211间隔绝缘设置。多个所述辅助通孔32分布于两层或两层以上的相邻的所述介质层22内。每个介质层22内的所述辅助通孔32连接位于所述介质层22两侧的所述布线层21上的所述辅助走线31。其中，所述辅助走线31不与任何结构进行电连接，没有任何的信号传输作用；所述辅助通孔32仅用于连接所述辅助走线31，无任何的信号传输作用。The first reinforcing structure 30 includes a plurality of auxiliary traces 31 and a plurality of auxiliary vias 32. A plurality of the auxiliary traces 31 are distributed on three or more of the wiring layers 21, and the auxiliary traces 31 in each of the wiring layers 21 and the metal traces 211 are spaced apart from each other. A plurality of the auxiliary through-holes 32 are distributed in two or more adjacent dielectric layers 22. The auxiliary through-holes 32 in each dielectric layer 22 are connected to the auxiliary traces 31 on the wiring layer 21 on both sides of the dielectric layer 22. The auxiliary trace 31 is not electrically connected to any structure, and has no signal transmission effect. The auxiliary through-hole 32 is only used to connect the auxiliary trace 31 without any signal transmission effect.

所述辅助走线31设于所述布线层21中相邻的金属走线211的间隙之间，一方面，可以提升互连线制造过程中工艺的均匀性，降低由于周围环境的不同而导致的互连线电学性能的差异；另一方面，通过插入辅助走线31也可以提升集成电路互连结构的机械强度及可靠性。The auxiliary trace 31 is disposed between the gaps of the adjacent metal traces 211 in the wiring layer 21. On the one hand, the uniformity of the process in the manufacturing process of the interconnect can be improved, and the damage caused by the different surrounding environments can be reduced The electrical performance of the interconnect lines is different; on the other hand, the mechanical strength and reliability of the integrated circuit interconnect structure can also be improved by inserting the auxiliary trace 31.

所述辅助通孔32内填充有填充材料322。本实施例中，所述填充材料322为金属材料。所述辅助通孔32连接所述介质层22两侧的布线层21内的辅助走线31。所述辅助通孔32设于所述介质层22内，可以增加所述介质层22的机械强度，使得所述介质层22不容易发生开裂。并且，对于已产生的裂纹，所述辅助通孔32也能够阻挡裂纹的延伸，进一步增加所述集成电路互连结构的可靠性。并且，通过将每个介质层22内的所述辅助通孔32连接位于所述介质层22两侧的所述布线层21内的所述辅助走线31，使得所述第一增强结构30的辅助走线31及辅助通孔32形成一体，保证了第一增强结构30能够提供更好的机械强度。本申请一些实施例中，所述第一增强结构30的辅助走线31及辅助通孔32内的填充材料为同种材料，从而在一些实施例中，制作得到所述第一增强结构30时，能够同时形成所述辅助走线31以及填充所述填充材料322，从而简化制程。并且，所述辅助通孔的填充材料322与其连接的所述辅助走线31的材料相同，使得所述辅助通孔32与所述辅助走线31之间的结合效果更好，以得到更加稳固的第一增强结构30。The auxiliary through hole 32 is filled with a filling material 322. In this embodiment, the filling material 322 is a metal material. The auxiliary through-holes 32 are connected to the auxiliary traces 31 in the wiring layer 21 on both sides of the dielectric layer 22. The auxiliary through hole 32 is provided in the dielectric layer 22, which can increase the mechanical strength of the dielectric layer 22, so that the dielectric layer 22 is not easily cracked. In addition, for the cracks that have occurred, the auxiliary through-holes 32 can also prevent the cracks from extending, further increasing the reliability of the integrated circuit interconnect structure. In addition, by connecting the auxiliary through-holes 32 in each dielectric layer 22 to the auxiliary traces 31 in the wiring layer 21 on both sides of the dielectric layer 22, the first reinforcing structure 30 The auxiliary wires 31 and the auxiliary through-holes 32 are integrated to ensure that the first reinforcing structure 30 can provide better mechanical strength. In some embodiments of the present application, the auxiliary wiring 31 and the filling material in the auxiliary through-hole 32 of the first reinforcement structure 30 are the same material. Therefore, in some embodiments, when the first reinforcement structure 30 is obtained, , The auxiliary trace 31 and the filling material 322 can be formed at the same time, thereby simplifying the manufacturing process. In addition, the filling material 322 of the auxiliary through-hole is the same as the material of the auxiliary wiring 31 connected thereto, so that the combining effect between the auxiliary through-hole 32 and the auxiliary wiring 31 is better, so as to obtain more stability. The first reinforcement structure 30.

进一步的，本申请中，位于相邻的介质层22内的所述辅助通孔32在垂直于布线层21方向上对齐或者部分对齐。换句话说，所述第一增强结构30的位于不同布线层21内的辅助通孔32在所述基板10上的垂直于布线层21方向的投影重合或者部分重合，避免了裂缝 从辅助通孔的错开位置在各个不同的布线层21及介质层22之间的延伸，从而减小了所述集成电路100的互连结构的可靠性风险。Further, in the present application, the auxiliary through holes 32 located in the adjacent dielectric layers 22 are aligned or partially aligned in a direction perpendicular to the wiring layer 21. In other words, the projections of the auxiliary through-holes 32 of the first reinforcement structure 30 located in different wiring layers 21 on the substrate 10 perpendicular to or in the direction of the wiring layer 21 overlap or partially overlap to prevent cracks from passing through the auxiliary through-holes. The staggered positions extend between different wiring layers 21 and dielectric layers 22, thereby reducing the reliability risk of the interconnection structure of the integrated circuit 100.

本申请的一些实施例中，相邻两层所述布线层21内的所述辅助走线31的延伸方向相垂直，所述辅助通孔32位于相邻两层所述布线层21内的所述辅助走线31交叠的位置。具体的，本申请一实施例中，相邻两层所述布线层21内的所述辅助走线31的延伸方向相垂直，位于同一所述布线层21内的辅助走线31与所述金属走线211的延伸方向相同。而位于相邻的所述布线层21内的所述金属走线211延伸方向相垂直，以满足设计规则的要求。本申请中，通过相邻的两个所述布线层21内的所述辅助走线31与所述金属走线211的延伸方向设置为相同，从而使得每一所述布线层21内的所述金属走线211与所述辅助走线31所处的环境尽量相同，可以提升所述金属走线211与所述辅助走线31的制造过程中工艺的均匀性，降低由于周围环境的不同而导致的所述金属走线31电学性能的差异。进一步的，通过将相邻的两个所述布线层21内的金属走线211及辅助走线31的延伸方向垂直，从而使得所述集成电路互连结构内的走线能够满足连接集成电路100内的微电子结构的需求。In some embodiments of the present application, the extension directions of the auxiliary traces 31 in the two adjacent wiring layers 21 are perpendicular, and the auxiliary through-holes 32 are located in the adjacent two layers of the wiring layers 21. The positions where the auxiliary traces 31 overlap are described. Specifically, in an embodiment of the present application, the extension directions of the auxiliary traces 31 in the two adjacent wiring layers 21 are perpendicular, and the auxiliary traces 31 and the metal located in the same wiring layer 21 are perpendicular to each other. The extension direction of the trace 211 is the same. The extension directions of the metal traces 211 in the adjacent wiring layers 21 are perpendicular to meet the requirements of the design rules. In this application, the extension directions of the auxiliary traces 31 and the metal traces 211 in two adjacent wiring layers 21 are set to be the same, so that the The environment where the metal wiring 211 and the auxiliary wiring 31 are located is the same as much as possible, which can improve the process uniformity in the manufacturing process of the metal wiring 211 and the auxiliary wiring 31 and reduce the causes caused by the difference in the surrounding environment. The electrical performance of the metal trace 31 is different. Further, the extending directions of the metal traces 211 and the auxiliary traces 31 in the two adjacent wiring layers 21 are perpendicular, so that the traces in the integrated circuit interconnection structure can meet the connection to the integrated circuit 100. The needs of microelectronic structures.

请同时参阅图1及图2，本申请一实施例的所述第一增强结构30中，所述多条辅助走线31分布于四个相邻的布线层21内，四个布线层21分别为第一布线层、第二布线层、第三布线层及第四布线层。每个所述布线层21内各设有一条所述辅助走线31。相邻的两个布线层21内的辅助走线31的延伸方向互相垂直。并且，位于不同布线层21内的延伸方向相同的所述辅助走线在垂直所述布线层21方向上重合或部分重合。例如，本实施例中，第一布线层与第三布线层中的辅助走线31在垂直与布线层21的方向上重合；第二布线层与第四布线层21c中的辅助走线31在垂直于布线层21的方向上重合，从而使得各个布线层21的辅助走线31的交叠位置在垂直于布线层21的方向上重合。所述辅助通孔32位于相邻的两层布线层21之间的介质层，并位于相邻的两层布线层21内的辅助走线31的交叠位置，使得位于相邻的介质层22内的所述辅助通孔32在垂直布线层21的方向上对齐或者部分对齐。。Please refer to FIG. 1 and FIG. 2 at the same time. In the first reinforcement structure 30 according to an embodiment of the present application, the plurality of auxiliary traces 31 are distributed in four adjacent wiring layers 21, and the four wiring layers 21 are respectively The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer. Each of the wiring layers 21 is provided with one auxiliary trace 31. The extension directions of the auxiliary traces 31 in two adjacent wiring layers 21 are perpendicular to each other. In addition, the auxiliary traces extending in the same direction in different wiring layers 21 overlap or partially overlap in a direction perpendicular to the wiring layer 21. For example, in this embodiment, the auxiliary wirings 31 in the first wiring layer and the third wiring layer overlap in a direction perpendicular to the wiring layer 21; the auxiliary wirings 31 in the second wiring layer and the fourth wiring layer 21c are at The directions perpendicular to the wiring layer 21 overlap, so that the overlapping positions of the auxiliary traces 31 of the respective wiring layers 21 overlap in the direction perpendicular to the wiring layer 21. The auxiliary through-holes 32 are located in the dielectric layer between the two adjacent wiring layers 21, and are located at the overlapping positions of the auxiliary traces 31 in the adjacent two wiring layers 21, so that they are located in the adjacent dielectric layer 22. The auxiliary through-holes 32 are aligned or partially aligned in the direction of the vertical wiring layer 21. .

请同时参阅图1及图3，本申请提供另一种实施例的所述第一增强结构30，其与图2所述实施例的差别在于，所述第一布线层与第三布线层分别设有两条所述辅助走线31，第二布线层及第四布线层设有三条辅助走线。从而使得每相邻两层布线层之间的介质层设有六个辅助通孔32。Please refer to FIG. 1 and FIG. 3 at the same time. The present application provides the first reinforcement structure 30 according to another embodiment, which is different from the embodiment shown in FIG. 2 in that the first wiring layer and the third wiring layer are respectively Two auxiliary traces 31 are provided, and three auxiliary traces are provided in the second wiring layer and the fourth wiring layer. As a result, the dielectric layer between each two adjacent wiring layers is provided with six auxiliary through holes 32.

可以理解的是，在本申请的其它实施例中，各个布线层21内的所述辅助走线211的数量可以根据实际情况进行变化，所述第一增强结构20的辅助走线211的层数也可以进行变化，并且所述辅助走线211的数量及层数发生变化时也会引起辅助通孔32数量的变化。本申请中每层所述布线层21中的所述金属走线211与所述辅助走线31的尺寸、辅助走线31与同其相邻的所述金属走线211之间的距离大小、所述辅助走线31之间的距离大小、相邻的金属走线211之间的距离大小，以及辅助通孔32的尺寸、各辅助通孔32之间的距离大小及辅助通孔32与通孔213之间的距离大小以及相邻的通孔213之间的距离大小均满足集成电路互连线设计规则的要求。It can be understood that, in other embodiments of the present application, the number of the auxiliary traces 211 in each wiring layer 21 may be changed according to an actual situation, and the number of layers of the auxiliary traces 211 of the first reinforcing structure 20 It may also be changed, and when the number and the number of layers of the auxiliary traces 211 are changed, the number of the auxiliary vias 32 may also be changed. The size of the metal trace 211 and the auxiliary trace 31 in each of the wiring layers 21 in this application, the distance between the auxiliary trace 31 and the metal trace 211 adjacent thereto, The distance between the auxiliary traces 31, the distance between adjacent metal traces 211, and the size of the auxiliary through-holes 32, the distance between each auxiliary through-hole 32, and the auxiliary through-holes 32 and The distance between the holes 213 and the distance between adjacent through holes 213 both meet the requirements of the design rules for integrated circuit interconnects.

进一步的，请参阅图1及图4，本申请的所述集成电路100还可以包括第二增强结构 40。所述第二增强结构40包括两层辅助走线41及连接两层辅助走线41的辅助通孔42。每层所述辅助走线41位于一层所述布线层21内并与所述布线层21内的金属走线211及所述第一增强结构30的辅助走线间隔并绝缘。所述第二增强结构40布设于所述集成电路100互连结构中空间大小不足够布设所述第一增强结构30的区域。通过在不足够布设所述第一增强结构30的位置布设所述第二增强结构40，增加所述布线层21内的辅助走线的密度以及所述介质层22内的辅助通孔的密度，可以进一步的增强所述集成电路100互连结构的机械强度，防止裂纹的产生及延伸。Further, referring to FIG. 1 and FIG. 4, the integrated circuit 100 of the present application may further include a second enhancement structure 40. The second reinforcing structure 40 includes two layers of auxiliary traces 41 and auxiliary through holes 42 connecting the two layers of auxiliary traces 41. The auxiliary traces 41 of each layer are located in one layer of the wiring layer 21 and spaced from and insulated from the metal traces 211 and the auxiliary traces of the first reinforcement structure 30 in the wiring layer 21. The second reinforcement structure 40 is arranged in an area of the interconnect structure of the integrated circuit 100 where the space is not sufficient to arrange the first reinforcement structure 30. By arranging the second reinforcement structure 40 at a location where the first reinforcement structure 30 is not sufficient, the density of the auxiliary traces in the wiring layer 21 and the density of the auxiliary vias in the dielectric layer 22 are increased. The mechanical strength of the interconnection structure of the integrated circuit 100 can be further enhanced to prevent the generation and extension of cracks.

请重新参阅图1，进一步的，所述集成电路100的互连结构内还可以包括第三增强结构50，所述第三增强结构50为独立的辅助走线。所述第三增强结构50布设于所述集成电路100的互连结构中不足够布设第一增强结构30及所述第二增强结构40的区域。所述第三增强结构50位于所述布线层21内，并与所述布线层21内的金属走线211、所述第一增强结构30的辅助走线及所述第二增强结构40的辅助走线相互隔离。Please refer to FIG. 1 again. Further, the interconnect structure of the integrated circuit 100 may further include a third reinforcing structure 50, and the third reinforcing structure 50 is an independent auxiliary wiring. The third reinforcing structure 50 is disposed in an area of the interconnect structure of the integrated circuit 100 where the first reinforcing structure 30 and the second reinforcing structure 40 are not sufficient. The third reinforcing structure 50 is located in the wiring layer 21, and is connected to the metal wiring 211 in the wiring layer 21, the auxiliary wiring of the first reinforcing structure 30, and the auxiliary of the second reinforcing structure 40. The traces are isolated from each other.

通过在不足够布设所述第一增强结构30及所述第二增强结构40的位置布设所述第三增强结构50，使得所述第三增强结构50设置于所述布线层21内的金属走线211之间的空隙中，可以进一步增强所述布线层21中的绝缘介质212的机械强度，并且，可以提升互连线制造过程中工艺的均匀性，降低由于周围环境的不同而导致的互连线电学性能的差异。。By arranging the third reinforcement structure 50 at a location where the first reinforcement structure 30 and the second reinforcement structure 40 are not enough, the third reinforcement structure 50 is disposed in the metal layer in the wiring layer 21. In the gap between the lines 211, the mechanical strength of the insulating medium 212 in the wiring layer 21 can be further enhanced, and the uniformity of the process in the manufacturing process of the interconnection line can be improved, and the interaction caused by the difference in the surrounding environment can be reduced. Difference in wiring electrical performance. .

进一步的，本申请中，位于同一布线层21的辅助走线31与金属走线211的材料可以相同或不同。请参阅图5，本申请一些实施例中，位于同一所述布线层21的所述金属走线211与所述辅助走线31的材料相同，同一所述布线层21的所述金属走线211与所述辅助走线31能够通过同一制程得到，制程简单。其中，所述布线层21的所述金属走线211与所述辅助走线31的具体制造过程为现有技术，在此不进行赘述。请参阅图6，本申请其它一些实施例，位于同一所述布线层21的所述金属走线211与所述辅助走线31的材料不相同。由于所述金属走线211主要用于信号传输，以电连接不同的微电子结构，因此，选用电学性能较好的材料形成所述金属走线211；而所述辅助走线31主要作用之一是为了增强所述集成电路100互连结构的机械强度，因此，选用机械强度较高的材料形成所述辅助走线31。Further, in the present application, materials of the auxiliary trace 31 and the metal trace 211 in the same wiring layer 21 may be the same or different. Referring to FIG. 5, in some embodiments of the present application, the metal traces 211 and the auxiliary traces 31 in the same wiring layer 21 are made of the same material, and the metal traces 211 in the same wiring layer 21 are the same. It can be obtained through the same process as the auxiliary wiring 31, and the process is simple. The specific manufacturing process of the metal trace 211 and the auxiliary trace 31 of the wiring layer 21 is the prior art, and details are not described herein. Referring to FIG. 6, in some other embodiments of the present application, the metal traces 211 and the auxiliary traces 31 in the same wiring layer 21 are made of different materials. Since the metal wiring 211 is mainly used for signal transmission to electrically connect different microelectronic structures, a material with better electrical performance is used to form the metal wiring 211; and one of the main functions of the auxiliary wiring 31 The purpose is to enhance the mechanical strength of the interconnect structure of the integrated circuit 100. Therefore, a material with higher mechanical strength is used to form the auxiliary wiring 31.

本申请中，每层所述布线层21中的所述金属走线211与所述辅助走线31的尺寸、辅助走线31与同其相邻的所述金属走线211之间的距离大小、所述辅助走线31之间距离大小、辅助通孔的尺寸及通孔之间的距离均满足集成电路互连线设计规则的要求。In this application, the size of the metal trace 211 and the auxiliary trace 31 in each layer of the wiring layer 21, and the distance between the auxiliary trace 31 and the adjacent metal trace 211. The size of the distance between the auxiliary traces 31, the size of the auxiliary vias and the distance between the vias all meet the requirements of the design rules for integrated circuit interconnects.

请再次参阅图5及图6，本申请中，所述介质层22包括刻蚀阻挡层23，所述刻蚀阻挡层23设于所述介质层22与所述布线层21贴合的一面。通过所述蚀刻阻挡层23，能够保证所述集成电路100互连结构的加工精度，使得所述集成电路100具有较好的品质。本申请其它实施例中，所述通孔213的内壁及所述辅助通孔32的内壁均沉积有一层扩散阻挡层24，从而避免所述通孔213及所述辅助通孔32内的金属材料扩散至绝缘介质中而造成漏电及电路的失效。可以理解的是，所述扩散阻挡层24的材料相对所述金属材料对应设置，以得到较好的扩散阻挡效果。例如，当填充的金属材料为铜时，所述扩散阻挡层的材料可以为TaN/Ta、或TaN/Co等；所述填充的金属材料为Co时，所述扩散阻挡层的材料可以为TiN等；所述填充的金属材料为钨(W)时，不需要扩散阻挡层。进一步的，所述金属走线211 及所述辅助走线31的表面也可以沉积所述扩散阻挡层24，从而避免所述金属走线211或者所述辅助走线31的金属材料扩散至所述绝缘介质212及22中而造成漏电及电路失效，进而保证所述集成电路100的品质。Please refer to FIG. 5 and FIG. 6 again. In this application, the dielectric layer 22 includes an etch barrier layer 23, and the etch barrier layer 23 is disposed on a side where the dielectric layer 22 and the wiring layer 21 are bonded. Through the etch stop layer 23, the processing accuracy of the interconnect structure of the integrated circuit 100 can be ensured, so that the integrated circuit 100 has better quality. In other embodiments of the present application, a diffusion barrier layer 24 is deposited on the inner wall of the through hole 213 and the inner wall of the auxiliary through hole 32, so as to avoid metal materials in the through hole 213 and the auxiliary through hole 32. Diffusion into the insulating medium causes leakage and circuit failure. It can be understood that the material of the diffusion barrier layer 24 is correspondingly disposed with respect to the metal material to obtain a better diffusion barrier effect. For example, when the filled metal material is copper, the material of the diffusion barrier layer may be TaN / Ta, or TaN / Co, and the like; when the filled metal material is Co, the material of the diffusion barrier layer may be TiN When the filled metal material is tungsten (W), a diffusion barrier layer is not required. Further, the diffusion barrier layer 24 may also be deposited on the surfaces of the metal wiring 211 and the auxiliary wiring 31, so as to prevent the metal material of the metal wiring 211 or the auxiliary wiring 31 from diffusing to the The insulation medium 212 and 22 cause leakage and circuit failure, thereby ensuring the quality of the integrated circuit 100.

本申请通过在所述集成电路100的集成电路互连结构中设置第一增强结构30、第二增强结构40及第三增强结构50，减少集成电路100互连结构的介质层22及绝缘介质212内裂纹的产生及延伸，以保证所述集成电路100互连结构的机械性能及可靠性。并将所述第一增强结构30中的辅助通孔32在垂直于所述布线层21的方向上对齐或部分对齐，避免裂纹在各布线层21穿过错开的辅助通孔进行延伸。The present application reduces the dielectric layer 22 and the insulating medium 212 of the interconnection structure of the integrated circuit 100 by providing the first reinforcement structure 30, the second reinforcement structure 40, and the third reinforcement structure 50 in the integrated circuit interconnection structure of the integrated circuit 100. Internal cracks are generated and extended to ensure the mechanical performance and reliability of the interconnect structure of the integrated circuit 100. The auxiliary through-holes 32 in the first reinforcing structure 30 are aligned or partially aligned in a direction perpendicular to the wiring layer 21 to prevent cracks from extending through the misaligned auxiliary through-holes in each wiring layer 21.

以上所揭露的仅为本申请一种较佳实施例而已，当然不能以此来限定本申请之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本申请权利要求所作的等同变化，仍属于发明所涵盖的范围。What has been disclosed above is only a preferred embodiment of the present application. Of course, the scope of rights of the present application cannot be limited by this. Those of ordinary skill in the art can understand all or part of the process of implementing the above embodiments and follow the rights of the present application. Equivalent changes required are still within the scope of the invention.

Claims (12)

一种集成电路互连结构，其特征在于，包括：An integrated circuit interconnect structure is characterized in that it includes: 内连线结构，包括三层或三层以上的层叠设置的布线层以及设于相邻两层布线层之间的介质层；每层所述布线层包括多条间隔设置的金属走线，以及设于间隔设置的所述金属走线之间的绝缘介质；和The interconnect structure includes three or more stacked wiring layers and a dielectric layer provided between two adjacent wiring layers; each wiring layer includes a plurality of spaced metal traces, and An insulating medium provided between the metal traces spaced apart; and 第一增强结构，包括多条辅助走线及多个辅助通孔；多条所述辅助走线分布于相邻的三个或三个以上的所述布线层，每个所述布线层内的所述辅助走线与所述金属走线之间相互绝缘；多个所述辅助通孔分布于两层或两层以上的相邻的所述介质层内；每个所述介质层内的所述辅助通孔连接位于所述介质层两侧的所述布线层内的所述辅助走线；位于相邻的所述介质层的所述辅助通孔在垂直于所述布线层的方向上对齐或者部分对齐。The first reinforced structure includes multiple auxiliary traces and multiple auxiliary through holes; the multiple auxiliary traces are distributed in three or more adjacent wiring layers, and each of the wiring layers The auxiliary trace and the metal trace are insulated from each other; a plurality of the auxiliary vias are distributed in two or more adjacent dielectric layers; The auxiliary vias connect the auxiliary traces in the wiring layer on both sides of the dielectric layer; the auxiliary vias in the adjacent dielectric layer are aligned in a direction perpendicular to the wiring layer Or partially aligned. 如权利要求1所述的集成电路互连结构，其特征在于，相邻两层所述布线层内的所述辅助走线的延伸方向相垂直，所述辅助通孔位于相邻两层所述布线层内的所述辅助走线交叠的位置。The integrated circuit interconnect structure according to claim 1, wherein extension directions of the auxiliary traces in two adjacent layers of the wiring layer are perpendicular, and the auxiliary through holes are located in the two adjacent layers. Where the auxiliary traces in the wiring layer overlap. 如权利要求1或2所述的集成电路互连结构，其特征在于，所述集成电路互联结构还包括第二增强结构，所述第二增强结构包括分设于相邻的两个所述布线层的辅助走线，以及位于相邻的两个布线层之间的介质层的辅助通孔，所述辅助通孔连接两个相邻的所述布线层内的辅助走线，所述第二增强结构的辅助走线与所述布线层内的金属走线以及所述第一增强结构辅助走线绝缘。The integrated circuit interconnection structure according to claim 1 or 2, wherein the integrated circuit interconnection structure further comprises a second reinforcement structure, and the second reinforcement structure includes two adjacent wiring layers. Auxiliary vias, and auxiliary vias in the dielectric layer between two adjacent wiring layers, the auxiliary vias connect auxiliary tracks in two adjacent wiring layers, and the second enhancement The auxiliary wiring of the structure is insulated from the metal wiring in the wiring layer and the auxiliary wiring of the first reinforcing structure. 如权利要求1-3任一项的所述集成电路互连结构，其特征在于，所述集成电路还包括第三增强结构，所述第三增强结构包括独立的辅助走线，所述第三增强结构位于所述布线层内，并与所述布线层内的金属走线、所述第一增强结构的辅助走线和所述第二增强结构的辅助走线绝缘。The integrated circuit interconnect structure according to any one of claims 1-3, wherein the integrated circuit further comprises a third enhanced structure, the third enhanced structure includes independent auxiliary wiring, and the third The reinforcing structure is located in the wiring layer, and is insulated from the metal wiring in the wiring layer, the auxiliary wiring of the first reinforcing structure, and the auxiliary wiring of the second reinforcing structure. 如权利要求1所述的集成电路互连结构，其特征在于，所述辅助通孔内填充有填充材料。The integrated circuit interconnect structure according to claim 1, wherein a filling material is filled in the auxiliary through hole. 如权利要求5所述的集成电路互连结构，其特征在于，所述辅助通孔内的填充材料与其连接的所述辅助走线的材料相同。The integrated circuit interconnect structure according to claim 5, wherein a filling material in the auxiliary through hole is the same as a material of the auxiliary trace connected to the via. 如权利要求5所述的集成电路互连结构，其特征在于，所述辅助通孔的内壁覆盖有扩散阻挡层。The integrated circuit interconnect structure according to claim 5, wherein an inner wall of the auxiliary through hole is covered with a diffusion barrier layer. 如权利要求1所述的集成电路互连结构，其特征在于，位于同一所述布线层的所述金属走线与所述辅助走线的材料不同。The integrated circuit interconnect structure according to claim 1, wherein the metal traces and the auxiliary traces located in the same wiring layer are made of different materials. 如权利要求1所述的集成电路互连结构，其特征在于，所述金属走线、辅助走线的表面设有扩散阻挡层。The integrated circuit interconnect structure according to claim 1, wherein a diffusion barrier layer is provided on a surface of the metal trace and the auxiliary trace. 如权利要求1所述的集成电路互连结构，其特征在于，所述介质层包括低介电常数材料或超低介电常数材料或极低介电常数材料。The integrated circuit interconnect structure according to claim 1, wherein the dielectric layer comprises a low dielectric constant material or an ultra-low dielectric constant material or an extremely low dielectric constant material. 一种集成电路，其特征在于，包括基板及形成于所述基板上的如权利要求1-10任一项的所述集成电路互连结构。An integrated circuit, comprising a substrate and the integrated circuit interconnection structure according to any one of claims 1-10 formed on the substrate. 如权利要求11的所述集成电路，其特征在于，所述基板具有多个微电子结构，所 述集成电路互连结构与所述微电子结构电连接。The integrated circuit according to claim 11, wherein said substrate has a plurality of microelectronic structures, and said integrated circuit interconnect structure is electrically connected to said microelectronic structure.
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