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WO2020000380A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2020000380A1
WO2020000380A1 PCT/CN2018/093694 CN2018093694W WO2020000380A1 WO 2020000380 A1 WO2020000380 A1 WO 2020000380A1 CN 2018093694 W CN2018093694 W CN 2018093694W WO 2020000380 A1 WO2020000380 A1 WO 2020000380A1
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WIPO (PCT)
Prior art keywords
layer
bonding
buffer layer
adhesion
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/093694
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English (en)
French (fr)
Inventor
王新胜
张莉
张高升
万先进
华子群
王家文
丁滔滔
朱宏斌
程卫华
杨士宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to PCT/CN2018/093694 priority Critical patent/WO2020000380A1/zh
Priority to CN201880096607.0A priority patent/CN112567506B/zh
Priority to CN202210808320.4A priority patent/CN115188731B/zh
Priority to TW107128306A priority patent/TWI682445B/zh
Priority to US16/377,244 priority patent/US10818631B2/en
Publication of WO2020000380A1 publication Critical patent/WO2020000380A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same.
  • two or more wafers formed with semiconductor devices are usually bonded by a wafer bonding technology to improve the integration of the chip.
  • a wafer bonding technology In the existing wafer bonding technology, a bonding film is formed on a wafer bonding surface, and wafer bonding is achieved by bonding the surface of the bonding film between two wafers.
  • silicon oxide and silicon nitride films are generally used as bonding films, and the bonding strength is insufficient, which causes defects to easily occur during the process, and the product yield is affected.
  • a metal connection structure is also formed in the bonding film.
  • the metal connection structure is prone to diffusion at the bonding interface, which affects product performance.
  • the technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the bonding quality.
  • the present invention provides a semiconductor structure including: a first substrate; a first adhesion layer on a surface of the first substrate; a first buffer layer on a surface of the first adhesion layer; The first bonding layer on the surface of the first buffer layer is denser than the first adhesive layer and the first buffer layer.
  • the materials of the first bonding layer and the first buffer layer are both dielectric materials containing element C, and the atomic concentration of C in the first bonding layer is greater than that in the first buffer layer. Atomic concentration of C.
  • the atomic concentration of C in the first bonding layer is greater than 35%, and the atomic concentration of C in the first buffer layer is 0-50%.
  • the atomic concentration of C in the first bonding layer increases as the thickness of the first bonding layer increases; the atomic concentration of C in the first buffer layer increases with the first buffer layer The thickness increases.
  • the material of the first adhesion layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the first bonding layer further includes Si and N.
  • the material of the first buffer layer further includes Si and N.
  • the thickness of the first adhesion layer is The thickness of the first buffer layer is
  • it further includes: a second substrate, a surface of the second substrate is formed with a second adhesive layer, a second buffer layer on the surface of the second adhesive layer, and a second buffer layer on the surface of the second buffer layer.
  • the material of the second bonding layer is the same as that of the first bonding layer
  • the material of the second buffer layer is the same as that of the first buffer layer
  • the second adhesion layer is the same as the material of the first bonding layer.
  • the material of the first adhesion layer is the same.
  • it further includes: a first bonding pad penetrating through the first bonding layer, the first buffer layer, and the first adhesive layer; penetrating through the second bonding layer, the second bonding layer A buffer layer and a second bonding pad of the second adhesion layer; the first bonding pad and the second bonding pad are oppositely bonded and connected.
  • a specific embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a first substrate; forming a first adhesive layer on a surface of the first substrate; Performing plasma bombardment to increase the density; forming a first buffer layer on the surface of the first adhesion layer; forming a first bonding layer on the surface of the first buffer layer, the first adhesion layer and the first The densities of the buffer layers are all greater than the densities of the first bonding layer.
  • the first adhesion layer contains H bonds; in the plasma bombardment step, N-containing plasma is used for bombardment to reduce the content of the first adhesion layer. H key.
  • the materials of the first bonding layer and the first buffer layer are both dielectric materials containing element C, and the atomic concentration of C in the first bonding layer is greater than that in the first buffer layer. Atomic concentration of C.
  • the material of the first bonding layer further includes Si and N.
  • the material of the first buffer layer further includes Si and N.
  • the material of the first adhesion layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide.
  • the thickness of the first adhesion layer is The thickness of the first buffer layer is
  • a first adhesion layer and a first buffer layer are provided between the first substrate and the first bonding layer of the semiconductor structure of the present invention, and the density of the first adhesion layer and the first buffer layer is greater than that of the first bonding layer. It is denser, thereby improving the adhesion between the first adhesion layer and the first substrate, the first adhesion layer and the first buffer layer, and the first buffer layer and the first bonding layer, so as to avoid cracking.
  • the first bonding layer can also have a strong bonding force on the bonding surface after bonding, and can block the diffusion of the metal material at the bonding interface, thereby improving the performance of the formed semiconductor structure.
  • 1 to 4 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • FIGS. 1 to 4 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.
  • a first substrate 100 is provided.
  • the first substrate 100 includes a first semiconductor substrate 101 and a first device layer 102 formed on a surface of the first semiconductor substrate 101.
  • the first semiconductor substrate 101 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI or a GOI, etc .; according to the actual needs of the device, a suitable first semiconductor substrate 101 may be selected, which is not limited herein. .
  • the first semiconductor substrate 101 is a single crystal silicon wafer.
  • the first device layer 102 includes a semiconductor device formed on the semiconductor substrate 101, a metal interconnection structure connected to the semiconductor device, a dielectric layer covering the semiconductor device and the metal interconnection structure, and the like.
  • the layer is usually silicon oxide, silicon nitride or silicon oxynitride.
  • the first device layer 102 may have a multi-layer or single-layer structure.
  • the first device layer 102 includes a dielectric layer and a 3D NAND structure formed in the dielectric layer.
  • a first adhesion layer 202, a first buffer layer 203 on the surface of the first adhesion layer 202, and a first buffer layer 203 on the surface of the first buffer layer 203 are sequentially formed on the surface of the first substrate 100.
  • a chemical vapor deposition process may be used to sequentially form the first adhesion layer 202, the first buffer layer 103, and the first bonding layer 201.
  • the first adhesion layer 202, the first buffer layer 203, and the first bonding layer 201 are formed by a plasma enhanced chemical vapor deposition process.
  • the material of the first adhesion layer 202 is a dielectric material having a density greater than that of the first bonding layer 201.
  • the material of the first adhesive layer 202 may be at least one of silicon nitride, silicon oxynitride, and silicon oxide. Based on the reaction gas used in the chemical vapor deposition process and the requirements of specific products, the first adhesive layer 202
  • the auxiliary layer 202 may also be doped with at least one of elements such as O, H, P, and F.
  • a material of the first adhesion layer 202 is silicon nitride, and the first adhesion layer 202 is formed by a plasma enhanced chemical vapor deposition process.
  • the reaction gases used include: SiH 4 and NH 3
  • the flow ratio range of SiH 4 and NH 3 is (0.8 ⁇ 1.2): 1, and the RF power range is 150W ⁇ 300W.
  • the first adhesion layer 202 having a higher density can be formed by adjusting process parameters in the deposition process.
  • the method for forming the first adhesion layer 202 includes: forming an adhesion material layer on the surface of the first substrate 100 by a deposition process, and then performing plasma bombardment on the adhesion material layer, In order to reduce the content of H in the adhesion material layer, the density of the first adhesion layer 202 formed is increased.
  • the plasma bombardment may use N-containing gas, such as N 2 , NH 3 and the like.
  • the plasma bombardment may use N 2 as a plasma source, the radio frequency power is 500 W, and the bombardment time is 30 s.
  • the plasma bombardment can remove H in the first adhesion layer 202, so that the unit area of the first adhesion layer 202 has more chemical bonds that can connect adjacent material layers, such as Si-, N-, etc., thereby improving the adhesion between the first adhesion layer 202, the first device layer 102, and the first buffer layer 203.
  • the material of the first buffer layer 203 is a dielectric material containing element C.
  • the first buffer layer 203 mainly includes Si, N, and C.
  • the first buffer layer 203 may further include Si, N, O, H, P, F and other elements. At least one.
  • the density of the first buffer layer 203 is greater than the density of the first bonding layer 201.
  • the density of the first buffer layer 203 is the same as that of the first adhesion layer 202. The density is close to or the same.
  • the material of the first buffer layer 203 can be silicon doped silicon nitride, carbon doped silicon oxynitride, nitrogen doped silicon oxycarbide, or the like. Because the first buffer layer 203 has a high density and a high density of chemical bonds at the interface with the first adhesion layer 202, it has a high adhesion with the first adhesion layer 202 Sex.
  • the first buffer layer 203 is formed by a plasma enhanced chemical vapor deposition process, and the reaction gas used includes one of trimethylsilane or tetramethylsilane and NH 3 , trimethyl
  • the flow ratio range of silane or tetramethylsilane to NH 3 is 1: (2 to 4), and the RF power range is 200W to 500W.
  • the density of the first buffer layer 203 and the atomic concentration of C in the first buffer layer 203 can be adjusted by adjusting the deposition process parameters.
  • the material of the first bonding layer 201 is a dielectric material containing element C, and the atomic concentration of C in the first bonding layer 201 is greater than the atomic concentration of C in the first buffer layer 203.
  • the first bonding layer 201 mainly includes Si, N, and C.
  • the first bonding layer 201 may further include Si, N, O, H, P, F and other elements. At least one.
  • the material of the first bonding layer 201 may be silicon doped silicon nitride, carbon doped silicon oxynitride, nitrogen doped silicon oxycarbide, or the like.
  • the composition of the first bonding layer 201 is close to or the same as that of the first buffer layer 203. Therefore, forming the first bonding layer 201 on the surface of the first buffer layer 203 can make the first bonding layer 201 A bonding layer 201 and the first buffer layer 203 have high adhesion. If the atomic concentration of C in the material layer is too high, the adhesion with other material layers will decrease. The atomic concentration of C in the first buffer layer 203 is smaller than the atomic concentration of C in the first bonding layer 201, compared with the formation of the first bonding layer 201 directly on the surface of the first bonding layer 202, The adhesion between the first buffer layer 203 and the first adhesion layer 202 is higher.
  • the first bonding layer 201 is formed by a plasma enhanced chemical vapor deposition process, and a reaction gas used includes at least one of trimethylsilane or tetramethylsilane and NH 3 , three The flow ratio of methylsilane or tetramethylsilane to NH 3 ranges from (1.6 to 2.4): 1, and the radio frequency power ranges from 500W to 1100W.
  • C in the first bonding layer 201 can effectively improve the bonding force between the first bonding layer 201 and other bonding layers during the bonding process.
  • the atomic concentration of C in the first bonding layer 201 is greater than 35%.
  • the atomic concentration of C in the first buffer layer 203 is smaller than the atomic concentration of C in the first bonding layer 201, so that the material structure of the first buffer layer 203 is more similar to that of the first adhesion layer 202. For close.
  • the atomic concentration of C in the first buffer layer 203 is 0-50%.
  • the first bonding layer 201 contains a higher concentration of the C element, the density of the first bonding layer 201 will be lower.
  • the first bonding layer 201 and the A first adhesive layer 202 and a first buffer layer 203 having a higher density are formed between the first substrates 100, and the atomic concentration of C in the first buffer layer 203 is lower than that of C in the first bonding layer 201. Atomic concentration can improve adhesion between layers.
  • the components of the first bonding layer 201 and the first adhesion layer 202 can be adjusted. Concentration, adjust the adhesion between the material layers and the dielectric constant.
  • process parameters may be gradually adjusted so that the first The component concentration in an adhesion layer 202 gradually changes, so that the material components on both sides of the interface between the first device layer 102 and the first adhesion layer 202 are close.
  • the parameters of the deposition process are adjusted to make the Si in the first adhesion layer 202 Atomic concentration gradually changes as the thickness of the first adhesive layer 202 increases.
  • the concentration of other components in the first adhesion layer 202 may be adjusted according to different surface materials of the first device layer 102.
  • the deposition process parameters may be kept unchanged, so that the atomic concentration of each element in the first adhesion layer 202 is maintained at different thickness positions. Consistent.
  • process parameters may be gradually adjusted so that the first The component concentration in the buffer layer 203 gradually changes, so that the material components on both sides of the interface between the first buffer layer 203 and the first adhesion layer 202 are close.
  • the parameters of the deposition process are adjusted so that the atomic concentration of C varies with the thickness of the first buffer layer 203. Increase and gradually increase.
  • the atomic concentration of C may be gradually decreased as the thickness of the first buffer layer 203 is increased, or gradually increased and then gradually decreased.
  • the deposition process parameters are kept unchanged, so that the atomic concentration of each element in the first buffer layer 203 is kept consistent at different thickness positions.
  • the process parameters can be gradually adjusted so that the first The component concentration in a bonding layer 201 gradually changes, so that the material components on both sides of the interface between the first bonding layer 201 and the first buffer layer 203 are close.
  • the parameters of the deposition process are adjusted so that the atomic concentration of C follows the first bonding The thickness of the layer 201 gradually increases.
  • the atomic concentration of C may be gradually decreased as the thickness of the first bonding layer 201 is increased, or gradually increased and then gradually decreased.
  • the deposition process parameters are kept unchanged, so that the elements in the first bonding layer 201 are kept consistent at different thickness positions.
  • the thickness of the first adhesion layer 202 is The thickness of the first buffer layer 203 is
  • the thickness of the first bonding layer 201 is greater than the thickness of the first adhesion layer 202 and the first buffer layer 203, so as to ensure that the first bonding layer 201 is bonded to other bonds.
  • the first bonding layer 201 has a sufficient bonding thickness.
  • the thickness of the first bonding layer 201 is greater than
  • the first bonding layer 201 may further include two or more sub-bonding layers stacked.
  • the materials of different sub-bond layers may be the same or different.
  • first adhesion layer and a first buffer layer between the first substrate and the first bonding layer of the semiconductor structure in the above specific embodiment.
  • the first adhesion layer and the first buffer layer have a higher density than the first bond.
  • the bonding layer is dense, thereby improving the adhesion between the first adhesion layer and the first substrate, and the adhesion between the first buffer layer and the first bonding layer; and the first buffer layer and the first An adhesion layer has a high density, and the first buffer layer and the first adhesion layer also have a high adhesion force, which can avoid problems such as breakage of the semiconductor structure.
  • the first bonding layer can also have a strong bonding force on the bonding surface after bonding, and can block the diffusion of the metal material at the bonding interface, thereby improving the performance of the formed semiconductor structure.
  • the method further includes: providing a second substrate 300; forming a second adhesive layer 402 on a surface of the second substrate 300, and a first adhesive layer 402 on a surface of the second adhesive layer 402.
  • the second substrate 300 includes a second semiconductor substrate 301 and a second device layer 302 on a surface of the second semiconductor substrate 201.
  • the material of the second adhesion layer 402 is a dielectric material with a density greater than that of the second bonding layer 401.
  • the material of the second adhesion layer 402 may be at least one of silicon nitride, silicon oxynitride, and silicon oxide. Based on the reaction gas used in the chemical vapor deposition process and the needs of specific products, the second adhesion layer
  • the additional layer 402 may further include at least one of O, H, P, and F elements.
  • the material of the second buffer layer 403 is a dielectric material having a density greater than that of the second buffer layer 403.
  • the material of the second buffer layer 403 is a dielectric material containing element C.
  • the second buffer layer 403 mainly includes Si, N, and C.
  • the second buffer layer 403 may further contain Si, N, O, H, P, F and other elements. At least one.
  • the material of the second bonding layer 401 is a dielectric material containing element C, and the atomic concentration of C in the first bonding layer 201 is greater than the atomic concentration of C in the first buffer layer 203.
  • the second bonding layer 401 mainly includes Si, N, and C.
  • the second bonding layer 401 may be doped with Si, N, O, H, P, F, etc. based on the reaction gas used in the chemical vapor deposition process and the needs of specific products. At least one of the elements. If the atomic concentration of C in the material layer is too high, the adhesion with other material layers will decrease.
  • the atomic concentration of C in the second buffer layer 403 is smaller than the atomic concentration of C in the second bonding layer 401, and compared with forming the second bonding layer 401 directly on the surface of the second bonding layer 402, The adhesion between the second buffer layer 403 and the second adhesion layer 402 is higher.
  • a chemical vapor deposition process is used to sequentially form the second adhesion layer 402, the second buffer layer 403, and the second bonding layer 401 on the surface of the second device layer 302.
  • the second adhesive layer 402, the second buffer layer 403, and the second bonding layer 401 please refer to the first adhesive layer 202, the first buffer layer 203, and The description of the first bonding layer 201 is not repeated here.
  • the material, structure, and formation method of the second adhesion layer 402 and the first adhesion layer 202 are the same; the materials, structure, and formation of the second buffer layer 403 and the first buffer layer 203 The methods are the same, and the materials, structures, and forming methods of the second bonding layer 401 and the first bonding layer 201 are the same.
  • the thickness of the second adhesion layer 402 is The thickness of the second buffer layer 403 is The thickness of the second bonding layer 401 is greater than
  • the surfaces of the second bonding layer 401 and the first bonding layer 201 are relatively bonded and fixed.
  • the second bonding layer 401 and the first bonding layer 201 both containing C, part C is present in the form of -CH 3, -CH 3 more susceptible to oxidation is -OH, and is formed in the Si-O bonding process Bonding, so that more silicon-oxygen bonds can be formed at the bonding interface, thereby forming a stronger bonding force.
  • a bonding force between the second bonding layer 401 and the first bonding layer 201 is greater than 2 J / M 2 .
  • a bonding layer containing no C is used for bonding, and the bonding force is usually less than 1.5 J / M 2 .
  • the first substrate 100 is a substrate on which a 3D NAND memory structure is formed
  • the second substrate 200 is a substrate on which a peripheral circuit is formed.
  • the above-mentioned adhesion layer and bonding layer may also be formed on both side surfaces of the substrate to achieve multilayer bonding.
  • the method further includes: forming a first bonding pad 501 penetrating through the first bonding layer 201, the first buffer layer 203, and the first adhesive layer 202; The second bonding pad 502 of the second bonding layer 401, the second buffer layer 403, and the second adhesion layer 402; the surface of the second bonding layer 401 is opposite to the surface of the first bonding layer 201 While the bonding is fixed, the first bonding pad 501 and the second bonding pad 502 are oppositely bonded to each other.
  • the first bonding pad 501 and the second bonding pad 502 may be connected to a semiconductor device and a metal interconnection layer in the first device layer 102 and the second device layer 302, respectively.
  • the method for forming the first bonding pad 501 includes: patterning the first bonding layer 201, the first buffer layer 203, and the first adhesion layer 202 to form a through-the-first bonding layer 201, Openings of the first buffer layer 203 and the first adhesion layer 202; metal materials are filled in the openings, and planarization is performed to form a first bonding pad 501 filling the openings.
  • the same method is used to form the second bonding pad 502 in the second bonding layer 401, the second buffer layer 403, and the second adhesion layer 402. Bonding the first bonding pad 501 and the second bonding pad 502 to each other can realize the electrical connection between the semiconductor devices in the first device layer 102 and the second device layer 302.
  • the materials of the first bonding pad 501 and the second bonding pad 502 may be metal materials such as Cu and W.
  • the first bonding layer 201 and the first bonding layer 401 contain C, which can effectively block the material of the first bonding pad 501 and the second bonding pad 502 from diffusing at the bonding interface, thereby improving the Performance of semiconductor structures.
  • an adhesion layer is formed on the substrate surface, a buffer layer is formed on the surface of the adhesion layer, and a bonding layer is formed on the surface of the buffer layer.
  • the density of the adhesion layer and the buffer layer is greater than that of the bonding layer. Density, thereby improving the adhesion between the adhesion layer, the buffer layer, the substrate, and the bonding layer, and the bonding layer can also have a strong bonding force on the bonding surface after bonding, which can block the metal material from Diffusion of the bonding interface, thereby improving the performance of the formed semiconductor structure.
  • the method for forming a semiconductor structure according to the above specific embodiment is also used for multi-piece substrate bonding.
  • a third substrate 600 is further provided, and a third adhesion layer 702, a third buffer layer 703, and a third substrate are sequentially formed on one side surface of the third substrate 600.
  • the surface is relatively bonded and fixed, and the fourth bonding layer 801 and the second bonding layer 401 are surface-bonded and fixed to form a three-layer bonding structure.
  • materials, structures and formation methods of 701 and the fourth bonding layer 801 please refer to the materials, structures, and formation methods of the first adhesion layer 202, the first buffer layer 203, and the first bonding layer 201 in the above specific embodiments, respectively. , Will not repeat them here.
  • the method for forming the semiconductor structure further includes: forming a third bonding pad 704 penetrating the third bonding layer 701, the third buffer layer 703, and the third adhesive layer 702 to form a penetrating layer.
  • the fourth bonding pad 804 of the fourth bonding layer 801, the fourth buffer layer 803, and the fourth adhesive layer 802 is connected to the third bonding pad 704 and the first bonding pad 501 to bond the The fourth bonding pad 804 is bonded to the second bonding pad 502.
  • the above method can also be used to form a bonding structure with more than four layers.
  • the type of semiconductor device in each substrate in the semiconductor structure is not limited to the given embodiment. Except for 3D NAND, it may be a CMOS circuit, a CIS circuit, or a TFT circuit. and many more.
  • a specific embodiment of the present invention also provides a semiconductor structure.
  • FIG. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • the semiconductor structure includes: a first substrate 100; a first adhesion layer 202 on a surface of the first substrate 100; a first buffer layer 203 on a surface of the first adhesion layer 202; The first bonding layer 201 on the surface of the buffer layer 203.
  • the first substrate 100 includes a first semiconductor substrate 101 and a first device layer 102 formed on a surface of the first semiconductor substrate 101.
  • the first semiconductor substrate 101 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI or a GOI, etc .; according to the actual needs of the device, a suitable first semiconductor substrate 101 may be selected, which is not limited herein. .
  • the first semiconductor substrate 101 is a single crystal silicon wafer.
  • the first device layer 102 includes a semiconductor device formed on the semiconductor substrate 101, a metal interconnection structure connected to the semiconductor device, a dielectric layer covering the semiconductor device and the metal interconnection structure, and the like.
  • the first device layer 102 may have a multi-layer or single-layer structure.
  • the first device layer 102 includes a dielectric layer and a 3D NAND structure formed in the dielectric layer.
  • the material of the first adhesion layer 202 is a dielectric material having a density greater than that of the first bonding layer 201.
  • the material of the first adhesive layer 202 may be at least one of silicon nitride, silicon oxynitride, and silicon oxide. Based on the reaction gas used in the chemical vapor deposition process and the requirements of specific products, the first adhesive layer 202
  • the auxiliary layer 202 may also be doped with at least one of elements such as O, H, P, and F.
  • the first adhesion layer 202 is SiN with high density.
  • the material of the first buffer layer 203 is a dielectric material containing element C.
  • the first buffer layer 203 mainly includes Si, N, and C.
  • the first buffer layer 203 may be doped with elements such as Si, N, O, H, P, and F. At least one of.
  • the density of the first buffer layer 203 is greater than the density of the first bonding layer 201, and the density of the first buffer layer 203 is the same as that of the first adhesion layer 202. The density is close or the same.
  • the material of the first buffer layer 203 can be silicon doped silicon nitride, carbon doped silicon oxynitride, nitrogen doped silicon oxycarbide, or the like. Because the first buffer layer 203 has a high density and a high density of chemical bonds at the interface with the first adhesion layer 202, it has a high adhesion with the first adhesion layer 202 Sex.
  • the material of the first bonding layer 201 is a dielectric material containing a C element.
  • the atomic concentration of C in the first bonding layer 201 is greater than the atomic concentration of C in the first buffer layer 203.
  • the first bonding layer 201 mainly includes Si, N, and C.
  • the first bonding layer 201 may be doped with Si, N, O, H, P, F, etc. based on the reaction gas used in the chemical vapor deposition process and the needs of specific products. At least one of the elements.
  • the material of the first bonding layer 201 may be silicon doped silicon nitride, carbon doped silicon oxynitride, nitrogen doped silicon oxycarbide, or the like.
  • the composition of the first bonding layer 201 is close to or the same as that of the first buffer layer 203. Therefore, the first bonding layer 201 is located on the surface of the first buffer layer 203, so that the first bonding layer 201 A bonding layer 201 and the first buffer layer 203 have high adhesion. If the atomic concentration of C in the material layer is too high, the adhesion with other material layers will decrease. The atomic concentration of C in the first buffer layer 203 is smaller than the atomic concentration of C in the first bonding layer 201, compared with the formation of the first bonding layer 201 directly on the surface of the first bonding layer 202, The adhesion between the first buffer layer 203 and the first adhesion layer 202 is higher.
  • C in the first bonding layer 201 can effectively improve the bonding force between the first bonding layer 201 and other bonding layers during the bonding process.
  • the atomic concentration of C in the first bonding layer 201 is greater than 35%.
  • the atomic concentration of C in the first buffer layer 203 is smaller than the atomic concentration of C in the first bonding layer 201, so that the material structure of the first buffer layer 203 is more similar to that of the first adhesion layer 202. For close.
  • the atomic concentration of C in the first buffer layer 203 is 0-50%.
  • the first bonding layer 201 contains a higher concentration of the C element, the density of the first bonding layer 201 will be lower.
  • the first bonding layer 201 and the A first adhesive layer 202 and a first buffer layer 203 having a higher density are formed between the first substrates 100, and the atomic concentration of C in the first buffer layer 203 is lower than that of C in the first bonding layer 201. Atomic concentration can improve adhesion between layers.
  • the component concentration in the first adhesion layer 202 gradually changes with the thickness, so that the first Material components on both sides of the interface between the device layer 102 and the first adhesion layer 202 are close.
  • the atomic concentration of Si in the first adhesion layer 202 gradually changes as the thickness of the first adhesion layer 202 increases.
  • the concentration of other components in the first adhesion layer 202 may also vary with thickness.
  • the atomic concentration of each element in the first adhesion layer 202 may also be kept consistent at different thickness positions.
  • the material composition on both sides of the interface between the first buffer layer 203 and the first adhesion layer 202 is close to .
  • the atomic concentration of C in the first buffer layer 203 gradually increases as the thickness of the first buffer layer 203 increases.
  • the atomic concentration of C in the first buffer layer 203 decreases gradually as the thickness of the first buffer layer 203 increases, or gradually increases and then gradually decreases.
  • the atomic concentration of each element in the first buffer layer 203 is kept consistent at different thickness positions.
  • the component concentration in the first bonding layer 201 may also gradually change with the thickness, so that the first The material composition on both sides of the interface between the bonding layer 201 and the first buffer layer 203 is close.
  • the C atom concentration in the first bonding layer 201 gradually increases as the thickness of the first bonding layer 201 increases.
  • the atomic concentration of C in the first bonding layer 201 gradually decreases as the thickness of the first bonding layer 201 increases, or gradually increases first and then gradually decreases.
  • each element in the first bonding layer 201 remains consistent at different thickness positions, and has a uniformly distributed atomic concentration.
  • the thickness of the first adhesive layer 202 and the first buffer layer 203 cannot be too large.
  • the thickness of the first adhesion layer 202 is The thickness of the first buffer layer 203 is
  • the thickness of the first bonding layer 201 is greater than the thickness of the first adhesion layer 202 and the first buffer layer 203, so as to ensure that When the bonding layer is bonded, the first bonding layer 201 has a sufficient bonding thickness. In a specific embodiment, the thickness of the first bonding layer 201 is greater than
  • the first bonding layer 201 may further include two or more sub-bond layers stacked, and materials between different sub-bond layers may be the same or different.
  • FIG. 4 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.
  • the semiconductor structure further includes: a second substrate 300, a second adhesion layer 402 is formed on a surface of the second substrate 300, and a second buffer layer 403 on the surface of the second adhesion layer 402 And a second bonding layer 401 on the surface of the second buffer layer 403; the second bonding layer 401 and the surface of the first bonding layer 201 are relatively bonded and fixed.
  • the second substrate 300 includes a second semiconductor substrate 301 and a second device layer 302 on a surface of the second semiconductor substrate 201.
  • the material of the second adhesion layer 402 is a dielectric material with a density greater than that of the second bonding layer 401.
  • the material of the second adhesion layer 402 may be at least one of silicon nitride, silicon oxynitride, and silicon oxide. Based on the reaction gas used in the chemical vapor deposition process and the needs of specific products, the second adhesion layer
  • the additional layer 402 may be doped with at least one of O, H, P, F and other elements.
  • the material of the second buffer layer 403 is a dielectric material having a density greater than that of the second buffer layer 403.
  • the material of the second buffer layer 403 is a dielectric material containing element C.
  • the second buffer layer 403 mainly includes Si, N, and C.
  • the second buffer layer 403 may also be doped with elements such as Si, N, O, H, P, and F. At least one of.
  • the material of the second bonding layer 401 is a dielectric material containing a C element.
  • the atomic concentration of C in the first bonding layer 201 is greater than the atomic concentration of C in the first buffer layer 203.
  • the second bonding layer 401 mainly includes Si, N, and C.
  • the second bonding layer 401 may be doped with Si, N, O, H, P, F, etc. based on the reaction gas used in the chemical vapor deposition process and the needs of specific products. At least one of the elements.
  • the atomic concentration of C in the second buffer layer 403 is smaller than the atomic concentration of C in the second bonding layer 401, so that the second buffer layer 403 and the second adhesion layer 402 have a relatively high atomic concentration. Adhesion.
  • the second adhesion layer 402 is The thickness of the second bonding layer 401 is greater than
  • Both the second bonding layer 401 and the first bonding layer 201 contain C, so that more silicon-oxygen bonds are formed on the bonding interface, which has a stronger bonding force.
  • a bonding force between the second bonding layer 401 and the first bonding layer 201 is greater than 1.7 J / M 2 .
  • the semiconductor structure may include more than three substrates, and adjacent substrates are bonded through an adhesion layer and a bonding layer in a specific embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention.
  • the semiconductor structure further includes: a first bonding pad 501 penetrating through the first bonding layer 201, a first buffer layer 203, and a first adhesion layer 202; penetrating the second bonding
  • the second bonding pad 502 of the layer 401, the second buffer layer 403, and the second adhesive layer 402; the surface of the second bonding layer 401 and the surface of the first bonding layer 201 are relatively bonded and fixed, and the first A bonding pad 501 and a second bonding pad 502 are oppositely connected to each other.
  • the first bonding pad 501 and the second bonding pad 502 may be connected to a semiconductor device and a metal interconnection layer in the first device layer 102 and the second device layer 302, respectively.
  • the materials of the first bonding pad 501 and the second bonding pad 502 may be metal materials such as Cu and W.
  • the first bonding layer 201 and the second bonding layer 401 contain C, which can effectively block the material of the first bonding pad 501 and the second bonding pad 502 from diffusing at the bonding interface, thereby improving the Performance of semiconductor structures.
  • the semiconductor structure further includes a third substrate 600, a third adhesion layer 702 on one side surface of the third substrate 600, and the third adhesive layer 702.
  • the third buffer layer 703 on the surface of the layer 702 and the third bonding layer 701 on the surface of the third buffer layer 703, the fourth adhesion layer 802 on the opposite surface of the third substrate 600, and the fourth adhesion layer 802
  • the third bonding layer 701 and the surface of the first bonding layer 201 are relatively bonded and fixed
  • the fourth bonding layer 801 and the second bonding layer 401 are surface-bonded and fixed to form a three-layer bonding structure.
  • materials and structures of the layer 801 please refer to the description of the material and structure of the first adhesion layer 202, the first buffer layer 203, and the first bonding layer 201 in the above specific implementations, respectively, and details are not described herein.
  • the semiconductor structure further includes: a third bonding pad 704 penetrating through the third bonding layer 701, a third buffer layer 703, and a third adhesive layer 702, penetrating the fourth bonding A fourth bonding pad 804 of the layer 801, a fourth buffer layer 803, and a fourth adhesive layer 802, the third bonding pad 704 is bonded to the first bonding pad 501, and the fourth bonding pad 804 Bonded to the second bonding pad 502.
  • the semiconductor structure may also be a bonding structure with more than four layers.

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Abstract

本发明涉及一种半导体结构及其形成方法，所述半导体结构包括：第一基底；位于所述第一基底表面的第一粘附层；位于所述第一粘附层表面的第一缓冲层；位于所述第一缓冲层表面的第一键合层，所述第一粘附层和第一缓冲层的致密度均大于所述第一键合层的致密度。所述半导体结构的第一粘附层与所述第一基底以及第一缓冲层之间、第一缓冲层与第一键合层之间具有较高的粘附性，有利于提高半导体结构的性能。

Description

半导体结构及其形成方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
在3D的芯片技术平台中，通常会将两片及以上形成有半导体器件的晶圆通过晶圆键合技术进行键合，以提高芯片的集成度。现有的晶圆键合技术，在晶圆键合面上形成键合薄膜，两层晶圆之间通过键合薄膜表面键合实现晶圆键合。
现有技术中，通常采用氧化硅和氮化硅薄膜作为键合薄膜，键合强度不够，导致工艺过程中容易出现缺陷，产品良率受到影响。
并且，键合薄膜内还形成有金属连接结构，在混合键合的过程中，所述金属连接结构容易在键合界面出现扩散现象，导致产品性能受到影响。
因此，如何提高晶圆键合的质量，是目前亟待解决的问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体结构及其形成方法，以提高键合质量。
为解决上述问题，本发明提供一种半导体结构，包括：第一基底；位于所述第一基底表面的第一粘附层；位于所述第一粘附层表面的第一缓冲层；位于所述第一缓冲层表面的第一键合层，所述第一粘附层和第一缓冲层的致密度均大于所述第一键合层的致密度。
可选的，所述第一键合层和所述第一缓冲层的材料均为包含C元素的介质材料，且所述第一键合层内C的原子浓度大于所述第一缓冲层内C的原子浓度。
可选的，所述第一键合层内C的原子浓度大于35％，所述第一缓冲层内C的原子浓度为0～50％。
可选的，所述第一键合层内，C的原子浓度随所述第一键合层厚度增加而增大；所述第一缓冲层内，C的原子浓度随所述第一缓冲层厚度增加而增大。
可选的，所述第一粘附层的材料包括氮化硅、氮氧化硅以及氧化硅中的至少一种。
可选的，所述第一键合层的材料还包括Si和N。
可选的，所述第一缓冲层的材料还包括Si和N。
可选的，所述第一粘附层的厚度为
Figure PCTCN2018093694-appb-000001
所述第一缓冲层的厚度为
Figure PCTCN2018093694-appb-000002
可选的，还包括：第二基底，所述第二基底表面形成有第二粘附层、位于所述第二粘附层表面的第二缓冲层，位于所述第二缓冲层表面的第二键合层；所述第二粘附层和第二缓冲层的致密度均大于所述第二键合层的致密度；所述第二键合层与所述第一键合层表面相对键合固定。
可选的，所述第二键合层与所述第一键合层的材料相同，所述第二缓冲层与所述第一缓冲层的材料相同，所述第二粘附层与所述第一粘附层的材料相同。
可选的，还包括：贯穿所述第一键合层、所述第一缓冲层和所述第一粘附层的第一键合垫；贯穿所述第二键合层、所述第二缓冲层和所述第二粘附层的第二键合垫；所述第一键合垫与所述第二键合垫相对键合连接。
为解决上述问题，本发明的具体实施方式还提供一种半导体结构的形成方法，包括：提供第一基底；在所述第一基底表面形成第一粘附层；对所述第一粘附层进行等离子体轰击，以提高致密度；在所述第一粘附层表面形成第一缓冲层；在所述第一缓冲层表面形成第一键合层，所述第一粘附层和第一缓冲层的致密度均大于所述第一键合层的致密度。
可选的，进行所述等离子体轰击之前，所述第一粘附层含有H键；在所述等离子体轰击步骤中，采用含N等离子体进行轰击，以减少所述第一粘附层中的H键。
可选的，所述第一键合层和所述第一缓冲层的材料均为包含C元素的介质材料，且所述第一键合层内C的原子浓度大于所述第一缓冲层内C的原子浓度。
可选的，所述第一键合层的材料还包括Si和N。
可选的，所述第一缓冲层的材料还包括Si和N。
可选的，所述第一粘附层的材料包括氮化硅、氮氧化硅以及氧化硅中的至少一种。
可选的，所述第一粘附层的厚度为
Figure PCTCN2018093694-appb-000003
所述第一缓冲层的厚度为
Figure PCTCN2018093694-appb-000004
本发明的半导体结构的第一基底与第一键合层之间具有第一粘附层和第一缓冲层，所述第一粘附层和第一缓冲层的致密度大于第一键合层致密度，从而提高第一粘附层与第一基底、第一粘附层与第一缓冲层以及第一缓冲层与第一键合层之间的粘附力，避免断裂。且所述第一键合层在键合后也能在键合表面具有较强的键合力，能够阻挡金属材料在键合界面的扩散，从而提高形成的半导体结构的性能。
附图说明
图1至图4为本发明一具体实施方式的半导体结构的形成过程的结构示意图；
图5为本发明一具体实施方式的半导体结构的结构示意图；
图6为本发明一具体实施方式的半导体结构的结构示意图。
具体实施方式
下面结合附图对本发明提供的半导体结构及其形成方法的具体实施方式做详细说明。
请参考图1至图4，为本发明一具体实施方式的半导体结构的形成过程的结构示意图。
请参考图1，提供第一基底100。
所述第一基底100包括第一半导体衬底101、形成于所述第一半导体衬底101表面的第一器件层102。
所述第一半导体衬底101可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等；根据器件的实际需求，可以选择合适的第一半导体衬底101，在此 不作限定。该具体实施方式中，所述第一半导体衬底101为单晶硅晶圆。
所述第一器件层102包括形成于所述半导体衬底101上的半导体器件、连接所述半导体器件的金属互连结构、覆盖所述半导体器件以及金属互连结构的介质层等，所述介质层通常为氧化硅、氮化硅或氮氧化硅。所述第一器件层102可以为多层或单层结构。在一个具体实施方式中，所述第一器件层102包括介质层以及形成于介质层内的3D NAND结构。
请参考图2，在所述第一基底100表面依次形成第一粘附层202、位于所述第一粘附层202表面的第一缓冲层203和位于所述第一缓冲层203表面的第一键合层201。
可以分别采用化学气相沉积工艺，依次形成所述第一粘附层202、第一缓冲层103和第一键合层201。该具体实施方式中，采用等离子体增强化学气相沉积工艺形成所述第一粘附层202、第一缓冲层203和第一键合层201。
所述第一粘附层202的材料为致密度大于所述第一键合层201致密度的介质材料。所述第一粘附层202的材料可以为氮化硅、氮氧化硅以及氧化硅中的至少一种，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一粘附层202内还可以掺杂有O、H、P、F等元素中的至少一种。
在一个具体实施方式中，所述第一粘附层202的材料为氮化硅，采用等离子增强化学气相沉积工艺形成所述第一粘附层202，采用的反应气体包括：SiH 4和NH 3，SiH 4和NH 3的流量比范围为(0.8～1.2)：1，射频功率范围为150W～300W。可以通过调整所述沉积工艺中的工艺参数，形成具有较高致密度的第一粘附层202。
在其他具体实施方式中，所述第一粘附层202的形成方法包括：采用沉积工艺在所述第一基底100表面形成粘附材料层，然后对所述粘附材料层进行等离子体轰击，以减少粘附材料层中H的含量，从而提高形成的第一粘附层202的致密度。所述等离子体轰击可以采用含N气体，例如N 2、NH 3等。在一个具体实施方式中，所述等离子体轰击可以采用N 2作为等离子体源，射频功率为500W，轰击时间为30s。通过所述等离子体轰击可以去除所述第一粘附层202内的H，从而使得所述第一粘附层202的单位面积内拥有更多可以连接相 邻材料层的化学键，例如Si-、N-等，从而提高所述第一粘附层202与第一器件层102、第一缓冲层203之间的粘附力。
所述第一缓冲层203的材料为包含C元素的介质材料，在一个具体实施方式中，所述第一缓冲层203主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一缓冲层203内还可以具有Si、N、O、H、P、F等元素中的至少一种。所述第一缓冲层203的致密度大于所述第一键合层201的致密度，在一个具体实施方式中，所述第一缓冲层203的致密度与所述第一粘附层202的致密度接近或相同。所述第一缓冲层203的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。由于所述第一缓冲层203的致密度较高，与所述第一粘附层202的界面上化学键的密度较大，因此与所述第一粘附层202之间具有较高的粘附性。
在一个具体实施方式中，采用等离子体增强化学气相沉积工艺形成所述第一缓冲层203，采用的反应气体包括：三甲基硅烷或四甲基硅烷中的一种以及NH 3，三甲基硅烷或四甲基硅烷与NH 3的流量比范围为1:(2～4)，射频功率范围为200W～500W。可以通过调整沉积工艺参数，调整所述第一缓冲层203的致密度，以及所述第一缓冲层203内的C的原子浓度。
所述第一键合层201的材料为包含C元素的介质材料，且所述第一键合层201内C的原子浓度大于所述第一缓冲层203内C的原子浓度。在一个具体实施方式中，所述第一键合层201主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一键合层201内还可以具有Si、N、O、H、P、F等元素中的至少一种。所述第一键合层201的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。所述第一键合层201的成分与所述第一缓冲层203的成分接近或相同，因此，在所述第一缓冲层203表面形成所述第一键合层201，可以使得所述第一键合层201与所述第一缓冲层203之间具有较高的粘附力。材料层内的C的原子浓度过高，会导致与其他材料层之间的粘附力下降。所述第一缓冲层203内的C的原子浓度小于所述第一键合层201内C的原子浓度，与直接在所述第一粘附层202表面形成第一键合层201相比，所述第一缓冲层203与所述第一粘附层202之 间的粘附力更高。
在一个具体实施方式中，采用等离子体增强化学气相沉积工艺形成所述第一键合层201，采用的反应气体包括：三甲基硅烷或四甲基硅烷中的至少一种以及NH 3，三甲基硅烷或四甲基硅烷与NH 3的流量比范围为(1.6～2.4):1，射频功率范围为500W～1100W。
所述第一键合层201中的C能够有效提高所述第一键合层201在键合过程中，与其他键合层之间的键合力。C浓度越高，与其他键合层之间进行键合时产生的键合力越大。在一个具体实施方式中，所述第一键合层201中，C的原子浓度大于35％。
所述第一缓冲层203中C的原子浓度小于所述第一键合层201中C的原子浓度，从而使得所述第一缓冲层203的材料结构与所述第一粘附层202的更为接近。在一个具体实施方式中，所述第一缓冲层203的C的原子浓度为0～50％。
由于所述第一键合层201中含有较高浓度的C元素，会导致第一键合层201的致密度较低，本申请的具体实施方式中，在所述第一键合层201与第一基底100之间形成有致密度更高的第一粘附层202、第一缓冲层203，且第一缓冲层203内的C的原子浓度低于所述第一键合层201内C的原子浓度，可以提高各层之间的粘附力。
通过控制所述第一键合层201、第一缓冲层203和第一粘附层202的形成工艺参数，可以调整所述第一键合层201和第一粘附层202内各组分的浓度，对各材料层之间粘附力以及介电系数进行调整。
由于不同材料层之间的粘附力与界面两侧的材料组分相关，材料组分越接近，粘附力越强。为了进一步增强所述第一粘附层202与所述第一器件层102之间的粘附力，可以在形成所述第一粘附层202的过程中，逐渐调整工艺参数，使得所述第一粘附层202内的组分浓度逐渐发生变化，使得所述第一器件层102与所述第一粘附层202界面两侧的材料组分接近。在一个具体实施方式中，在形成所述第一粘附层202的过程中，随着第一粘附层202厚度的增加，通过调整沉积工艺的参数，使得第一粘附层202内的Si的原子浓度随第一粘附层 202厚度增加而逐渐改变。在其他具体实施方式中，根据所述第一器件层102表面材料的不同，也可以对所述第一粘附层202内的其他成分浓度进行调整。在其他具体实施方式中，也可以在形成所述第一粘附层202的过程中，保持沉积工艺参数不变，使得第一粘附层202内的各元素的原子浓度在不同厚度位置处保持一致。
为了进一步增强所述第一粘附层202与所述第一缓冲层203之间的粘附力，可以在形成所述第一缓冲层203的过程中，逐渐调整工艺参数，使得所述第一缓冲层203内的组分浓度逐渐发生变化，使得所述第一缓冲层203与所述第一粘附层202界面两侧的材料组分接近。在一个具体实施方式中，在形成所述第一缓冲层203的过程中，随着第一缓冲层203厚度的增加，通过调整沉积工艺的参数，使得C的原子浓度随第一缓冲层203厚度增加而逐渐增大。在其他具体实施方式中，也可以使得C的原子浓度随第一缓冲层203厚度增加而逐渐减小或者先逐渐增大再逐渐减小。在其他具体实施方式中，在形成所述第一缓冲层203的过程中，保持沉积工艺参数不变，使得第一缓冲层203中各元素的原子浓度在不同厚度位置处分别保持一致。
为了进一步增强所述第一缓冲层203与所述第一键合层201之间的粘附力，可以在形成所述第一键合层201的过程中，逐渐调整工艺参数，使得所述第一键合层201内的组分浓度逐渐发生变化，使得所述第一键合层201与所述第一缓冲层203界面两侧的材料组分接近。在一个具体实施方式中，在形成所述第一键合层201的过程中，随着第一键合层201厚度的增加，通过调整沉积工艺的参数，使得C的原子浓度随第一键合层201厚度增加而逐渐增大。在其他具体实施方式中，也可以使得C的原子浓度随第一键合层201厚度增加而逐渐减小或者先逐渐增大再逐渐减小。在其他具体实施方式中，在形成所述第一键合层201的过程中，保持沉积工艺参数不变，使得第一键合层201中各元素在不同厚度位置处保持一致。
为了使得所述第一粘附层202和第一缓冲层203各厚度处均具有较高的致密度，为了在形成所述第一粘附层202的离子轰击过程中，能够尽可能多的减少所述第一粘附层202内的H，使所述第一粘附层202各厚度处的致密性均得 到提高，所述第一粘附层202的厚度不能过大。在一个具体实施方式中，所述第一粘附层202的厚度为
Figure PCTCN2018093694-appb-000005
所述第一缓冲层203的厚度为
Figure PCTCN2018093694-appb-000006
Figure PCTCN2018093694-appb-000007
在一些具体实施方式中，所述第一键合层201的厚度大于所述第一粘附层202、第一缓冲层203的厚度，以确保在将所述第一键合层201与其他键合层进行键合时，所述第一键合层201具有足够的键合厚度。在一个具体实施方式中，所述第一键合层201的厚度大于
Figure PCTCN2018093694-appb-000008
在其他具体实施方式中，所述第一键合层201还可以包括两层以上堆叠的子键合层。不同子键合层的材料可以相同也可以不同。
上述具体实施方式的半导体结构的第一基底与第一键合层之间具有第一粘附层和第一缓冲层，所述第一粘附层和第一缓冲层的致密度大于第一键合层致密度，从而提高第一粘附层与第一基底之间的粘附力，以及第一缓冲层与第一键合层之间的粘附力；并且所述第一缓冲层与第一粘附层均具有较高的致密度，所述第一缓冲层与第一粘附层之间也具有较高粘附力，可以避免所述半导体结构发生断裂等问题。并且所述第一键合层在键合后也能在键合表面具有较强的键合力，能够阻挡金属材料在键合界面的扩散，从而提高形成的半导体结构的性能。
请参考图3，在另一具体实施方式中，还包括：提供第二基底300；在所述第二基底300表面形成第二粘附层402、位于所述第二粘附层402表面的第二缓冲层403以及位于所述第二缓冲层403表面的第二键合层401。
所述第二基底300包括第二半导体衬底301以及位于所述第二半导体衬底201表面的第二器件层302。
所述第二粘附层402的材料为致密度大于所述第二键合层401致密度的介质材料。所述第二粘附层402的材料可以为氮化硅、氮氧化硅以及氧化硅中的至少一种，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第二粘附层402内还可以具有O、H、P、F等元素中的至少一种。
所述第二缓冲层403的材料为致密度大于所述第二缓冲层403致密度的介质材料。所述第二缓冲层403的材料为包含C元素的介质材料，在一个具体实 施方式中，所述第二缓冲层403主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第二缓冲层403内还可以具有Si、N、O、H、P、F等元素中的至少一种。
所述第二键合层401的材料为包含C元素的介质材料，且所述第一键合层201内C的原子浓度大于所述第一缓冲层203内C的原子浓度。在一个具体实施方式中，所述第二键合层401主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第二键合层401内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。材料层内的C的原子浓度过高，会导致与其他材料层之间的粘附力下降。所述第二缓冲层403内的C的原子浓度小于所述第二键合层401内C的原子浓度，与直接在所述第二粘附层402表面形成第二键合层401相比，所述第二缓冲层403与所述第二粘附层402之间的粘附力更高。
采用化学气相沉积工艺在所述第二器件层302表面依次形成所述第二粘附层402、第二缓冲层403和第二键合层401。所述第二粘附层402、第二缓冲层403和第二键合层401的具体材料、结构及形成方法请参考上述具体实施方式中的第一粘附层202、第一缓冲层203和第一键合层201的描述，在此不再赘述。在一个具体实施方式中，所述第二粘附层402与第一粘附层202的材料、结构及形成方法相同；所述第二缓冲层403和第一缓冲层203的材料、结构及形成方法相同，所述第二键合层401和第一键合层201的材料、结构及形成方法均相同。
在一个具体实施方式中，所述第二粘附层402的厚度为
Figure PCTCN2018093694-appb-000009
所述第二缓冲层403的厚度为
Figure PCTCN2018093694-appb-000010
所述第二键合层401的厚度大于
Figure PCTCN2018093694-appb-000011
请参考图4，将所述第二键合层401所述第一键合层201表面相对键合固定。
所述第二键合层401与第一键合层201内均含有C，部分C以-CH 3的形式存在，-CH 3更易被氧化为-OH，并在键合过程中形成Si-O键，使得在键合界面上能够形成更多的硅氧键，从而形成较强的键合力。在一个具体实施方式中，所述第二键合层401与第一键合层201之间的键合力大于2J/M 2。而现有 技术中采用不含C的键合层进行键合，通常键合力小于1.5J/M 2。
在一个具体实施方式中，所述第一基底100为形成有3D NAND存储结构的基底，而所述第二基底200为形成有外围电路的基底。
在其他具体实施方式中，还可以在基底的两侧表面均形成上述粘附层和键合层，以实现多层键合。
请参考图5，在另一具体实施方式中，还包括：形成贯穿所述第一键合层201、第一缓冲层203和第一粘附层202的第一键合垫501；形成贯穿所述第二键合层401、第二缓冲层403和第二粘附层402的第二键合垫502；在将所述第二键合层401表面与所述第一键合层201表面相对键合固定的同时，将所述第一键合垫501与第二键合垫502相对键合连接。
所述第一键合垫501和第二键合垫502可以分别连接至所述第一器件层102和第二器件层302内的半导体器件以及金属互连层。
所述第一键合垫501的形成方法包括：对所述第一键合层201、第一缓冲层203和第一粘附层202进行图形化，形成贯穿所述第一键合层201、第一缓冲层203和第一粘附层202的开口；在所述开口内填充金属材料，并进行平坦化，形成填充满所述开口的第一键合垫501。采用相同的方法在所述第二键合层401、第二缓冲层403第二粘附层402内形成所述第二键合垫502。将所述第一键合垫501与第二键合垫502键合连接，可以实现所述第一器件层102和第二器件层302内的半导体器件之间的电连接。
所述第一键合垫501和第二键合垫502的材料可以是Cu、W等金属材料。所述第一键合层201和第一键合层401内含有C，能够有效阻挡所述第一键合垫501和第二键合垫502的材料在键合界面发生扩散，从而提高所述半导体结构的性能。
上述具体实施方式，在基底表面形成粘附层、在粘附层表面形成缓冲层，再在所述缓冲层表面形成键合层，所述粘附层和缓冲层的致密度大于键合层致密度，从而提高粘附层、缓冲层与基底、键合层之间的粘附力且所述键合层在键合后也能在键合表面具有较强的键合力，能够阻挡金属材料在键合界面的扩散，从而提高形成的半导体结构的性能。
上述具体实施方式的半导体结构形成方法还用于多片基底键合。
请参考图6，在本发明一具体实施方式中，还包括提供第三基底600，在所述第三基底600的一侧表面依次形成第三粘附层702、第三缓冲层703以及第三键合层701，在另一侧相对表面上依次形成第四粘附层802、第四缓冲层803以及第四键合层801；将所述第三键合层701与第一键合层201表面相对键合固定，将所述第四键合层801与第二键合层401表面键合固定，形成三层键合结构。
所述第三粘附层702和第四粘附层802的材料、结构及形成方法，所述第三缓冲层703和第四缓冲层803材料、结构及形成方法，所述第三键合层701和第四键合层801材料、结构以及形成方法，请分别参考上述具体实施方式中，第一粘附层202、第一缓冲层203以及第一键合层201的材料、结构及形成方法，在此不再赘述。
该具体实施方式中，所述半导体结构的形成方法还包括：形成贯穿所述第三键合层701、第三缓冲层703以及第三粘附层702的第三键合垫704，形成贯穿所述第四键合层801、第四缓冲层803以及第四粘附层802的第四键合垫804，将所述第三键合垫704与第一键合垫501键合连接，将所述第四键合垫804与第二键合垫502键合连接。
在其他具体实施方式中，还可以采用上述方法形成四层以上的键合结构。
需说明的是，在本发明的技术方案中，半导体结构中各个基底内的半导体器件类型并不应局限于所给实施例，除了3D NAND之外，其可以为CMOS电路、CIS电路、TFT电路等等。
本发明的具体实施方式还提供一种半导体结构。
请参考图2，为本发明一具体实施方式的半导体结构的结构示意图。
所述半导体结构，包括：第一基底100；位于所述第一基底100表面的第一粘附层202；位于所述第一粘附层202表面的第一缓冲层203；位于所述第一缓冲层203表面的第一键合层201。
所述第一基底100包括第一半导体衬底101、形成于所述第一半导体衬底101表面的第一器件层102。
所述第一半导体衬底101可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等；根据器件的实际需求，可以选择合适的第一半导体衬底101，在此不作限定。该具体实施方式中，所述第一半导体衬底101为单晶硅晶圆。
所述第一器件层102包括形成于所述半导体衬底101上的半导体器件、连接所述半导体器件的金属互连结构、覆盖所述半导体器件以及金属互连结构的介质层等。所述第一器件层102可以为多层或单层结构。在一个具体实施方式中，所述第一器件层102包括介质层以及形成于介质层内的3D NAND结构。
所述第一粘附层202的材料为致密度大于所述第一键合层201致密度的介质材料。所述第一粘附层202的材料可以为氮化硅、氮氧化硅以及氧化硅中的至少一种，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一粘附层202内还可以掺杂有O、H、P、F等元素中的至少一种。在一个具体实施方式中，所述第一粘附层202为具有高致密度的SiN。
所述第一缓冲层203的材料为包含C元素的介质材料，在一个具体实施方式中，所述第一缓冲层203主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一缓冲层203内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。该具体实施方式中，所述第一缓冲层203的致密度大于所述第一键合层201的致密度，所述第一缓冲层203的致密度与所述第一粘附层202的致密度接近或相同。所述第一缓冲层203的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。由于所述第一缓冲层203的致密度较高，与所述第一粘附层202的界面上化学键的密度较大，因此与所述第一粘附层202之间具有较高的粘附性。
所述第一键合层201的材料为包含C元素的介质材料。所述第一键合层201内C的原子浓度大于所述第一缓冲层203内C的原子浓度。在一个具体实施方式中，所述第一键合层201主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一键合层201内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。所述第一键合层201的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。所述第一键合层201的成分与所述第一缓冲层203的成分接近或相同，因此，在 所述第一键合层201位于所述第一缓冲层203表面，可以使得所述第一键合层201与所述第一缓冲层203之间具有较高的粘附力。材料层内的C的原子浓度过高，会导致与其他材料层之间的粘附力下降。所述第一缓冲层203内的C的原子浓度小于所述第一键合层201内C的原子浓度，与直接在所述第一粘附层202表面形成第一键合层201相比，所述第一缓冲层203与所述第一粘附层202之间的粘附力更高。
所述第一键合层201中的C能够有效提高所述第一键合层201在键合过程中，与其他键合层之间的键合力。C浓度越高，与其他键合层之间进行键合时产生的键合力越大。在一个具体实施方式中，所述第一键合层201中，C的原子浓度大于35％。
所述第一缓冲层203中C的原子浓度小于所述第一键合层201中C的原子浓度，从而使得所述第一缓冲层203的材料结构与所述第一粘附层202的更为接近。在一个具体实施方式中，所述第一缓冲层203的C的原子浓度为0～50％。
由于所述第一键合层201中含有较高浓度的C元素，会导致第一键合层201的致密度较低，本申请的具体实施方式中，在所述第一键合层201与第一基底100之间形成有致密度更高的第一粘附层202、第一缓冲层203，且第一缓冲层203内的C的原子浓度低于所述第一键合层201内C的原子浓度，可以提高各层之间的粘附力。
由于不同材料层之间的粘附力与界面两侧的材料组分相关，材料组分越接近，粘附力越强。为了进一步增强所述第一粘附层202与所述第一器件层102之间的粘附力，所述第一粘附层202内的组分浓度随厚度逐渐发生变化，使得所述第一器件层102与所述第一粘附层202界面两侧的材料组分接近。在一个具体实施方式中，所述第一粘附层202内的Si的原子浓度随第一粘附层202厚度增加而逐渐改变。在其他具体实施方式中，根据所述第一器件层102表面材料的不同，所述第一粘附层202内的其他成分浓度也可以随厚度进行变化。在其他具体实施方式中，也可以使得第一粘附层202内的各元素的原子浓度在不同厚度位置处保持一致。
为了进一步增强所述第一粘附层202与所述第一缓冲层203之间的粘附力，所述第一缓冲层203与所述第一粘附层202界面两侧的材料组分接近。在一个具体实施方式中，第一缓冲层203内C的原子浓度随第一缓冲层203厚度增加而逐渐增大。在其他具体实施方式中，所述第一缓冲层203内C的的原子浓度随第一缓冲层203厚度增加而逐渐减小或者先逐渐增大再逐渐减小。在其他具体实施方式中，所述第一缓冲层203中各元素的原子浓度在不同厚度位置处分别保持一致。
为了进一步增强所述第一缓冲层203与所述第一键合层201之间的粘附力，所述第一键合层201内的组分浓度也可以随厚度逐渐变化，使得所述第一键合层201与所述第一缓冲层203界面两侧的材料组分接近。在一个具体实施方式中，随着第一键合层201厚度的增加，第一键合层201内的C原子浓度随第一键合层201厚度增加而逐渐增大。在其他具体实施方式中，第一键合层201内的C的原子浓度随第一键合层201厚度增加而逐渐减小或者先逐渐增大再逐渐减小。在其他具体实施方式中，所述第一键合层201中各元素在不同厚度位置处分别保持一致，具有均匀分布的原子浓度。
为了使得所述第一粘附层202和第一缓冲层203各厚度处均具有较高的致密度，所述第一粘附层202和第一缓冲层203的厚度不能过大。在一个具体实施方式中，所述第一粘附层202的厚度为
Figure PCTCN2018093694-appb-000012
所述第一缓冲层203的厚度为
Figure PCTCN2018093694-appb-000013
在一些具体实施方式中，所述第一键合层201的厚度大于所述第一粘附层202、第一缓冲层203的厚度，以确保在将所述第一键合层201与其他键合层进行键合时，所述第一键合层201具有足够的键合厚度。在一个具体实施方式中，所述第一键合层201的厚度大于
Figure PCTCN2018093694-appb-000014
在其他具体实施方式中，所述第一键合层201还可以包括两层以上堆叠的子键合层，不同子键合层之间的材料可以相同也可以不同。
请参考图4，为本发明另一具体实施方式的半导体结构的示意图。
该具体实施方式中，所述半导体结构还包括：第二基底300，所述第二基底300表面形成有第二粘附层402、位于所述第二粘附层402表面的第二缓冲 层403和位于所述第二缓冲层403表面的第二键合层401；所述第二键合层401与所述第一键合层201表面相对键合固定。
所述第二基底300包括第二半导体衬底301以及位于所述第二半导体衬底201表面的第二器件层302。
所述第二粘附层402的材料为致密度大于所述第二键合层401致密度的介质材料。所述第二粘附层402的材料可以为氮化硅、氮氧化硅以及氧化硅中的至少一种，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第二粘附层402内还可以掺杂有O、H、P、F等元素中的至少一种。
所述第二缓冲层403的材料为致密度大于所述第二缓冲层403致密度的介质材料。所述第二缓冲层403的材料为包含C元素的介质材料，在一个具体实施方式中，所述第二缓冲层403主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第二缓冲层403内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。
所述第二键合层401的材料为包含C元素的介质材料。所述第一键合层201内C的原子浓度大于所述第一缓冲层203内C的原子浓度。在一个具体实施方式中，所述第二键合层401主要包含Si、N和C。在其他具体实施方式中，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第二键合层401内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。所述第二缓冲层403内的C的原子浓度小于所述第二键合层401内C的原子浓度使得所述第二缓冲层403与所述第二粘附层402之间具有较高的粘附力。
所述第二粘附层402、第二缓冲层403和所述第二键合层401的具体材料与结构请参考上述具体实施方式中的第一粘附层202、第一缓冲层203和第一键合层201的描述，在此不再赘述。在一个具体实施方式中，所述第二粘附层402与第一粘附层202的材料、结构相同；第二缓冲层403与第一缓冲层203的材料、结构相同；所述第二键合层401和第一键合层201的材料、结构相同。在一个具体实施方式中，所述第二粘附层402的厚度为
Figure PCTCN2018093694-appb-000015
第二键合层401的厚度大于
Figure PCTCN2018093694-appb-000016
所述第二键合层401与第一键合层201内均含有C，使得在键合界面上形 成较多的硅氧键，具有较强的键合力。在一个具体实施方式中，所述第二键合层401与第一键合层201之间的键合力大于1.7J/M 2。
在其他具体实施方式中，所述半导体结构可以包括三个以上的基底，相邻基底之间均通过本发明具体实施方式中的粘附层和键合层进行键合。
请参考图5，为发明另一具体实施方式的半导体结构的结构示意图。
该具体实施方式中，所述半导体结构还包括：贯穿所述第一键合层201、第一缓冲层203和第一粘附层202的第一键合垫501；贯穿所述第二键合层401、第二缓冲层403和第二粘附层402的第二键合垫502；所述第二键合层401表面与所述第一键合层201表面相对键合固定且所述第一键合垫501与第二键合垫502相对键合连接。
所述第一键合垫501和第二键合垫502可以分别连接至所述第一器件层102和第二器件层302内的半导体器件以及金属互连层。
所述第一键合垫501和第二键合垫502的材料可以是Cu、W等金属材料。所述第一键合层201和第二键合层401内含有C，能够有效阻挡所述第一键合垫501和第二键合垫502的材料在键合界面发生扩散，从而提高所述半导体结构的性能。
请参考图6，在本发明一具体实施方式中，所述半导体结构还包括第三基底600，位于所述第三基底600的一侧表面的第三粘附层702、位于所述第三粘附层702表面的第三缓冲层703以及位于第三缓冲层703表面的第三键合层701，位于第三基底600的另一侧相对表面的第四粘附层802、位于所述第四粘附层802表面的第四缓冲层803以及位于第四缓冲层803表面的第四键合层801；所述第三键合层701与第一键合层201表面相对键合固定，所述第四键合层801与第二键合层401表面键合固定，构成三层键合结构。
所述第三粘附层702和第四粘附层802的材料、结构，所述第三缓冲层703和第四缓冲层803材料、结构，所述第三键合层701和第四键合层801材料、结构，请分别参考上述具体实施方式中第一粘附层202、第一缓冲层203以及第一键合层201的材料、结构的描述，在此不再赘述。
该具体实施方式中，所述半导体结构还包括：贯穿所述第三键合层701、 第三缓冲层703以及第三粘附层702的第三键合垫704，贯穿所述第四键合层801、第四缓冲层803以及第四粘附层802的第四键合垫804，所述第三键合垫704与第一键合垫501键合连接，所述第四键合垫804与第二键合垫502键合连接。
在其他具体实施方式中，所述半导体结构还可以为四层以上的键合结构。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (18)

  1. 一种半导体结构，其特征在于，包括：
    第一基底；
    位于所述第一基底表面的第一粘附层；
    位于所述第一粘附层表面的第一缓冲层；
    位于所述第一缓冲层表面的第一键合层，所述第一粘附层和第一缓冲层的致密度均大于所述第一键合层的致密度。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述第一键合层和所述第一缓冲层的材料均为包含C元素的介质材料，且所述第一键合层内C的原子浓度大于所述第一缓冲层内C的原子浓度。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述第一键合层内C的原子浓度大于35％，所述第一缓冲层内C的原子浓度为0～50％。
  4. 根据权利要求2所述的半导体结构，其特征在于，所述第一键合层内，C的原子浓度随所述第一键合层厚度增加而增大；所述第一缓冲层内，C的原子浓度随所述第一缓冲层厚度增加而增大。
  5. 根据权利要求1所述的半导体结构，其特征在于，所述第一粘附层的材料包括氮化硅、氮氧化硅以及氧化硅中的至少一种。
  6. 根据权利要求2所述的半导体结构，其特征在于，所述第一键合层的材料还包括Si和N。
  7. 根据权利要求2所述的半导体结构，其特征在于，所述第一缓冲层的材料还包括Si和N。
  8. 根据权利要求1所述的半导体结构，其特征在于，所述第一粘附层的厚度为
    Figure PCTCN2018093694-appb-100001
    所述第一缓冲层的厚度为
    Figure PCTCN2018093694-appb-100002
  9. 根据权利要求1所述的半导体结构，其特征在于，还包括：第二基底，所述第二基底表面形成有第二粘附层、位于所述第二粘附层表面的第二缓冲层，位于所述第二缓冲层表面的第二键合层；所述第二粘附层和第二缓冲层的致密度均大于所述第二键合层的致密度；所述第二键合层与所述第一键合层表面相对键合固定。
  10. 根据权利要求9所述的半导体结构，其特征在于，所述第二键合层与所述第一键合层的材料相同，所述第二缓冲层与所述第一缓冲层的材料相同，所述第二粘附层与所述第一粘附层的材料相同。
  11. 根据权利要求9所述的半导体结构，其特征在于，还包括：贯穿所述第一键合层、所述第一缓冲层和所述第一粘附层的第一键合垫；贯穿所述第二键合层、所述第二缓冲层和所述第二粘附层的第二键合垫；所述第一键合垫与所述第二键合垫相对键合连接。
  12. 一种半导体结构的形成方法，其特征在于，包括：
    提供第一基底；
    在所述第一基底表面形成第一粘附层；
    对所述第一粘附层进行等离子体轰击，以提高致密度；
    在所述第一粘附层表面形成第一缓冲层；
    在所述第一缓冲层表面形成第一键合层，所述第一粘附层和第一缓冲层的致密度均大于所述第一键合层的致密度。
  13. 根据权利要求12所述的半导体结构的形成方法，其特征在于，进行所述等离子体轰击之前，所述第一粘附层含有H键；在所述等离子体轰击步骤中，采用含N等离子体进行轰击，以减少所述第一粘附层中的H键。
  14. 根据权利要求12所述的半导体结构的形成方法，其特征在于，所述第一键合层和所述第一缓冲层的材料均为包含C元素的介质材料，且所述第一键合层内C的原子浓度大于所述第一缓冲层内C的原子浓度。
  15. 根据权利要求14所述的半导体结构的形成方法，其特征在于，所述第一键合层的材料还包括Si和N。
  16. 根据权利要求14所述的半导体结构的形成方法，其特征在于，所述第一缓冲层的材料还包括Si和N。
  17. 根据权利要求12所述的半导体结构的形成方法，其特征在于，所述第一粘附层的材料包括氮化硅、氮氧化硅以及氧化硅中的至少一种。
  18. 根据权利要求12所述的半导体结构的形成方法，其特征在于，所述第一粘 附层的厚度为
    Figure PCTCN2018093694-appb-100003
    所述第一缓冲层的厚度为
    Figure PCTCN2018093694-appb-100004
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