WO2020082547A1 - Shaping circuit and display device - Google Patents

Abstract

A shaping circuit and a display device. The shaping circuit comprises: a gate switch voltage input end (Vg-in) and a gate switch voltage output end (Vg-out); a first switch circuit (10), configured to be turned on upon receiving a first timing control signal (CV1) so as to control the gate switch voltage input end (Vg-in) to be connected to the gate switch voltage output end (Vg-out), and to output a received gate-on voltage; a second switch circuit (20), configured to be turned on upon receiving a second timing control signal (CV2); a discharge circuit (30), configured to release the input electric energy when the second switch circuit (20) is turned on; and a current limiting circuit (40), configured to reduce the release speed of the electric energy input from the gate switch voltage output end (Vg-out).

Description

 Angle cutting circuit and display device The

Related patents

This application requires October 24, 2018, the application number is 201821735153.0, the priority of the application for the Chinese patent application titled "Chamfering Circuit and Display Device", the full text of which is hereby incorporated by reference.

Technical field

The present application relates to the technical field of electronic circuits, in particular to a corner-cutting circuit and a display device.

Background technique

At present, in the display device, when driving the display panel, most of the devices are provided with a chamfering process for the gate-on voltage output to the gate driver to reduce the gate-on voltage and the gate-off voltage when the thin film transistor in the display panel is off The voltage difference between them reduces the impact on the data signal voltage.

However, when the high-level gate turn-on voltage suddenly changes to the low-level gate turn-off voltage, the pixel voltage will also change suddenly, causing the display panel to flicker.

Application content

The main purpose of the present application is to propose an angle-cut circuit and a display device, aiming to improve the brightness consistency of the display device.

In order to achieve the above object, the present application proposes an angle-cutting circuit, which is applied to a display device. The display device includes a timing controller that outputs a first timing control signal and a second timing control signal of opposite polarities. include:

Gate switch voltage input terminal and gate switch voltage output terminal;

The first switch circuit is configured to be turned on when the first timing control signal is received, to control the gate switch voltage input terminal to be electrically connected to the gate switch voltage output terminal, and to connect the gate switch voltage The gate turn-on voltage received at the input terminal is output to the gate switch voltage output terminal; the second switch circuit is set to be turned on when the second timing control signal is received;

A second switch circuit configured to be turned on when the second timing control signal is received;

A discharge circuit configured to release electrical energy connected to the voltage output of the gate switch when the second switch circuit is turned on; and,

The current limiting circuit is configured to reduce the speed of releasing electric energy connected to the voltage output end of the gate switch.

Optionally, the current limiting circuit includes a first inductor, the first inductor is arranged in series between the gate switch voltage output terminal and the input terminal of the second switch circuit, and the first inductor is provided In order to reduce the release speed of the electric energy connected to the voltage output end of the gate switch.

Optionally, the first switch circuit includes a first switch tube, a second switch tube, and a voltage dividing unit, the controlled end of the first switch tube is used to receive the first timing signal, and the first switch The output end of the tube is connected to the first input end of the voltage dividing unit, and the second input end of the voltage dividing unit is interconnected with the gate switch voltage input end and the input end of the second switch tube; The output terminal of the second switch tube is connected to the gate switch voltage output terminal, and the controlled terminal of the second switch tube is connected to the output terminal of the voltage dividing unit.

Optionally, the voltage dividing unit includes a first resistor and a second resistor, the first terminal of the first resistor is the second input terminal of the voltage dividing unit, the second terminal of the first resistor and the second resistor The first terminal of the second resistor is connected, and the common terminal of the first resistor and the second resistor is the output terminal of the voltage dividing unit; the second terminal of the second resistor is the first terminal of the voltage dividing unit Input.

Optionally, the second switch circuit includes a third switch tube, an input terminal of the third switch tube and an input terminal of the second switch circuit, an output terminal of the third switch tube is grounded, the The controlled end of the third switch tube is used to receive the second timing signal.

Optionally, the third switch tube is an N-type field effect transistor or an N-type thin film transistor.

Optionally, the discharge circuit further includes a third resistor, a first terminal of the third resistor is connected to the gate switch voltage output terminal, and a second terminal of the third resistor is connected to the second switch circuit Input connection.

Optionally, the third resistor is a variable resistor.

Optionally, the angle-cut circuit further includes a voltage stabilizing diode, a cathode of the voltage stabilizing diode is connected to one end of the first inductor, and an anode of the voltage stabilizing diode is connected to the input end of the second switching circuit .

The present application also proposes an angle-cutting circuit. The angle-cutting circuit includes:

Gate switch voltage input terminal and gate switch voltage output terminal;

A first switch circuit is provided in series between the gate switch voltage input terminal and the gate switch voltage output terminal, the first switch circuit is configured to be turned on when the first timing control signal is received, and Output the gate turn-on voltage received by the gate switch voltage input terminal to the gate switch voltage output terminal;

A second switch circuit configured to be turned on when a second timing control signal is received, the second timing control signal and the first timing control signal being pulse voltage signals of opposite polarities to each other;

The discharge circuit includes:

A first inductor, the first inductor is arranged in series between the gate switch voltage output terminal and the second switch circuit input terminal, the first inductor is set to reduce the gate switch voltage output terminal The release speed of the connected electrical energy;

A third resistor, a first terminal of the third resistor is connected to the gate switch voltage output terminal, and a second terminal of the third resistor is connected to the input terminal of the second switch circuit;

A voltage stabilizing diode, the cathode of the voltage stabilizing diode is connected to one end of the first inductor, and the anode of the voltage stabilizing diode is connected to the input end of the second switching circuit.

The present application also proposes a display device including the above-mentioned angle-cut circuit; the angle-cut circuit includes: a gate switch voltage input terminal and a gate switch voltage output terminal; a first switch circuit, which is arranged in series on the gate Between the pole switch voltage input terminal and the gate switch voltage output terminal, the first switch circuit is configured to turn on when the first timing control signal is received, and connect the gate switch voltage input terminal The received gate-on voltage is output to the gate switch voltage output terminal; the second switch circuit is set to be turned on when the second timing control signal is received; the discharge circuit is set to the second switch circuit When turned on, the electrical energy connected to the voltage output end of the gate switch is released; and, the current limiting circuit is set to reduce the speed of electrical energy release connected to the voltage output end of the gate switch.

Optionally, the current limiting circuit includes a first inductor, the first inductor is arranged in series between the gate switch voltage output terminal and the input terminal of the second switch circuit, and the first inductor is provided In order to reduce the release speed of the electric energy connected to the voltage output end of the gate switch.

Optionally, the first switch circuit includes a first switch tube, a second switch tube, and a voltage dividing unit, the controlled end of the first switch tube is used to receive the first timing signal, and the first switch The output end of the tube is connected to the first input end of the voltage dividing unit, and the second input end of the voltage dividing unit is interconnected with the gate switch voltage input end and the input end of the second switch tube; The output terminal of the second switch tube is connected to the gate switch voltage output terminal, and the controlled terminal of the second switch tube is connected to the output terminal of the voltage dividing unit.

Optionally, the voltage dividing unit includes a first resistor and a second resistor, the first terminal of the first resistor is the second input terminal of the voltage dividing unit, the second terminal of the first resistor and the second resistor The first terminal of the second resistor is connected, and the common terminal of the first resistor and the second resistor is the output terminal of the voltage dividing unit; the second terminal of the second resistor is the first terminal of the voltage dividing unit Input.

Optionally, the second switch circuit includes a third switch tube, an input terminal of the third switch tube and an input terminal of the second switch circuit, an output terminal of the third switch tube is grounded, the The controlled end of the third switch tube is used to receive the second timing signal.

Optionally, the discharge circuit further includes a third resistor, a first terminal of the third resistor is connected to the gate switch voltage output terminal, and a second terminal of the third resistor is connected to the second switch circuit Input connection.

Optionally, the third resistor is a variable resistor.

Optionally, the angle-cut circuit further includes a voltage stabilizing diode, a cathode of the voltage stabilizing diode is connected to one end of the first inductor, and an anode of the voltage stabilizing diode is connected to the input end of the second switching circuit .

Optionally, the display device further includes:

Source driver, set to provide data signals;

The gate driver is connected to the gate switch voltage output end of the angle-cutting circuit, and the gate driver is configured to provide a gate signal according to the gate turn-on voltage output by the gate switch voltage output end;

The display panel is respectively connected to the row scanning line of the gate driver and the data line of the source driver, and the display panel is configured to display images according to the data signal and the gate signal.

Optionally, the display panel is composed of a plurality of pixels, and each pixel is composed of three sub-pixels of red, green, and blue; each of the sub-pixels is composed of a thin film transistor and a pixel capacitor, and a plurality of thin film transistors Thin film transistor array.

Optionally, the display device further includes:

Source driver, set to provide data signals;

The gate driver is connected to the gate switch voltage output end of the angle-cutting circuit, and the gate driver is configured to provide a gate signal according to the gate turn-on voltage output by the gate switch voltage output end;

The display panel is respectively connected to the row scanning line of the gate driver and the data line of the source driver, and the display panel is configured to display images according to the data signal and the gate signal.

The angle-cutting circuit of the present application is provided with a first switch circuit, and the first switch circuit is arranged in series between the gate switch voltage input terminal and the gate switch voltage output terminal to turn on when the first timing control signal is received And output the gate turn-on voltage received by the gate switch voltage input to the gate switch voltage output; the angle-cut circuit is also provided with a second switch circuit and a discharge circuit, and turns on when the second timing control signal is received, Therefore, the discharge circuit releases the electrical energy connected to the voltage output terminal of the gate switch; wherein, the discharge circuit includes a first inductor, a third resistor and a voltage stabilizing diode, wherein the first inductor is connected in series to the voltage output terminal of the gate switch And the input end of the second switch circuit, so that when the discharge circuit releases the connected electric energy, the electric energy release speed is reduced. This application solves the problem that when the grid voltage Vg changes from a high-level gate turn-on voltage to a low-level gate turn-off voltage, the pixel voltage will also change suddenly, so that the voltage on the liquid crystal capacitor will also change suddenly, resulting in a display panel The light transmittance has changed, and the display panel has flicker (flickering) problems. This application improves the brightness consistency of the display device.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, without paying any creative labor, other drawings can be obtained according to the structures shown in these drawings.

FIG. 1 is a schematic diagram of functional modules of an embodiment of an angle-cutting circuit of the present application;

2 is a schematic diagram of a circuit structure of an embodiment of an angle-cut circuit of the present application;

FIG. 3 is a schematic diagram of functional modules of an embodiment in which the angle-cut circuit of the present application is applied to a display device.

The implementation, functional characteristics and advantages of the present application will be further described in conjunction with the embodiments and with reference to the drawings.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in this application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of this application.

It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application, the directional indication is only used to explain the specific posture If the specific posture changes, the directional indicator will change accordingly.

In addition, if there are descriptions related to "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are for descriptive purposes only, and cannot be interpreted as indications or hints Its relative importance or implicitly indicates the number of technical features indicated. Thus, the features defined with "first" and "second" may include at least one of the features either explicitly or implicitly. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary people in the art to achieve, when the combination of technical solutions conflicts with each other or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.

The present application proposes an angle-cut circuit suitable for display devices with display panels, such as televisions, mobile phones, and computers. The display device includes timing control for outputting first and second timing control signals of opposite polarities. Device.

Referring to FIGS. 1 and 2, in an embodiment of the present application, in the angle-cutting circuit, the angle-cutting circuit includes:

Gate switch voltage input terminal Vg-in and gate switch voltage output terminal Vg-out;

The first switch circuit 10, the first switch circuit 10 is set to be turned on when receiving the first timing control signal CV1 to control the gate switch voltage input terminal Vg-in and the gate switch voltage output terminal Vg-out is electrically connected, and outputs the gate-on voltage received by the gate switch voltage input terminal Vg-in to the gate switch voltage output terminal Vg-out;

The second switch circuit 20 is set to be turned on when the second timing control signal CV2 is received, and the second timing control signal CV2 and the first timing control signal CV1 are pulse voltage signals of opposite polarities to each other;

The discharge circuit 30 is configured to release the electrical energy connected to the gate switch voltage output terminal Vg-out when the second switch circuit 20 is turned on; and,

The current limiting circuit 40 is configured to reduce the energy release speed of the gate switch voltage output terminal Vg-out.

When the polarity of the capacitor in the pixel array is reversed, and the potential of the common electrode remains unchanged, the AC drive of the liquid crystal molecules is equivalent to the change of the potential of the other electrode of the capacitor relative to the potential of the common electrode. . That is, the data signal output by the source driver rises or falls relative to the common electrode voltage. In the process of switching the data signal voltage relative to the common electrode voltage from a negative voltage to a positive voltage, or decreasing it to switch from a positive voltage to a negative voltage, the data signal voltage crossover voltage is relatively large, and because The reason for the RC load, the voltage switching requires climbing time. Therefore, in the case of a certain charging time, the charging rate of the sub-pixels that need to undergo voltage switching, that is, the ramping time, is lower than the charging rate of the sub-pixels whose voltage tends to be stable, that is, the charging saturation of the former pixel is less than that of the latter The degree of saturation, and the brightness of pixels that are fully charged is greater than that of pixels that are not fully saturated, resulting in flickering. Therefore, the driving circuit of the display panel is generally provided with a chamfering circuit to chamfer the gate-on voltage Vgh, so as to step down the corresponding gate-on voltage Vgh, so as to keep the pixel charging voltage consistent. Furthermore, the screen flicker of the display panel is avoided, and the brightness of each area of the display panel is kept consistent.

The second timing control signal CV2 and the first timing control signal CV1 are pulse voltage signals of opposite polarities to each other. Specifically, these two signals can be generated by a timing controller and an inverter. Both the first timing control signal CV1 and the second timing control signal CV2 include two high-level and low-level states. In this embodiment, the first switch circuit 10 can be turned on when the first timing control signal CV1 receiving the high level is turned on, and turned off when the first timing control signal CV1 receiving the low level is turned off, and the second switching circuit 20 can receive the low The second timing control signal CV2 of the level is turned on, and is turned off when the second timing control signal CV2 of the high level is received. Or when the first switching circuit 10 receives the low-level first timing control signal CV1 and turns on, and when receiving the high-level first timing control signal CV1 turns off, the second switching circuit 20 receives the high-level The second timing control signal CV2 is turned on, and is turned off when the low level second timing control signal CV2 is received. That is, the first switch circuit 10 and the second switch circuit 20 are not turned on at the same time. When the first switch circuit 10 is turned on, the second switch circuit 20 is in an off state, and when the second switch circuit 20 is turned on, the first switch The circuit 10 is in the off state.

It can be understood that, by adjusting the duty ratio of the second timing control signal CV2 and the first timing control signal CV1, thereby controlling the discharge time of the discharge circuit 30, it is also possible to adjust the angle of the angle cut circuit to ensure the brightness of the display panel be consistent. The

Specifically, when the first switch circuit 10 is turned on, the gate turn-on voltage received at the gate switch voltage input terminal Vg-in is output to the gate switch voltage output terminal Vg-out, and when the first switch circuit 10 is turned off, then Stop the gate voltage and turn on the voltage output.

The second switch circuit 20 controls the discharge circuit 30 to discharge or stop working by turning on or off. Specifically, when the second switch circuit 20 is turned on, the gate turn-on voltage transmitted by the discharge circuit 30 to the switching voltage output terminal has a preset discharge slope The voltage is reduced to form a chamfered voltage and output to ground through the second switch circuit 20; when the second switch circuit 20 is turned off, the discharge circuit 30 stops working.

It should be noted that the display panel generally has a thin film transistor and a pixel capacitor, where G, D, and S are the gate, drain, and source of the thin film transistor, Clc is the pixel equivalent capacitance, Cst is the storage capacitance, and Cgs is G , The parasitic capacitance between S. Clc, Cst, Cgs. The three capacitors satisfy the principle of charge conservation, that is, the pixel voltage Vs will also change with the sudden change of the G pole voltage. When the gate voltage Vg is abruptly changed from the high-level gate-on voltage Vgh to the low-level gate-off voltage Vgl, the pixel voltage Vs will also be abruptly ΔV. Then the voltage on the liquid crystal capacitor will also change abruptly, thereby changing the light transmittance of the display panel, resulting in the flicker of the display panel. among them,

△ V = Vs-Vs ’, which can be expressed as: △ V = (Vgh-Vgl) * Cgs / (Cgs + Cst + Clc).

In order to solve the above problem, in this embodiment, the current limiting circuit 40 may be implemented by using an inductance. Specifically, the current limiting circuit 40 includes a first inductance L1, and the first inductance L1 is arranged in series at the gate switching voltage Between the output terminal Vg-out and the input terminal of the second switch circuit 20, the first inductance L1 is set to reduce the energy release speed of the gate switch voltage output terminal Vg-out. According to the principle that the current flowing through both ends of the inductor cannot be abruptly changed, the discharge rate of the gate turn-on voltage is controlled, thereby reducing the loss of the second switching circuit 20. In addition, when the load, that is, the thin film transistor is pumped, the energy accumulated in the inductor L can also provide a load current for the load. In this embodiment, the angle-cutting circuit also has a first capacitor C1, which is a parasitic capacitance of each scanning line in the display panel, an LC circuit composed of the first capacitor C1 and the first inductor L1, and the first capacitor L1 When there is no resonance with the first capacitor C1, the current in the discharge circuit 30 can be limited by the first inductor L1. That is, in this embodiment, it is not necessary to provide a discharge resistor, that is, power consumption can be reduced and temperature rise can be reduced. This application can solve the problem of components in the angle-cut circuit, such as severe heating of the resistor, which brings hidden safety problems.

When the first inductor L1 and the first capacitor C1 resonate, the frequency of the second timing control signal CV2 and the first inductor L1 and the first capacitor C1 have the following relationship: f = 1 / (2π√LC). At this time, the discharge circuit of the chamfered voltage is equivalent to a purely resistive circuit. At this time, by setting the discharge resistor and adjusting the resistance value of the discharge resistor, the linear discharge slope of the chamfered voltage can be changed to control the discharge speed . In the above embodiment, the number of the first inductances may be multiple, and the multiple first inductances may be set in series or in parallel, which may be set according to the resonance frequency, which is not limited here.

The angle-cutting circuit of the present application provides the first switch circuit 10 and the first switch circuit 10 in series between the gate switch voltage input terminal Vg-in and the gate switch voltage output terminal Vg-out to receive Turns on when the first timing control signal CV1 is turned on, and outputs the gate turn-on voltage received by the gate switch voltage input terminal Vg-in to the gate switch voltage output terminal Vg-out; the angle-cut circuit is also provided with a second switch circuit 20 And the discharge circuit 30, and turn on when the second timing control signal CV2 is received, so that the discharge circuit 30 releases the electric energy connected to the gate switch voltage output terminal Vg-out; wherein, the discharge circuit 30 includes the first inductor L1 The first inductor L1 is arranged in series between the gate switch voltage output terminal Vg-out and the input terminal of the second switch circuit 20 to reduce the discharge speed of the power when the discharge circuit 30 discharges the connected power. This application solves the problem that when the grid voltage Vg changes from a high-level gate turn-on voltage to a low-level gate turn-off voltage, the pixel voltage will also change suddenly, so that the voltage on the liquid crystal capacitor will also change suddenly, resulting in a display panel The light transmittance has changed, and the display panel has flicker (flickering). This application improves the brightness consistency of the display device.

1 and 2, in an alternative embodiment, the first switching circuit 10 includes a first switching tube Q1, a second switching tube Q2 and a voltage dividing unit, the controlled end of the first switching tube Q1 For receiving the first timing signal, the output terminal of the first switch Q1 is connected to the first input terminal of the voltage dividing unit 11; the second input terminal of the voltage dividing unit 11 is connected to the gate The switching voltage input terminal Vg-in and the input terminal of the second switching tube Q2 are interconnected; the output terminal of the second switching tube Q2 is connected to the gate switching voltage output terminal Vg-out, and the second switching tube Q2 The controlled terminal of is connected to the output terminal of the gate voltage dividing unit 11.

In this embodiment, the first switching transistor Q1 may be selected as an N-type field effect transistor or an N-type thin film transistor, and the second switching transistor Q2 may be selected as a P-type field effect transistor or a P-type thin film transistor; this embodiment The first switching transistor Q1 is an N-type field effect transistor, and the second switching transistor Q2 is a P-type field effect transistor as an example for description. Wherein, the gate of the N-type field effect transistor is the controlled end of the first switching transistor Q1, the drain of the N-type field effect transistor is the output end of the first switching transistor Q1, and the N-type field effect The source of the tube is grounded; the gate of the P-type field effect tube is the controlled end of the second switching tube Q2, the drain of the P-type field effect tube and the gate switch voltage input terminal Vg-in Connected, the source of the P-type field effect transistor is connected to the gate switch voltage output terminal Vg-out. The

In this embodiment, the first switch Q1 is based on the control of the timing controller, and is turned on when it receives the first timing control signal CV1 that the timing controller outputs a high level, and receives the first A timing control signal CV1 is turned on, so that when the first switch Q1 is turned on, the voltage dividing unit 11 is divided in series to output a trigger signal to the second switch Q2, thereby triggering the second switch Q2 to turn on, Thus, the gate turn-on voltage received by the gate switch voltage input terminal Vg-in is output to the gate switch voltage output terminal Vg-out.

Further, the voltage dividing unit 11 includes a first resistor R1 and a second resistor R2, the first end of the first resistor R1 is the second input terminal of the voltage dividing unit 11, the first resistor R1 The second terminal is connected to the first terminal of the second resistor, the common terminal of the first resistor R1 and the second resistor R2 is the output terminal of the voltage dividing unit 11; the second terminal of the second resistor R2 It is the first input terminal of the voltage dividing unit 11.

In this embodiment, the first resistor R1 and the second resistor R2 form a series voltage divider circuit, and when the first switch Q1 is turned on, a series voltage divider is performed to trigger the second switch Q2 to turn on. In practical applications, the resistance of the first resistor R1 can be set to be greater than the resistance of the second resistor R2, so as to effectively trigger the second switch Q2 to be turned on when the first switch Q1 is turned on.

Referring to FIGS. 1 and 2, in an alternative embodiment, the second switch circuit 20 includes a third switch tube Q3, and the input end of the third switch tube Q3 is the input of the second switch circuit 20 End, the output end of the third switch Q3 is grounded, and the controlled end of the third switch Q3 is used to receive the second timing signal.

In this embodiment, the third switching transistor Q3 is an N-type field effect transistor or an N-type thin film transistor, the gate of the N-type field effect transistor is the controlled end of the third switching transistor Q3, and the N-type The drain of the field effect transistor is the input end of the third switching transistor Q3, and the source of the N-type field effect transistor is grounded. The third pass tube is based on the control of the timing controller, and is turned on when the timing controller outputs a high-level second timing control signal CV2, and when the timing controller outputs a low-level second timing control signal CV2 Turn on, so that the discharge circuit 30 releases the electrical energy connected to the gate switch voltage output terminal Vg-out, and under the current limitation of the first inductor L1, thereby controlling the discharge speed of the discharge circuit 30 to reduce the When the gate voltage Vg is abruptly changed from the high-level gate-on voltage Vgh to the low-level gate-off voltage Vgl, the pixel voltage Vs will also abruptly change the voltage ΔV. After the current is limited by the first inductor L1, the high voltage The voltage difference between the flat gate turn-on voltage Vgh and the low-level gate turn-off voltage Vgl is reduced to Vd-Vgl, thereby reducing ΔV. This application is beneficial to improving the flicker phenomenon of the picture and improving the picture quality.

1 and 2, in an alternative embodiment, the discharge circuit 30 further includes a third resistor R3, the first end of the third resistor R3 is connected to the gate switch voltage output terminal Vg-out The second terminal of the third resistor R3 is connected to the input terminal of the second switch circuit 20.

In this embodiment, the third resistor R3 is a discharge resistor. It can be understood that when the first inductor L1 and the first capacitor C1 resonate, the frequency of the second timing control signal CV2 and the first inductor L1 and the first The capacitor C1 has the following relationship: f = 1 / (2π√LC). At this time, the discharge circuit of the chamfered voltage is equivalent to a purely resistive circuit. At this time, a discharge resistor, that is, a third resistor R3 may be provided. The third resistor R3 may be implemented as a variable resistor, and By adjusting the resistance of the discharge resistor, the linear discharge slope of the chamfered voltage can be changed to control the discharge speed.

1 and 2, in an alternative embodiment, the angle-cut circuit further includes a zener diode ZD1, a cathode of the zener diode ZD1 is connected to one end of the first inductor L1, and the voltage regulator The anode of the diode ZD1 is connected to the input terminal of the second switching circuit 20.

In this embodiment, the discharge circuit 30 may further include a voltage stabilizing diode ZD1 to regulate the voltage when the discharge circuit 30 releases the electric energy connected to the gate switch voltage output terminal Vg-out.

The present application also proposes a chamfering circuit.

1 and 2, the angle-cut circuit includes:

Gate switch voltage input terminal Vg-in and gate switch voltage output terminal Vg-out;

The first switch circuit 10 is disposed in series between the gate switch voltage input terminal Vg-in and the gate switch voltage output terminal Vg-out. The first switch circuit 10 is configured to receive the first The timing control signal CV1 is turned on, and the gate turn-on voltage received by the gate switch voltage input terminal Vg-in is output to the gate switch voltage output terminal Vg-out;

The second switch circuit 20 is set to be turned on when the second timing control signal CV2 is received, and the second timing control signal CV2 and the first timing control signal CV1 are pulse voltage signals of opposite polarities to each other;

The discharge circuit 30 includes:

The first inductance L1, the first inductance L1 are arranged in series between the gate switch voltage output terminal Vg-out and the input end of the second switch circuit 20, and the first inductance L1 is set to reduce the The energy release speed of the gate switch voltage output terminal Vg-out is described.

A third resistor R3, the first end of the third resistor R3 is connected to the gate switch voltage output terminal Vg-out, and the second end of the third resistor R3 is connected to the input terminal of the second switch circuit 20 connection.

A zener diode ZD1, a cathode of the zener diode ZD1 is connected to one end of the first inductor L1, and an anode of the zener diode ZD1 is connected to an input end of the second switching circuit 20.

The angle-cutting circuit of the present application provides the first switch circuit 10 and the first switch circuit 10 in series between the gate switch voltage input terminal Vg-in and the gate switch voltage output terminal Vg-out to receive Turns on when the first timing control signal CV1 is turned on, and outputs the gate turn-on voltage received by the gate switch voltage input terminal Vg-in to the gate switch voltage output terminal Vg-out; the angle-cut circuit is also provided with a second switch circuit 20 And the discharge circuit 30, and turn on when the second timing control signal CV2 is received, so that the discharge circuit 30 releases the electric energy connected to the gate switch voltage output terminal Vg-out; wherein, the discharge circuit 30 includes the first inductor L1 , A third resistor R3 and a Zener diode ZD1, wherein the first inductor L1 is connected in series between the gate switch voltage output terminal Vg-out and the input terminal of the second switch circuit 20 to connect the discharge circuit 30 When the electrical energy is released, the speed of the electrical energy release is reduced. This application solves the problem that when the grid voltage Vg changes from a high-level gate turn-on voltage to a low-level gate turn-off voltage, the pixel voltage will also change suddenly, so that the voltage on the liquid crystal capacitor will also change suddenly, resulting in a display panel The light transmittance has changed, and the display panel has flicker (flickering). This application improves the brightness consistency of the display device.

The application also proposes a display device.

Referring to FIG. 3, the display device includes a chamfer circuit 600 as described above. For the detailed structure of the angle-cutting circuit 600, reference may be made to the above-mentioned embodiment, which will not be repeated here; it can be understood that, because the above-mentioned angle-cutting circuit 600 is used in the display device of the present application, the embodiments of the display device of the present application All the technical solutions of all the embodiments of the above-mentioned angle-cut circuit 600, and the technical effects achieved are also completely the same, which will not be repeated here.

With continued reference to FIG. 3, the display device further includes:

Source driver 200, set to provide data signals;

The gate driver 100 is connected to the gate switch voltage output terminal of the chamfering circuit 600. The gate driver 100 is configured to provide a gate signal according to the gate turn-on voltage output by the gate switch voltage output terminal ;

The display panel 200 is respectively connected to the row scanning line of the gate driver 100 and the data line of the source driver 300, and the display panel 200 is configured to display images according to the data signal and the gate signal .

The display device further includes a timing controller 400 and a driving power supply 500 connected to the gate driver 100, the source driver 300, and the driving power supply 500, respectively, and the timing controller 400 is configured to receive data output from an external circuit module The signals, control signals, and clock signals are converted into data signals, control signals, and clock signals suitable for the gate driver 100 and the source driver 300 to realize the image display of the liquid crystal panel. The control signals output by the timing controller 400 include gate control signals and source control signals. The driving power supply 500 integrates a plurality of DC-DC conversion circuits with different circuit functions, and each conversion circuit outputs a different voltage value. The input voltage of the input terminal of the driving power supply 500 is generally 5V or 12V. The output voltage includes the operating voltage DVDD provided to the timing controller 400, and the gate turn-on voltage Vgh and the turn-off voltage provided to the gate driver 100. The display panel 200 is composed of a plurality of pixels, and each pixel is composed of three sub-pixels of red, green, and blue. Each sub-pixel is composed of a thin film transistor and a pixel capacitor, and multiple thin film transistors constitute a thin film transistor array.

In this embodiment, the timing controller 400 is respectively connected to the gate driver 100, the source driver 300, the chamfer circuit 600, and the driving power supply 500. The timing controller 400 is configured to receive data signals and control signals output by external circuit modules And the clock signal is converted into a data signal, a control signal and a clock signal suitable for the gate driver 100 and the source driver 300 to realize the image display of the liquid crystal panel. The control signals output by the timing controller 400 include gate control signals and source control signals. The driving power supply 500 integrates a plurality of DC-DC conversion circuits with different circuit functions, and each conversion circuit outputs a different voltage value. The input voltage of the input terminal of the driving power supply 500 is generally 5V or 12V. The output voltage includes the operating voltage DVDD provided to the timing controller 400, and the gate turn-on voltage Vgh and the turn-off voltage provided to the gate driver 100. In this embodiment, the angle-cut circuit 600 is provided to angle-cut the gate-on voltage Vgh, so as to step down the corresponding gate-on voltage Vgh, so that the charging voltage of the pixels remains the same, thereby avoiding the display panel 200 The screen flickers to keep the brightness of each area of the display panel 200 consistent.

The above is only an optional embodiment of the present application, and therefore does not limit the patent scope of the present application. Any equivalent structural transformations made by the description and drawings of this application under the application concept of this application, or direct / indirect Applications in other related technical fields are included in the scope of patent protection of this application.

Claims (19)

An angle-cut circuit is applied to a display device. The display device includes a timing controller that outputs a first timing control signal and a second timing control signal. The angle-cutting circuit includes: Gate switch voltage input terminal and gate switch voltage output terminal; The first switch circuit is configured to be turned on when the first timing control signal is received to control the gate switch voltage input terminal and the gate switch voltage output terminal to be electrically connected, and connect the gate switch The gate turn-on voltage received by the voltage input terminal is output to the gate switch voltage output terminal; A second switch circuit configured to be turned on when the second timing control signal is received; A discharge circuit configured to release electrical energy connected to the voltage output of the gate switch when the second switch circuit is turned on; and, The current limiting circuit is configured to reduce the speed of releasing electric energy connected to the voltage output end of the gate switch. The chamfering circuit of claim 1, wherein the current limiting circuit includes a first inductor, the first inductor is disposed in series between the gate switch voltage output terminal and the second switch circuit input terminal In the meantime, the first inductance is set to reduce the release speed of the electric energy connected to the voltage output end of the gate switch. The chamfering circuit according to claim 1, wherein the first switching circuit includes a first switching tube, a second switching tube, and a voltage dividing unit, and the controlled end of the first switching tube is used to receive the first A timing signal, the output end of the first switching tube is connected to the first input end of the voltage dividing unit, the second input end of the voltage dividing unit is connected to the gate switch voltage input end and the second The input terminals of the switch tubes are interconnected; the output terminal of the second switch tube is connected to the gate switch voltage output terminal, and the controlled terminal of the second switch tube is connected to the output terminal of the voltage dividing unit. The chamfering circuit of claim 3, wherein the voltage dividing unit includes a first resistor and a second resistor, a first end of the first resistor is a second input terminal of the voltage dividing unit, the The second terminal of the first resistor is connected to the first terminal of the second resistor, the common terminal of the first resistor and the second resistor is the output terminal of the voltage dividing unit; the second terminal of the second resistor It is the first input end of the voltage dividing unit. The chamfering circuit according to claim 1, wherein the second switching circuit includes a third switching tube, an input terminal of the third switching tube and an input terminal of the second switching circuit, the third The output end of the switch is grounded, and the controlled end of the third switch is used to receive the second timing signal. The chamfering circuit according to claim 1, wherein the discharge circuit further includes a third resistor, a first end of the third resistor is connected to the gate switch voltage output terminal, and a third resistor The two terminals are connected to the input terminal of the second switch circuit. The chamfering circuit according to claim 1, wherein the third resistor is a variable resistor. The chamfering circuit of claim 1, wherein the chamfering circuit further comprises a zener diode, a cathode of the zener diode is connected to one end of the first inductor, and an anode of the zener diode is connected to all The input terminal of the second switch circuit is connected. An angle-cut circuit, wherein the angle-cut circuit includes: Gate switch voltage input terminal and gate switch voltage output terminal; A first switch circuit is provided in series between the gate switch voltage input terminal and the gate switch voltage output terminal, the first switch circuit is configured to be turned on when the first timing control signal is received, and Output the gate turn-on voltage received by the gate switch voltage input terminal to the gate switch voltage output terminal; A second switch circuit configured to be turned on when a second timing control signal is received, the second timing control signal and the first timing control signal being pulse voltage signals of opposite polarities to each other; The discharge circuit includes: A first inductor, the first inductor is arranged in series between the gate switch voltage output terminal and the second switch circuit input terminal, the first inductor is set to reduce the gate switch voltage output terminal The release speed of the connected electrical energy; A third resistor, a first terminal of the third resistor is connected to the gate switch voltage output terminal, and a second terminal of the third resistor is connected to the input terminal of the second switch circuit; A voltage stabilizing diode, the cathode of the voltage stabilizing diode is connected to one end of the first inductor, and the anode of the voltage stabilizing diode is connected to the input end of the second switching circuit. A display device, comprising the angle-cutting circuit according to claim 1; The chamfering circuit includes: Gate switch voltage input terminal and gate switch voltage output terminal; The first switch circuit is configured to be turned on when the first timing control signal is received to control the gate switch voltage input terminal and the gate switch voltage output terminal to be electrically connected, and connect the gate switch The gate turn-on voltage received by the voltage input terminal is output to the gate switch voltage output terminal; A second switch circuit configured to be turned on when the second timing control signal is received; A discharge circuit configured to release electrical energy connected to the voltage output of the gate switch when the second switch circuit is turned on; and, The current limiting circuit is configured to reduce the speed of releasing electric energy connected to the voltage output end of the gate switch. The display device of claim 10, wherein the current limiting circuit includes a first inductor, the first inductor is disposed in series between the gate switch voltage output terminal and the second switch circuit input terminal , The first inductance is set to reduce the release rate of electrical energy connected to the voltage output end of the gate switch. The display device of claim 10, wherein the first switching circuit comprises a first switching tube, a second switching tube, and a voltage dividing unit, and the controlled end of the first switching tube is used to receive the first Timing signal, the output end of the first switch is connected to the first input end of the voltage dividing unit, the second input end of the voltage dividing unit is connected to the gate switch voltage input end and the second switch The input terminals of the tubes are interconnected; the output terminal of the second switch tube is connected to the gate switch voltage output terminal, and the controlled terminal of the second switch tube is connected to the output terminal of the voltage dividing unit. The display device according to claim 12, wherein the voltage dividing unit includes a first resistor and a second resistor, a first end of the first resistor is a second input terminal of the voltage dividing unit, the first The second terminal of a resistor is connected to the first terminal of the second resistor, the common terminal of the first resistor and the second resistor is the output terminal of the voltage dividing unit; the second terminal of the second resistor is The first input end of the voltage dividing unit. The display device according to claim 10, wherein the second switch circuit includes a third switch tube, an input terminal of the third switch tube is an input terminal of the second switch circuit, and the third switch The output end of the tube is grounded, and the controlled end of the third switch tube is used to receive the second timing signal. The display device of claim 10, wherein the discharge circuit further comprises a third resistor, a first terminal of the third resistor is connected to the gate switch voltage output terminal, and a second terminal of the third resistor The terminal is connected to the input terminal of the second switch circuit. The display device according to claim 10, wherein the third resistor is a variable resistor. The display device according to claim 10, wherein the angle-cut circuit further includes a zener diode, a cathode of the zener diode is connected to one end of the first inductor, and an anode of the zener diode is connected to the The input terminal of the second switch circuit is connected. The display device of claim 10, wherein the display device further comprises: Source driver, set to provide data signals; The gate driver is connected to the gate switch voltage output end of the angle-cutting circuit, and the gate driver is configured to provide a gate signal according to the gate turn-on voltage output by the gate switch voltage output end; The display panel is respectively connected to the row scanning line of the gate driver and the data line of the source driver, and the display panel is configured to display images according to the data signal and the gate signal. The display device according to claim 18, wherein the display panel is composed of a plurality of pixels, and each of the pixels is composed of three sub-pixels of red, green, and blue; each of the sub-pixels is composed of a thin film transistor and a pixel capacitor A plurality of the thin film transistors constitute a thin film transistor array. The