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WO2020062554A1 - Procédé de lecture des données pour la mémoire, appareil d'affichage et support d'enregistrement lisible par ordinateur - Google Patents

Procédé de lecture des données pour la mémoire, appareil d'affichage et support d'enregistrement lisible par ordinateur Download PDF

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Publication number
WO2020062554A1
WO2020062554A1 PCT/CN2018/119148 CN2018119148W WO2020062554A1 WO 2020062554 A1 WO2020062554 A1 WO 2020062554A1 CN 2018119148 W CN2018119148 W CN 2018119148W WO 2020062554 A1 WO2020062554 A1 WO 2020062554A1
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WO
WIPO (PCT)
Prior art keywords
storage area
data
storage
checksum
timing controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/119148
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English (en)
Chinese (zh)
Inventor
赵文勤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Publication of WO2020062554A1 publication Critical patent/WO2020062554A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present application relates to the field of memory technology, and in particular, to a method for reading data from a memory, a display device, and a computer-readable storage medium.
  • the static read only memory in the timing controller TCON IC static read only Data in memory (SROM) cannot be saved after power-off, but Erasable Memory (Electrically Erasable Programmable read only
  • SROM static read only Data in memory
  • Erasable Memory Electrical Erasable Programmable read only
  • the data stored in the flash memory can be saved even after power off, so the control program of the timing controller will be stored in the erasable memory or flash memory.
  • the timing controller After power-on, the timing controller will initialize and read timing control data from the external memory through the bus. The data in the memory cannot be modified during the normal operation of the display device. Once modified, it will cause the timing controller to read the timing control data incorrectly, and the display device will display abnormally.
  • the main purpose of the present application is to provide a method for reading data from a memory, a display device, and a computer-readable storage medium. occur.
  • the present application proposes a method for reading data from a memory, which is applied to a display device, where the display device includes:
  • a memory configured to store data or signals, the memory including a first storage area and a second storage area storing the same storage data, the first storage area is electrically connected to the timing controller, wherein data in the memory is read
  • the extraction method includes the following steps:
  • the second storage area is assigned to the storage data of the first storage area.
  • the step of comparing the stored data of the first storage area with preset stored data specifically includes:
  • the method further includes:
  • a read instruction is output to trigger the timing controller to communicate with the first storage area for reading by the timing controller.
  • the second storage area is assigned to the storage data of the first storage area.
  • the method for reading data from the memory further includes:
  • a read instruction is output to trigger the timing controller to communicate with the first storage area and provide the timing controller with Reading the stored data of the first storage area.
  • the present application also proposes a display device, which includes:
  • the timing controller is configured to send a logical address when the display device is powered on.
  • a memory configured to store data or signals, the memory including:
  • the first storage area and the second storage area store the same storage data, and the first storage area is communicatively connected with the book sequence controller; and,
  • An inspector configured to set preset storage data according to storage data stored in the first storage area and the second storage area;
  • triggering the second storage area to assign the stored data to the first storage area triggering the timing controller and the The first storage area is communicatively connected for the timing controller to read the storage data assigned to the first storage area by the second storage area.
  • the checker is specifically configured to:
  • the checker is further configured as:
  • a read instruction is output, and the timing controller is triggered to communicate with the first storage area for the timing controller to read the
  • the second storage area is assigned to the storage data of the first storage area.
  • the display device further includes a connector and a serial communication bus
  • the memory is communicatively connected with the timing controller through the serial communication bus
  • the memory is further connected through the connector and serial communication
  • the bus is connected to the upper computer.
  • serial communication bus is an I2C (Inter-Integrated Circuit) communication bus.
  • I2C Inter-Integrated Circuit
  • the connector is a bilateral connector.
  • the memory is an erasable memory or a flash memory.
  • the display device further includes a display panel, and a source driver, a gate driver, and a driving power source driving the display panel;
  • the timing controller is connected to the gate driver, the source driver, and the driving power source, respectively.
  • the timing controller is configured to read the control signal and the setting signal stored in the memory when the display device is powered on to perform initialization, and receive the data signal, the control signal output from the external circuit module, and The clock signal is converted into a data signal, a control signal, and a clock signal suitable for the gate driver and the source driver, thereby realizing the image display of the liquid crystal panel.
  • control signals output by the timing controller include a gate control signal and a source control signal.
  • the present application also proposes a computer-readable storage medium on which a data reading program of a memory is stored, wherein the data reading program of the memory implements a data reading method of the memory when executed by a processor; the data of the memory
  • the reading method is applied to a display device, which includes:
  • a memory configured to store data or signals, the memory including a first storage area and a second storage area storing the same storage data, the first storage area being electrically connected to a timing controller, and a data reading method of the memory It includes the following steps:
  • the second storage area is assigned to the storage data of the first storage area.
  • the step of comparing the stored data of the first storage area with the preset stored data specifically includes:
  • the method further includes:
  • a read instruction is output to trigger the timing controller to communicate with the first storage area for reading by the timing controller.
  • the second storage area is assigned to the storage data of the first storage area.
  • the method for reading data from the memory further includes:
  • a read instruction is output to trigger the timing controller to communicate with the first storage area and provide the timing controller with Reading the stored data of the first storage area.
  • the data reading method of the memory of the present application sets preset storage data according to the storage data stored in the first storage area and the second storage area; and obtains a logical address sent by a timing controller; When the logical address is the same as the stored logical address, the storage data of the first storage area is compared with the first storage data, and when the storage data of the first storage area is not consistent with the preset storage data, the second storage area is stored The stored data is assigned to the first storage area, and the timing controller is triggered to read the stored data after the second storage area is assigned to the first storage area.
  • This application is beneficial to avoid that the timing control data stored in the memory is rewritten by interference signals, or when the memory is performing read and write operations, an unexpected power failure occurs, causing the internal data of the memory to be lost, and the timing control data read by the timing controller being wrong , Causing the phenomenon that the display screen of the display panel cannot be driven normally.
  • FIG. 1 is a schematic flowchart of an embodiment of a data method for a memory of this application
  • FIG. 2 is a detailed flowchart of step S200 in the data reading method of the memory of the present application shown in FIG. 1;
  • FIG. 3 is a schematic flowchart of another embodiment of a data method for a memory
  • FIG. 4 is a schematic diagram of functional modules of an embodiment of a display device of the present application.
  • FIG. 5 is a schematic diagram of functional modules of another embodiment of the display device of the present application shown in FIG. 4;
  • FIG. 6 is a schematic structural diagram of a data reading device in a memory of a hardware operating environment according to an embodiment of the present application.
  • the directivity indication is only set to be interpreted in a specific posture (as shown in the accompanying drawings). (Shown) the relative positional relationship, movement, etc. of the various components, if the specific posture changes, the directional indicator will change accordingly.
  • This application proposes a method for reading data from a memory, which is applied to a display device.
  • the display device is provided with a timing controller and a memory.
  • the display device may be a display device such as a mobile phone, a computer, a television, a tablet computer, or a projector.
  • Both memory and timing controller can be set in timing control (Timing Controller (TCON) PCB, because the data in the internal static read-only memory SROM of the timing controller cannot be saved after power-down, the erasable memory (Electrically Erasable Programmable read only data stored in memory (EEPROM) or flash memory can be saved even after power failure, so the control program of the timing controller is stored in erasable memory EEPROM or flash memory flash.
  • TCON Timing Controller
  • the timing controller will initialize and read the timing control signals and other setting data from the external memory through the communication bus to perform initial settings. That is, the memory may store a control signal configured to drive the gate driving integrated circuit and the source driving integrated circuit in the display device to work, and communicate with the timing controller through a serial communication bus.
  • the timing controller When the display device is powered on, the timing controller reads the control signals in the memory and performs other initial settings to generate the corresponding timing control signals to drive the source driver integrated circuit of the display panel in the display device. And gate drive integrated circuits.
  • the data in the memory cannot be modified during the normal operation of the display device. Once modified, the initialization or error of the timing controller will cause the display device to display abnormally.
  • most of the memory is provided with a write-protect pin (WP pin), and when the input is high, you can control the memory to write data, and at the low level, you cannot write data. At this time, the memory is only for the timing controller to read data.
  • WP pin write-protect pin
  • the data reading method of the memory includes the following steps:
  • Step S100 Set preset storage data according to the storage data stored in the first storage area and the second storage area.
  • the memory includes a first storage area and a second storage area that respectively store the first storage data, and the first storage area is communicatively connected to the timing controller, that is, the storage area of the memory is divided in this embodiment. In the case of two or more, two can be selected in this embodiment, and they are respectively a first storage area and a second storage area.
  • the first storage area and the second storage area are respectively The same stored data is stored.
  • the written stored data is defined as the first stored data.
  • the first stored data is also a control signal and other setting data for initialization by the timing controller.
  • the stored data is written by the host computer.
  • the preset storage data may be set as the first storage data, that is, the storage data written to the first storage area and the second storage area by a host computer.
  • Step S200 Obtain a logical address sent by the timing controller.
  • the timing controller is equivalent to the master device, and the memory and other functional circuits are equivalent to the slave devices.
  • Each slave device passes the communication bus, such as I2C (Inter-Integrated Circuit)
  • the communication bus is in communication with the timing controller.
  • the timing controller reads the stored data in the memory
  • the timing controller will send a logical address.
  • the memory obtains the logical address and matches the logical address stored in the memory
  • the timing controller communicates with the memory and reads Fetch the data stored in the memory.
  • Step S300 When the obtained logical address sent by the timing controller is the same as the stored logical address, compare the stored data of the first storage area with the preset stored data;
  • the timing controller is communicatively connected to a register in the first storage area of the memory, and is configured to read only the data in the first storage area, but not the data in the second storage area.
  • This setting can prevent Accidental power loss loses data in both storage areas.
  • the register in the first storage area of the control memory is communicatively connected with the timing controller, and the current storage data of the first storage area is now connected. Compare with the preset storage data to prevent the stored data in the first storage area from entering the first storage area due to the parasitic capacitance and impedance generated by the impedance on the I2C bus of the timing controller.
  • the storage data of a storage area is rewritten, and the timing controller reads the rewritten storage data, so that the timing controller cannot normally drive the display panel display screen.
  • Step S400 When the storage data in the first storage area is inconsistent with the preset storage data, assign the first storage data stored in the second storage area to the first storage area, and trigger the timing The controller reads the storage data assigned to the first storage area by the second storage area.
  • the first storage area is connected to the timing controller through a communication bus, and the second storage area is only communicatively connected to the first storage area. Therefore, after the storage data of the first storage area is rewritten, the first storage area is rewritten.
  • the storage data of the second storage area may be assigned to the first storage area.
  • the data read by the timing controller is the first storage data after the second storage area is assigned to the first storage area, that is, the control signals stored in the memory and other setting data are initially set to generate the corresponding Timing control signals to drive the source driving integrated circuit and the gate driving integrated circuit of the display panel in the display device to work.
  • the data reading method of the present application sets preset storage data according to the storage data stored in the first storage area and the second storage area; and obtains a logical address sent by a timing controller; When the sent logical address is the same as the stored logical address, the stored data of the first storage area is compared with the first stored data, and when the stored data of the first storage area is not consistent with the preset storage data, the second storage area is The stored first storage data is assigned to the first storage area, and the timing controller is triggered to read the first storage data after the second storage area is assigned to the first storage area.
  • This application is beneficial to avoid that the timing control data stored in the memory is rewritten by interference signals, or when the memory is performing read and write operations, an unexpected power failure occurs, causing the internal data of the memory to be lost, and the timing control data read by the timing controller being wrong. , Causing the phenomenon that the display screen of the display panel cannot be driven normally.
  • comparing the stored data in the first storage area with the first storage includes:
  • Step S210 Set a preset checksum according to the storage data stored in the first storage area and the second storage area.
  • Step S220 Calculate a checksum of the first storage area and record the checksum as a first detection checksum
  • Step S230 Compare the first checksum with a preset checksum.
  • Step S240 When the first checksum is inconsistent with the preset checksum, determine that the storage data in the first storage area is inconsistent with the preset storage data.
  • the preset checksum may be a communication connection between the memory and the upper computer, and the checksum obtained after the first computer writes the first stored data, that is, the preset checksum, may be specifically written by Add the value to the first storage area register or the second storage area and add the last six digits as the value of the preset checksum.
  • the preset checksum in this embodiment is in the form of a hexadecimal number system. .
  • the values in the first storage area register may be added and the last six digits taken as the checksum value, that is, the first detection Checksum.
  • the checksum of the data currently stored in the first storage area that is, the first detection checksum is inconsistent with the preset checksum
  • the method further includes:
  • Step S410 Recalculate the stored data after the first storage area is assigned, and record it as the second detection checksum
  • Step S420 Compare the second detection checksum with a preset checksum.
  • Step S430 When the second checksum is consistent with the preset checksum, output a read instruction to trigger the timing controller to communicate with the first storage area for reading by the timing controller. Fetch the storage data assigned to the first storage area by the second storage area.
  • the value currently stored in the first storage area register may be added and the last six digits taken as the value of the checksum, that is, the second Check the checksum.
  • the checksum preset checksum of the data currently stored in the first storage area is consistent, it means that the value assigned to the first storage area by the second storage area is successful, that is, the current value of the first storage area is currently
  • the stored data is the first stored data that has not been rewritten.
  • the data read by the timing controller is the stored data after the second storage area is assigned to the first storage area, that is, the control signals stored in the memory and other setting data are initially set to generate the corresponding timing.
  • the control signal drives the source driving integrated circuit and the gate driving integrated circuit of the display panel in the display device to operate.
  • the method for reading data from the memory further includes:
  • a read instruction is output to trigger the timing controller to communicate with the first storage area and read by the timing controller. Stored data in the first storage area.
  • the value of the first storage area register can be added and calculated, and the last six digits can be used as the value of the checksum.
  • the first detection checksum is preset as the checksum of the data currently stored in the first storage area. When the checksums are consistent, it can be determined that the currently stored storage data in the first storage area is consistent with the first storage data, and the data currently stored in the first storage area has not been rewritten.
  • the timing controller can read the storage data of the first storage area, that is, the control signals stored in the memory, and other setting data to perform initial settings to generate corresponding timing control signals, thereby driving the display in the display device.
  • the source driver IC and the gate driver IC of the panel work.
  • the present application also proposes a display device.
  • the display device includes:
  • the timing controller 100 is configured to send a logical address when the display device is powered on.
  • the display device further includes a display panel 200, a source driver 300, a gate driver 400, and a driving power source 500 that drive the display panel 200 to work.
  • the timing controller 100 is connected to the gate driver 400 and the source driver 300, respectively.
  • the driving power supply 500 is connected, and the timing controller 100 is configured to read the control signals and setting signals stored in the memory 600 when the display device is powered on to perform initialization, and receive data signals and control signals output by external circuit modules
  • the signal and the clock signal are converted into data signals, control signals, and clock signals suitable for the gate driver 400 and the source driver 300 to realize the image display of the liquid crystal panel.
  • the control signals output by the timing controller 100 include a gate control signal and a source control signal.
  • the memory 600 is configured to store data or signals.
  • the memory 600 includes:
  • the first storage area 610 and the second storage area 620 respectively store first storage data, and the first storage area 610 is communicatively connected with the book sequence controller; and,
  • the checker 630 is configured to set preset storage data according to the storage data stored in the first storage area and the second storage area; and obtain the logical address sent by the timing controller 100 and the obtained logical address.
  • the logical address stored in the memory 600 is the same, comparing the stored data of the first storage area 610 with preset storage data;
  • the memory 600 may be an electrically erasable memory (Electrically Erasable Programmable read only memory, EEPROM) or flash memory.
  • the data stored in the memory can be saved even after power failure, so the control program of the timing controller is stored in the erasable memory or flash memory.
  • the storage area of the memory 600 may be divided into two or more. In this embodiment, two storage areas may be selected, and they are a first storage area 610 and a second storage area 620, respectively.
  • the first storage area 610 and the second storage area 620 may be implemented by using a circuit module such as a register. When the data is written to the memory 600, the same storage data is stored in the first storage area 610 and the second storage area 620.
  • This embodiment defines the written storage data as the first storage data.
  • a stored data is a control signal and other setting data for initialization of the timing controller 100.
  • the first stored data is written by a host computer. After writing, the first storage data needs to be write-protected to ensure that the data in the memory 600 cannot be rewritten in the case of non-program update.
  • the preset storage data may be set as the first storage data, that is, the same storage data stored in the first storage area and the second storage area by the upper computer.
  • the timing controller 100 is communicatively connected to a register in the first storage area 610 of the memory 600, and is configured to read only the data of the first storage area 610, but not the data of the second storage area 620. This setting prevents Accidental power loss loses data in both storage areas.
  • the register in the first storage area 610 of the control memory 600 is communicatively connected with the timing controller 100, and the first storage area is now connected.
  • the current stored data of 610 is compared with the first stored data to prevent the stored data of the first storage area 610 from being disturbed by interference signals generated by the parasitic capacitance and impedance on the I2C bus of the memory 600 and the timing controller 100.
  • the first storage area 610 causes the stored data in the first storage area 610 to be rewritten, and the timing controller 100 reads the rewritten storage data, so that the timing controller 100 cannot normally drive the display panel 200 to display a screen.
  • the checker 630 detects whether the data in the first storage area 610 is rewritten. If the data stored in the first storage area 610 is rewritten, the stored data in the first storage area 610 and the preset storage data are caused. When they are not consistent, the second storage area 620 may be controlled to assign the stored storage data to the first storage area 610. If it is not rewritten, the timing controller 100 may be triggered to read the first storage data after the first storage area 610, that is, the control signals stored in the memory 600 and other setting data are initially set to generate corresponding The timing control signals drive the source driving integrated circuit and the gate driving integrated circuit of the display panel 200 in the display device to operate.
  • the display device of the present application sets a checker 630 in the memory 600 to set preset storage data according to the storage data stored in the first storage area and the second storage area, and obtain a logical address sent by the timing controller 100 ;
  • the obtained logical address sent by the timing controller 100 is the same as the stored logical address, compare the stored data of the first storage area 610 with the preset storage data, and store the stored data in the first storage area 610 with the first
  • the timing controller 100 is triggered to read the storage data after the second storage area 620 is assigned to the first storage area 610.
  • This application is beneficial to avoid that the timing control data stored in the memory 600 is rewritten by interference signals, or when the memory 600 is performing read and write operations, an unexpected power failure occurs, causing the internal data of the memory 600 to be lost, and the timing read by the timing controller 100.
  • the control data is incorrect, which causes the phenomenon that the display screen of the display panel 200 cannot be driven normally.
  • the checker 630 is specifically configured to:
  • the checker 630 can obtain the checksum after the first computer writes the first stored data, that is, the preset checksum, which can be specifically written to the first storage area register or the second storage area.
  • the numerical values of are added and calculated, and the last six digits are taken as the value of the preset checksum.
  • the preset checksum in this embodiment is in the form of a hexadecimal number system.
  • the stored data of the first storage area and the preset can be determined.
  • the stored data is inconsistent, that is, the data currently stored in the first storage area has been rewritten.
  • the checker 630 is further configured to:
  • the second storage area 620 is assigned to the storage data of the first storage area 610.
  • the checker 630 may perform addition calculation on the values currently stored in the first storage area 610 register and take the last six digits as the checksum. Value of the first storage area 610 when the checksum preset checksum of the data currently stored in the first storage area 610 is the same Success, that is, the data currently stored in the first storage area 610 is the first stored data that has not been rewritten.
  • the display device further includes a connector (not shown) and I2C (Inter-Integrated Circuit) communication bus
  • the memory is communicatively connected to the timing controller through the I2C communication bus
  • the memory is also connected to a host computer through the connector and the I2C communication bus.
  • the connector may be a bilateral connector.
  • the communication connection between the memory and the timing controller and the upper computer can be realized.
  • the timing controller and an external controller such as a display device
  • the main controller on the main control board and other communication connections to receive corresponding control signals and data signals, thereby driving the display panel to display the corresponding screen.
  • the present application also proposes a computer-readable storage medium on which a data reading program of a memory is stored.
  • the data reading program of the memory is executed by a processor, the data reading method of the memory as described above is implemented.
  • FIG. 5 is a schematic structural diagram of a terminal of a hardware operating environment involved in the solution of the embodiment of the present application, that is, a data reading device of a memory.
  • the terminal may be a server, a PC, or a smart phone, a tablet computer, an e-book reader, or MP3 (Moving Picture Experts Group Audio Layer III, standard audio layer 3) player, MP4 (Moving Picture Experts Group Audio Layer IV, moving picture expert compression standard audio layer 3) Mobile terminal devices with display functions such as players, portable computers.
  • MP3 Moving Picture Experts Group Audio Layer III, standard audio layer 3
  • MP4 Moving Picture Experts Group Audio Layer IV, moving picture expert compression standard audio layer 3
  • Mobile terminal devices with display functions such as players, portable computers.
  • the terminal may include a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002.
  • the communication bus 1002 is configured to implement connection and communication between these components.
  • the user interface 1003 may include a display, an input unit such as a keyboard, and the optional user interface 1003 may further include a standard wired interface and a wireless interface.
  • the network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface).
  • the memory 1005 may be a high-speed RAM memory or a non-volatile memory. memory), such as disk storage.
  • the memory 1005 may optionally be a storage device independent of the foregoing processor 1001.
  • terminal structure shown in FIG. 4 does not constitute a limitation on the terminal, and may include more or fewer components than shown in the figure, or combine some components, or arrange different components.
  • the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a data reading program of the memory.
  • the network interface 1004 is mainly configured to connect to the background server and perform data communication with the background server;
  • the user interface 1003 is mainly configured to connect to the client (user) and perform data communication with the client;
  • the processor 1001 may be configured to call a data reading program of a memory stored in the memory 1005 and execute the method steps of the embodiments of data reading of the memory as described above.

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Abstract

La présente invention concerne un procédé de lecture des données pour une mémoire, un appareil d'affichage et un support d'enregistrement lisible par ordinateur, ledit procédé comprenant les étapes suivantes : la configuration, en fonction des données de mémoire mémorisées dans une première zone de mémoire et une deuxième zone de mémoire, des données de mémoire prédéterminées ; l'acquisition d'une adresse logique envoyée par un contrôleur de temporisation ; la comparaison, lorsque l'adresse logique envoyée par le contrôleur de temporisation et une adresse logique mémorisée sont les mêmes, des données de mémoire de la première zone de mémoire avec les données de mémoire prédéterminées ; et l'attribution, lorsque les données de mémoire ne sont pas les mêmes, les données de mémoire de la deuxième zone de mémoire à la première zone de mémoire, et le déclenchement du contrôleur de temporisation pour lire les données de mémoire de la première zone de mémoire.
PCT/CN2018/119148 2018-09-30 2018-12-04 Procédé de lecture des données pour la mémoire, appareil d'affichage et support d'enregistrement lisible par ordinateur Ceased WO2020062554A1 (fr)

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CN110675794B (zh) 2019-09-12 2021-07-06 Tcl华星光电技术有限公司 电源管理芯片及其驱动方法、驱动系统
CN111913883A (zh) 2020-07-28 2020-11-10 惠科股份有限公司 显示面板、代码的读取方法和计算机可读存储介质
CN113098490A (zh) * 2021-03-12 2021-07-09 山东英信计算机技术有限公司 一种动态修改电源时序的系统、方法及服务器
TWI774272B (zh) * 2021-03-15 2022-08-11 瑞昱半導體股份有限公司 影像顯示系統、影像處理電路與面板驅動方法

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