WO2019211888A1 - Method for forming gate insulation film, method for producing transistor, method for producing circuit substrate, transistor, circuit substrate, and electronic device - Google Patents

Abstract

[Problem] To provide a transistor that exhibits excellent properties. [Solution] Provided is a method for forming a gate insulation film for a bottom gate-type transistor, the method comprising: forming a resist layer on a gate electrode using a photosensitive negative-type resist; and exposing at least a part of the resist layer by moving exposure light and the resist layer relative to each other in a direction non-orthogonal to a channel direction of the transistor.

Description

Method for forming gate insulating film, method for manufacturing transistor, method for manufacturing circuit board, transistor, circuit board, and electronic device

The present invention relates to a method for forming a gate insulating film, a method for manufacturing a transistor, a method for manufacturing a circuit board, a transistor, a circuit board, and an electronic device.

2. Description of the Related Art A direct drawing type exposure apparatus that performs pattern exposure by scanning spot light of a beam irradiated on an irradiated body is known (see, for example, Patent Document 1 below).

JP 2016-071009 A

According to a first aspect of the present invention, there is provided a method of forming a gate insulating film of a bottom gate type transistor, wherein a resist layer is formed on a gate electrode using a negative resist having photosensitivity. Providing a method for forming a gate insulating film, comprising: exposing at least part of the resist layer by relatively moving the exposure light and the resist layer in a non-orthogonal direction with respect to a channel direction in the transistor Is done.

According to a second aspect of the present invention, there is provided a method for manufacturing a bottom gate type transistor, comprising forming a gate insulating film by the method for forming a gate insulating film according to the first aspect. Is provided.

According to a third aspect of the present invention, there is provided a circuit board manufacturing method including forming a transistor on a substrate by the transistor manufacturing method of the second aspect.

According to a fourth aspect of the present invention, a bottom-gate transistor is provided with a gate insulating film on a gate electrode, and the gate insulating film has a recess and / or a non-orthogonal direction in a channel direction of the semiconductor layer. Alternatively, a transistor is provided which has a convex portion and a striped portion extending in a non-orthogonal direction at the interface with the semiconductor layer.

According to the fifth aspect of the present invention, there is provided a circuit board comprising the transistor of the fourth aspect on the substrate.

According to the sixth aspect of the present invention, an electronic device including the circuit board according to the fifth aspect is provided.

It is a flowchart which shows an example of the manufacturing method of a circuit board including the formation method of the gate insulating film which concerns on this embodiment, and the manufacturing method of a transistor. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) And (B) is process drawing which shows an example of the manufacture process of the circuit board which concerns on this embodiment, respectively. (A) is a cross-sectional view showing an example of a transistor according to this embodiment, and (B) is a cross-sectional view taken along the line AA in (A). It is a schematic diagram which shows an example of the electronic device and circuit board which concern on this embodiment. It is a schematic diagram which shows an example of an electronic device manufacturing system. It is a figure which shows an example of a rotating drum. It is a figure which shows an example of a light source device. It is a figure which shows an example of the optical structure of a scanning unit. (A) is an optical microscope image of the organic transistor which concerns on an Example, (B) is a figure which shows a transfer characteristic.

When a transistor is manufactured using a direct-drawing type exposure apparatus, the negative resist may be exposed by scanning the spot light of the beam irradiated on the irradiated object in a direction orthogonal to the channel direction in the transistor. is there. When this resist is used as a gate insulating layer, streaky irregularities resulting from uneven exposure are generated in a direction perpendicular to the channel direction. When an organic semiconductor layer is laminated on the surface of this insulating layer, for example, a plurality of steps are produced in the channel direction at the interface between the organic semiconductor layer and the insulating layer, and the substantial channel length is increased, for example, the response speed of the transistor It becomes a factor to become slow.

In the present embodiment, a method for forming a gate insulating film, a method for manufacturing a transistor, which can improve or improve the transistor characteristics by eliminating or reducing a step generated in the channel direction at the interface between the organic semiconductor layer and the insulating layer, And a method of manufacturing a circuit board.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments described below. Further, in the drawings, in order to describe the embodiment, the scale is appropriately changed and expressed, for example, a part is enlarged or emphasized. In this embodiment, for example, a case where a circuit board such as a flexible display, a flexible wiring, or a flexible sensor as an electronic device is manufactured will be described as an example. Hereinafter, the case where a flexible display is manufactured as an electronic device will be described as an example. Examples of the flexible display include an organic EL display and a liquid crystal display.

When the electronic device according to the present embodiment is manufactured, the substrate is sent from a supply roll (not shown) in which a flexible sheet-like substrate (sheet substrate) is wound in a roll shape, and various types of the substrate are sent to the electronic device. A so-called roll-to-roll system in which a substrate after various treatments is continuously wound and then wound with a collection roll (not shown) is employed. The substrate has a strip shape in which the moving direction of the substrate is the longitudinal direction (long) and the width direction is the short direction (short). The substrate sent from the supply roll is sequentially subjected to various processes such as pre-processing, exposure processing, and post-processing, and is taken up by a recovery roll. In addition, it is not limited to conveying a board | substrate by roll-to-roll, For example, it is the form which carries out various processes in the middle of conveyance, conveying a several rectangular board | substrate continuously or intermittently in a predetermined direction. There may be.

FIG. 1 is a flowchart showing an example of a circuit board manufacturing method according to the present embodiment. The follow chart shown in FIG. 1 includes a gate insulating film forming method and a transistor manufacturing method according to this embodiment. The circuit board manufacturing method according to the present embodiment includes a transistor manufacturing method for manufacturing a bottom-gate transistor on the substrate. The transistor manufacturing method includes a gate insulating film forming method for forming a gate insulating film of a bottom-gate transistor.

As shown in FIG. 1, a circuit board manufacturing method uses a first step (step S01) for forming a gate electrode on a substrate and a negative type (hereinafter referred to as N type) resist on the gate electrode. A second step (step S02) for forming the resist layer, a third step (step S03) for exposing the resist layer by scanning the exposure light in a non-orthogonal direction with respect to the channel direction, and an unexposed portion of the resist layer. A fourth step (step S04) to be removed, a fifth step (step S05) for forming the source electrode and the drain electrode, a sixth step (step S06) for forming the semiconductor layer, and a wiring layer on the substrate 7th process (step S07). The method for forming the gate insulating film according to the present embodiment is mainly performed from step S02 to step S04 described above. The manufacturing method of the transistor according to this embodiment mainly includes step S01 to step S06.

2 to 10 are process diagrams showing an example of a manufacturing process of the circuit board according to this embodiment. 1 will be described below with reference to FIGS. 2 to 10 as appropriate. First, as shown in FIG. 2, in the first step S01, the gate electrode 101 is formed on the substrate FS by, for example, photolithography. Examples of the material constituting the gate electrode 101 include metal materials such as Au, Cu, Ag, and Ca, alloys such as NiP (nickel-phosphorus), inorganic materials such as ITO (Indium Tin Oxide), graphene, and carbon nanotubes. Organic materials, conductive polymers, charge transfer complexes, and the like. The formation of the gate electrode 101 is not limited to the photolithography method, and for example, an ink jet method or the like may be used.

For the substrate FS, for example, a resin film, or a foil (foil) made of a metal or alloy such as stainless steel is used. Examples of the material of the resin film include polyethylene resin, polypropylene resin, polyester resin, ethylene vinyl copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, polycarbonate resin, polystyrene resin, and vinyl acetate resin. Among them, one containing at least one or more may be used. Further, the thickness and rigidity (Young's modulus) of the substrate FS may be in a range that does not cause folds due to buckling or irreversible wrinkles in the substrate FS when passing through the transport path of the exposure apparatus EX. As a base material of the substrate FS, a film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) having a thickness of about 25 μm to 200 μm is typical of a suitable sheet substrate.

Since the substrate FS may receive heat in each step, it is preferable to select a substrate FS having a material whose thermal expansion coefficient is not significantly large. For example, the thermal expansion coefficient can be suppressed by mixing an inorganic filler with a resin film. The inorganic filler may be, for example, titanium oxide, zinc oxide, alumina, or silicon oxide. The substrate FS may be a single layer of ultrathin glass having a thickness of about 100 μm manufactured by a float process or the like, or a laminate in which the above resin film, foil, etc. are bonded to the ultrathin glass. It may be.

The flexibility of the substrate FS refers to the property that the substrate FS can be bent without being sheared or broken even when a force of its own weight is applied to the substrate FS. In addition, flexibility includes a property of bending by a force of about its own weight. The degree of flexibility varies depending on the material, size, and thickness of the substrate FS, the layer structure formed on the substrate FS, the environment such as temperature and humidity, and the like. Substrate FS buckles and creases or breaks (breaks or breaks) when substrate FS is correctly wound around a conveyance direction change member such as various conveyance rollers and rotating drums provided in the conveyance path. If it can be smoothly transported without being), it can be said to be a flexible range.

Next, a gate insulating film of a bottom gate type transistor is formed by the second step S02 to the fourth step S04. In the second step S02, as shown in FIG. 2B, a resist layer R is formed on the gate electrode 101 using a photosensitive N-type resist. The resist layer R is formed so as to cover the gate electrode 101 over a predetermined region of the substrate FS by using, for example, a slit nozzle. The resist layer R may be an ink jet method instead of using a slit nozzle. Further, the resist layer R may be formed by pressure-bonding a resist film previously formed in a film shape to the substrate FS. As the N-type resist, for example, a liquid material obtained by adding a photopolymerization initiator to a UV-curable resist material such as acrylic, epoxy, or enethiol can be used (for example, TMMR-S2000 (manufactured by Tokyo Ohka Kogyo Co., Ltd.)). TDUR-N908 (manufactured by Tokyo Ohka Kogyo Co., Ltd., NFR103G (manufactured by JSR), etc.).

In the third step S03, a part of the resist layer R is exposed by scanning exposure light in a non-orthogonal direction with respect to the channel direction in the transistor. A non-orthogonal direction means a direction that is not orthogonal in this specification. That is, the non-orthogonal direction with respect to the channel direction is a direction that is not orthogonal to the channel direction. FIG. 3A shows other components of the bottom-gate transistor, that is, the gate insulating film 102, the source electrode 103, the drain electrode 104, the semiconductor layer 105, and the channel region in the state where the second step S02 is completed. 106 is indicated by an imaginary line (dashed line). As shown in FIG. 3A, the direction in which the source electrode 103 and the drain electrode 104 face each other is the channel direction Dc.

In the third step S03, as shown in FIG. 3B, the exposure light (spot light) SP is scanned in the same or substantially the same direction (non-orthogonal direction) with respect to the channel direction Dc. The region Ra to be the gate insulating film 102 is irradiated with the exposure light SP. In the present embodiment, the resist layer R is a photosensitive N-type resist. Therefore, the region Ra reacts and cures when irradiated with the exposure light SP, and the resist layer R is formed with a region Ra that is an exposed portion and a region Rb that is a non-exposed portion. Although the case where the region Ra and the region Rb are formed in the resist layer R has been described here, the entire surface of the resist layer R may be exposed to form only the region Ra in the resist layer R.

The exposure light SP is, for example, ultraviolet light having a peak wavelength in a wavelength band of 370 nm or less. The exposure light SP can be irradiated by, for example, a direct drawing type exposure apparatus that does not use a mask, that is, a so-called raster scan type exposure apparatus. The configuration of the exposure apparatus that irradiates the exposure light SP will be described later. The diameter of the exposure light SP, that is, the diameter D1 of the spot light is set to be smaller than the channel length L1 (see FIG. 3A) between the source electrode 103 and the drain electrode 104 created in a later step. .

The exposure light SP is, for example, a circular shape shown in FIGS. 4 to 6 below, but is not limited to this example. For example, the exposure light SP is elliptical, oval, square, rectangular. Other shapes such as a trapezoidal shape, a rhombus shape, and a polygonal shape excluding a square shape may be used. 4 to 6 show a case where one exposure light SP is irradiated to the substrate FS, but the present invention is not limited to this mode, and a plurality of exposure light SP is irradiated to the substrate FS. May be. For example, as will be described later, three exposure lights SP are arranged side by side in a direction orthogonal to the transport direction Dt of the substrate FS, and such three exposure lights SP are arranged in two rows in the transport direction Dt of the substrate FS. May be. That is, a configuration in which six exposure lights SP are applied to the substrate FS may be employed. In this case, each of the six exposure lights SP exposes different areas on the substrate FS.

Here, the non-orthogonal direction with respect to the channel direction Dc is a direction different from the direction orthogonal or substantially orthogonal to the channel direction Dc. The substantially orthogonal direction includes an error in the formation position when forming the transistor and an error in the scanning position or scanning direction when scanning the exposure light SP.

4 to 6 are diagrams showing examples of directions in which the exposure light SP is scanned with respect to the substrate FS. In FIG. 4 to FIG. 6, for easy identification, the transistor formation region TR is indicated by a solid line, and the corresponding channel direction Dc is indicated by an arrow. 4 to 6, the substrate FS wound in a roll shape is drawn out and a part thereof is shown. The black arrow in the figure indicates the scanning direction Ds of the exposure light SP, and the white arrow indicates the transport direction Dt of the substrate FS. 4 to 6, the substrate FS is provided with an alignment mark AM detected by an alignment microscope. The substrate FS and the exposure light SP are positioned using the detection result of the alignment mark AM by the alignment microscope.

First, the case where the channel directions Dc of the plurality of transistors TR formed on the substrate FS are all the same will be described. For example, as shown in FIG. 4A, when all the transistors TR formed on the substrate FS have the channel direction Dc set in a direction orthogonal to the transport direction Dt of the substrate FS, the exposure light SP The scanning direction Ds can be the same or substantially the same as the channel direction Dc. In the case shown in FIG. 4A, the scanning direction Ds of the exposure light SP coincides with or substantially coincides with the channel direction Dc and is orthogonal or substantially orthogonal to the transport direction Dt of the substrate FS.

In FIG. 4A, the case where all the transistors TR on the substrate FS have the same channel direction Dc has been described. However, the present invention is not limited to this mode. For example, the substrate FS has a predetermined length in the longitudinal direction. When the plurality of transistors TR included in the range have the channel direction Dc in a direction orthogonal to the transport direction Dt of the substrate FS, the scanning direction Ds of the exposure light SP is the same as the channel direction Dc in the range or The directions may be almost the same.

FIG. 4A illustrates the case where all the channel directions Dc of the transistors TR on the substrate FS are orthogonal to the transport direction Dt of the substrate FS. However, the present invention is not limited to this configuration, and the transistors TR on the substrate FS. All the channel directions Dc may be directions that are not orthogonal to the transport direction Dt of the substrate FS. In this case, the scanning direction Ds of the exposure light SP may be set in any direction as long as it is different from the channel direction Dc.

Next, the case where the channel direction Dc of at least one transistor TR among the plurality of transistors TR formed on the substrate FS is different from that of the other transistors TR will be described as an example. For example, as shown in FIG. 4B, a transistor TR having a channel direction Dc in a direction orthogonal to the transport direction Dt and a transistor TR1 having a channel direction Dc in the transport direction Dt are to be formed on the substrate FS. It is. In this case, when the transistor TR having the channel direction Dc in the direction orthogonal to the transport direction Dt of the substrate FS is larger than the transistor TR1 as the transistor TR formed on the substrate FS, the scanning direction Ds of the exposure light SP is larger. The direction can be the same or substantially the same as the channel direction Dc of the transistor TR.

4B, the scanning direction Ds of the exposure light SP is a direction orthogonal to the transport direction Dt of the substrate FS. Thus, the scanning direction Ds of the exposure light SP can be set so that the number of transistors TR whose channel direction Dc is a non-orthogonal direction with respect to the scanning direction Ds of the exposure light SP is maximized. In the case shown in FIG. 4B, the scanning direction Ds of the exposure light SP may be set to be a non-orthogonal direction with respect to the channel direction Dc of the transistor TR1.

Next, as shown in FIG. 5A, as a transistor TR formed on the substrate FS, a transistor TR having a channel direction Dc in a direction orthogonal to the transport direction Dt of the substrate FS and a transport direction Dt of the substrate FS When the transistor TR1 having the channel direction Dc in the parallel direction is present at a ratio of approximately 1: 1, the scanning direction Ds of the exposure light SP is, for example, a direction inclined by 45 ° with respect to the transport direction Dt of the substrate FS. can do.

In the case shown in FIG. 5A, the scanning direction Ds of the exposure light SP is a direction intersecting with the transport direction Dt of the substrate FS, for example, inclined by 45 degrees. The scanning direction Ds of the exposure light SP is set in a non-orthogonal direction with respect to the channel direction Dc in both the transistor TR and the transistor TR1, that is, for all the transistors TR and TR1. As described above, the channel direction Dc of all the transistors TR and TR1 is non-orthogonal with respect to the scanning direction Ds of the exposure light SP, or the channel direction Dc is non-directional with respect to the scanning direction Ds of the exposure light SP. The scanning direction Ds of the exposure light SP can be set so that the transistors TR and TR1 in the orthogonal direction are maximized.

Next, as illustrated in FIG. 5B, as a transistor TR formed over the substrate FS, a transistor TR having a channel direction Dc in a direction orthogonal to the transport direction Dt of the substrate FS is formed in the transport direction Dt of the substrate FS. When the number is larger than that of the transistor TR1 having the channel direction Dc in the parallel direction, the scanning direction Ds of the exposure light SP is orthogonal to the transport direction Dt of the substrate FS corresponding to the channel direction Dc of the large number of transistors TR. The direction may be inclined by 30 ° from the direction. As a result, the scanning direction Ds of the exposure light SP is set at an angle close to the channel direction Dc for the transistor TR with a large number, and the non-orthogonal direction with respect to the channel direction Dc with respect to the transistor TR1 with a small number. The scanning direction Ds of the exposure light SP can be set.

In the case shown in FIG. 5B, the scanning direction Ds of the exposure light SP is not limited to 30 ° as long as it is an angle close to the channel direction Dc with respect to a large number of transistors TR. For example, the direction orthogonal to the transport direction Dt It may be set in a state tilted by 10 °, 20 ° and 40 °. At any angle, the scanning direction Ds of the exposure light SP is set at an angle close to the channel direction Dc for the transistor TR having a large number, and the channel direction Dc is also set for the transistor TR1 having a small number. The scanning direction Ds of the exposure light SP is set in the non-orthogonal direction.

Next, as illustrated in FIG. 6A, as the transistor TR formed over the substrate FS, the transistor TR1 having the channel direction Dc in a direction parallel to the transport direction Dt of the substrate FS is converted into the transport direction Dt of the substrate FS. When the number of the scanning direction Ds of the exposure light SP is larger than that of the transistor TR having the channel direction Dc in a direction orthogonal to the channel TR, the scanning direction Ds of the exposure light SP is orthogonal to the transport direction Dt of the substrate FS corresponding to the channel direction Dc of the transistor TR having a small number. The direction may be inclined by 60 ° from the direction. As a result, the scanning direction Ds of the exposure light SP is set at an angle close to the channel direction Dc for the transistor TR1 with a large number, and the non-orthogonal direction with respect to the channel direction Dc is set for the transistor TR with a small number. The scanning direction Ds of the exposure light SP can be set.

In the case shown in FIG. 5B, the scanning direction Ds of the exposure light SP is not limited to 60 ° as long as it is an angle close to the channel direction Dc with respect to the transistor TR1 having a large number. For example, the direction orthogonal to the transport direction Dt It may be set in a state tilted by 50 °, 70 ° and 80 °. At any angle, the scanning direction Ds of the exposure light SP is set at an angle close to the channel direction Dc for the transistor TR1 having a large number, and the channel direction Dc is also set for the transistor TR having a small number. The scanning direction Ds of the exposure light SP is set in the non-orthogonal direction.

Next, as shown in FIG. 6B, the transistor TR formed over the substrate FS is mostly a transistor TR having a channel direction Dc in a direction parallel to the transport direction Dt of the substrate FS. When the transistor TRD having the channel direction Dc in the direction orthogonal to the FS transport direction Dt is a transistor TRD having a predetermined function such as a driver of the circuit board, the scanning direction Ds of the exposure light SP is the main transistor TRD (or The direction may be perpendicular to the transport direction Dt of the substrate FS so as to be along the channel direction Dc of the important transistor TRD).

In each of the examples shown in FIGS. 4 to 6, the scanning direction Ds of the exposure light SP is set according to the channel direction Dc of the transistors TR, TR1, and TRD formed on the substrate FS. However, the present invention is not limited to this form. 5A, 5B, and 6A, the scanning direction Ds of the exposure light SP is set to be inclined with respect to the transport direction Dt of the substrate FS. In this case, if the exposure light SP is scanned to the full width of the substrate FS, the scanning distance becomes long. Therefore, as shown in FIGS. 4A, 4B, and 6B, setting the scanning direction Ds of the exposure light SP in a direction orthogonal to the transport direction Dt of the substrate FS is scanning of the exposure light SP. This is preferable in terms of shortening the distance.

For example, in the case where the scanning direction Ds of the exposure light SP is set in a direction orthogonal to the transport direction Dt of the substrate FS, in order to realize the configuration shown in FIGS. 5 (A), 5 (B) and 6 (A), This can be achieved by designing the transistors TR and TR1 formed on the substrate FS so as to be inclined. For example, when the configuration shown in FIG. 5A is realized, the arrangement of the transistors TR and TR1 is designed so as to be inclined by 45 °, so that the exposure light SP set in the direction orthogonal to the transport direction Dt of the substrate FS can be obtained. Each channel direction Dc can be set to a non-orthogonal direction with respect to the scanning direction Ds.

Similarly, in the case of realizing the configuration illustrated in FIG. 5B, by designing the arrangement of the transistors TR and TR1 so as to be rotated 30 ° counterclockwise from the arrangement illustrated in FIG. ) Can be realized. In order to realize the configuration shown in FIG. 6A, the arrangement of the transistors TR and TR1 is designed so as to be rotated by 60 ° counterclockwise from the illustrated arrangement, so that FIG. The configuration shown in FIG.

As described above, the arrangement of the transistors TR and TR1 formed on the substrate FS is inclined and designed on the assumption that the scanning direction Ds of the exposure light SP is set in a direction orthogonal to the transport direction Dt of the substrate FS. The scanning direction Ds of the exposure light SP can be easily set in a non-orthogonal direction with respect to the channel direction Dc of the transistors TR and TR1. Further, when designing the arrangement of the transistors TR formed on the substrate FS, as shown in FIG. 4A, the direction of the channel direction Dc of all or most of the transistors TR is set to the transport direction Dt of the substrate FS. By designing to be orthogonal, the scanning direction Ds of the exposure light SP can be matched or substantially matched with the channel direction Dc.

Further, when designing the arrangement of the transistors TR formed on the substrate FS, the channel directions Dc of the transistors TR and TR1 are designed to be the same for each predetermined length range in the substrate FS. Also good. The predetermined length in the longitudinal direction may be set for each device to be created, for example. Further, when designing the arrangement of the transistors TR formed on the substrate FS, as the transistors TR and TR1 formed on the substrate FS, the channel direction Dc is parallel to the transport direction Dt of the substrate FS and the transport direction Dt. It may be designed in such an arrangement that it is limited to two types with the orthogonal direction.

In the third step S03, the exposure light SP, which is spot light, is scanned in a direction orthogonal to the transport direction Dt while transporting the substrate FS in the transport direction Dt. Therefore, the exposure light SP is scanned with respect to the substrate FS while being shifted in the transport direction Dt. At this time, the transport speed of the substrate FS and the scanning speed of the exposure light PS are set so that the exposure light partially overlaps in the forward path and the return path of the exposure light SP. As a result, a desired surface on the substrate FS can be exposed with the exposure light SP.

Next, in the fourth step S04, by using a solvent or the like that dissolves the N-type resist, as shown in FIG. 7A, the non-exposed portion region Rb of the resist layer R is removed, and the exposed portion region is removed. Ra is formed as the gate insulating film 102. As described above, the area Ra of the exposed portion is exposed by scanning with the exposure light PS. Here, the exposure light SP, which is spot light, may not have the same energy density in the entire spot, but may have a Gaussian distribution with the central portion at the maximum, for example. As a result, even when scanning is performed so as to partially overlap the irradiation locus of the exposure light SP, unevenness in the exposure amount occurs in the area Ra of the exposed portion. In particular, if the transport speed of the substrate FS or the scanning speed of the exposure light PS is increased in order to increase the efficiency of the exposure process, the unevenness of the exposure amount tends to increase. When the entire surface of the resist layer R is exposed in the third step S03, the fourth step may be omitted because the region Rb to be removed is not formed.

The unevenness of the exposure amount in the exposed portion area Ra is a streak along the scanning direction of the exposure light PS on the surface of the area Ra when the non-exposed portion area Rb of the resist layer R is removed by a solvent or the like in the fourth step S04. Will be formed. That is, a striped portion to be described later is formed by removing a portion with a small exposure amount in the region Ra of the exposed portion with a solvent or the like. The striped portion has continuous irregularities in a direction orthogonal to the scanning direction of the exposure light PS. The form of the striped portion will be described later. In the present specification, “unevenness” means non-planar. That is, when it is considered that it has only a concave part with respect to a certain plane, when it is considered that it has only a convex part, it expresses as having an unevenness | corrugation in all the cases where it is considered that it has both a concave part and a convex part.

Next, in the fifth step S05, as shown in FIG. 7B, the source electrode 103 and the drain electrode 104 are formed on the gate insulating film 102 by various patterning techniques such as photolithography. The material constituting the source electrode 103 and the drain electrode 104 is similar to the material of the gate electrode 101, for example, a metal material such as Au, Cu, Ag, Ca, an alloy such as NiP (nickel-phosphorus), ITO (Indium Tin). Inorganic materials such as Oxide), organic materials such as graphene and carbon nanotubes, conductive polymers, and charge transfer complexes. Note that the materials of the gate electrode 101, the source electrode 103, and the drain electrode 104 may be the same, or at least one material may be different from the others.

FIGS. 8A and 8B and FIGS. 9A and 9B are diagrams illustrating an example of the substrate FS viewed from the top in a state where the source electrode 103 and the drain electrode 104 are formed. . As shown in FIGS. 8 and 9, the striped portions 102b1 to 102b4 are formed on the surface 102a of the gate insulating film 102 between the source electrode 103 and the drain electrode 104 as described above. The striped portions 102b1 to 102b4 may be collectively referred to as the striped portion 102b. The striped portion 102b is formed along the scanning direction Ds of the exposure light SP. The striped portion 102b has irregularities in a non-orthogonal direction with respect to the channel direction Dc. The striped portion 102b is formed by irradiating the resist layer R while scanning the exposure light SP, and by the influence of the ablation of the exposure light SP in addition to the influence of the exposure unevenness described above.

8A, the striped portion 102b1 is formed between the source electrode 103 and the drain electrode 104 so as to extend in parallel with the channel direction Dc. The striped portion 102b1 in this state is formed when the scanning direction Ds of the exposure light SP is the same as or substantially the same as the channel direction Dc. The unevenness of the striped portion 102b1 is a state in which a concave portion and a convex portion are arranged in a direction orthogonal to the channel direction Dc. The striped portion 102b1 is formed in the transistor TR shown in FIGS. 4A and 4B and the transistor TRD shown in FIG. 6B. Note that the striped portion 102 b 1 is not uneven along the channel direction Dc between the source electrode 103 and the drain electrode 104.

8B, the striped portion 102b2 is formed between the source electrode 103 and the drain electrode 104 in a state extending in a direction inclined by an angle θ1 = 45 ° with respect to the channel direction Dc. The striped portion 102b2 in such a state is formed when the scanning direction Ds of the exposure light SP is inclined by 45 ° with respect to the channel direction Dc. The unevenness of the striped portion 102b2 is a state in which a concave portion and a convex portion are arranged in a direction that intersects with the channel direction Dc at an angle of 45 °. The striped portion 102b2 is formed in the transistors TR and TR1 shown in FIG. Note that the striped portion 102b2 has irregularities along the channel direction Dc between the source electrode 103 and the drain electrode 104, but the scanning direction Ds of the exposure light SP is a direction orthogonal to the channel direction Dc. In comparison, the number of irregularities in the channel direction Dc is reduced. Also, the number of irregularities in the channel direction Dc is smaller than that of a striped portion 102b4 described later.

9A, the striped portion 102b3 is formed between the source electrode 103 and the drain electrode 104 in a state extending in a direction inclined by an angle θ2 = 30 ° with respect to the channel direction Dc. The striped portion 102b3 in such a state is formed when the scanning direction Ds of the exposure light SP is inclined by 30 ° with respect to the channel direction Dc. The unevenness of the striped portion 102b3 is a state in which a concave portion and a convex portion are arranged in a direction intersecting with the channel direction Dc at an angle of 60 °. The stripe portion 102b3 is formed in the transistor TR illustrated in FIG. 5B and the transistor TR1 illustrated in FIG. Note that the striped portion 102b3 has irregularities along the channel direction Dc between the source electrode 103 and the drain electrode 104, but the scanning direction Ds of the exposure light SP is a direction orthogonal to the channel direction Dc. In comparison, the number of irregularities in the channel direction Dc is reduced. In addition, the number of irregularities in the channel direction Dc is reduced as compared with the above-described striped portion 102b2.

9B, the striped portion 102b4 is formed between the source electrode 103 and the drain electrode 104 so as to extend in a direction inclined by an angle θ3 = 60 ° with respect to the channel direction Dc. The striped portion 102b4 in this state is formed when the scanning direction Ds of the exposure light SP is inclined by 60 ° with respect to the channel direction Dc. The unevenness of the striped portion 102b4 is a state in which a concave portion and a convex portion are arranged in a direction intersecting with the channel direction Dc by being inclined by 30 °. The stripe portion 102b4 is formed in the transistor TR1 illustrated in FIG. 5B and the transistor TR illustrated in FIG. Note that the striped portion 102b4 has irregularities along the channel direction Dc between the source electrode 103 and the drain electrode 104, but the scanning direction Ds of the exposure light SP is a direction orthogonal to the channel direction Dc. In comparison, the number of irregularities in the channel direction Dc is reduced.

Next, in the sixth step S06, as shown in FIG. 10A, the semiconductor layer 105 is formed using an organic material such as pentacene or naphthacene. Note that the semiconductor layer 105 may be formed using a polymer organic material, and is not limited to an organic material, and may be formed using an inorganic material. For the formation of the semiconductor layer 105, for example, a method of patterning an organic material by an ink jet method may be used, or a method of patterning by a photolithography process may be used.

By forming the semiconductor layer 105, the channel region 106 of the semiconductor layer 105 is formed between the source electrode 103 and the drain electrode 104. The channel region 106 is formed in a state following the shape of the surface 102 a on the surface (interface) 106 a in contact with the surface 102 a of the gate insulating film 102. In other words, in the channel region 106, the unevenness corresponding to the striped portion 102b is formed at the interface 106a in a state of extending in the non-orthogonal direction with respect to the channel direction Dc. The unevenness (striped portion) of the interface 106a is formed according to the form of the striped portions 102b1 to 102b4 described above.

Thus, the bottom gate-bottom contact type transistor 100 is formed by the first step S01 to the sixth step S06. FIG. 11A is a cross-sectional view showing an example of the transistor 100 according to this embodiment, and FIG. 11B is a cross-sectional view taken along line AA in FIG. 11A. As shown in FIG. 11A, the transistor 100 has no unevenness along the channel direction Dc in the channel region 106 as compared with the case where the scanning direction Ds of the exposure light SP is set to a direction orthogonal to the channel direction Dc. Or the unevenness is reduced. That is, since the average roughness of the interface 106a in the channel direction Dc is suppressed, carrier mobility can be improved in the vicinity of the interface 106a of the semiconductor layer 105. In addition, the ON / OFF ratio and S value of the transistor 100 can be improved, and hysteresis can be reduced. Therefore, the transistor 100 excellent in various characteristics can be obtained.

Here, for example, when the striped portion 102b is formed in a direction orthogonal to the channel direction Dc of the transistor 100, carrier mobility may be reduced due to unevenness of the striped portion 102b. In order to suppress the generation of the striped portion 102b, it is necessary to take measures such as reducing one or both of the scanning speed of the exposure light SP and the transport speed of the substrate FS, or increasing the output of the exposure light SP. . On the other hand, in this embodiment, as shown in FIG. 11B, the striped portion 102b is formed in the channel direction Dc (or the channel direction Dc) of the transistor 100 so that irregularities remain in the direction orthogonal to the channel direction Dc. Therefore, it is not necessary to decrease the scanning speed of the exposure light SP and the transport speed of the substrate FS, and it is not necessary to increase the output of the exposure light SP. Therefore, a decrease in throughput for manufacturing the transistor 100 can be suppressed, and an increase in manufacturing cost can be avoided.

Next, in the seventh step S07, as shown in FIG. 10B, the circuit layer 200 is formed by forming the wiring layer 107 on the substrate FS, for example, by photolithography or the like. Since the circuit board 200 formed in this manner is equipped with the transistor 100 having various characteristics, high quality is ensured. FIG. 12 is a schematic diagram illustrating an example of the electronic device TB and the circuit board 200 according to the present embodiment. An electronic device TB shown in FIG. 12 shows a flexible display including an organic EL display DP. Note that the electronic device TB includes various products to which the circuit board 200 can be applied, such as a portable terminal such as a tablet or smartphone, a notebook or desktop personal computer, and various sensors.

The circuit board 200 shows one pixel configuration of the organic EL display DP. The configuration of the circuit board 200 shown in FIG. 12 is an example, and other configurations may be used. One pixel configuration includes transistors TR and TR1, a gate line 201, a signal line 202, a power supply line 203, an organic EL element 204, and a ground line 205. The organic EL display DP is configured by arranging the pixel configuration in a matrix. In addition, the circuit board 200 may include a drive circuit for driving the organic EL display DP or a power supply circuit.

Next, a device manufacturing system 10 for realizing the above-described circuit board manufacturing method will be described. FIG. 13 is a diagram illustrating a schematic configuration of a device manufacturing system 10 including an exposure apparatus EX that performs an exposure process on the substrate (irradiated body) FS of the embodiment. In the following description, unless otherwise specified, an XYZ orthogonal coordinate system in which the gravity direction is the Z direction is set, and the X direction, the Y direction, and the Z direction will be described according to the arrows shown in the drawing. The direction indicated by the arrow will be described as a + direction (for example, + X direction), and the opposite direction will be described as a − direction (for example, −X direction).

The device manufacturing system 10 is a manufacturing system in which a manufacturing line for manufacturing a flexible display, a flexible sensor, or the like as the electronic device TB is constructed, for example. The following description is based on the assumption that a flexible display is used as the electronic device.

The device manufacturing system 10 sends out a substrate FS from a supply roll (not shown) obtained by winding a flexible sheet-like substrate (sheet substrate) FS in a roll shape, and continuously performs various processes on the delivered substrate FS. After the application, the substrate FS after various treatments is wound up by a collecting roll (not shown), and has a so-called roll-to-roll structure. The substrate FS has a strip shape in which the moving direction of the substrate FS is the longitudinal direction (long) and the width direction is the short direction (short). The substrate FS sent from the supply roll is sequentially subjected to various processes by the process apparatus PR1, the exposure apparatus (drawing apparatus, beam scanning apparatus) EX, the process apparatus PR2, and the like, and is taken up by the collection roll.

The X direction is a direction (conveyance direction) from the process apparatus PR1 to the process apparatus PR2 through the exposure apparatus EX in the horizontal plane. The Y direction is a direction orthogonal to the X direction in the horizontal plane, and is the width direction (short direction) of the substrate FS. The Z direction is a direction (upward direction) orthogonal to the X direction and the Y direction, and is parallel to the direction in which gravity acts.

The process apparatus PR1 performs a pre-process on the substrate FS exposed by the exposure apparatus EX. The process apparatus PR1 sends the substrate FS that has been processed in the previous process toward the exposure apparatus EX. By this pre-process, the substrate FS sent to the exposure apparatus EX is a substrate having a resist layer R formed on the surface thereof.

In this embodiment, the exposure apparatus EX as a beam scanning apparatus is a direct drawing type exposure apparatus that does not use a mask, that is, a so-called raster scan type exposure apparatus. The exposure apparatus EX irradiates the irradiated surface of the substrate FS supplied from the process apparatus PR1 with a light pattern corresponding to a predetermined pattern for an electronic device, circuit, wiring, or the like for display. While exposing the substrate FS in the + X direction, the exposure apparatus EX scans the exposure light SP of the exposure beam LB one-dimensionally in the predetermined scanning direction (Y direction) on the irradiated surface of the substrate FS, The intensity of the exposure light SP is modulated (ON / OFF) at high speed according to the pattern data (drawing data). With this configuration, a light pattern corresponding to a predetermined pattern such as an electronic device, a circuit, or a wiring is drawn and exposed on the irradiated surface of the substrate FS.

That is, the exposure light SP is relatively two-dimensionally scanned on the irradiated surface of the substrate FS by the conveyance of the substrate FS and the scanning of the exposure light SP, and a predetermined pattern is drawn and exposed on the substrate FS. Further, since the substrate FS is transported along the transport direction (+ X direction), the exposure region W where the pattern is exposed by the exposure apparatus EX is spaced at a predetermined interval along the longitudinal direction of the substrate FS. A plurality will be provided. Since an electronic device is formed in the exposure area W, the exposure area W is also an electronic device formation area. Since the electronic device is configured by superimposing a plurality of pattern layers (layers on which patterns are formed), a pattern corresponding to each layer may be exposed by the exposure apparatus EX.

The process apparatus PR2 performs post-process processing (for example, plating processing, development / etching processing, etc.) on the substrate FS exposed by the exposure apparatus EX. By this subsequent process, a pattern layer of the electronic device is formed on the substrate FS.

Since the electronic device is configured by overlapping a plurality of pattern layers, one pattern layer is generated through at least each process of the device manufacturing system 10. Therefore, in order to generate an electronic device, each process of the device manufacturing system 10 as shown in FIG. 13 must be performed at least twice. Therefore, a pattern layer can be laminated | stacked by mounting | wearing another device manufacturing system 10 with the collection | recovery roll by which board | substrate FS was wound up as a supply roll. Such an operation is repeated to form an electronic device. Therefore, the processed substrate FS is in a state in which a plurality of electronic device formation regions are connected along the longitudinal direction of the substrate FS at a predetermined interval. That is, the substrate FS is a multi-sided substrate.

The exposure apparatus EX is stored in the temperature control chamber ECV. This temperature control chamber ECV suppresses a shape change due to the temperature of the substrate FS transported inside by keeping the inside at a predetermined temperature. The temperature control chamber ECV is disposed on the installation surface E of the manufacturing factory via passive or active vibration isolation units SU1 and SU2. The anti-vibration units SU1 and SU2 reduce vibration from the installation surface E. The installation surface E may be the floor surface of the factory itself, or may be a surface on an installation base that is installed on the floor surface in order to obtain a horizontal surface. The exposure apparatus EX includes a substrate transport mechanism 12, a light source device 14, a beam switching member 16, an exposure head 18, a control device 20, and a plurality of alignment microscopes AMm (AM1 to AM4).

The substrate transport mechanism 12 transports the substrate FS transported from the process apparatus PR1 at a predetermined speed in the exposure apparatus EX, and then sends the substrate FS to the process apparatus PR2 at a predetermined speed. The substrate transport mechanism 12 defines a transport path for the substrate FS transported in the exposure apparatus EX. The substrate transport mechanism 12 includes an edge position controller EPC, a driving roller R1, a tension adjusting roller RT1, a rotating drum (cylindrical drum) DR, a tension adjusting roller RT2, in order from the upstream side (−X direction side) in the transport direction of the substrate FS. A driving roller R2 and a driving roller R3 are provided.

The substrate transport mechanism 12 transports the substrate FS transported from the process apparatus PR1 at a predetermined speed in the exposure apparatus EX, and then sends the substrate FS to the process apparatus PR2 at a predetermined speed. The substrate transport mechanism 12 defines a transport path for the substrate FS transported in the exposure apparatus EX. The substrate transport mechanism 12 includes an edge position controller EPC, a driving roller R1, a tension adjusting roller RT1, a rotating drum DR, a tension adjusting roller RT2, a driving roller R2, in order from the upstream side (−X direction side) in the transport direction of the substrate FS. And it has drive roller R3.

The light source device 14 has a light source (pulse light source) and emits a pulsed beam (pulse light, laser) LB. This beam LB is ultraviolet light having a peak wavelength in a wavelength band of 370 nm or less, and the oscillation frequency (light emission frequency) of the beam LB is Fs. The beam LB emitted from the light source device 14 enters the exposure head 18 via the beam switching member 16. The light source device 14 emits and emits the beam LB at the oscillation frequency Fs under the control of the control device 20. The light source device 14 includes, for example, a semiconductor laser element that generates pulsed light in the infrared wavelength range, a fiber amplifier, and a wavelength conversion element (harmonic) that converts amplified pulsed light in the infrared wavelength range into pulsed light in the ultraviolet wavelength range. It is assumed that a fiber amplifier laser light source is used that is capable of obtaining high-intensity ultraviolet pulsed light having an oscillation frequency Fs of several hundred MHz and a light emission time of one pulse of about picoseconds.

In the beam switching member 16, the beam LB from the light source device 14 is incident on one scanning unit Un that performs one-dimensional scanning of the exposure light SP among the plurality of scanning units Un (U1 to U6) constituting the exposure head 18. As described above, the optical path of the beam LB is switched.

The exposure head 18 includes a plurality of scanning units Un (U1 to U6) on which the beams LB are incident. The exposure head 18 draws a pattern on a part of the substrate FS supported by the circumferential surface of the rotary drum DR by a plurality of scanning units Un (U1 to U6). The exposure head 18 is a so-called multi-beam type exposure head in which a plurality of scanning units Un (U1 to U6) having the same configuration are arranged. Since the exposure head 18 repeatedly performs pattern exposure for an electronic device on the substrate FS, an exposure region W (electronic device formation region) where the pattern is exposed is a predetermined length along the longitudinal direction of the substrate FS. A plurality are provided at intervals. The odd-numbered scanning units U1, U3, U5 are arranged on the upstream side (−X direction side) in the transport direction of the substrate FS with respect to the center plane Poc, and are arranged along the Y direction. The even-numbered scanning units U2, U4, and U6 are arranged on the downstream side (+ X direction side) in the transport direction of the substrate FS with respect to the center plane Poc, and are arranged along the Y direction. The odd-numbered scanning units U1, U3, and U5 and the even-numbered scanning units U2, U4, and U6 are provided symmetrically with respect to the center plane Poc.

The scanning unit Un projects the beam LB from the light source device 14 so as to converge on the exposure light SP on the irradiated surface of the substrate FS, and the exposure light SP on the irradiated surface of the substrate FS has a predetermined linear shape. A one-dimensional scan is performed by a rotating polygon mirror PM (see FIG. 17) along a simple drawing line (scanning line) SLn.

As shown in FIG. 14, scale portions SD (SDa, SDb) having scales formed in an annular shape over the entire circumferential direction of the outer peripheral surface of the rotary drum DR are provided at both ends of the rotary drum DR. Yes. The scale portion SD (SDa, SDb) is a diffraction grating having concave or convex grating lines at a constant pitch (for example, 20 μm) in the circumferential direction of the outer peripheral surface of the rotary drum DR, and is configured as an incremental scale. Is done. Three encoders ENn (EN1a, EN2a, EN3a) are provided to face the scale part SDa provided at the end portion on the −Y direction side of the rotary drum DR. Similarly, three encoders ENn (EN1b, EN2b, EN3b) are provided so as to face the scale part SDb provided at the + Y direction side end of the rotary drum DR.

FIG. 15 is a diagram showing the configuration of the light source device (pulse light source device, pulse laser device) 14. The light source device 14 as a fiber laser device includes a DFB semiconductor laser element 30, a DFB semiconductor laser element 32, a polarization beam splitter 34, an electro-optic element 36 as a drawing light modulator, a drive circuit 36a for the electro-optic element 36, a polarization A control circuit 52 including a beam splitter 38, an absorber 40, an excitation light source 42, a combiner 44, a fiber optical amplifier 46, wavelength conversion optical elements 48 and 50, a plurality of lens elements GL, and a clock generator 52a is provided.

Next, the optical configuration of the scanning units Un (U1 to U6) will be described with reference to FIG. Since each scanning unit Un (U1 to U6) has the same configuration, only the scanning unit U1 will be described, and the description of the other scanning units Un will be omitted. In FIG. 16, the direction parallel to the irradiation center axis Len (Le1) is the Zt direction, and the substrate FS is on the plane orthogonal to the Zt direction, and the substrate FS passes from the process apparatus PR1 through the exposure apparatus EX to the process apparatus PR2. The direction going to the Xt direction is defined as the Yt direction, and the direction perpendicular to the Xt direction on the plane orthogonal to the Zt direction is defined as the Yt direction. That is, the three-dimensional coordinates Xt, Yt, and Zt in FIG. 16 are the same as the three-dimensional coordinates X, Y, and Z in FIG. 10, and the Z-axis direction is parallel to the irradiation center axis Len (Le1). The three-dimensional coordinates rotated as described above.

As shown in FIG. 16, in the scanning unit U1, along the traveling direction of the beam LB1 from the incident position of the beam LB1 to the irradiated surface of the substrate FS, the reflection mirror M20, the beam expander BE, the reflection mirror M21, and the polarization Beam splitter BS, reflection mirror M22, image shift optical member SR, field aperture FA, reflection mirror M23, λ / 4 wavelength plate QW, cylindrical lens CYa, reflection mirror M24, polygon mirror PM, fθ lens FT, reflection mirror M25, cylindrical A lens CYb is provided. Furthermore, in the scanning unit U1, an optical lens system G10 and a photodetector DT1 are provided for detecting reflected light from the irradiated surface of the substrate FS via the polarization beam splitter BS.

The beam LB1 incident on the scanning unit U1 travels in the −Zt direction and enters the reflection mirror M20 inclined by 45 ° with respect to the XtYt plane. The axis of the beam LB1 incident on the scanning unit U1 is incident on the reflection mirror M20 so as to be coaxial with the irradiation center axis Le1. The reflection mirror M20 functions as an incident optical member that causes the beam LB1 to enter the scanning unit U1, and the incident beam LB1 is directed toward the reflection mirror M21 along the optical axis set in parallel with the Xt axis in the −Xt direction. reflect. Therefore, the optical axis of the beam LB1 traveling parallel to the Xt axis is orthogonal to the irradiation center axis Le1 in a plane parallel to the XtZt plane. The beam LB1 reflected by the reflection mirror M20 passes through the beam expander BE arranged along the optical axis of the beam LB1 traveling in parallel with the Xt axis and enters the reflection mirror M21. The beam expander BE expands the diameter of the transmitted beam LB1. The beam expander BE includes a condensing lens Be1 and a collimating lens Be2 that collimates the beam LB1 that diverges after being converged by the condensing lens Be1.

The reflection mirror M21 is disposed at an angle of 45 ° with respect to the YtZt plane, and reflects the incident beam LB1 toward the polarization beam splitter BS in the −Yt direction. The polarization separation surface of the polarization beam splitter BS is inclined by 45 ° with respect to the YtZt plane, reflects a P-polarized beam, and transmits a linearly polarized (S-polarized) beam polarized in a direction orthogonal to the P-polarized light. . Since the beam LB1 incident on the scanning unit U1 is a P-polarized beam, the polarization beam splitter BS reflects the beam LB1 from the reflection mirror M21 in the -Xt direction and guides it to the reflection mirror M22 side.

The reflection mirror M22 is disposed with an inclination of 45 ° with respect to the XtYt plane, and reflects the incident beam LB1 in the −Zt direction toward the reflection mirror M23 that is separated from the reflection mirror M22 in the −Zt direction. The beam LB1 reflected by the reflection mirror M22 passes through the image shift optical member SR and the field aperture (field stop) FA along the optical axis parallel to the Zt axis, and enters the reflection mirror M23. The image shift optical member SR two-dimensionally adjusts the center position in the cross section of the beam LB1 in a plane (XtYt plane) orthogonal to the traveling direction of the beam LB1. The image shift optical member SR is composed of two quartz parallel plates Sr1 and Sr2 arranged along the optical axis of the beam LB1 traveling parallel to the Zt axis, and the parallel plate Sr1 can be tilted around the Xt axis. The parallel flat plate Sr2 can be tilted around the Yt axis. The parallel plates Sr1 and Sr2 are inclined about the Xt axis and the Yt axis, respectively, so that the position of the center of the beam LB1 is shifted two-dimensionally by a minute amount on the XtYt plane orthogonal to the traveling direction of the beam LB1. The parallel plates Sr1 and Sr2 are driven by an actuator (drive unit) (not shown) under the control of the control device 20.

The beam LB1 that has passed through the image shift optical member SR passes through the circular aperture of the field aperture FA and reaches the reflection mirror M23. The circular aperture of the field aperture FA is a stop that cuts the skirt portion of the intensity distribution in the cross section of the beam LB1 expanded by the beam expander BE. If a variable iris diaphragm having an adjustable aperture of the circular aperture of the field aperture FA is used, the intensity (luminance) of the exposure light SP can be adjusted.

The reflection mirror M23 is disposed at an angle of 45 ° with respect to the XtYt plane, and reflects the incident beam LB1 in the + Xt direction toward the reflection mirror M24 that is separated from the reflection mirror M23 in the + Xt direction. The beam LB1 reflected by the reflection mirror M23 passes through the λ / 4 wavelength plate QW and the cylindrical lens CYa and enters the reflection mirror M24. The reflection mirror M24 reflects the incident beam LB1 toward the polygon mirror (rotating polygon mirror, scanning deflection member) PM. The polygon mirror PM reflects the incident beam LB1 in the + Xt direction toward the fθ lens FT having the optical axis AXf parallel to the Xt axis.

The polygon mirror PM deflects (reflects) the incident beam LB1 in a plane parallel to the XtYt plane in order to scan the exposure light SP of the beam LB1 on the irradiated surface of the substrate FS. Specifically, the polygon mirror PM has a rotation axis AXp extending in the Zt axis direction and a plurality of reflection surfaces RP (eight reflection surfaces RP in the present embodiment) formed around the rotation axis AXp. By rotating the polygon mirror PM around the rotation axis AXp in a predetermined rotation direction, the reflection angle of the pulsed beam LB1 irradiated on the reflection surface RP can be continuously changed. As a result, the reflection direction of the beam LB1 is deflected by the single reflection surface RP, and the exposure light SP of the beam LB1 irradiated onto the irradiated surface of the substrate FS is along the scanning direction (the width direction of the substrate FS, the Yt direction). Can be scanned.

The exposure light SP of the beam LB1 can be scanned along the drawing line SL1 by one reflecting surface RP. For this reason, the number of drawing lines SL1 in which the exposure light SP is scanned on the irradiated surface of the substrate FS by one rotation of the polygon mirror PM is eight, which is the same as the number of the reflecting surfaces RP. The polygon mirror PM is rotated at a constant speed by a polygon driving unit RM including a motor and the like. The rotation of the polygon mirror PM by the polygon drive unit RM is controlled by the control device 20. As described above, the effective length (for example, 30 mm) of the drawing line SL1 is set to a length equal to or shorter than the maximum scanning length (for example, 31 mm) that allows the exposure light SP to be scanned by the polygon mirror PM. In the initial setting (design), the center point of the drawing line SL1 (the irradiation center axis Le1 passes) is set at the center of the maximum scanning length.

The cylindrical lens CYa converges the incident beam LB1 in a slit shape on the reflection surface RP of the polygon mirror PM in the non-scanning direction (Zt direction) orthogonal to the scanning direction (rotation direction) of the polygon mirror PM. Even if the reflecting surface RP is inclined with respect to the Zt direction (inclination of the reflecting surface RP with respect to the normal line of the XtYt plane) by the cylindrical lens CYa in which the generatrix is parallel to the Yt direction, the influence is exerted. It can suppress, and it suppresses that the irradiation position of beam LB1 irradiated on the to-be-irradiated surface of board | substrate FS shifts | deviates to a Xt direction.

The fθ lens FT having an optical axis AXf extending in the Xt axis direction is a telecentric scan lens that projects the beam LB1 reflected by the polygon mirror PM onto the reflection mirror M25 so as to be parallel to the optical axis AXf on the XtYt plane. It is. The incident angle θ of the beam LB1 to the fθ lens FT changes according to the rotation angle (θ / 2) of the polygon mirror PM. The fθ lens FT projects the beam LB1 to the image height position on the irradiated surface of the substrate FS in proportion to the incident angle θ through the reflection mirror M25 and the cylindrical lens CYb. When the focal length is fo and the image height position is y, the fθ lens FT is designed to satisfy the relationship y = fo · θ. Therefore, the fθ lens FT enables the beam LB1 (exposure light SP) to be scanned accurately at a constant speed in the Yt direction (Y direction). When the incident angle θ to the fθ lens FT is 0 degree, the beam LB1 incident on the fθ lens FT travels along the optical axis AXf.

The reflection mirror M25 reflects the incident beam LB1 in the −Zt direction toward the substrate FS via the cylindrical lens CYb. By the fθ lens FT and the cylindrical lens CYb in which the generatrix is parallel to the Yt direction, the beam LB1 projected onto the substrate FS is minute exposure light having a diameter of about several μm (for example, 3 μm) on the irradiated surface of the substrate FS. Converged to SP. Further, the exposure light SP projected onto the irradiated surface of the substrate FS is one-dimensionally scanned by the polygon mirror PM along the drawing line SL1 extending in the Yt direction. The optical axis AXf of the fθ lens FT and the irradiation center axis Le1 are on the same plane, and the plane is parallel to the XtZt plane.

Therefore, the beam LB1 traveling on the optical axis AXf is reflected in the −Zt direction by the reflecting mirror M25, and is projected on the substrate FS coaxially with the irradiation center axis Le1. In the present embodiment, at least the fθ lens FT functions as a projection optical system that projects the beam LB1 deflected by the polygon mirror PM onto the irradiated surface of the substrate FS. Further, at least the reflecting members (reflecting mirrors M21 to M25) and the polarizing beam splitter BS function as an optical path deflecting member that bends the optical path of the beam LB1 from the reflecting mirror M20 to the substrate FS. By this optical path deflecting member, the incident axis of the beam LB1 incident on the reflection mirror M20 and the irradiation center axis Le1 can be made substantially coaxial. With respect to the XtZt plane, the beam LB1 passing through the scanning unit U1 passes through a substantially U-shaped or U-shaped optical path, and then travels in the −Zt direction and is projected onto the substrate FS.

In this way, by scanning the exposure light SP of the beam LBn one-dimensionally in the scanning direction (Y direction) by each scanning unit Un (U1 to U6) while the substrate FS is transported in the X direction, The exposure light SP can be relatively two-dimensionally scanned on the irradiated surface of the substrate FS. Therefore, a predetermined pattern can be drawn and exposed on the exposure region W of the substrate FS.

Examples of the transistor manufactured by the above-described transistor manufacturing method will be described. In the following examples, an organic transistor is formed as a transistor. In this example, PET (Cosmo Shacin A4100 (smooth surface); manufactured by Toyobo Co., Ltd.) was used as the substrate. After depositing 50 nm of Cu on the entire surface of the substrate, heat treatment was performed at 105 degrees for 30 minutes. Next, a dry film resist (hereinafter referred to as DFR) was thermocompression bonded to the entire surface of the substrate, and then the i-line was irradiated to the desired pattern by 120 mJ / cm ² using the exposure apparatus EX of the device manufacturing system 10 described above.

After the DFR protective film was peeled off, the substrate was immersed in a 2.4% TMAH aqueous solution for 60 seconds to develop the DFR. After washing with water, the substrate was immersed in an etching solution for 80 seconds to pattern the Cu film. An aqueous solution containing 3% of citric acid and hydrogen peroxide was used as an etching solution. After etching, the substrate was washed with water, and then the substrate was immersed in a 2.4% TMAH aqueous solution heated to 45 degrees for 3 minutes to peel off the DFR. Then, it washed with water and heat-processed for 30 minutes at 105 degree | times, and produced the gate electrode on the board | substrate.

Next, a gate insulating layer was formed. The substrate on which the gate electrode was produced was subjected to UV / O ³ treatment for 2.4 minutes to clean the substrate surface. Next, the SU-8 solution was formed on the substrate by die coating. In the SU-8 solution, SU-8 3005 (manufactured by Nippon Kayaku Co., Ltd.) was diluted with cyclohexanone so that the SU-8 solid content was 17 wt%, and Surflon 651 (AGC Seimi Chemical Co., Ltd.) was added to the SU-8 solid content. Manufactured) was added at 0.06 wt%. The die coat film formation was performed under the condition that the liquid film thickness was 6.8 μm. After the die coat film formation, prebaking was performed at 105 degrees for 20 minutes, and then the i-line was irradiated to the desired pattern by 240 mJ / cm ² using the exposure apparatus EX of the device manufacturing system 10 described above. After the exposure, heat treatment was performed at 105 ° C. for 1 hour, and then the substrate was immersed in a propylene glycol 1-monomethyl ether 2-acetate (hereinafter referred to as PGMEA) solvent to develop the SU-8 film. After washing with water, heat treatment was performed at 105 ° C. for 2 hours, and a gate insulating layer made of SU-8 was formed on the substrate.

Next, an upper electrode (source electrode, drain electrode) was formed. The substrate on which the gate insulating layer was formed was subjected to UV / O ³ treatment for 2.4 minutes to activate the substrate surface. Next, a 0.5 wt% 3- (2-aminoethylamino) propyltrimethoxysilane methyl isobutyl ketone solution was dip-coated on the substrate. The lifting speed of the dip coat was 1 mm / s. Next, after heat treatment at 105 ° C. for 15 minutes, the substrate was immersed in a 5 wt% ammonium peroxodisulfate aqueous solution to remove the exposed oxide film on the Cu surface. After washing with water, the substrate was immersed in an aqueous Pd solution (Activator 7331; manufactured by Meltex) for 1 minute, and then placed in an electroless Ni plating bath (NI-867; manufactured by Meltex) (74 degrees) for 1 minute. It was immersed and an electroless Ni plating film was formed on the entire surface of the substrate.

After washing with water and drying, a positive resist (OFPR-5000; manufactured by Tokyo Ohka Kogyo Co., Ltd.) was die-coated on the substrate. The die coat film formation was performed under the condition that the liquid film thickness was 6.8 μm. After the resist film was formed, i-line was irradiated to a desired pattern by 120 mJ / cm ² using the exposure apparatus EX of the device manufacturing system 10 described above. Subsequently, the substrate was immersed in a 2.4% TMAH aqueous solution for 45 seconds to develop the resist. After washing with water and post-baking at 105 degrees for 20 minutes to cure the resist, the substrate was immersed in an etching solution (60 degrees) for 15 seconds to pattern the electroless Ni plating film. As an etching solution for the electroless Ni plating film, a mixture of phosphoric acid, nitric acid, acetic acid and water in a weight ratio of 10: 1: 1: 2 was used.

After washing with water and irradiating the entire surface with i-line, the substrate was dipped in the order of 2.4% TMAH aqueous solution and ethanol to remove the resist. After washing with water, the substrate was immersed in a 5 wt% ammonium peroxodisulfate aqueous solution to remove the oxide film on the electroless Ni plating surface. Next, the substrate was placed in a replacement Au plating bath (Supermex # 255; manufactured by EM Chemcat) (68 degrees) for 1.5 minutes and reduced Au plating bath (Supermex # 880; manufactured by EM Chemcat) (68). The substrate was immersed for 2 minutes, and the electroless Ni plating surface was coated with Au. After Au plating, the substrate was washed with water and heat-treated at 105 ° C. for 30 minutes to produce an upper electrode (source electrode, drain electrode) on the substrate.

Finally, an organic semiconductor layer was formed on the substrate. The substrate on which the upper electrode was produced was subjected to UV / O ³ treatment for 2.4 minutes to activate the substrate surface. Next, a 1 wt% trimethoxysilane phenylsilane toluene solution was dip-coated on the substrate. The lifting speed of the dip coat was 1 mm / s. After film formation of the silane agent, heat treatment was performed at 100 ° C. for 10 minutes, and then the substrate was immersed in a 1 wt% pentafluorobenzenethiol toluene solution for 5 minutes to modify the upper electrode surface. Next, an organic semiconductor solution was formed on the entire surface of the substrate using a die coater. As the semiconductor solution, a solution diluted with toluene so that TIPS pentacene was 1.2 wt% and polystyrene was 0.5 wt% was used.

The die coat film formation was performed under the conditions of a liquid film thickness of 6.8 μm and a substrate transfer speed of 0.01 m / min. After the formation of the semiconductor solution, a 4 wt% BIOSURFINE-AWP (manufactured by Toyo Gosei Co.) aqueous solution was die coated on the entire surface of the substrate. The die coat film formation was performed under the conditions of a liquid film thickness of 7.5 μm and a substrate transfer speed of 0.15 m / min. Next, after the substrate was dried at 60 degrees for 5 minutes, i-line was irradiated to the desired pattern by 120 mJ / cm ² using the exposure apparatus EX of the device manufacturing system 10 described above. After the exposure, the BIOSURFINE-AWP film was developed by immersing the substrate in pure water and applying ultrasonic waves. Next, the substrate was immersed in toluene, and the semiconductor layer was patterned. Finally, an organic transistor was manufactured by performing a heat treatment at 105 degrees for 48 hours. The manufactured organic transistor has a channel width of 480 μm and a channel length of 54 μm.

FIG. 17A is an optical microscope image of an organic transistor manufactured by the above method. FIG. 17B is a diagram illustrating transfer characteristics of the organic transistor according to the example. As shown in FIG. 17B, it was confirmed from the transfer characteristics of the manufactured organic transistor that the mobility of the organic transistor was 0.09 cm ² / Vs.

As mentioned above, although embodiment and the Example were described, the technical scope of this invention is not limited to the aspect demonstrated by the above-mentioned embodiment, Example, etc. In addition, one or more of the requirements described in the above embodiments and examples may be omitted. In addition, the requirements described in the above embodiments and examples can be combined as appropriate. For example, in the above-described embodiment, the case where the bottom-gate / bottom-contact transistor 100 is manufactured has been described as an example. However, the present invention is not limited to this, and the bottom-gate / top-contact transistor is manufactured. Even can be applied. In the above-described embodiment, the exposure is performed by scanning the resist layer R with the exposure light SP. However, the present invention is not limited to this mode. For example, the resist is applied to the exposure light SP with a fixed irradiation position. The exposure light SP and the resist layer R may be moved relative to each other by moving the layer R or by moving both the exposure light SP and the resist layer R in opposite directions or in the same direction. In addition, as far as permitted by law, the disclosure of all documents cited in this specification is incorporated as part of the description of the text.

R ... resist layer, Ra, Rb ... region, FS ... substrate, S01 ... first step, S02 ... second step, S03 ... third step, S04 ... first 4 steps, S05 ... 5th step, S06 ... 6th step, S07 ... 7th step, EX ... exposure apparatus, Dc ... channel direction, Ds ... scanning direction, Dt. ..Transport direction, SP ... exposure light, TR ... formation region, Ra, Rb ... region, 10 ... electronic device manufacturing system, 100 ... transistor, 101 ... gate electrode, 102 ... Gate insulating film, 102a ... surface, 102b ... striped portion, 103 ... source electrode, 104 ... drain electrode, 105 ... semiconductor layer, 106 ... channel region, 106a ... Interface, 107 ... Wiring layer, 200 ... Circuit base , TB ··· electronic device

Claims (31)

A method of forming a gate insulating film of a bottom gate type transistor,
Forming a resist layer on the gate electrode using a negative resist having photosensitivity;
And exposing at least a part of the resist layer by relatively moving exposure light and the resist layer in a non-orthogonal direction with respect to a channel direction in the transistor. . The method for forming a gate insulating film according to claim 1, wherein at least a part of the resist layer is exposed by scanning the exposure light. 3. The method of forming a gate insulating film according to claim 2, wherein the exposure light is scanned in the same or substantially the same direction as the channel direction. 4. The method for forming a gate insulating film according to claim 1, further comprising removing an unexposed portion of the resist layer after exposing at least a part of the resist layer. * 5. The method for forming a gate insulating film according to claim 1, wherein a beam diameter of the exposure light applied to the resist layer is smaller than a channel length in the organic transistor. 6. The method for forming a gate insulating film according to claim 1, wherein the transistor is a bottom contact type. The method for forming a gate insulating film according to any one of claims 1 to 6, wherein the semiconductor layer included in the transistor includes an organic material. A method of manufacturing a bottom-gate transistor,
A method for manufacturing a transistor, comprising: forming a gate insulating film by the method for forming a gate insulating film according to claim 1. A method for manufacturing a circuit board, comprising forming the transistor on a substrate by the method for manufacturing a transistor according to claim 8. The circuit board manufacturing method according to claim 9, comprising scanning the exposure light while moving the board. The method for manufacturing a circuit board according to claim 10, wherein a moving direction of the substrate intersects a scanning direction of the exposure light. 12. The method for manufacturing a circuit board according to claim 11, wherein the moving direction of the substrate is orthogonal to the scanning direction of the exposure light. The method for manufacturing a circuit board according to claim 9, wherein at least one of the plurality of transistors formed on the substrate has a channel direction different from that of other transistors. . 14. The method of manufacturing a circuit board according to claim 13, further comprising: setting the scanning direction of the exposure light so that the number of the transistors whose channel direction is a non-orthogonal direction with respect to the scanning direction of the exposure light is maximized. Method. The arrangement of the plurality of transistors in the substrate is designed so that the number of the organic transistors in which the channel direction is a non-orthogonal direction with respect to the scanning direction of the exposure light is maximized. A method of manufacturing a circuit board. Setting the scanning direction of the exposure light such that the channel direction of the transistor having a predetermined function among the plurality of transistors is a non-orthogonal direction with respect to the scanning direction of the exposure light. Item 14. A method for manufacturing a circuit board according to Item 13. The method for manufacturing a circuit board according to any one of claims 9 to 16, wherein the board is made of a resin material. The method for manufacturing a circuit board according to any one of claims 9 to 17, wherein the board has flexibility. 19. The method for manufacturing a circuit board according to claim 18, wherein the substrate is drawn out from a roll state and wound into a roll state after part or all of the processing for manufacturing the transistor. A bottom-gate transistor,
A gate insulating film is provided on the gate electrode,
The transistor, wherein the gate insulating film has a concave portion and / or a convex portion in a non-orthogonal direction with respect to a channel direction of the semiconductor layer and has a striped portion extending in the non-orthogonal direction at an interface with the semiconductor layer. The transistor according to claim 20, wherein the striped portion extends in the channel direction. The transistor according to claim 20 or 21, wherein the gate insulating film is formed by exposing a negative resist. The transistor according to any one of claims 20 to 22, which is a bottom contact type. The transistor according to any one of claims 20 to 23, wherein the semiconductor layer includes an organic material. A circuit board comprising the transistor according to any one of claims 20 to 24 on a substrate. 26. The circuit board according to claim 25, comprising a plurality of the transistors, wherein at least one of the plurality of transistors is different from the other transistors in the channel direction. 27. The circuit board according to claim 26, wherein among the plurality of transistors, the number of the transistors in which the extending direction of the stripe portion is the same is the most. 27. The circuit board according to claim 26, wherein a direction in which the striped portion of the transistor having a predetermined function extends among the plurality of transistors is a non-orthogonal direction with respect to the channel direction. The circuit board according to any one of claims 25 to 28, wherein the board is made of a resin material. The circuit board according to any one of claims 25 to 29, wherein the board has flexibility. An electronic device comprising the circuit board according to any one of claims 25 to 30.

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