WO2019243949A1 - Method for operating imaging device - Google Patents

Abstract

Provided is a method for operating an imaging device. The present invention is a method for operating and imaging device having: a first node at which one electrode of a capacitor and one electrode of a photodiode are electrically connected; and a second node at which the other electrode of the capacitor and the gate of a transistor are electrically connected. It is possible to correct the output of a transistor by holding correction data at the second node. Moreover, it is possible to operate an avalanche photodiode having a high operating voltage by adding the potential of the second node to the first node by capacitive coupling.

Description

Operation method of imaging device

One embodiment of the present invention relates to an operation method of an imaging device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one embodiment of the present invention disclosed in this specification includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, the storage device, the display device, the imaging device, and the electronic device sometimes include a semiconductor device.

Attention has been focused on a technique for forming a transistor using an oxide semiconductor thin film formed over a substrate. For example, Patent Document 1 discloses an imaging device in which a transistor including an oxide semiconductor and having extremely low off-state current is used for a pixel circuit.

Patent Document 2 discloses a memory device having a structure in which a transistor with extremely low off-state current is used for a memory cell.

JP 2011-119711 A JP 2011-119974 A

2. Description of the Related Art In a solid-state imaging device such as a CMOS image sensor, a method of holding a data potential obtained by photoelectric conversion in a charge storage portion of a pixel is often used. This method has problems such as outflow of charges from the charge storage unit and mixing of noise accompanying reading.

For example, a source follower circuit is used for reading out the potential of the charge storage portion, but there is a problem of non-uniformity of the threshold voltage of the transistors constituting the circuit. This problem becomes apparent by displaying the acquired image, and causes unnecessary distribution of light and darkness in the image.

It is difficult to solve the non-uniformity of the threshold voltage only by improving the manufacturing process of the transistor, and a method of adding correction data to the gate of the transistor is generally used. The correction means includes internal correction for generating correction data in a pixel and external correction for supplying correction data to a pixel from the outside.

Although a correction effect is recognized in each case, a correction operation having a plurality of steps is added to the normal imaging operation, which hinders high-speed operation. Therefore, a simpler correction operation with a smaller number of steps is desired.

To increase the resolution of the image sensor, it is necessary to reduce the area per pixel and increase the pixel density. Since the reduction of the pixel area is accompanied by the reduction of the light receiving area of the photoelectric conversion device, the light sensitivity is reduced. In particular, in imaging under low illuminance, the S / N ratio of imaging data may be significantly reduced. That is, the image sensor having the conventional configuration has a problem that the resolution and the sensitivity have a trade-off relationship.

One solution to the above problem is to use a photoelectric conversion device utilizing the avalanche multiplication effect with high photosensitivity. However, in order to utilize the avalanche multiplication effect, a relatively high voltage needs to be applied to the photoelectric conversion device, and a dedicated power supply circuit or the like must be used.

Therefore, an object of one embodiment of the present invention is to provide an operation method of an imaging device for performing output correction of image data. Another object is to provide an operation method of an imaging device in which output correction of image data can be performed in a small number of steps. Alternatively, it is another object to provide an operation method of an imaging device which holds correction data in a pixel. Another object is to provide an operation method of an imaging device that adds correction data held in a pixel and acquired image data. Another object is to provide an operation method of an imaging device capable of generating a high voltage in a pixel. Another object is to provide an operation method of an imaging device in which a high voltage can be applied to a photoelectric conversion device without using a dedicated power supply circuit.

Another object is to provide a method for operating an imaging device with low power consumption. Another object is to provide an operation method of an imaging device which can perform imaging at high speed. Another object is to provide a highly reliable operation method of an imaging device. Another object is to provide a novel operation method of an imaging device and the like. Alternatively, it is another object to provide a novel imaging device or the like. Another object is to provide a novel semiconductor device or the like.

Note that the description of these objects does not disturb the existence of other objects. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that issues other than these are obvious from the description of the specification, drawings, claims, etc., and that other issues can be extracted from the description of the description, drawings, claims, etc. It is.

One embodiment of the present invention relates to an operation method of an imaging device that stores correction data in pixels. Alternatively, the present invention relates to an operation method of an imaging device that adds image data to correction data in a pixel and outputs the result.

One embodiment of the present invention provides a first node in which one electrode of a capacitor and one of a source and a drain of the first transistor are electrically connected; a second electrode of the capacitor and a gate of the second transistor; And a second node electrically connected to the first transistor, and the other of the source and the drain of the first transistor is electrically connected to one electrode of the photodiode. A first step of supplying and holding a second potential to a second node while supplying a first potential to one node, and changing a potential of the first node by an operation of a photodiode; and A second step of changing the potential of the second node by capacitive coupling of the capacitor; and fixing the potential of the second node and reading the potential of the second node by operating the second transistor. A step of, which is the operation method of the imaging apparatus performs the above order.

In the above operation, the first potential is lower than the second potential, and the difference can be equal to or higher than the threshold voltage of the second transistor.

Another embodiment of the present invention is a first node in which one electrode of a capacitor is electrically connected to one of a source and a drain of a first transistor; A second node electrically connected to a gate of the transistor; and a source or drain of the first transistor, the other of which is electrically connected to one electrode of the photodiode. A first step of supplying and holding a first potential to a first node while supplying a second potential to a second node; and supplying a third potential to the second node. A second step of changing the potential of the first node by capacitive coupling of the capacitor; a step of changing the potential of the first node by the operation of the photodiode; and a potential of the second node by capacitive coupling of the capacitor. The third method of changing the potential and the fourth step of fixing the potential of the second node and reading the potential of the second node by operating the second transistor in the above order are the operation methods of the imaging apparatus. is there.

In the above operation, the first potential can be higher than the second potential.

The imaging device includes a third transistor, and supply of potential to the first node can be performed through the third transistor. Alternatively, the supply of the potential to the first node may be performed through a photodiode.

The imaging device includes a fourth transistor, and writing of the potential to the second node may be performed through the fourth transistor.

At least one of the transistors included in the imaging device includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

By using one embodiment of the present invention, an operation method of an imaging device for correcting output of image data can be provided. Alternatively, it is possible to provide an operation method of an imaging device in which output correction of image data can be performed in a few steps. Alternatively, it is possible to provide an operation method of an imaging device that holds correction data in a pixel. Alternatively, it is possible to provide an operation method of an imaging device that adds correction data held in a pixel and acquired image data. Alternatively, an operation method of an imaging device capable of generating a high voltage in a pixel can be provided. Alternatively, an operation method of an imaging device which can apply a high voltage to a photoelectric conversion device without using a dedicated power supply circuit can be provided.

Alternatively, an operation method of an imaging device with low power consumption can be provided. Alternatively, an operation method of an imaging device which can perform imaging at high speed can be provided. Alternatively, a highly reliable operation method of an imaging device can be provided. Alternatively, a new operation method of the imaging device can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a novel semiconductor device or the like can be provided.

FIG. 1 is a diagram illustrating a pixel circuit. FIG. 2 is a diagram illustrating a pixel circuit. FIG. 3 is a diagram illustrating a pixel circuit. FIG. 4 is a diagram illustrating a pixel circuit. FIG. 5 illustrates the operation of the pixel circuit. FIG. 6 is a diagram illustrating the operation of the pixel circuit. FIG. 7 illustrates the operation of the pixel circuit. FIG. 8 illustrates the operation of the pixel circuit. FIG. 9 illustrates the operation of the pixel circuit. FIG. 10 illustrates the operation of the pixel circuit. FIG. 11 illustrates the operation of the pixel circuit. FIGS. 12A and 12B are diagrams illustrating a pixel circuit. FIGS. 13A and 13B are diagrams illustrating a pixel circuit. FIG. 14 is a block diagram illustrating an imaging device. FIG. 15 is a diagram illustrating a simulation result. FIG. 16 is a diagram illustrating the simulation result. FIGS. 17A to 17E are diagrams illustrating a configuration of a pixel of an imaging device. FIGS. 18A and 18B are diagrams illustrating a configuration of a pixel of an imaging device. FIGS. 19A to 19C are diagrams illustrating a transistor. FIGS. 20A and 20B are diagrams illustrating a configuration of a pixel of an imaging device. FIGS. 21A to 21D are diagrams illustrating a transistor. FIGS. 22A to 22C are diagrams illustrating a configuration of a pixel of an imaging device. 23 (A1) to (A3) and (B1) to (B3) are perspective views of a package and a module containing the imaging device. FIGS. 24A to 24F are diagrams illustrating electronic devices.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated in some cases. In addition, the hatching of the same element which comprises a figure may be suitably omitted or changed between different drawings.

In addition, even if the element is illustrated as a single element on the circuit diagram, the element may be configured by a plurality of elements unless there is a functional inconvenience. For example, in some cases, a plurality of transistors operating as switches may be connected in series or in parallel. Further, the capacitor may be divided and arranged at a plurality of positions.

In addition, one conductor may have a plurality of functions such as a wiring, an electrode, and a terminal in some cases, and in this specification, a plurality of names may be used for the same element. In addition, even when the elements are illustrated as being directly connected on the circuit diagram, the elements may actually be connected via a plurality of conductors in some cases. In this document, such a configuration is also included in the category of direct connection.

(Embodiment 1)
In this embodiment, an imaging device which is one embodiment of the present invention and an operation method thereof will be described with reference to drawings.

One embodiment of the present invention is an operation method for correcting output of a source follower circuit included in a pixel circuit of an imaging device. By causing the charge detector to hold a threshold voltage unique to a transistor included in the source follower circuit, the threshold voltage of the transistor can be corrected. Therefore, image quality can be improved.

Further, a boost operation can be performed using the same pixel circuit. By generating a high voltage in a pixel, an avalanche photodiode can be operated without using a high-voltage power supply. Therefore, an imaging device with low power consumption and high sensitivity can be provided.

<Configuration Example 1>
FIG. 1 illustrates a pixel 10a that can be used for an imaging device of one embodiment of the present invention. The pixel 10a includes a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a transistor 106, a capacitor 107, and a capacitor 108. Note that a structure without the capacitor 108 may be employed.

One electrode (cathode) of the photoelectric conversion device 101 is electrically connected to one of a source and a drain of the transistor 102. The other of the source and the drain of the transistor 102 is electrically connected to one electrode of the capacitor 107. One electrode of the capacitor 107 is electrically connected to one of a source and a drain of the transistor 103. The other electrode of the capacitor 107 is electrically connected to one of the source and the drain of the transistor 104. One of a source and a drain of the transistor 104 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105. One of a source and a drain of the transistor 105 is electrically connected to one of a source and a drain of the transistor 106.

Here, a wiring connecting the other of the source or the drain of the transistor 102, one electrode of the capacitor 107, and one of the source or the drain of the transistor 103 is referred to as a node AD. A wiring connecting one of the source and the drain of the transistor 104, the other electrode of the capacitor 107, the one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD. The node AD can function as a charge storage unit, and the node FD can function as a charge detection unit.

The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to the wiring 122. The gate of the transistor 102 is electrically connected to the wiring 125. The other of the source and the drain of the transistor 103 is electrically connected to the wiring 123. The gate of the transistor 103 is electrically connected to the wiring 126. The other of the source and the drain of the transistor 104 is electrically connected to the wiring 128. The gate of the transistor 104 is electrically connected to the wiring 124. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring, for example. The other of the source and the drain of the transistor 105 is electrically connected to the wiring 121. The gate of the transistor 106 is electrically connected to the wiring 127. The other of the source and the drain of the transistor 106 is electrically connected to the wiring 129.

The wirings 121 and 122 can function as power supply lines. Further, the wiring 123 can have a function of supplying a reset potential. The potentials of the wirings 122 and 123 differ depending on the connection direction of the photoelectric conversion device 101. In the structure illustrated in FIG. 1, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, and the node AD is reset to a high potential to operate. Therefore, the wiring 122 has a low potential and the wiring 123 has a low potential. High potential. When the connection direction of the photoelectric conversion device 101 is opposite to that in FIG. 1, the wiring 122 may have a high potential and the wiring 123 may have a low potential. The wiring 128 can have a function of supplying correction data.

The wirings 124, 125, 126, and 127 can function as signal lines for controlling conduction of each transistor. The wiring 129 can function as an output line.

As the photoelectric conversion device 101, a photodiode can be used. To increase the light detection sensitivity, it is preferable to use an avalanche photodiode.

The transistor 102 has a function of supplying a specific potential to the node AD. The transistor 103 has a function of controlling the potential of the node AD. The transistor 104 has a function of supplying a specific potential to the node FD. The transistor 105 functions as a source follower circuit and can output the potential of the node FD to the wiring 129 as image data. The transistor 106 has a function of selecting a pixel to output image data.

When an avalanche photodiode is used for the photoelectric conversion device 101, a high voltage may be applied, and a transistor with a high withstand voltage is preferably used as a transistor connected to the photoelectric conversion device 101. As the high breakdown voltage transistor, for example, a transistor including a metal oxide in a channel formation region (hereinafter, an OS transistor) can be used. Specifically, it is preferable to apply an OS transistor to the transistors 102, 103, 104, and the like. Alternatively, an OS transistor may be used as the transistors 105 and 106.

Further, the OS transistor has a characteristic of extremely low off-state current. When an OS transistor is used for the transistors 102, 103, and 104, the period in which charge can be held at the node AD and the node FD can be extremely long. Therefore, it is possible to apply a global shutter method in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method.

Note that the present invention is not limited to the above, and an OS transistor and a transistor including Si in a channel formation region (hereinafter, a Si transistor) may be arbitrarily combined and applied. Further, all the transistors may be OS transistors or Si transistors. Examples of the Si transistor include a transistor including amorphous silicon, a transistor including crystalline silicon (typically, low-temperature polysilicon, single crystal silicon), and the like.

<Configuration Example 2>
The structure of the pixel 10b illustrated in FIG. 2 may be used for the imaging device of one embodiment of the present invention. This configuration is different from the pixel 10a illustrated in FIG. 1 in that the connection direction of the photoelectric conversion device 101 is reversed. The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to one of a source and a drain of the transistor 102, and one electrode (cathode) of the photoelectric conversion device 101 is electrically connected to a wiring 122. Other configurations are the same as those of the pixel 10a.

<Configuration Example 3>
The structure of the pixel 10c illustrated in FIG. 3 may be used for the imaging device of one embodiment of the present invention. This structure is different from the pixel 10a illustrated in FIG. 1 in that the transistor 103 is not provided. Other configurations are the same as those of the pixel 10a.

Although the transistor 103 included in the pixel 10a has a function of supplying a specific potential to the node AD, the pixel 10c can perform an operation of supplying a specific potential to the node AD through the photoelectric conversion device 101.

<Configuration Example 4>
The structure of the pixel 10d illustrated in FIG. 4 may be used in the imaging device of one embodiment of the present invention. This configuration differs from the pixel 10c illustrated in FIG. 3 in that the connection direction of the photoelectric conversion device 101 is reversed. The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to one of a source and a drain of the transistor 102, and one electrode (cathode) of the photoelectric conversion device 101 is electrically connected to a wiring 122. Other configurations are the same as those of the pixel 10c.

In the pixels 10a to 10d, the node AD and the node FD have a function as a storage node. Further, the capacitor 107 can hold the potential of the difference between the node AD and the node FD. Further, by the capacitive coupling of the capacitor 107, a potential corresponding to a change in the node AD can be added to the node FD in accordance with the capacitance ratio between the node FD and the capacitor 107. Alternatively, a potential corresponding to a change in the node FD can be added to the node AD.

By using these functions, the correction data can be held in the node FD, and the output of the source follower circuit can be corrected. Specifically, by holding the threshold voltage of the transistor 105 at the node FD, output characteristics of the transistor 105 between pixels can be uniform, and image quality can be improved.

In the pixels 10a and 10c, the potential of the node AD can be increased by capacitive coupling, and the avalanche photodiode can be operated. The operation of the avalanche photodiode requires the application of a high voltage.However, since the high voltage can be generated in the pixel by the above-described boosting operation, the avalanche photodiode can be operated without using a high voltage generation circuit. it can.

<Operation 1 of Configuration Example 1>
An example of the operation of the pixel 10a illustrated in FIG. 1 will be described with reference to a timing chart illustrated in FIG. In the description of the timing chart in this specification, the high potential is “HH” or “H” (“HH”> “H”), the low potential is “L”, and the reset potential is “VRS (H)” or Expressed as “VRS (L)”. The reset potential used differs depending on the configuration of the pixel. The threshold voltage of a specific transistor is represented by “Vth”, and the forward voltage of a photoelectric conversion device (photodiode) is represented by “Vf”. It is assumed that “H” is constantly supplied to the wiring 121.

Note that detailed changes in potential distribution, coupling, or loss due to a circuit configuration, operation timing, or the like are not considered here. The change in potential due to capacitive coupling using a capacitor depends on the capacitance ratio between the capacitor and the connected element, but for clarity of explanation, the capacitance value of the element is assumed to be sufficiently small. I do.

First, the operation 1 in the pixel 10a will be described. This operation is an operation in which the node FD holds the threshold voltage “Vth” of the transistor 105 as correction data, and corrects image data output from the transistor 105.

In the period T1, the potential of the wiring 123 is “L”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “H”, and the potential of the wiring 127 is “L”. When the potential of 128 is set to “Vth”, the transistor 103 is turned on, and the potential “L” of the wiring 123 is supplied to the node AD. Further, the transistor 104 is turned on, and the correction data “Vth” is written to the node FD. In the above operation, "Vth-L" is held in the capacitor 107.

Here, the correction data “Vth” is a threshold voltage of the transistor 105, and outputs an electrical characteristic of the transistor 105 to the wiring 129 before an imaging operation, and outputs the threshold voltage to an external circuit connected to the wiring 129. Is generated in advance. That is, the pixel circuit has a function of performing external correction, and the external circuit is electrically connected to the wiring 128.

In the period T2, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “H”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “L”, the potential “VRS (H)” of the wiring 123 is supplied to the node AD. At this time, the potential of the node FD becomes “Vth + VRS (H) −L ′” due to the capacitive coupling of the capacitor 107 (reset operation).

Assuming that the capacitance value of the capacitor 107 is C ₁₀₇ and the capacitance value of the node FD is C _FD , the potential of the node FD is (“Vth”) + (C ₁₀₇ / (C ₁₀₇ + C _FD )) × (“VRS (H) -L "). _Therefore, if it possible to ignore the value of increasing the value of _{C 107 C FD,} the potential of the node FD becomes "Vth + VRS (H) -L " at maximum. Here, assuming that “L” is 0 V and C _FD has an appropriate value, the potential of the node FD can be expressed as “Vth + VRS (H) ′”.

In the period T3, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. When the potential of the wiring 128 is set to “L”, the potential of the node AD decreases in accordance with the operation of the photoelectric conversion device 101, and the potential of the node FD also decreases due to capacitive coupling of the capacitor 107 (accumulation operation).

In the period T4, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “L”, the potentials of the node AD and the node FD are determined and held. Here, assuming that the decrease in the potential of the node AD is "X", the potential of the node AD is "VRS (H) -X", and the potential of the node FD is "Vth + VRS (H) '-X" in consideration of the capacitance ratio. Can be represented as' ”.

In the period T5, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “H”. When the potential of the wiring 128 is set to “L”, the transistor 106 is turned on and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, since the potential of the node FD is “Vth + VRS (H) ′ − X ′”, “VRS (H) ′ − X ′” which does not include “Vth” of the transistor 105 is read to the wiring 129. That is, even when the threshold voltage of the transistor 105 is not uniform in each pixel, data can be read without relating the threshold voltage.

The periods T11 to T14 show the operation of the second frame assuming a moving image. In the period T1 of the first frame, “Vth−L” held in the capacitor 107 does not change ideally, so that it is not necessary to perform the “Vth” write operation again. In the second and subsequent frames, imaging can be performed by repeating the operation in the periods T2 to T5 of the first frame.

Note that in order to prevent “Vth−L” held in the capacitor 107 from being changed, it is preferable to use an OS transistor with low off-state current for the transistors 102, 103, and 104 as described above. Note that in order to perform the correction with high accuracy, the write operation of “Vth” may be performed at regular intervals. When a still image or the like is captured, the writing operation of “Vth” may be performed every time.

In the above description of the operation, the correction data held at the node FD is “Vth”, but a fixed potential Y such as “Vth + Y” may be added. Alternatively, correction data for performing correction such as luminance may be used.

<Operation 2 of Configuration Example 1>
Next, the operation 2 in the pixel 10a will be described with reference to the timing chart of FIG. This operation is an operation in which the node FD holds the threshold voltage “Vth” of the transistor 105 + the reset potential “VRS (H)” as correction data, and corrects image data output from the transistor 105.

In this operation, “VRS (H)” is also written at the time of writing “Vth”, so that the imaging operation can be shortened.

In the period T1, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “H”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “Vth + VRS (H)”, the transistor 103 is turned on and the potential “VRS (H)” of the wiring 123 is supplied to the node AD. Further, the transistor 104 is turned on, and the correction data “Vth + VRS (H)” is written to the node FD (reset operation). In the above operation, “Vth” is held in the capacitor 107.

In the period T2, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. When the potential of the wiring 128 is set to “L”, the potential of the node AD decreases in accordance with the operation of the photoelectric conversion device 101, and the potential of the node FD also decreases due to capacitive coupling of the capacitor 107 (accumulation operation).

In the period T3, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “L”, the potentials of the node AD and the node FD are determined and held. Here, assuming that the drop in the potential of the node AD is “X”, the potential of the node AD is “VRS (H) −X”, and the potential of the node FD is “Vth + VRS (H) −X ′ in consideration of the capacitance ratio. ".

In the period T4, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “H”. When the potential of the wiring 128 is set to “L”, the transistor 106 is turned on and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, since the potential of the node FD is “Vth + VRS (H) −X ′”, “VRS (H) −X ′” which does not include “Vth” of the transistor 105 is read out to the wiring 129. That is, data to which the threshold voltage of the transistor 105 is not related in each pixel can be read.

The periods T11 to T14 show the operation of the second frame assuming a moving image. Since “Vth” held in the capacitor 107 does not change ideally, the reset operation of the node FD can be performed by supplying “VRS (H)” to the node AD in the second and subsequent frames, so that imaging can be performed. It can be carried out.

<Operation 3 of Configuration Example 1>
Next, operation 3 in the pixel 10a will be described with reference to the timing chart of FIG. This operation is an operation in which the potential of the node AD is boosted and applied to the photoelectric conversion device 101. By performing the operation, the avalanche photodiode can be operated without using a high-voltage power supply. In performing the operation, it is preferable to use an avalanche photodiode for the photoelectric conversion device 101.

In the period T1, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “H”, and the potential of the wiring 127 is “L”. When the potential of the wiring 128 is set to “L”, the transistor 104 is turned on and the potential “L” of the wiring 128 is supplied to the node FD. Further, the transistor 103 is turned on, so that the potential “VRS (H)” of the wiring 123 is written to the node AD. In the above operation, “VRS (H) −L” is held in the capacitor 107.

In the period T2, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “VRS (H)”, the potential “VRS (H)” of the wiring 128 is supplied to the node FD. At this time, the potential of the node AD becomes “VRS (H) + VRS (H) ′” = “HH” due to the capacitive coupling of the capacitor 107 (reset operation).

_{C 107} the value of the capacitance of the capacitor 107 and the capacitance value of the node AD and _{C AD,} the potential of the node _{AD, ( "VRS (H)} ") + (C 107 / (C 107 + C AD)) × ( "VRS (H) -L "). _Here, by increasing the value of _{C 107,} if negligible values of _{C AD,} the potential of the node AD becomes "VRS (H) + VRS ( H) -L" at maximum. Here, assuming that “L” is 0 V and _CAD has an appropriate value, the potential of the node AD can be expressed as “VRS (H) + VRS (H) ′” = “HH”. .

“VRS (H)” is preferably set so that the photoelectric conversion device 101 reaches a voltage that exhibits avalanche multiplication characteristics at “VRS (H) + VRS (H) ′”. For example, “VRS (H)” is a voltage higher than 電 圧 of the voltage at which the photoelectric conversion device 101 exhibits avalanche multiplication characteristics.

In the period T3, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. When the potential of the wiring 128 is set to “L”, the potential of the node AD decreases in accordance with the operation of the photoelectric conversion device 101, and the potential of the node FD also decreases due to capacitive coupling of the capacitor 107 (accumulation operation).

In the period T4, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “L”, the potentials of the node AD and the node FD are determined and held. Here, assuming that the decrease in the potential of the node AD is “X”, the potential of the node AD is “VRS (H) + VRS (H) ′ − X”, and the potential of the node FD is “VRS (H) −X ′”. Can be expressed as

In the period T5, the potential of the wiring 123 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “H”. When the potential of the wiring 128 is set to “L”, the transistor 106 is turned on and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, the potential of the node FD is “VRS (H) −X ′”, and “VRS (H) −X′−Vth” is read to the wiring 129. Since the high voltage “HH” is not applied to the node FD including the reset operation period, the reliability of the transistor connected to the node FD can be improved.

The periods T11 to T14 show the operation of the second frame assuming a moving image. In the period T1 of the first frame, “VRS (H) −L” held in the capacitor 107 does not change ideally, so that it is not necessary to write “VRS (H)” to the node AD again. In the second and subsequent frames, imaging can be performed by repeating the operation in the periods T2 to T5 of the first frame.

<Operation of Configuration Example 2>
Next, the operation of the pixel 10b will be described with reference to the timing chart of FIG. This operation is an operation in which the node FD holds the threshold voltage “Vth” of the transistor 105 as correction data, and corrects image data output from the transistor 105.

In this operation, since “VRS (L)” is also written at the time of writing “Vth”, the imaging operation can be shortened.

In the period T1, the potential of the wiring 123 is “VRS (L)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “H”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “Vth”, the transistor 103 is turned on and the potential “VRS (L)” of the wiring 123 is supplied to the node AD. Further, the transistor 104 is turned on, and the correction data “Vth” is written to the node FD (reset operation). In the above operation, “Vth−VRS (L)” is held in the capacitor 107.

In the period T2, the potential of the wiring 123 is “VRS (L)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. When the potential of the wiring 128 is set to “L”, the potential of the node AD increases in accordance with the operation of the photoelectric conversion device 101, and the potential of the node FD also increases due to capacitive coupling of the capacitor 107 (accumulation operation).

In the period T3, the potential of the wiring 123 is “VRS (L)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “L”. Assuming that the potential of the wiring 128 is “L”, the potentials of the node AD and the node FD are determined and held. Here, assuming that the increase in the potential of the node AD is “X”, the potential of the node AD can be represented as “VRS (L) + X”, and the potential of the node FD can be represented as “Vth + X ′” in consideration of the capacitance ratio. .

In the period T4, the potential of the wiring 123 is “VRS (L)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 126 is “L”, and the potential of the wiring 127 is “H”. When the potential of the wiring 128 is set to “L”, the transistor 106 is turned on and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, since the potential of the node FD is “Vth + X ′”, “X ′” which does not include “Vth” of the transistor 105 is read to the wiring 129. That is, data to which the threshold voltage of the transistor 105 is not related in each pixel can be read.

The periods T11 to T14 show the operation of the second frame assuming a moving image. Since “Vth−VRS (L)” held in the capacitor 107 does not change ideally, the reset operation of the node FD is performed by supplying “VRS (L)” to the node AD in the second and subsequent frames. And imaging can be performed.

<Operation 1 of Configuration Example 3>
Next, the operation 1 in the pixel 10c will be described with reference to the timing chart of FIG. This operation is an operation in which the node FD holds the threshold voltage “Vth” of the transistor 105 + the reset potential “VRS (H)” as correction data, and corrects image data output from the transistor 105. Note that in this operation, the reset potential “VRS (H)” is set to a value sufficiently larger than the forward voltage “Vf” of the photoelectric conversion device 101.

In the period T1, the potential of the wiring 122 is “VRS (H)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “H”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “Vth + VRS”. (H), a forward current flows through the photoelectric conversion device 101, and the potential “VRS (H)” − “Vf” of the wiring 122 is supplied to the node AD. Further, the transistor 104 is turned on, and the correction data “Vth + VRS (H)” is written to the node FD (reset operation). In the above operation, “Vth−Vf” is held in the capacitor 107.

In the period T2, the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. The potential of the node AD decreases in accordance with the operation of the photoelectric conversion device 101, and the potential of the node FD also decreases due to capacitive coupling of the capacitor 107 (accumulation operation).

In the period T3, when the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. , Node AD and node FD are determined and held. Here, assuming that the drop in the potential of the node AD is “X”, the potential of the node AD is “VRS (H) −Vf−X”, and the potential of the node FD is “Vth + VRS (H) − in consideration of the capacitance ratio. X '".

In the period T4, the potential of the wiring 122 is “VRS (H)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “H”, and the potential of the wiring 128 is “L”. ", The transistor 106 is turned on, and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, since the potential of the node FD is “Vth + VRS (H) −X ′”, “VRS (H) −X ′” which does not include “Vth” of the transistor 105 is read out to the wiring 129. That is, data to which the threshold voltage of the transistor 105 is not related in each pixel can be read.

The periods T11 to T14 show the operation of the second frame assuming a moving image. Since “Vth−Vf” held in the capacitor 107 does not change ideally, the reset operation of the node FD can be performed by supplying “VRS (H)” to the node AD after the second frame. Imaging can be performed.

<Operation 2 of Configuration Example 3>
Next, the operation 2 in the pixel 10c will be described with reference to the timing chart of FIG. This operation is an operation in which the potential of the node AD is boosted and applied to the photoelectric conversion device 101, similarly to the operation 2 of the pixel 10a.

In the period T1, the potential of the wiring 122 is “VRS (H)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. ", The transistor 104 is turned on, and the potential" L "of the wiring 128 is supplied to the node FD. In addition, a forward current flows through the photoelectric conversion device 101, and the potential “VRS (H)” − “Vf” of the wiring 122 is supplied to the node AD. In the above operation, “VRS (H) −Vf−L” is held in the capacitor 107.

In the period T2, the potential of the wiring 122 is “VRS (H)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “VRS”. (H), the potential “VRS (H)” of the wiring 128 is supplied to the node FD. At this time, the potential of the node AD becomes “VRS (H) −Vf + VRS (H) ′” = “HH” due to the capacitive coupling of the capacitor 107 (reset operation).

_{C 107} the value of the capacitance of the capacitor 107 and the capacitance value of the node AD and _{C AD,} the potential of the node _{AD, ( "VRS (H)} ") + (C 107 / (C 107 + C AD)) × ( "VRS (H) -Vf "). _Here, by increasing the value of _{C 107,} if negligible values of _{C AD,} the potential of the node AD becomes "VRS (H) -Vf + VRS (H)" at the maximum. _Here, the _{C AD} is assumed to have an appropriate value, the potential of the node FD may be represented as "VRS (H) -Vf + VRS (H) '" = "HH".

“VRS (H)” is preferably set such that “VRS (H) −Vf + VRS (H) ′” reaches a voltage at which the photoelectric conversion device 101 exhibits avalanche multiplication characteristics. For example, “VRS (H) −Vf” is a voltage higher than 電 圧 of the voltage at which the photoelectric conversion device 101 exhibits the avalanche multiplication characteristic.

In the period T3, when the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. The potential of the node AD decreases in accordance with the operation of the photoelectric conversion device 101, and the potential of the node FD also decreases due to capacitive coupling of the capacitor 107 (accumulation operation).

In the period T4, when the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. , Node AD and node FD are determined and held. Here, assuming that the decrease in the potential of the node AD is “X”, the potential of the node AD is “VRS (H) −Vf + VRS (H) ′ − X”, and the potential of the node FD is “VRS (H) −X ′”. ".

In the period T5, the potential of the wiring 122 is “H”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “H”, and the potential of the wiring 128 is “L”. Then, the transistor 106 is turned on, and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, the potential of the node FD is “VRS (H) −X ′”, and “VRS (H) −X′−Vth” is read to the wiring 129. Since the high voltage “HH” is not applied to the node FD including the reset operation period, the reliability of the transistor connected to the node FD can be improved.

The periods T11 to T14 show the operation of the second frame assuming a moving image. In the period T1 of the first frame, since “VRS (H) −Vf−L” held in the capacitor 107 does not change ideally, it is necessary to write “VRS (H) −Vf” to the node AD again. There is no. In the second and subsequent frames, imaging can be performed by repeating the operation in the periods T2 to T5 of the first frame.

<Operation of Configuration Example 4>
Next, the operation of the pixel 10d will be described with reference to the timing chart of FIG. This operation is an operation in which the node FD holds the threshold voltage “Vth” of the transistor 105 as correction data, and corrects image data output from the transistor 105. In this operation, the reset potential “VRS (L)” is set to a value smaller than the forward voltage “Vf” of the photoelectric conversion device 101.

In the period T1, the potential of the wiring 122 is “VRS (L)”, the potential of the wiring 124 is “H”, the potential of the wiring 125 is “H”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “Vth”. ", A forward current flows through the photoelectric conversion device 101, and the potential of the node AD becomes" VRS (L) "+" Vf ". Further, the transistor 104 is turned on, and the correction data “Vth” is written to the node FD (reset operation). In the above operation, “Vth−VRS (L) + Vf” is held in the capacitor 107.

In the period T2, the potential of the wiring 122 is “H”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “H”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. The potential of the node AD rises in response to the operation of the photoelectric conversion device 101, and the potential of the node FD also rises due to the capacitive coupling of the capacitor 107 (accumulation operation).

In the period T3, when the potential of the wiring 122 is “H”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”. , Node AD and node FD are determined and held. Here, assuming that the increase in the potential of the node AD is “X”, the potential of the node AD can be represented as “VRS (L) + VF + X”, and the potential of the node FD can be represented as “Vth + X ′” in consideration of the capacitance ratio. .

In the period T4, the potential of the wiring 122 is “VRS (L)”, the potential of the wiring 124 is “L”, the potential of the wiring 125 is “L”, the potential of the wiring 127 is “H”, and the potential of the wiring 128 is “L”. ", The transistor 106 is turned on, and the potential of the node FD is read out to the wiring 129 by the source follower operation of the transistor 105. At this time, since the potential of the node FD is “Vth + X ′”, “X ′” which does not include “Vth” of the transistor 105 is read to the wiring 129. That is, data to which the threshold voltage of the transistor 105 is not related in each pixel can be read.

The periods T11 to T14 show the operation of the second frame assuming a moving image. Since “Vth−VRS (L) + Vf” held in the capacitor 107 does not change ideally, the reset operation of the node FD is performed by supplying “VRS (L)” to the node AD after the second frame. And imaging can be performed.

Further, in one embodiment of the present invention, as illustrated in FIGS. 12A and 12B, a structure in which a back gate is provided for a transistor may be employed. FIG. 12A illustrates a structure in which the back gate is electrically connected to the front gate, which has an effect of increasing on-state current. FIG. 12B illustrates a structure in which the back gate is electrically connected to a wiring which can supply a constant potential, so that the threshold voltage of the transistor can be controlled.

Alternatively, a structure in which each transistor can perform appropriate operation, such as a combination of FIGS. 12A and 12B, may be employed. Further, the pixel circuit may include a transistor without a back gate. Note that a structure in which a back gate is provided for a transistor can be applied to all of the pixels 10a to 10d.

In a pixel including the transistor 103, one of a source and a drain of the transistor 103 and one electrode of the photoelectric conversion device 101 may be electrically connected to each other as illustrated in FIG. In this structure, when a potential is supplied from the wiring 123 to the node AD, an operation of turning on the transistor 102 and the transistor 103 may be performed.

Further, in all of the pixels 10a to 10d, a transistor 106 may be electrically connected between the transistor 105 and the wiring 121 as illustrated in FIG.

FIG. 14 is an example of a block diagram illustrating a circuit configuration of an imaging device of one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels 10 arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, and a circuit 23 having a function of reading data from the pixels 10. And a circuit 27 having a function of generating correction data, and a circuit 28 (column driver) having a function of supplying the correction data to the pixels 10. Any of the pixels 10a, 10b, 10c, and 10d can be used as the pixel 10.

The circuit 23 includes a circuit 24 (column driver) having a function of selecting a column of the pixel array 21, a circuit 25 (CDS circuit) for performing correlated double sampling processing on output data of the pixel 10, and a circuit 25. Circuit 26 (such as an A / D conversion circuit) that has a function of converting analog data output from the device into digital data.

The circuit 23 is electrically connected to the wiring 129 and can output data output from the pixel 10 to the circuit 27. Alternatively, data output from the pixel 10 can be converted into digital data and then output to the outside. For example, the output destination may be a neural network, a storage device, a display device, a communication device, or the like.

The circuit 27 can generate correction data from the input data. The generated correction data is supplied to the pixel 10 via the circuit 28 and the wiring 128.

All the operations of the pixels 10a to 10d described in this embodiment can be applied to the imaging device in the block diagram in FIG. Note that in the case where the operation 3 of the pixel 10a and the operation 2 of the pixel 10c are performed, a configuration in which the circuit 27 and the circuit 28 are omitted may be employed.

Next, a simulation result regarding the operation of the pixel circuit will be described. In the simulation, assuming the circuit and operation 1 of the pixel 10a shown in FIG. 1, the potential change and the output value of the node AD and the node FD were calculated. Note that 0 V, 1 V, or 2 V was used as the correction data.

The parameters used in the simulation are as follows. The transistor size is L / W = 3 μm / 10 μm (transistors 102, 103, 104), L / W = 3 μm / 50 μm (transistors 105 and 106), and the capacitance value of the capacitor 107 Is 2 pF, the capacitance value of the capacitor 108 is 0.2 pF, and the reset potential (VRS) is 20 V. Further, the voltage applied to the gate of the transistor was +26 V for “H” and 0 V for “L”. Note that SPICE was used as the circuit simulation software.

FIG. 15 shows a simulation result until reading of the second frame when 1 V corresponding to “Vth” is used as the correction data. The horizontal axis is the common time, the vertical axis VRS is the potential of the wiring 123, SE2 is the potential of the wiring 124, TX is the potential of the wiring 125, RS is the potential of the wiring 126, SE1 is the potential of the wiring 127, and CAL is the potential of the wiring 128. The potential, AD indicates the potential of the node AD, FD indicates the potential of the node FD, and OUT indicates the potential of the wiring 129.

As in the timing chart shown in FIG. 5, it was confirmed that writing of Vth, resetting of the node AD, potential change of the node FD due to capacitive coupling, and reading can be performed.

FIG. 16 is a diagram illustrating a potential change of the node FD when the correction data is set to 0 V, 1 V, and 2 V. Since there is no change in the difference between the correction data at the time of reset and at the time of reading, it was confirmed that the correction data was held without change.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, an example of a structure of an imaging device of one embodiment of the present invention will be described.

FIGS. 17A and 17B illustrate a structure of a pixel included in an imaging device. The pixel illustrated in FIG. 17A is an example in which a layered structure of a layer 561 and a layer 562 is provided.

The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can be a stack of a layer 565a, a layer 565b, and a layer 565c as illustrated in FIG.

The photoelectric conversion device 101 illustrated in FIG. 17C is a pn junction photodiode. For example, a p ⁺ -type semiconductor can be used for the layer 565a, an n-type semiconductor can be used for the layer 565b, and an n ⁺ -type semiconductor can be used for the layer 565c. Alternatively, an n ⁺ -type semiconductor may be used for the layer 565a, a p-type semiconductor for the layer 565b, and a p ⁺ -type semiconductor for the layer 565c. Alternatively, a pin junction photodiode in which the layer 565b is an i-type semiconductor may be used.

The pn junction photodiode or the pin junction photodiode can be formed using single crystal silicon. Further, the pin junction photodiode can be formed using a thin film of amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

The photoelectric conversion device 101 included in the layer 561 may be a stack of a layer 566a, a layer 566b, a layer 566c, and a layer 566d as illustrated in FIG. The photoelectric conversion device 101 illustrated in FIG. 17D is an example of an avalanche photodiode. The layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to photoelectric conversion portions.

It is preferable to use a low-resistance metal layer or the like for the layer 566a. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

For the layer 566d, a conductive layer having high light-transmitting property with respect to visible light is preferably used. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that a structure in which the layer 566d is omitted can be employed.

The layers 566b and 566c of the photoelectric conversion portion can have a configuration of a pn junction photodiode using a selenium-based material as a photoelectric conversion layer, for example. It is preferable that a selenium-based material which is a p-type semiconductor be used for the layer 566b and gallium oxide which is an n-type semiconductor be used for the layer 566c.

A photoelectric conversion device using a selenium-based material has characteristics of high external quantum efficiency with respect to visible light. In the photoelectric conversion device, amplification of electrons with respect to the amount of incident light (Light) can be increased by using avalanche multiplication. In addition, since the selenium-based material has a high light absorption coefficient, it has an advantage in production such that a photoelectric conversion layer can be formed using a thin film. The selenium-based material thin film can be formed by a vacuum evaporation method, a sputtering method, or the like.

Examples of the selenium-based material include crystalline selenium such as single-crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, and a compound of selenium (CIS) or a compound of copper, indium, gallium, and selenium (CIGS). Can be used.

The n-type semiconductor is preferably formed using a material having a wide band gap and a property of transmitting visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, an oxide in which they are mixed, or the like can be used. In addition, these materials also have a function as a hole injection blocking layer and can reduce dark current.

The photoelectric conversion device 101 included in the layer 561 may be a stack of a layer 567a, a layer 567b, a layer 567c, a layer 567d, and a layer 567e as illustrated in FIG. The photoelectric conversion device 101 illustrated in FIG. 17D is an example of an organic photoconductive film, in which the layers 567a and 567e correspond to electrodes, and the layers 567b, 567c, and 567d correspond to photoelectric conversion portions.

One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer and the other can be an electron transport layer. Further, the layer 567c can be a photoelectric conversion layer.

As the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transporting layer, for example, fullerenes such as C60 and C70 or derivatives thereof can be used.

As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

As the layer 562 illustrated in FIG. 17A, a silicon substrate can be used, for example. The silicon substrate has a Si transistor and the like. With the use of the Si transistor, a circuit for driving the pixel circuit, a circuit for reading an image signal, an image processing circuit, and the like can be provided in addition to the pixel circuit. Specifically, part or all of the transistors included in the pixel circuit and the peripheral circuit (the pixel 10, the circuits 22, 23, 27, and 28) described in Embodiment 1 can be provided in the layer 562.

Further, the pixel may have a stacked structure of a layer 561, a layer 563, and a layer 562 as illustrated in FIG.

The layer 563 can include an OS transistor (eg, the transistors 102, 103, and 104 of the pixel 10a). At this time, the layer 562 may include a Si transistor (eg, the transistors 105 and 106 of the pixel 10a). Further, some of the transistors included in the peripheral circuit described in Embodiment 1 may be provided in the layer 563.

With such a structure, the elements and the peripheral circuits included in the pixel circuit can be dispersed in a plurality of layers and the elements or the element and the peripheral circuit can be provided in an overlapping manner; thus, the area of the imaging device can be reduced. be able to. Note that in the structure in FIG. 17B, the layer 562 may be used as a supporting substrate, and the layer 561 and the layer 563 may be provided with the pixel 10 and a peripheral circuit.

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium or the like is used; for example, a CAAC-OS or a CAC-OS described later can be used. The CAAC-OS has stable atoms in its crystal and is suitable for a transistor or the like in which reliability is emphasized. In addition, since the CAC-OS has high mobility characteristics, it is suitable for a transistor that drives at high speed or the like.

The OS transistor has an extremely low off-current characteristic of several yA / μm (current value per 1 μm of channel width) because the energy gap of the semiconductor layer is large. Further, the OS transistor has characteristics different from those of the Si transistor, such as generation of impact ionization, avalanche breakdown, and a short-channel effect, and can form a highly reliable circuit with high withstand voltage. In addition, variation in electrical characteristics due to non-uniformity of crystallinity, which is a problem in the Si transistor, hardly occurs in the OS transistor.

The semiconductor layer included in the OS transistor is formed using an In-M-Zn-based oxide including, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). Can be obtained.

In the case where the oxide semiconductor included in the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. As atomic ratios of metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 and the like are preferable. Note that each of the atomic ratios of the semiconductor layers to be formed includes a variation of ± 40% of the atomic ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, further preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3. ³ or less, more preferably less than 1 × 10 ¹⁰ / cm ³ , and an oxide semiconductor with a carrier density of 1 × 10 ⁻⁹ / cm ³ or more can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect states and has stable characteristics.

Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electric characteristics (eg, field-effect mobility and threshold voltage) of the transistor. In addition, in order to obtain necessary semiconductor characteristics of a transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like be appropriate. .

When the oxide semiconductor included in the semiconductor layer contains silicon or carbon, which is one of Group 14 elements, oxygen vacancies increase and the semiconductor becomes n-type. For this reason, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is set to 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, an alkali metal and an alkaline earth metal may generate carriers when combined with an oxide semiconductor, which may increase off-state current of a transistor. For this reason, the concentration of the alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To

In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons serving as carriers are generated, the carrier density is increased, and the semiconductor is likely to be n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, when hydrogen is contained in the oxide semiconductor included in the semiconductor layer, oxygen reacts with oxygen bonded to a metal atom to become water, so that oxygen vacancies may be formed in the oxide semiconductor in some cases. When oxygen vacancies are contained in a channel formation region in an oxide semiconductor, the transistor might have normally-on characteristics. Further, a defect in which hydrogen is contained in an oxygen vacancy functions as a donor, and an electron serving as a carrier may be generated. Further, in some cases, part of hydrogen is bonded to oxygen which is bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor including an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics.

A defect in which hydrogen is contained in an oxygen vacancy can function as a donor of an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, in some cases, an oxide semiconductor is evaluated not by a donor concentration but by a carrier concentration. Therefore, in this specification and the like, a carrier concentration which assumes a state where an electric field is not applied may be used instead of a donor concentration as a parameter of an oxide semiconductor in some cases. That is, the “carrier concentration” described in this specification and the like may be referred to as a “donor concentration” in some cases.

Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is lower than 1 × 10 ²⁰ atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm 3. ^{It is} less than ³ , more preferably less than 5 × 10 ¹⁸ atoms / cm ³ , further preferably less than 1 × 10 ¹⁸ atoms / cm ³ . When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electric characteristics can be provided.

Further, the semiconductor layer may have a non-single-crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a crystal oriented in the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystalline component. Alternatively, an oxide semiconductor film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.

Note that even when the semiconductor layer is a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. The mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions, for example.

The structure of a cloud-aligned composite (CAC) -OS, which is one embodiment of a non-single-crystal semiconductor layer, is described below.

The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of, for example, 0.5 nm or more and 10 nm or less, preferably, 1 nm or more and 2 nm or less. Note that in the following, one or more metal elements are unevenly distributed in an oxide semiconductor, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or a size in the vicinity thereof. The state mixed by is also referred to as a mosaic shape or a patch shape.

Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Or one or more selected from the above.

For example, a CAC-OS in an In-Ga-Zn oxide (an In-Ga-Zn oxide may be referred to as a CAC-IGZO among CAC-OSs) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium Oxide (hereinafter, referred to as GaO _X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers larger than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That is, the CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are mixed. Note that in this specification, for example, it is assumed that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that of the region No. 2.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are _represented by InGaO 3 _(ZnO) m1 (m1 is a natural number), or _{In (1 + x0) Ga (} 1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.

The above crystalline compound has a single crystal structure, a polycrystal structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, the CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, a region which is observed in the form of a nanoparticle mainly containing Ga as a part and a nanoparticle mainly containing In as a part. A region observed in a shape refers to a configuration in which each region is randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure including two layers of a film mainly containing In and a film mainly containing Ga is not included.

Note that in some cases, a clear boundary cannot be observed between a region where GaO _X3 is a main component and a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component.

Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like In the case where one or a plurality of kinds are included, the CAC-OS is divided into a region which is observed in the form of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each of the regions is randomly dispersed in a mosaic shape.

The CAC-OS can be formed by, for example, a sputtering method under conditions in which the substrate is not heated intentionally. In the case where the CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas is used as a deposition gas. Good. Further, it is preferable that the flow ratio of the oxygen gas to the total flow rate of the film formation gas at the time of film formation be as low as possible. .

The CAC-OS is characterized in that a clear peak is not observed when measured using a θ / 2θ scan by an Out-of-plane method, which is one of X-ray diffraction (X-ray diffraction) measurement methods. Have. That is, from the X-ray diffraction measurement, it is understood that the orientation in the a-b plane direction and the c-axis direction of the measurement region is not observed.

In addition, the CAC-OS includes, in an electron beam diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm, a region (ring region) having a high luminance in a ring shape and the ring region. Multiple bright spots are observed in the area. Accordingly, the electron diffraction pattern shows that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in a planar direction and a cross-sectional direction.

In addition, for example, in a CAC-OS in an In-Ga-Zn oxide, GaO _X3 or the like is a main component by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that a certain region and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are unevenly distributed and mixed.

The CAC-OS has a different structure from an IGZO compound in which metal elements are uniformly distributed, and has different properties from the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component. Has a mosaic structure.

Here, a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is a region having higher conductivity than a region in which GaO _X3 or the like is a main component. That is, the conductivity of the oxide semiconductor is exhibited by the flow of carriers in a region containing In _X2 Zn _Y3 O _Z2 or InO _X1 as a main component. Therefore, high field-effect mobility (μ) can be realized by distributing a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component in a cloud shape in the oxide semiconductor.

On the other hand, a region containing GaO _X3 or the like as a main component is a region having higher insulating properties than a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component. That is, a region in which GaO _X3 or the like is a main component is distributed in the oxide semiconductor, so that a leak current can be suppressed and a favorable switching operation can be realized.

Therefore, in the case where a CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, so that high performance is obtained. On-state current (I _on ) and high field-effect mobility (μ) can be realized.

A semiconductor element using the CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material of various semiconductor devices.

FIG. 18A illustrates an example of a cross section of the pixel illustrated in FIG. The layer 561 includes, as the photoelectric conversion device 101, a pn junction photodiode including silicon as a photoelectric conversion layer. The layer 562 includes a Si transistor, and FIG. 18A illustrates the transistors 102 and 103 included in a pixel circuit.

In the photoelectric conversion device 101, the layer 565a can be a p ⁺ -type region, the layer 565b can be an n-type region, and the layer 565c can be an n ⁺ -type region. In the layer 565b, a region 536 for connecting a power supply line to the layer 565c is provided. For example, region 536 can be ap ⁺ type region.

The Si transistor illustrated in FIG. 18A is a fin type having a channel formation region in a silicon substrate 540, and a cross section in the channel width direction is illustrated in FIG. The Si transistor may be of a planar type as shown in FIG.

Alternatively, as illustrated in FIG. 19C, a transistor including a silicon thin film semiconductor layer 545 may be used. The semiconductor layer 545 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed over the insulating layer 546 over the silicon substrate 540.

FIG. 18A illustrates an example of a structure in which an element included in the layer 561 and an element included in the layer 562 are electrically connected to each other by a bonding technique.

The layer 561 is provided with an insulating layer 542, a conductive layer 533, and a conductive layer 534. Each of the conductive layers 533 and 534 has a region embedded in the insulating layer 542. The conductive layer 533 is electrically connected to the layer 565a. The conductive layer 534 is electrically connected to the region 536. The surfaces of the insulating layer 542, the conductive layer 533, and the conductive layer 534 are flattened so that their heights are the same.

The insulating layer 541, the conductive layer 531, and the conductive layer 532 are provided for the layer 562. Each of the conductive layers 531 and 532 has a region embedded in the insulating layer 541. The conductive layer 532 is electrically connected to a power supply line. The conductive layer 531 is electrically connected to a source or a drain of the transistor 102. The surfaces of the insulating layer 541, the conductive layer 531 and the conductive layer 532 are flattened so that their heights are the same.

Here, it is preferable that the main components of the conductive layer 531 and the conductive layer 533 be the same metal element. It is preferable that the main components of the conductive layer 532 and the conductive layer 534 be the same metal element. Further, the insulating layer 541 and the insulating layer 542 are preferably formed using the same component.

For example, for the conductive layers 531, 532, 533, and 534, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used. Cu, Al, W, or Au is preferably used from the viewpoint of easy joining. For the insulating layers 541 and 542, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used.

That is, it is preferable to use the same metal material described above for each of the combination of the conductive layers 531 and 533 and the combination of the conductive layers 532 and 534. Further, it is preferable to use the same insulating material described above for each of the insulating layer 541 and the insulating layer 542. With this structure, bonding can be performed with the boundary between the layer 561 and the layer 562 as a bonding position.

Through the bonding, electrical connection of each of the combination of the conductive layers 531 and 533 and the combination of the conductive layers 532 and 534 can be obtained. Further, a connection having mechanical strength between the insulating layer 541 and the insulating layer 542 can be obtained.

For the bonding of the metal layers, a surface activated bonding method in which an oxide film on the surface, an adsorption layer of impurities, and the like are removed by a sputtering process or the like and the cleaned and activated surfaces are brought into contact with each other and bonded together can be used. . Alternatively, a diffusion bonding method in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that a bonding excellent not only electrically but also mechanically can be obtained.

In addition, in order to bond insulating layers to each other, after obtaining high flatness by polishing or the like, the surfaces subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other to temporarily join them, and then to perform the final joining by dehydration by heat treatment. A joining method or the like can be used. Since bonding at the atomic level also occurs in the hydrophilic bonding method, mechanically excellent bonding can be obtained.

In the case where the layer 561 and the layer 562 are bonded to each other, an insulating layer and a metal layer are mixed on each bonding surface. Therefore, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

For example, a method may be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the surfaces. Moreover, the surface of the metal layer may be made of a hardly oxidizable metal such as Au and subjected to a hydrophilic treatment. Note that a joining method other than the method described above may be used.

FIG. 18B is a cross-sectional view in the case where a pn junction photodiode including a selenium-based material as a photoelectric conversion layer is used for the pixel layer 561 illustrated in FIG. It has a layer 566a as one electrode, layers 566b and 566c as a photoelectric conversion layer, and a layer 566d as the other electrode.

In this case, the layer 561 can be formed directly on the layer 562. The layer 566a is electrically connected to a source or a drain of the transistor 102. The layer 566d is electrically connected to a power supply line through a conductive layer 537. Note that when an organic photoconductive film is used for the layer 561, the connection with the transistor is similar.

FIG. 20A illustrates an example of a cross section of the pixel illustrated in FIG. The layer 561 includes, as the photoelectric conversion device 101, a pn junction photodiode including silicon as a photoelectric conversion layer. The layer 562 includes a Si transistor. FIG. 20A illustrates the transistors 105 and 106 included in a pixel circuit. The layer 563 includes an OS transistor. FIG. 20A illustrates the transistors 102 and 103 included in a pixel circuit. The structure example in which the layer 561 and the layer 563 obtain electrical connection by bonding is illustrated.

FIG. 21A illustrates details of the OS transistor. The OS transistor illustrated in FIG. 21A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a groove which reaches the semiconductor layer is provided to form a source electrode 205 and a drain electrode 206. It is a structure of.

The OS transistor can have a structure including a gate electrode 201 and a gate insulating film 202 in addition to a channel formation region, a source region 203, and a drain region 204 formed in the oxide semiconductor layer. At least the gate insulating film 202 and the gate electrode 201 are provided in the groove. An oxide semiconductor layer 207 may be further provided in the groove.

The OS transistor may have a self-aligned structure in which a source region and a drain region are formed in a semiconductor layer using the gate electrode 201 as a mask, as illustrated in FIG.

Alternatively, as illustrated in FIG. 21C, a non-self-aligned top-gate transistor including a region where the source electrode 205 or the drain electrode 206 and the gate electrode 201 overlap with each other may be used.

Although the transistors 102 and 103 have a structure including the back gate 535, a structure without a back gate may be employed. The back gate 535 may be electrically connected to a front gate of a transistor provided to be opposed to the transistor as illustrated in a cross-sectional view in the channel width direction of the transistor illustrated in FIG. Note that FIG. 21D illustrates the transistor in FIG. 20A as an example, but the same applies to transistors having other structures. Further, a configuration in which a fixed potential different from that of the front gate may be supplied to the back gate 535 may be employed.

An insulating layer 543 having a function of preventing diffusion of hydrogen is provided between a region where the OS transistor is formed and a region where the Si transistor is formed. Hydrogen in an insulating layer provided near the channel formation region of the transistors 105 and 106 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the channel formation region of the transistors 102 and 103 is one of the factors that generate carriers in the oxide semiconductor layer.

The reliability of the transistors 105 and 106 can be improved by confining hydrogen in one layer with the insulating layer 543. In addition, by suppressing diffusion of hydrogen from one layer to the other layer, the reliability of the transistors 102 and 103 can be improved.

As the insulating layer 543, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

FIG. 20B is a cross-sectional view in the case where a pn junction photodiode including a selenium-based material as a photoelectric conversion layer is used for the pixel layer 561 illustrated in FIG. 17B. The layer 561 can be formed directly on the layer 563. For details of the layers 561, 562, and 563, the above description can be referred to. Note that when an organic photoconductive film is used for the layer 561, the connection with the transistor is similar.

FIG. 22A is a perspective view illustrating an example in which a color filter and the like are added to pixels of the imaging device of one embodiment of the present invention. In the perspective view, cross sections of a plurality of pixels are also shown. An insulating layer 580 is formed over the layer 561 where the photoelectric conversion device 101 is formed. As the insulating layer 580, a silicon oxide film with high light-transmitting property with respect to visible light can be used. Further, a silicon nitride film may be stacked as a passivation film. Further, a dielectric film such as hafnium oxide may be laminated as an antireflection film.

A light-blocking layer 581 may be formed over the insulating layer 580. The light-blocking layer 581 has a function of preventing color mixture of light passing through the upper color filter. As the light-blocking layer 581, a metal layer such as aluminum or tungsten can be used. Further, the metal layer and a dielectric film having a function as an antireflection film may be stacked.

An organic resin layer 582 can be provided as a planarization film over the insulating layer 580 and the light-blocking layer 581. A color filter 583 (color filters 583a, 583b, 583c) is formed for each pixel. For example, by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters 583a, 583b, 583c, Can be obtained.

An insulating layer 586 having a property of transmitting visible light can be provided over the color filter 583.

Further, as shown in FIG. 22B, an optical conversion layer 585 may be used instead of the color filter 583. With such a configuration, an imaging device that can obtain images in various wavelength regions can be provided.

For example, when a filter that blocks light having a wavelength equal to or less than the wavelength of visible light is used for the optical conversion layer 585, an infrared imaging device can be obtained. Further, when a filter that blocks light having a wavelength of near-infrared rays or less is used for the optical conversion layer 585, a far-infrared imaging device can be obtained. When a filter that blocks light having a wavelength equal to or longer than the wavelength of visible light is used for the optical conversion layer 585, an ultraviolet imaging device can be obtained.

In addition, when a scintillator is used for the optical conversion layer 585, an imaging device that obtains an image in which the intensity of radiation used in an X-ray imaging device or the like is visualized can be obtained. When radiation such as X-rays transmitted through a subject enters a scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Then, the photoelectric conversion device 101 detects the light to acquire image data. Further, the imaging device having the above configuration may be used for a radiation detector or the like.

The scintillator includes a substance that, when irradiated with radiation such as X-rays or gamma rays, absorbs the energy and emits visible light or ultraviolet light. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO, etc. Those dispersed in resin or ceramics can be used.

Note that in the photoelectric conversion device 101 using a selenium-based material, radiation such as X-rays can be directly converted into electric charges, so that a structure in which a scintillator is not necessary can be employed.

Further, as shown in FIG. 22C, a microlens array 584 may be provided over the color filter 583. Light that passes through the individual lenses of the microlens array 584 passes through the color filter 583 directly below and irradiates the photoelectric conversion device 101. Further, a microlens array 584 may be provided over the optical conversion layer 585 illustrated in FIG.

Hereinafter, an example of a package containing an image sensor chip and a camera module will be described. The structure of the imaging device can be used for the image sensor chip.

FIG. 23A1 is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 410 for fixing the image sensor chip 450, a cover glass 420, an adhesive 430 for bonding the two, and the like.

FIG. 23A2 is an external perspective view of the lower surface side of the package. A BGA (Ball grid array) having solder balls as bumps 440 is provided on the lower surface of the package. Not only BGA but also LGA (Land Grid Array), PGA (Pin Grid Array), or the like may be used.

FIG. 23 (A3) is a perspective view of the package illustrated with the cover glass 420 and a part of the adhesive 430 omitted. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected via a through hole. The electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.

FIG. 23B1 is an external perspective view of the upper side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing the image sensor chip 451, a lens cover 421, a lens 435, and the like. Further, an IC chip 490 having functions such as a driving circuit and a signal conversion circuit of the imaging device is provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System @ in @ package). I have.

FIG. 23 (B2) is an external perspective view of the lower surface side of the camera module. The lower surface and the side surface of the package substrate 411 have a QFN (Quad flat no-lead package) configuration in which mounting lands 441 are provided. Note that this configuration is an example, and a QFP (Quad @ flat @ package) or the aforementioned BGA may be provided.

FIG. 23 (B3) is a perspective view of the module illustrated with the lens cover 421 and a part of the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471.

By mounting the image sensor chip in the above-described package, mounting on a printed circuit board or the like is facilitated, and the image sensor chip can be incorporated in various semiconductor devices and electronic devices.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
As electronic devices that can use the imaging device of one embodiment of the present invention, a display device, a personal computer, an image storage device or an image reproducing device provided with a recording medium, a mobile phone, a game machine including a portable device, and a mobile data terminal , E-book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound reproducers (car audio, digital audio players, etc.), copiers, facsimile machines, printers, multifunction printers , An automatic teller machine (ATM), a vending machine, and the like. Specific examples of these electronic devices are illustrated in FIGS.

FIG. 24A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. All operations such as making a call and inputting characters can be performed by touching the display portion 982 with a finger, a stylus, or the like. The operation method of the imaging device of one embodiment of the present invention can be applied to the image acquisition operation of the mobile phone.

FIG. 24B illustrates a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using the touch panel function of the display portion 912. In addition, a character or the like can be recognized from an image acquired by the camera 919, and the character can be output as sound using the speaker 913. The operation method of the imaging device of one embodiment of the present invention can be applied to the image acquisition operation of the portable data terminal.

FIG. 24C illustrates a monitoring camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotating mechanism and the like, and can be installed on a ceiling to capture an image of the entire periphery. The imaging device of one embodiment of the present invention and an operation method thereof can be applied to an element for acquiring an image in the camera unit. Note that the surveillance camera is a conventional name and does not limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

FIG. 24D illustrates a video camera, which includes a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display portion 973 is provided on the second housing 972. The operation method of the imaging device of one embodiment of the present invention can be applied to the image acquisition operation of the video camera.

FIG. 24E illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The operation method of the imaging device of one embodiment of the present invention can be applied to an image acquisition operation of the digital camera.

FIG. 24F illustrates a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating an information terminal. The display portion 932 and the housing / wristband 933 have flexibility and are excellent in attachment to the body. The operation method of the imaging device of one embodiment of the present invention can be applied to the image acquisition operation of the information terminal.

This embodiment can be combined with any of the other embodiments as appropriate.

10: pixel, 10a: pixel, 10b: pixel, 10c: pixel, 10d: pixel, 21: pixel array, 22: circuit, 23: circuit, 24: circuit, 25: circuit, 26: circuit, 27: circuit, 28 : Circuit, 101: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: capacitor, 108: capacitor, 121: wiring, 122: wiring, 123: wiring, 124 : Wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 201: gate electrode, 202: gate insulating film, 203: source region, 204: drain region, 205: source electrode, 206 : Drain electrode, 207: oxide semiconductor layer, 410: package substrate, 411: package base , 420: cover glass, 421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: land, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: wire, 471: wire, 490: IC chip, 531: conductive layer, 532: conductive layer, 533: conductive layer, 534: conductive layer, 535: back gate, 536: region, 540: silicon substrate, 541: insulating Layer, 542: insulating layer, 543: insulating layer, 545: semiconductor layer, 546: insulating layer, 561: layer, 562: layer, 563: layer, 565a: layer, 565b: layer, 565c: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e Layer, 580: insulating layer, 581: light-shielding layer, 582: organic resin layer, 583: color filter, 583a: color filter, 583b: color filter, 583c: color filter, 584: microlens array, 585: optical conversion layer, 586: insulating layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: support base, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation key, 975: Lens, 976: Connection, 977: Speaker, 978: Microphone, 981: Housing, 982: Display, 983: Operation Button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera

Claims (8)

A first node in which one electrode of the capacitor is electrically connected to one of a source and a drain of the first transistor, and an other electrode of the capacitor electrically connected to a gate of the second transistor; A second node, and an operation method of the imaging device, wherein the other of the source or the drain of the first transistor is electrically connected to one electrode of the photodiode.
A first step of supplying and holding a second potential to the second node while supplying a first potential to the first node;
A second step of changing the potential of the first node by operating the photodiode and changing the potential of the second node by capacitive coupling of the capacitor;
A third step of fixing the potential of the second node and reading out the potential of the second node by operating the second transistor;
Are performed in the order described above. In claim 1,
The method according to claim 1, wherein the first potential is lower than the second potential, and a difference between the first potential and the second potential is equal to or higher than a threshold voltage of the second transistor. A first node in which one electrode of the capacitor is electrically connected to one of a source and a drain of the first transistor, and an other electrode of the capacitor electrically connected to a gate of the second transistor; A second node, and an operation method of the imaging device, wherein the other of the source or the drain of the first transistor is electrically connected to one electrode of the photodiode.
A first step of supplying and holding a first potential to the first node while supplying a second potential to the second node;
A second step of supplying a third potential to the second node and changing the potential of the first node by capacitive coupling of the capacitor;
A third step of changing the potential of the first node by operating the photodiode and changing the potential of the second node by capacitive coupling of the capacitor;
A fourth step of fixing the potential of the second node and reading out the potential of the second node by operating the second transistor;
Are performed in the order described above. In claim 3,
The operation method of the imaging device, wherein the first potential is higher than the second potential. In any one of claims 1 to 4,
The imaging device has a third transistor;
The operation method of the imaging device, in which the supply of the potential to the first node is performed through a third transistor. In any one of claims 1 to 5,
The operation method of the imaging device, wherein the supply of the potential to the first node is performed through the photodiode. In any one of claims 1 to 6,
The imaging device has a fourth transistor,
The method for operating the imaging device, wherein the supply of the potential to the second node is performed through a fourth transistor. In any one of claims 1 to 7,
At least one of the transistors included in the imaging device has a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

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