WO2019242273A1 - N-level pcie expansion case control method and system, and readable storage medium - Google Patents

Abstract

Disclosed are an N-level PCIE expansion case control method and system, and a readable storage medium. The method comprises: a BMC for an i-level PCIE expansion case detecting, after receiving a startup trigger signal, whether there is an (i + 1)-level PCIE expansion case connected to the BMC; if not, executing a startup operation; if so, sending the startup trigger signal to the (i + 1)-level PCIE expansion case, querying a power-on flag bit of the (i + 1)-level PCIE expansion case according to a preset rule, and when the power-on flag bit of the (i + 1)-level PCIE expansion case is in a first state, executing the startup operation; and a BMC of a CPU server controlling, when finding that the power-on flag bits of all the PCIE expansion cases are all in the first state, a CPLD of the CPU server to start a second power-on timing sequence. The method is easy to implement, and only one instance of control is required during the control of a CPU server combination connected to N-level PCIE expansion cases, thereby saving on a lot of human and material resources.

Description

Control method, system and readable storage medium of N-level PCIE expansion box

This application claims the priority of a Chinese patent application filed on June 20, 2018 with the Chinese Patent Office, application number 201810635279.9, and invention name "Control Method, System and Readable Storage Medium for N-Class PCIE Expansion Box", which The entire contents are incorporated herein by reference.

Technical field

The present invention relates to the field of computer technology, and in particular, to a control method, system, and readable storage medium for an N-level PCIE expansion box.

Background technique

With the continuous development of cloud computing and big data, various fields have gradually transformed the traditional data computing model into cloud computing. With the increase of business volume, the amount of data storage and processing in the server system is also increasing. In order to save costs, the prior art generally uses a series or parallel connection of multiple PCIE expansion boxes on the server to increase the storage space. And the purpose of improving computing power. During on-site delivery and system upgrade, staff need to manually control each PCIE (Peripheral Component Interconnect Express) high-speed serial computer expansion bus standard expansion box and CPU (Central Processing Unit, central processing unit) server on / off, in order to achieve connection The CPU server combination with N PCIE expansion boxes has to be turned on / off manually. The staff needs to manually control N + 1 times, which greatly wastes manpower and material resources. At the same time, the control process is cumbersome and wastes time.

Therefore, how to provide a solution to the above technical problems is a topic that needs to be solved by those skilled in the art.

Summary of the Invention

The purpose of the present invention is to provide a control method, system and readable storage medium for N-level PCIE expansion box, which is easy to implement. When controlling a combination of CPU servers connected to N-level PCIE expansion box, only one control is needed, which saves a lot of Human and material resources.

To solve the above technical problems, the present invention provides a method for controlling an N-level PCIE expansion box, including:

After receiving the power-on trigger signal, the baseboard management controller BMC of the i-level high-speed serial computer expansion bus standard PCIE expansion box detects whether there is an i + 1-level PCIE expansion box connected to it, i = 1, 2, ..., N, N is a positive integer;

If not, perform a boot operation; if yes, send the boot trigger signal to the i + 1th level PCIE expansion box, and query the power-on flag of the i + 1th level PCIE expansion box according to a preset rule, when The power-on mark of the i + 1th level PCIE expansion box is in the first state, and the power-on operation is performed; wherein the power-on operation includes controlling a complex programmable logic device CPLD to start a first power-on sequence, and After the power is completed, place the power-on mark in the first state;

When the BMC of the central processing unit CPU server finds that all the power-on flags of the PCIE expansion boxes are set to the first state, the CPLD controlling the CPU server starts a second power-on sequence to start the CPU. server.

Preferably, after receiving the power-on trigger signal, the BMC of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE expansion box connected to it:

After receiving the power-on trigger signal, the BMC of the i-level PCIE expansion box detects whether there is an address of the i + 1-level PCIE expansion box connected to it through the integrated line bus protocol IIC.

Preferably, the process of querying the power-on flag of the i + 1th level PCIE expansion box according to a preset rule is specifically:

Query the power-on flag of the i + 1th PCIE expansion box according to the preset period through the IIC.

Preferably, the number of the i-th PCIE expansion boxes is M, and M is a positive integer.

Preferably, after the power-on flag of the i + 1th level PCIE expansion box is queried according to a preset rule, the control method further includes:

When the number of inquiries reaches a preset value, an alarm signal is generated to remind the staff to perform maintenance on the i + 1th level PCIE expansion box.

Preferably, the control method further includes:

After receiving the shutdown signal, the BMC of the CPU server controls the CPLD of the CPU server to start the first power-off sequence. After the power-off is completed, the power-on flag of the CPU server is set to the second state, and a shutdown trigger is generated. signal;

After receiving the shutdown trigger signal, the BMC of the i-th PCIE expansion box performs a shutdown operation; when the i + 1-th PCIE expansion box is present, sending the shutdown to the i + 1-th PCIE expansion box A trigger signal, so that the BMC of the i + 1th level PCIE expansion box performs the shutdown operation after receiving the shutdown trigger signal;

The shutdown operation includes controlling the CPLD to start a second power-off sequence, and setting the power-on flag to the second state after the power-off is completed.

In order to solve the above technical problems, the present invention also provides a control system of an N-level PCIE expansion box, including:

Central processing unit CPU server and N PCIE expansion boxes, N is a positive integer;

Among them, the baseboard management controller BMC of the i-th level PCIE expansion box is used to detect whether there is an i + 1-th level PCIE expansion box connected to it after receiving the power-on trigger signal, i = 1, 2, ..., N; When the i + 1th level PCIE expansion box does not exist, perform a boot operation; when the i + 1th level PCIE expansion box exists, sending the boot trigger signal to the i + 1th level PCIE expansion box, and Querying the power-on flag bit of the i + 1th-level PCIE expansion box according to a preset rule, and performing the power-on operation when the power-on flag of the i + 1th-level PCIE expansion box is in the first state; The booting operation includes controlling the CPLD to start the first power-on sequence, and setting the power-on flag to the first state after power-on is completed;

The BMC of the CPU server is used to control the CPU server's CPLD to start a second power-on sequence when it is found that the power-on flags of all the PCIE expansion boxes are set to the first state. CPU server.

Preferably, after receiving the power-on trigger signal, the BMC of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE expansion box connected to it:

After receiving the power-on trigger signal, the BMC of the i-level PCIE expansion box detects whether there is an address of the i + 1-level PCIE expansion box connected to it through the integrated line bus protocol IIC.

Preferably, the BMC of the CPU server is further configured to control the CPLD of the CPU server to start the first power-off sequence after receiving the shutdown signal, and place the power-on flag of the CPU server at the first position after power-off is completed. Two states, and generate a shutdown trigger signal;

The BMC of the i-th level PCIE expansion box is further configured to perform a shutdown operation after receiving the shutdown trigger signal; when the i + 1-th level PCIE expansion box exists, extend to the i + 1-th level PCIE The box sends the shutdown trigger signal, so that the BMC of the i + 1th level PCIE expansion box performs the shutdown operation after receiving the shutdown trigger signal; wherein the shutdown operation includes controlling the CPLD to start a second Electrical sequence, after the power-off is completed, the power-on flag is set to the second state.

In order to solve the above technical problem, the present invention also provides a readable storage medium. The readable storage medium stores a computer program, and when the computer program is executed by a processor, the N-level PCIE is implemented as described in any one of the foregoing. Steps of the control method of the expansion box.

The invention provides a method for controlling an N-level PCIE expansion box, which includes: after receiving a power-on trigger signal, the BMC of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE expansion box connected to it, i = 1,2, ..., N, N are positive integers; if not, perform the boot operation; if yes, send a boot trigger signal to the i + 1 level PCIE expansion box, and query the i + 1 level PCIE expansion box according to preset rules Power-on flag, when the power-on flag of the i + 1 level PCIE expansion box is in the first state, the power-on operation is performed; wherein the power-on operation includes controlling the CPLD to start the first power-on sequence, and it will power on after the power-on is completed The flag position is in the first state; when the BMC of the CPU server queries the power-on flag bits of all PCIE expansion boxes, it is set to the first state, and the CPLD that controls the CPU server starts the second power-on sequence to start the CPU server.

It can be seen that, in practical applications, the present invention is easy to implement. When controlling a combination of CPU servers connected with N PCIE expansion boxes, only one control is needed, which saves a lot of manpower and material resources. At the same time, the CPU server queries N expansion boxes. After booting, ensure that the CPU server can successfully enumerate PCIE.

The invention also provides a control system and a readable storage medium of the N-level PCIE expansion box, which has the same beneficial effects as the control method of the N-level PCIE expansion box.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly explain the technical solutions in the embodiments of the present invention, the following describes the prior art and the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some of the present invention. For those of ordinary skill in the art, other embodiments may be obtained based on these drawings without paying creative effort.

FIG. 1 is a flowchart of steps in a method for controlling an N-level PCIE expansion box provided by the present invention; FIG.

2 is a schematic structural diagram of an embodiment of a method for controlling an N-level PCIE expansion box provided by the present invention;

3 is a schematic structural diagram of another embodiment of a control method for a N-level PCIE expansion box provided by the present invention;

4 is a schematic structural diagram of another embodiment of a control method for an N-level PCIE expansion box provided by the present invention;

FIG. 5 is a schematic structural diagram of a control system for an N-level PCIE expansion box provided by the present invention.

detailed description

The core of the present invention is to provide a control method, system and readable storage medium for N-level PCIE expansion box, which is easy to implement. When controlling a combination of CPU servers connected to N-level PCIE expansion box, it only needs to be controlled once, which saves a lot of time. Human and material resources.

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Please refer to FIG. 1. FIG. 1 is a flowchart of steps of a method for controlling an N-level PCIE expansion box provided by the present invention, including:

Step 1: After receiving the power-on trigger signal, the baseboard management controller BMC of the i-level high-speed serial computer expansion bus standard PCIE expansion box detects whether there is an i + 1-level PCIE expansion box connected to it, i = 1, 2 , ..., N, N are positive integers, if not, go to step 2, if yes, go to step 3;

Step 2: Perform a power-on operation, where the power-on operation includes controlling a complex programmable logic device CPLD to start a first power-on sequence, and after the power-on is completed, set a power-on flag to a first state;

Step 3: Send a power-on trigger signal to the i + 1th-level PCIE expansion box, and query the power-on flag of the i + 1th-level PCIE expansion box according to preset rules;

Step 4: Determine whether the power-on flag of the i + 1th level PCIE expansion box is set to the first state, and if yes, go to step 2;

Step 5: When the BMC of the central processing unit CPU server finds that the power-on flags of all PCIE expansion boxes are set to the first state, the CPLD controlling the CPU server starts the second power-on sequence to start the CPU server.

As a preferred embodiment, the number of the i-th PCIE expansion boxes is M, and M is a positive integer.

Specifically, for a CPU (Central Processing Unit) server combination connected with N PCIE expansion boxes, there can be at least two connection structures, one is a serial structure, that is, a CPU server and a first-level PCIE expansion Box, the second-level PCIE expansion box up to the N-th level PCIE expansion box are connected in series, which is equivalent to including the N-level PCIE expansion box, and each level includes only one PCIE expansion box; the other is a parallel structure, that is, each PCIE expansion box The boxes are connected to the CPU server, which is equivalent to only one level of PCIE expansion box, but the number of this level of PCIE expansion boxes is multiple; of course, in addition to the above two connection structures, it also includes a mixed connection structure, as shown in Figure 2, The first level PCIE expansion box E1, the second level PCIE expansion box E2 up to the p level PCIE expansion box EP are connected in series, and the M p + 1 level PCIE expansion boxes EP + 1 are connected in parallel with the p level PCIE expansion box EP, p = 1,2, ..., N-1, M is a positive integer.

It should be noted in advance that each PCIE expansion box includes a BMC (Baseboard Management Controller) and a CPLD that works in conjunction with the BMC. The CPU server includes a BMC and a CPLD that works in conjunction with the BMC.

Specifically, the BMC of the CPU server generates a power-on trigger signal after receiving a Power Button or a remote power-on signal, and the BMC (generally a first-level PCIE expansion box) of the PCIE expansion box connected to the CPU server receives the power-on trigger signal. , First detect whether there is a next-level PCIE expansion box connected to it. If it does not exist, the PCIE expansion box of this level performs a boot operation. If it exists, send a boot-up trigger signal to the next-level PCIE expansion box and query the preset rules. The power-on flag of the PCIE expansion box of the first level, and so on, until the BMC of the PCIE expansion box that receives the power-on trigger signal cannot query the next level of the PCIE expansion box. In order to control the booting of the PCIE expansion box of this level, the process of the BMC of the PCIE expansion box performing the boot operation is specifically: the BMC sends an open signal to the CPLD, and the CPLD starts a self-set first power-on sequence after receiving the open signal, and powers on After the power is completed, the power-on flag is set to the first state. Generally, the initial state of the power-on flag is the second state, and the state of the power-on flag is low. High level 1 means that the first state, that is, the power-on state is represented by high level 1, and the second state, that is, the off state, is represented by low level 0. When the BMC of the t-1 level PCIE expansion box queries the t level When the boot mark of the PCIE expansion box is in the first state, the BMC of the t-1 level PCIE expansion box performs the above booting operation to control the t-1 level of the PCIE expansion box to start until the first level of the PCIE expansion box is turned on. t = 2,3, ..., N. When the BMC of the CPU server finds that the power-on flag of the PCIE expansion box connected to it is in the first state, the power-on operation is performed, that is, the CPLD that controls the CPU server starts the second power-on sequence. After power-on is completed, PWRGD is sent to the BMC. The BMC detects the level status of the PWRGD to implement the power-on function. It can be understood that when the booting mark position of the PCIE expansion box is in the first state, it indicates that the PCIE expansion box has been powered on.

Specifically, the booting steps of the N-level PCIE expansion box with a serial structure are exemplified. Taking three PCIE expansion boxes as an example, referring to FIG. 3, the CPU server, the first-level PCIE expansion box E11, and the second-level PCIE expansion box E12. The third-level PCIE expansion box E13 is connected in sequence. After receiving the Power Button or remote power-on signal, the CPU server generates a power-on trigger signal and queries the first-level PCIE expansion box E11's power-on flag according to preset rules. The first level After receiving the power-on trigger signal and detecting the presence of the second-level PCIE expansion box E12, the BMC of the PCIE expansion box E11 sends a power-on trigger signal to the second-level PCIE expansion box E12, and queries the second-level PCIE expansion box according to preset rules. After the power-on flag of E12, the BMC of the second-level PCIE expansion box E12 receives the power-on trigger signal, and then detects the presence of the third-level PCIE expansion box E13, sends a power-on trigger signal to the third-level PCIE expansion box E13, and presses The preset rule queries the boot flag of the third-level PCIE expansion box E13. After receiving the power-on trigger signal, the BMC of the third-level PCIE expansion box E13 detects the absence of the next-level PCIE expansion box and executes the boot. Operation, that is, the BMC sends an open signal to the CPLD. The CPLD starts the first power-on sequence after receiving the open signal. The BMC detects that the power-on flag is set to the first state after power-on is completed. When the second-level PCIE expansion box E12 BMC When the power-on flag of the third-level PCIE expansion box E13 is queried as the first state, the power-on operation is performed. When the BMC of the first-level PCIE expansion box E11 is queried, the power-on flag of the second-level PCIE expansion box E12 is the first state. When the power-on operation is performed, when the BMC of the CPU server finds that the power-on flag of the first-level PCIE expansion box E11 is in the first state (this is equivalent to the power-on flag of all PCIE expansion boxes in the first state), control The CPLD starts the second power-on sequence to control the CPU server to start, thereby starting the entire CPU server combination with three PCIE expansion boxes connected in series.

Specifically, the booting steps of an N-level PCIE expansion box with a parallel structure are exemplified. Taking three PCIE expansion boxes as an example, referring to FIG. 4, the first PCIE expansion box E21, the second PCIE expansion box E22, and the third PCIE expansion Box E23 is connected to the CPU server respectively. After receiving the Power Button or remote power-on signal, the CPU server generates a boot trigger signal and sends it to the first PCIE expansion box E21, the second PCIE expansion box E22, and the third PCIE expansion box E23. There are no strict requirements on the sending sequence. When the BMC of the first PCIE expansion box E21, the BMC of the second PCIE expansion box E22, and the BMC of the third PCIE expansion box E23 receive the power-on trigger signal, they detect whether there are any For the first-level PCIE expansion box, since the first-level parallel connection is taken as an example in this embodiment, there is no next-level PCIE expansion box connected to the first PCIE expansion box E21, the second PCIE expansion box E22, and the third PCIE expansion box E23. Therefore, the first PCIE expansion box E21, the second PCIE expansion box E22, and the third PCIE expansion box E23 all perform the above boot operation. When the BMC of the CPU server finds that the boot flags of the three PCIE expansion boxes are the first When state, the second control CPLD power-up sequence starts, the server CPU to control the power to initiate a CPU server entire parallel combination of three expansion enclosure.

In summary, after receiving the power-on trigger signal, the BMC of the i-th PCIE expansion box first detects whether there is an i + 1-th PCIE expansion box connected to it, and if it exists, it sends the i + 1-level PCIE expansion box to the Send a power-on trigger signal and query the power-on flag of the i + 1 level PCIE expansion box according to the preset rules; if it does not exist, control the CPLD to start the first power-on sequence to control the boot of the PCIE expansion box; in the serial structure, The boot sequence of the CPU server combination connected with N PCIE expansion boxes is the Nth level PCIE expansion box, the N-1th level PCIE expansion box, ..., the first level PCIE expansion box, and the CPU server; in a parallel structure, N The PCIE expansion box is powered on first, and the boot sequence is not strictly required. When all PCIE expansion boxes are powered on, the CPU server is powered on. The above can ensure that the CPU server is powered on after querying that the boot flag of each PCIE expansion box is in the first state. The PCIE expansion box can be enumerated successfully. The entire boot process is easy to implement and stable. Only one manual operation is needed to control the startup of the CPU server combination connected to the N-level expansion box, which saves a lot of manpower. Force.

The invention provides a method for controlling an N-level PCIE expansion box, which includes: after receiving a power-on trigger signal, the BMC of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE expansion box connected to it, i = 1,2, ..., N, N are positive integers; if not, perform the boot operation; if yes, send a boot trigger signal to the i + 1 level PCIE expansion box, and query the i + 1 level PCIE expansion box according to preset rules Power-on flag, when the power-on flag of the i + 1 level PCIE expansion box is in the first state, the power-on operation is performed; wherein the power-on operation includes controlling the CPLD to start the first power-on sequence, and it will power on after the power-on is completed The flag position is in the first state; when the BMC of the CPU server queries the power-on flag bits of all PCIE expansion boxes, it is set to the first state, and the CPLD that controls the CPU server starts the second power-on sequence to start the CPU server.

It can be seen that, in practical applications, the present invention is easy to implement. When controlling a combination of CPU servers connected with an N-level PCIE expansion box, it only needs to be controlled once, saving a lot of manpower and material resources. After booting, ensure that the CPU server can successfully enumerate PCIE.

On the basis of the above embodiments:

As a preferred embodiment, after receiving the power-on trigger signal, the BMC of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE expansion box connected to it:

After receiving the power-on trigger signal, the BMC of the i-level PCIE expansion box detects whether there is an address of the i + 1-level PCIE expansion box connected to it through the integrated line bus protocol IIC.

Specifically, the BMC of the i-th level PCIE expansion box detects the presence of the i + 1th level PCIE expansion box through the IIC (Inter-Integrated Circuit) protocol. If there is an address for the i + 1th level PCIE through the IIC protocol, The expansion box sends a power-on trigger signal and queries the boot flag of the i + 1 level PCIE expansion box at the same time. It can be understood that each PCIE expansion box corresponds to an address. Before booting, the detailed IIC topology needs to be drawn in advance to avoid Address conflict. When multiple PCIE expansion boxes are connected in parallel to the CPU server, each PCIE expansion box corresponds to an IIC protocol. For example, the CPU server sends a startup trigger signal to the first PCIE expansion box through IIC-1 and queries the first according to preset rules. The boot flag of the PCIE expansion box, the CPU server sends a boot trigger signal to the second PCIE expansion box through IIC-2 and queries the boot flag of the second PCIE expansion box according to preset rules, and so on. The CPU server passes the IIC-N. Send a boot trigger signal to the Nth PCIE expansion box and query the boot flag of the Nth PCIE expansion box according to preset rules.

As a preferred embodiment, the process of querying the power-on flag of the i + 1th level PCIE expansion box according to a preset rule is specifically:

Use the IIC to query the power-on flag of the i + 1th PCIE expansion box according to a preset period.

Specifically, the BMC of the i-th PCIE expansion box can query the power-on flag of the i + 1-th PCIE expansion box according to the preset period through the IIC. Of course, it can also query in real time. The set value of the preset period meets the actual engineering needs. That is, the present invention is not limited herein.

As a preferred embodiment, the number of the i-th PCIE expansion boxes is M, and M is a positive integer.

As a preferred embodiment, after querying the power-on flag of the i + 1th level PCIE expansion box according to a preset rule, the control method further includes:

When the number of inquiries reaches the preset value, an alarm signal is generated to remind the staff to perform maintenance on the i + 1 level PCIE expansion box.

It can be understood that while the BMC of the i-th PCIE expansion box queries the power-on flag of the i + 1-th PCIE expansion box according to preset rules, it should also record the number of queries. The number of queries here refers to the query. The number of times that the power-on flag of the i + 1 level PCIE expansion box is in the second state can also refer to the total number of queries. If it refers to the total number of queries, then the i-level PCIE expansion needs to be guaranteed during program design If the power-on flag bit of the i + 1th level PCIE expansion box is queried as the first state, it will not be queried again. Therefore, the number of queries in the present invention still refers to the case where the power-on flag bit is queried as the second state. The number of times that when the BMC of the i-th PCIE expansion box finds that the power-on flag of the i + 1-th PCIE expansion box is in the second state exceeds the preset value, it indicates that the i + 1-th PCIE expansion box is abnormal. An alarm signal is generated from time to time to remind staff to perform timely maintenance on abnormal PCIE expansion boxes. Specifically, in a tandem structure, if there is an abnormal PCIE expansion box, in order to avoid affecting the normal startup of other PCIE expansion boxes and the CPU server, when performing maintenance on the abnormal PCIE expansion box, the staff will change the PCIE on both sides of the abnormal PCIE expansion box. The expansion boxes are connected in series; in the parallel structure, if there is an abnormal PCIE expansion box, in order to avoid affecting the normal startup of the CPU server, the staff disconnects the abnormal PCIE expansion box from the CPU server when performing maintenance on the abnormal PCIE expansion box.

As a preferred embodiment, the control method further includes:

After receiving the shutdown signal, the BMC of the CPU server controls the CPLD of the CPU server to start the first power-off sequence. After the power-off is completed, the power-on flag of the CPU server is set to the second state, and a shutdown trigger signal is generated;

After receiving the shutdown trigger signal, the BMC of the i-th PCIE expansion box performs the shutdown operation; when the i + 1-th PCIE expansion box exists, it sends a shutdown trigger signal to the i + 1-th PCIE expansion box so that the i + After receiving the shutdown trigger signal, the BMC of the level 1 PCIE expansion box performs the shutdown operation;

The shutdown operation includes controlling the CPLD to start the second power-off sequence, and setting the power-on flag to the second state after the power-off is completed.

Specifically, in the series structure, the shutdown sequence is opposite to the startup sequence. The specific control sequence is: When the BMC of the CPU server receives the shutdown signal, the CPLD is controlled to start the first power-off sequence. After the power-off is completed, the shutdown signal is sent to the IIC to The first level PCIE expansion box, the first level PCIE expansion box receives the shutdown signal and performs the shutdown operation, and then sends the second level PCIE expansion box to the shutdown signal, and the second level PCIE expansion box performs the shutdown operation after receiving the shutdown signal. By analogy, the shutdown operation is completed until the Nth PCIE expansion box is executed.

In the parallel structure, when the BMC of the CPU server receives the shutdown signal, the CPLD is controlled to start the first power-off sequence. After the power-off is completed, the shutdown signal is sent through the IIC corresponding to each PCIE expansion box. Each PCIE expansion box receives the shutdown signal. After performing the shutdown operation.

Please refer to FIG. 5. FIG. 5 is a control system of an N-level PCIE expansion box provided by the present invention. It should be noted in advance that FIG. 5 is a control system of an N-level PCIE expansion box shown in a serial structure. The control system of an N-level PCIE expansion box provided by the invention can also be expressed in a parallel structure, including:

Central processing unit CPU server 1 and N PCIE expansion boxes, N is a positive integer;

Among them, the baseboard management controller BMC of the i-th PCIE expansion box is used to detect whether there is an i + 1-th PCIE expansion box connected to it after receiving the power-on trigger signal, i = 1, 2, ..., N ; When there is no i + 1 level PCIE expansion box, perform the boot operation; when there is an i + 1 level PCIE expansion box, send a boot trigger signal to the i + 1 level PCIE expansion box, and query the ith according to preset rules The power-on flag of the +1 level PCIE expansion box. When the power-on flag of the i + 1 level PCIE expansion box is in the first state, the power-on operation is performed. The power-on operation includes controlling the CPLD E12 to start the first power-on sequence. After the power-on is completed, the power-on mark is placed in the first state;

The BMC 11 of the CPU server 1 is used to control the CPLD 12 of the CPU server 1 to start the second power-on sequence when it is found that the power-on flags of all PCIE expansion boxes are set to the first state.

As a preferred embodiment, after receiving the power-on trigger signal, the BMC E11 of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE expansion box connected to it:

After receiving the power-on trigger signal, the BMC E11 of the i-level PCIE expansion box detects whether there is an address of the i + 1-level PCIE expansion box connected to it through the integrated line bus protocol IIC.

As a preferred embodiment, the BMC 11 of the CPU server 1 is further configured to control the CPLD 12 of the CPU server 1 to start the first power-off sequence after receiving the shutdown signal, and power on the CPU server 1 after the power-off is completed. The marker position is in the second state, and a shutdown trigger signal is generated;

The BMC E11 of the i-th PCIE expansion box is also used to perform the shutdown operation after receiving the shutdown trigger signal; when the i + 1-th PCIE expansion box exists, it sends the shutdown trigger signal to the i + 1-th PCIE expansion box. So that the BMC E11 of the i + 1 level PCIE expansion box performs the shutdown operation after receiving the shutdown trigger signal; wherein the shutdown operation includes controlling the CPLD E12 to start the second power-down sequence, and after the power-off is completed, the power-on flag is positioned at The second state.

Correspondingly, the present invention also provides a readable storage medium. A computer program is stored on the readable storage medium. When the computer program is executed by a processor, the steps of the control method for implementing an N-level PCIE expansion box as described above are implemented.

The invention also provides a control system and a readable storage medium of the N-level PCIE expansion box, which has the same beneficial effects as the control method of the N-level PCIE expansion box.

For the introduction of the control system and readable storage medium of an N-level PCIE expansion box provided by the present invention, please refer to the above embodiments, and the present invention will not repeat them here.

The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same and similar parts between the embodiments, refer to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part may refer to the description of the method.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but shall conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

A control method for an N-level PCIE expansion box, which includes: After receiving the power-on trigger signal, the baseboard management controller BMC of the i-level high-speed serial computer expansion bus standard PCIE expansion box detects whether there is an i + 1-level PCIE expansion box connected to it, i = 1, 2, ..., N, N is a positive integer; If not, perform a boot operation; if yes, send the boot trigger signal to the i + 1th level PCIE expansion box, and query the power-on flag of the i + 1th level PCIE expansion box according to a preset rule, when The power-on mark of the i + 1th level PCIE expansion box is in the first state, and the power-on operation is performed; wherein the power-on operation includes controlling a complex programmable logic device CPLD to start a first power-on sequence, and After the power is completed, place the power-on mark in the first state; When the BMC of the central processing unit CPU server finds that all the power-on flags of the PCIE expansion boxes are set to the first state, the CPLD controlling the CPU server starts a second power-on sequence to start the CPU. server. The method for controlling an N-level PCIE expansion box according to claim 1, wherein the BMC of the i-th level PCIE expansion box detects whether there is an i + 1-th level PCIE connected to the BMC after receiving the power-on trigger signal. The process of the expansion box is specifically: After receiving the power-on trigger signal, the BMC of the i-level PCIE expansion box detects whether there is an address of the i + 1-level PCIE expansion box connected to it through the integrated line bus protocol IIC. The method for controlling an N-level PCIE expansion box according to claim 2, wherein the process of querying the power-on flag of the i + 1th-level PCIE expansion box according to a preset rule is specifically: Query the power-on flag of the i + 1th PCIE expansion box according to the preset period through the IIC. The method for controlling an N-level PCIE expansion box according to claim 2, wherein the number of the i-th level PCIE expansion boxes is M, and M is a positive integer. The method for controlling an N-level PCIE expansion box according to any one of claims 1-4, wherein after querying a power-on flag of the i + 1th-level PCIE expansion box according to a preset rule, the Control methods also include: When the number of inquiries reaches a preset value, an alarm signal is generated to remind the staff to perform maintenance on the i + 1th level PCIE expansion box. The method for controlling an N-level PCIE expansion box according to claim 5, wherein the control method further comprises: After receiving the shutdown signal, the BMC of the CPU server controls the CPLD of the CPU server to start the first power-off sequence. After the power-off is completed, the power-on flag of the CPU server is set to the second state, and a shutdown trigger is generated. signal; After receiving the shutdown trigger signal, the BMC of the i-th PCIE expansion box performs a shutdown operation; when the i + 1-th PCIE expansion box is present, sending the shutdown to the i + 1-th PCIE expansion box A trigger signal, so that the BMC of the i + 1th level PCIE expansion box performs the shutdown operation after receiving the shutdown trigger signal; The shutdown operation includes controlling the CPLD to start a second power-off sequence, and setting the power-on flag to the second state after the power-off is completed. A control system for an N-level PCIE expansion box, which includes: Central processing unit CPU server and N PCIE expansion boxes, N is a positive integer; Among them, the baseboard management controller BMC of the i-th level PCIE expansion box is used to detect whether there is an i + 1-th level PCIE expansion box connected to it after receiving the power-on trigger signal, i = 1, 2, ..., N; When the i + 1th level PCIE expansion box does not exist, perform a boot operation; when the i + 1th level PCIE expansion box exists, sending the boot trigger signal to the i + 1th level PCIE expansion box, and Querying the power-on flag bit of the i + 1th-level PCIE expansion box according to a preset rule, and performing the power-on operation when the power-on flag of the i + 1th-level PCIE expansion box is in the first state; The booting operation includes controlling the CPLD to start the first power-on sequence, and setting the power-on flag to the first state after power-on is completed; The BMC of the CPU server is used to control the CPU server's CPLD to start a second power-on sequence when it is found that the power-on flags of all the PCIE expansion boxes are set to the first state. CPU server. The control system for an N-level PCIE expansion box according to claim 7, wherein the BMC of the i-th PCIE expansion box detects whether there is an i + 1-th PCIE connected to the BMC after receiving the power-on trigger signal. The process of the expansion box is specifically: After receiving the power-on trigger signal, the BMC of the i-level PCIE expansion box detects whether there is an address of the i + 1-level PCIE expansion box connected to it through the integrated line bus protocol IIC. The control system of the N-level PCIE expansion box according to claim 7 or 8, wherein the BMC of the CPU server is further configured to control the CPLD of the CPU server to start the first time after receiving the shutdown signal. Power-on sequence, after the power-off is completed, the power-on flag of the CPU server is set to the second state, and a shutdown trigger signal is generated; The BMC of the i-th level PCIE expansion box is further configured to perform a shutdown operation after receiving the shutdown trigger signal; when the i + 1-th level PCIE expansion box exists, extend to the i + 1-th level PCIE expansion box The box sends the shutdown trigger signal, so that the BMC of the i + 1th level PCIE expansion box performs the shutdown operation after receiving the shutdown trigger signal; wherein the shutdown operation includes controlling the CPLD to start a second Electrical sequence, after the power-off is completed, the power-on flag is set to the second state. A readable storage medium, characterized in that a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the N-level PCIE expansion box according to any one of claims 1-6 is implemented. Control method steps.

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