WO2019132994A1

WO2019132994A1 - Memory arrays

Info

Publication number: WO2019132994A1
Application number: PCT/US2017/069090
Authority: WO
Inventors: Elijah V. KARPOV; Brian S. Doyle; Ravi Pillarisetty; Abhishek Sharma; Prashant Majhi
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-12-29
Filing date: 2017-12-29
Publication date: 2019-07-04
Anticipated expiration: 2020-06-29

Abstract

In an embodiment, described herein are systems, methods, and apparatuses directed towards segmentation of a large cross-point memory a memory array (or tile) into two or more memory arrays (sub-tiles) of smaller size for use as an embedded memory. In an embodiment, the memory array can be a three-dimensional x-point memory. In an embodiment, a portion of the memory can be segmented laterally, such that the sub-tiles are substantially arranged in a horizontal plane. In an embodiment, the sub-tiles can be fabricated in the same interconnect layer. In another embodiment, a portion of the memory can be segmented vertically, such that the sub-tiles are substantially arranged in a vertical plane.

Description

MEMORY ARRAYS

TECHNICAL FIELD

[0001] This disclosure generally relates to memory arrays.

BACKGROUND

[0002] Modern electronics devices, such as non-volatile memories, may make use of various devices, for example, for the storage of bits. The memory devices can be distributed in arrays, for example, on a chip.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a diagram of a portion (for example, bit) of a memory array, in accordance with one or more example embodiments of a disclosure.

[0005] FIG. 2 shows a diagram representing a view of a portion of a memory array that includes a plurality of selectors and memory devices, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 3 shows a diagram of a laterally segmented portion of a memory or array, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 4 shows a diagram of a vertically segmented portion of a memory array, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 5 shows the flow diagram that represents aspects of the fabrication of a portion of a memory array, in accordance with one or more example embodiments of a disclosure.

[0009] FIG. 6 shows an example diagram of a processing flow for the fabrication of a portion of the memory array, in accordance with one or more example embodiments of the disclosure.

[0010] FIG. 7 depicts an example of a system, in accordance with to one or more embodiments of the disclosure.

DETAILED DESCRIPTION

[0011] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0012] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0013] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0014]“An embodiment,”“various embodiments,” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First,”“second,”“third,” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0015] The term“horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as“on,”“above,”“below,”“bottom,”“top,”“side” (as in“sidewall”), “higher,” “lower,” “upper,” “over,” and“under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The term“processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.

[0016] Modern electronics devices, such as non-volatile memories, may make use of various devices, for example, for the storage of bits. The memory devices can be distributed in arrays, for example, on the surface of the chip. One-bit memory cells can be grouped in small units called words which can be accessed together as a single memory address. Memory can be manufactured in word length that is usually a power of two, for example, 1, 2, 4 or 8 bits.

[0017] In various embodiments, disclosed herein are systems, methods, and apparatuses that generally relate to semiconductor devices. More particularly, some embodiments relate to memory devices, such as non-volatile memory (NVM) devices. Such memory devices, for example, can be incorporated into standalone memory devices, such as universal serial bus (USB) or other types of portable storage units, or integrated circuits (ICs), such as microcontrollers or system on chips (SoCs). The devices or ICs can be incorporated into or used with, for example, consumer electronic products, or relate to other types of devices.

[0018] In an embodiment, described herein are systems, methods, and apparatuses directed towards segmentation of a memory array into two or more memory arrays (referred to alternatively or additionally as memory sub-arrays herein) of smaller size. In an embodiment, the memory array can be a three-dimensional memory array, for example, an x-point memory, a crosspoint memory, and the like for use as an embedded memory,

[0019] In an embodiment, a portion of the memory can be segmented laterally, such that the sub-arrays are substantially arranged in a horizontal plane. In an embodiment, the subarrays can be fabricated in the same interconnect layer. In another embodiment, a portion of the memory can be segmented vertically, such that the sub-arrays are substantially arranged in a vertical plane. In an embodiment, the vertically segmented subarrays can be fabricated in different interconnect layers, for example, in an integer number of different interconnect layers. In an embodiment, at least a portion of the memory can be segmented both substantially laterally and substantially vertically, in a grid-like pattern. [0020] In an embodiment, there may be an insulator (for example, a dielectric) material that can be used to encapsulate at least a portion of the memory subarrays and can therefore be present in some areas between the individual subarrays. In an embodiment, the insulator can serve to protect at least portions of the memory array, including the various subarrays from environmental factors such as oxygen, humidity, and the like.

[0021] In an embodiment, one or more of the memory subarrays can include memories fabricated using back-end-of-line (BEOL) processing and fabrication techniques. In an embodiment, the bandwidth of the memory array comprising the two or more memory subarrays can be increased in comparison with the bandwidth of the memory array that is individually addressed and having the same number of bits as that of the segmented memory comprising the memory subarrays. In an example embodiment, for a memory array including 100 subarrays, each subarray can have a read-write speed of approximately 10-100 Mb/s and the read- write speed of the memory array can be approximately 1-10 Gb/s; however, the bandwidth of a similar memory array of the same size that is not segmented into individual subarrays may have a read-write speed that is less than the 100 Mb/s.

[0022] In an embodiment, one or more of the memory subarrays can include resistive random- access memory (RRAM), conductive-bridging RAM (CBRAM), and the like. In an embodiment, one or more of the memory subarrays can include phase change memory (PCMs). In an embodiment, one or more of the memory subarrays can include memories that include p- magnetic tunneling junctions (pMJT) devices. In an embodiment, the memory subarrays can include an spin-transfer torque memory (STTM) memory. In another embodiment, the memory subarray can include a negative differential resistance (NDR) material based memory. In an embodiment, one or more of the memory subarrays can include memory devices that do not use transistors to store a memory state. In an embodiment, one or more of the memory subarrays can include memory devices that are non-volatile. In an embodiment, such non volatile memory subarrays can include a memory device configured such that data can be written to the cells individually rather than in block arrays concurrently, that is, memory states can be written at the bit level.

[0023] In an embodiment, each memory sub-array can have individual memory elements, for example, individual memory elements at the intersection of a bitline and a wordline of the memory subarray. Each subarray can have a plurality of wordlines and bitlines to enable the memory elements. In an embodiment, the memory elements can include a memory device and a selector. In an embodiment, the memory device can include a two-terminal device, that is, a device that includes two electrodes.

[0024] In an embodiment, the memory device can include a material that changes its resistance in order to store a given memory state, for example, a“1” or a‘0.” In an embodiment, a high resistance state (HRS) in the material can be used to store a“0,” and a low resistance state (LRS) in the material can be used to store a“1.” In an embodiment, the selector can be used in connection with the memory device and a corresponding wordline and bitline to activate a memory device. In an embodiment, the selector can pass current when the wordline and bitline are at a given voltage, but can block current otherwise.

[0025] In an embodiment, the fabrication of the memory array including the various memory subarrays and individual memory elements can include various lithography, patterning, etching, insulator deposition, and polishing steps, to be discussed further herein.

[0026] In an embodiment, the memory array can have a size of N bits by M bits (NxM), where N and M are positive integers. In an embodiment, Such an NxM memory array can be segmented into K memory subarrays, where K is a positive integer that is less than NxM. In an embodiment, the NxM memory array can be subdivided into K mxn subarrays. Typical value for n and m are between 10 and 300, while K can be between 10 and 1000. In an embodiment, in such an example, N x M equals

[0027] For example, if N is equal to 1000 and M is equal to 1000, then the memory array can have a size of 1 million bits. This 1000x1000 bit memory array can be subdivided, for example, into K=l00 memory subarrays, each memory subarray having the same size of 100 x 100 bits. There can be many different ways to subdivide the memory subarray and the above represents just one example.

[0028] In an embodiment, the sub-arrays can each have individual electronics for operating the subarrays. In an example embodiment, each subarray can have a decoder (for example, a wordline decoder, or a bitline decoder). In another example embodiment, each subarray can have a buffer, for example, a wordline buffer and/or a bitline buffer. In one example embodiment, the memory can have a memory controller which can select a given subarray for memory storage. In an embodiment, each subarray can have a driver, that can be used to power various elements of the memory subarray. In an embodiment, the memory array and/or one or more of the memory subarrays can include processor(s) to control at least an aspect of the memory array and/or the memory subarrays. In an embodiment, the memory array and/or one or more of the memory subarrays can include amplifiers, for example, amplifiers to amplify a given memory state stored in the various memory devices of the memory array and the memory subarrays. In an embodiment, some of the various electronics, for example, the decoders, can be shared between memory subarrays.

[0029] FIG. 1 shows a diagram of a portion of a memory array 100, in accordance with one or more example embodiments of a disclosure. In an embodiment the portion of the memory array 100 can include a selector 101 and a memory device 103. In an embodiment, the selector 101 and the memory device 103 can be stacked on one another and can be electrically connected in series. In an embodiment, the selector 101 and the memory device 103 can be sandwiched by a bitline 104 and a wordline 106. In an embodiment, the bitline 104 and wordline 106 can provide electrical power to the selector and the memory device. In an embodiment, the bitline 104 and the wordline 106 can be part of the portion of many bitlines and wordlines used in the portion of the memory array. In an embodiment, bitlines and wordlines can be formed as thin films of a conductor, such as aluminum or polysilicon, deposited on insulating materials on a semiconductor surface and defined as lines lithographically. In an embodiment, while the terms “wordline” and“bitline” are used herein, any addressing line may be utilized in some embodiments of the present disclosure.

[0030] In an embodiment the selector 101 can represent a two terminal device. In an embodiment the selector 101 can include an active material sandwiched by two electrodes as will be further discussed below. In an embodiment, as mentioned, the portion of a memory array 100 can include a bitline 104. In an embodiment, the bitline 104 an include a conductive material. In an embodiment, the conductive materials used for the hitline 104 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, metal nitrides such as TiN or any combination thereof, and the like. In an embodiment, the bitline 104 can include a metallic material. In an embodiment, the bitline 104 can include an inert metal. In an embodiment, the metallic material can include gold, tungsten, copper, cobalt, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitline 104 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bitline 104 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the bitline 104 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, ALD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0031] In another embodiment, as mentioned, the portion of a memory array 100 can include a wordline 106. In an embodiment, the wordline 106 an include a conductive material. In an embodiment, the conductive materials used for the wordline 106 can include, but are not limited to, metals, for example, copper, cobalt, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the wordline 106 can include a metallic material. In an embodiment, the wordline 106 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the wordline 106 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordline 106 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the wordline 106 may be deposited by any suitable mechanism including, but not limited to, PVD, ALD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0032] In an embodiment, the selector 101 as described herein can be used in connection with a memory arrays having a three-dimensional lattice-like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline. In an embodiment, the selector 101 can include an IMT or IMT-like device, and/or a diode or diode-like device. In an embodiment, the IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the selector 101 can include a chalcogenide-based alloy and include Te, Se, and S. In an embodiment, the selector can be also based on oxide material when one of the electrodes contain silver.

[0033] In an embodiment the portion of the memory array 100 can include a memory device 103. In another embodiment the memory device 103 can represent a two terminal device. In one embodiment the memory device 103 can include a stack of materials sandwiched by two electrodes as will be discussed further below. In an embodiment, the memory device 103 can include transistor-based memory devices or negative-resistance memory devices. In an embodiment, the memory device 103 can include a spin transfer torque memory (STTM) device or the like.

[0034] In one embodiment the portion of the memory array 100 can include a first electrode 108 of the selector 101. In an embodiment, the first electrode 108 can include a metallic material. In an embodiment, the first electrode 108 can include an inert metal. In an embodiment, the metallic material can include tungsten, cobalt, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode 108 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode 108 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first electrode 108 may be deposited by any suitable mechanism including, but not limited to, PVD, ALD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0035] In an embodiment the portion of the memory array 100 can include an active layer 110 of the selector 101, which can also referred to as an insulator 110 herein. In another embodiment the active layer 110 or the insulator 110 can include an oxide. In one embodiment the insulator 110 can include a dielectric. In an embodiment, the insulator 110 can include a silicon dioxide (SiCk), or a low-K material. In one embodiment, the thickness of the insulator 110 can be determined by an integrated circuit design. In one embodiment, the insulator 110 can comprises one or more oxide layers, e.g., a silicon oxide layer, a doped porous silicon oxide, an aluminum oxide, a carbon doped silicon oxide, other electrically insulating layer. In alternate embodiments, the insulator 110 can comprise organic materials, inorganic materials, or both. In one embodiment, insulator 110 can have a thickness from about 50 nanometers to about 200 nm. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0036] In an embodiment the portion of the memory array 100 can include a second electrode 112 of the selector 101. In an embodiment, the second electrode 112 can include a metallic material. In an embodiment, the second electrode 112 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second electrode 112 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second electrode 112 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second electrode 112 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0037] In an embodiment the portion of the memory array 100 can include a first electrode 114 of the memory device 103. In an embodiment, the first electrode 114 can include a metallic material. In an embodiment, the first electrode 114 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode 114 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode 114 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first electrode 114 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0038] In another embodiment the portion of the memory array 100 can include active layers, for example, first magnetic layer 116, tunneling layer 118 and/or second magnetic layer 120 that are associated with the memory device 103. In one embodiment, the first magnetic layer 116 can also be referred to as a reference layer, and the tunneling layer 118 can also be referred to as a metal oxide layer, for example, a magnesium oxide layer, MgO. In another embodiment, the second magnetic layer 120 can also be referred to as a free layer. In one embodiment, a combination of the first magnetic layer 116, the tunneling layer 118, and the second magnetic layer 120 can be referred to as the active layers of the memory device 103.

[0039] In one embodiment the first magnetic layer 116 can have a perpendicular anisotropy. In another embodiment, the second magnetic layer 120 can have a perpendicular anisotropy. In one embodiment the first magnetic layer 116 can include a metal or a metal alloy material. For example, the first magnetic layer 116 can include a cobalt iron, boron based metal, and/or metal alloy material. In another embodiment, the tunneling layer 118 can include a metal oxide layer, for example, a magnesium oxide (MgO) material. In one embodiment the second magnetic layer 120 can also include a metal and/or a metal alloy material, for example, including, but not limited to a cobalt iron, boron based metal, and/or metal alloy material.

[0040] In one embodiment, the first magnetic layer 116 can have a thickness of approximately 0.4 nm to approximately 20 nm. In another embodiment the first magnetic layer 116 can be deposited using PVD, CVD, and/or ALD. In one embodiment the tunneling layer 118 can have a thickness of approximately 0.4 nm to approximately 20 nm. In another embodiment, the tunneling layer 118 can be deposited using PVD, CVD, and/or ALD. In one embodiment the second magnetic 120 can have a thickness of approximately 0.4 nm to approximately 20 nm. In another embodiment the second magnetic layer 120 can be deposited using PVD, CVD, and/or ALD.

[0041] In an embodiment the portion of the memory array 100 can further include a second electrode 122 of the memory device 103. In an embodiment, the second electrode 122 can include a metallic material. In an embodiment, the second electrode 122 can include an inert metal. In an embodiment, the metallic material can include tantalum, gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second electrode 122 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second electrode 122 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second electrode 122 may be deposited by any suitable mechanism including, but not limited to, PVD, ALD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0042] In an embodiment, the portion of the memory array 100 can be included on a substrate (not shown). In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).

[0043] In an embodiment, the substrate can include a flexible substrate. In various embodiments, substrate can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and M0S2, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, polycrystalline Ge, polycrystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, substrate can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, substrate comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate is a monocrystalline Si substrate.

[0044] In one embodiment, the substrate, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, substrate can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon.

[0045] FIG. 2 shows a diagram representing a view of a portion of a memory array 200 that includes a plurality of selectors and memory devices, in accordance with one or more example embodiments of the disclosure. In an embodiment, the memory array 200 can include elements fabricated using back-end-of-line (BEOL) processing and fabrication techniques.

[0046] In an embodiment, the memory array 200 can have individual memory cells 203, for example, individual memory elements at the intersection of a bitline 202 and a wordline 204 of the memory array 200. the memory array 200 can have a plurality of wordlines 204 and bitlines 202 to enable the memory elements. In an embodiment, the memory cells 203 can include a memory device 206 and a selector 208. In an embodiment, the memory device 206 can include a two-terminal device, that is, a device that includes two electrodes. In an embodiment, the selector 208 can also include a two-terminal device, that is, a device that includes two electrodes.

[0047] In an embodiment, the memory device 206 can include a material that changes its resistance in order to store a given memory state, for example, a“1” or a‘0.” In an embodiment, a high resistance state (HRS) in the material can be used to store a“0,” and a low resistance state (LRS) in the material can be used to store a“1.” In an embodiment, the selector 206 can be used in connection with the memory device 208 and a corresponding wordline 204 and bitline 202 to activate a memory device 208. In an embodiment, the selector 206 can pass current when the wordline 204 and bitline 202 are at a given voltage, but can block current otherwise. In an embodiment, the fabrication of the memory array 200 can include various lithography, patterning, etching, insulator deposition, and polishing steps, to be discussed further herein.

[0048] In an embodiment, the memory array 200 can have electronics for operating the memory array 200. In an example embodiment, the memory array 200 can have a decoder (for example, a wordline decoder, or a bitline decoder). In another example embodiment, the memory array 200 can have a buffer, for example, a wordline buffer and/or a bitline buffer. In an embodiment, the memory array 200 can have a driver, that can be used to power various elements of the memory array 200. In an embodiment, the memory array 200 include processor(s) to control at least an aspect of the memory array 200. In an embodiment, the memory array 200 can include amplifiers, for example, amplifiers to amplify a given memory state stored in the various memory devices 206 of the memory array 200.

[0049] In an embodiment the portion of the memory array 200 can include a bitline 202. In an embodiment, the bitline 202 can include a conductive material. In an embodiment, the conductive materials used for the bitline 202 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the bitline 202 can include a metallic material. In an embodiment, the bitline 202 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitline 202 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bitline 202 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the bitline 202 may be deposited by any suitable mechanism including, but not limited to, PVD, ALD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0050] In another embodiment the portion of the memory array 200 can include a memory cell 203. In an embodiment the memory cell 203 can include a memory device 206 and a selector 208 to be discussed below.

[0051] In an embodiment the portion of the memory array 200 can include a wordline 204. In an embodiment, the wordline 204 can include a conductive material. In an embodiment, the conductive materials used for the wordline 204 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, and metal nitrides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the wordline 204 can include a metallic material. In an embodiment, the wordline 204 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the wordline 204 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordline 204 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the wordline 204 may be deposited by any suitable mechanism including, but not limited to, PVD, ALD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0052] In an embodiment the portion of the memory array 200 can include a selector 208. In an embodiment, the selector 208 can include an IMT or IMT-like device, and/or a diode or diode-like device. In an embodiment, the IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the selector 208 can include chalcogenide-based alloys and can include Te, Se, or S. In an embodiment, the selector 208 can be based on ab oxide material when one of the electrodes contain silver. In an embodiment, the selector 208 can be used in connection with a memory arrays having a three-dimensional lattice-like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline.

[0053] In an embodiment the portion of the memory array 200 can include a memory device 206. In an embodiment, the memory device 206 can include transistor-based memory devices or negative-resistance memory devices. In an embodiment, the memory device 103 used for each memory element in connection with the selector 101 described herein can include an spin transfer torque memory (STTM) device, or the like.

[0054] In an embodiment, the portion of the memory array 200 can be included on a substrate (not shown). In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate can include a flexible substrate. In various embodiments, substrate can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and MoS₂, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, polycrystalline Ge, polycrystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, substrate can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, substrate comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate is a monocrystalline Si substrate.

[0055] In one embodiment, the substrate, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, substrate can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon.

[0056] FIG. 3 shows a diagram of a laterally segmented portion of a memory or array 300, in accordance with one or more example embodiments of the disclosure. In an embodiment the portion of the memory array 300 can include one or more or a plurality of memory sub-arrays 302, 304 and 306 (also referred to herein as memory arrays 302, 304, and 306) arranged in a substantially horizontal or lateral formation. In an embodiment the memory arrays 302, 304 and 306 only represent exemplary number of memory arrays. In an embodiment the diagram of the portion of the memory array 300 can further include an indication 303 of more memory arrays that are also substantially horizontally connected to the memory arrays 302, 304 and 306. In an embodiment, the memory arrays 302, 304, and 306 can be fabricated in the same interconnect layer.

[0057] In an embodiment, there may be an insulator (for example, a dielectric) material (not shown) that can be used to encapsulate at least a portion of the memory array 300 and can therefore be present in some areas between the individual memory arrays, for example, memory arrays 302, 304 and 306. In an embodiment, the insulator can serve to protect at least portions of the memory array 300, including the various subarrays from environmental factors such as oxygen, humidity, and the like. In an embodiment, the memory array 300 can include memories fabricated using back-end-of-line (BEOL) processing and fabrication techniques.

[0058] In an embodiment the portion of the memory array 300 can include electronics 310, 312 and 314. In an embodiment the electronics 310, 312 and 314 can include decoders such as wordline decoders and/or bitline decoders, driving circuitry, wordline and/or bitline buffers and/or memory controllers and processors. In an embodiment the wordline and/or bitline decoders can serve to select a given wordline and/or bitline to store a bit or bits of information on the memory arrays 302, 304 and/or 306. In an embodiment the wordline and/or bitline buffers can serve to store data that is in the memory arrays 302, 304 and/or 306, for example, during read and/or write operations. In an embodiment the memory controller can serve to select one or more of the memory arrays 302, 304 and/or 306 for operation while disabling a portion of other memory arrays such as memory arrays 302, 304 and/or 306. In an embodiment the electronics 310, 312 and/or 314 can include a processor that is communicatively coupled to the memory arrays 302, 304 and/or 306 and/or the memory controller not shown. In an embodiment the electronics can include a portion of on-chip electronics. In another embodiment the electronics 310, 312 and/or 314 can exist off chip.

[0059] In an embodiment the portion of the memory array 300 can include bitlines 320, 322 and 324. In an embodiment, the bitlines 320, 322 and 324 an include a conductive material. In an embodiment, the conductive materials used for the bitlines 320, 322 and 324 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the bitlines 320, 322 and 324 can include a metallic material. In an embodiment, the bitlines 320, 322 and 324 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitlines 320, 322 and 324 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitlines 320, 322 and 324 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bitlines 320, 322 and 324 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the bitline 104 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0060] In an embodiment the memory array 300 can include wordlines 330, 332 and 334. In an embodiment, the wordlines 330, 332 and 334 can include a conductive material. In an embodiment, the conductive materials used for the wordlines 330, 332 and 334 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminu carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the wordlines 330, 332 and 334 can include a metallic material. In an embodiment, the wordlines 330, 332 and 334 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the wordlines 330, 332 and 334 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the wordlines 330, 332 and 334 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordlines 330, 332 and 334 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the wordlines 330, 332 and 334 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0061] In an embodiment the portion of the memory array 300 can further include memory cells 340, 342, and 344. In an embodiment the memory cells 340, 342 and 344 can include selectors and memory devices such as those shown in connection with FIG. 2 memory device 206 and selector 208. In an embodiment, the selector can include an IMT or IMT-like device, and/or a diode or diode-like device. In an embodiment, the IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the selector 208 can include chalcogenide-based alloys and can include Te, Se, or S. In an embodiment, the selector 208 can be based on ab oxide material when one of the electrodes contain silver. In an embodiment, the selector can be used in connection with a memory arrays having a three-dimensional lattice-like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline. In an embodiment, the memory device can include transistor-based memory devices or negative-resistance memory devices. In an embodiment, the memory device used for each memory element in connection with the selector described herein can include an spin transfer torque memory (STTM) device, or the like.

[0062] FIG. 4 shows a diagram of a vertically segmented portion of a memory array 400 in accordance with one or more example embodiments of the disclosure. In an embodiment the portion of the memory array 400 can include memory arrays 402, 404, 406, 408 and 410. In an embodiment the diagram of the portion of the memory array 400 can further include an indication 403 of more memory array devices which are not shown for diagrammatic reasons.

[0063] In an embodiment the portion of the memory array 400 can include electronics 412, 414, 416, 418 and 420. In an embodiment the electronics 412, 414, 416, 418 and 420 can include decoders such as wordline decoders and/orbitline decoders, driving circuitry, wordline and/or bitline buffers and/or memory controllers and processors. In an embodiment the wordline and/or bitline decoders can serve to select a given wordline and/or bitline to store a bit or bits of information on the memory arrays 402, 404, 406, 408 and 410. In an embodiment the wordline and/or bitline buffers can serve to store data that is in the memory arrays 402, 404, 406, 408 and 410, for example, during read and/or write operations. In an embodiment the memory controller can serve to select one or more of the memory arrays 402, 404, 406, 408 and 410 for operation while disabling a portion of other memory arrays such as memory arrays 402, 404, 406, 408 and 410. In an embodiment the electronics 412, 414, 416, 418 and 420 can include a processor that is communicatively coupled to the memory arrays 402, 404, 406, 408 and 410 and/or the memory controller, not shown. In an embodiment the electronics can include a portion of on-chip electronics. In another embodiment the electronics 402, 404, 406, 408 and 410 can exist off chip.

[0064] In an embodiment the portion of the memory array 400 can include bitlines 422, 424, 426, 428 and 430. In an embodiment, the bitlines 422, 424, 426, 428 and 430 can include a conductive material. In an embodiment, the conductive materials used for the bitlines 422, 424, 426, 428 and 430 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titaniu carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the bitlines 422, 424, 426, 428 and 430 can include a metallic material. In an embodiment, the bitlines 422, 424, 426, 428 and 430 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitlines 422, 424, 426, 428 and 430 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordlines bitlines 422, 424, 426, 428 and 430 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the bitlines 422, 424, 426, 428 and 430 may be deposited by any suitable mechanism including, but not limited to, PVD, ALD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0065] In an embodiment the portion of the memory array 400 can include wordlines 432, 434, 436, 438 and 440. In an embodiment, the wordlines 432, 434, 436, 438 and 440 can include a conductive material. In an embodiment, the conductive materials used for the wordlines 432, 434, 436, 438 and 440 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the wordlines 432, 434, 436, 438 and 440 can include a metallic material. In an embodiment, the wordlines 432, 434, 436, 438 and 440 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the wordlines 432, 434, 436, 438 and 440 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordlines 432, 434, 436, 438 and 440 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the wordlines 432, 434, 436, 438 and 440 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0066] In an embodiment the portion of the memory array 400 can include memory cells 442, 444, 446, 448 and 450. In an embodiment the memory cells 442, 444, 446, 448 and 450 can include selectors and memory devices similar to but not necessarily identical to memory devices 206 and selectors 208 shown and described in connection with FIG. 2. In an embodiment, the selector can include an IMT or IMT-like device, and/or a diode or diode-like device. In an embodiment, the IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the selector can include chalcogenide-based alloys and can include Te, Se, or S. In an embodiment, the selector can be based on ab oxide material when one of the electrodes contain silver. In an embodiment, the selector can be used in connection with a memory arrays having a three- dimensional lattice-like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline. In an embodiment, the memory device can include transistor-based memory devices or negative-resistance memory devices. In an embodiment, the memory device used for each memory element in connection with the selector described herein can include an spin transfer torque memory (STTM) device, or the like.

[0067] FIG. 5 shows the flow diagram 500 that represents aspects of the fabrication of a portion of a memory array, in accordance with one or more example embodiments of a disclosure. In an embodiment the diagram 500 includes a first partial structure 501 for the fabrication of a portion of the memory array.

[0068] In an embodiment the first partial structure can include a wordline 502. In an embodiment, the wordline 502 can include a conductive material. In an embodiment, the conductive materials used for the wordline 502 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the wordline 502 can include a metallic material. In an embodiment, the wordline 502 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the wordline 502 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the wordline 502 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordline 502 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the wordline 502 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0069] In an embodiment the first partial structure 501 can include a selector 504. In an embodiment, the selector 504 as described herein can be used in connection with a memory arrays having a three-dimensional lattice-like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline. In an embodiment, the selector 504 can include an IMT or IMT-like device, and/or a diode or diode like device. In an embodiment, the IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbC , SmNiCb, and the like. In an embodiment, the selector 504 can include chalcogenide-based alloys and can include Te, Se, or S. In an embodiment, the selector 504 can be based on ab oxide material when one of the electrodes contain silver.

[0070] In an embodiment the first partial structure 501 can include middle electrode 506. In an embodiment the middle electrode 506 can be shared between a memory device 508 and a selector 504. In an embodiment, the middle electrode 506 can include a conductive material. In an embodiment, the conductive materials used for the middle electrode 506 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the middle electrode 506 can include a metallic material. In an embodiment, the middle electrode 506 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the middle electrode 506 can comprise a semi- metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the middle electrode 506 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the middle electrode 506 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the middle electrode 506 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0071] In an embodiment the first partial structure 501 can include a memory device 508. In another embodiment the memory device 508 can include an STTM memory device.

[0072] In an embodiment the diagram 500 can further include a second partial structure 503 that represents aspects of the fabrication of the portion of the memory array. In an embodiment the second partial structure 503 can include a pre-patterned bitline 510. In an embodiment a pre-patterned bitline 510 can represent a bitline that has not yet been patterned into final form.

[0073] In an embodiment the second partial structure 503 can be encapsulated with an insulator, such as a nitride (not shown). In one embodiment, the thickness of the insulator can be determined by an integrated circuit design. In one embodiment, the insulator can comprises one or more oxide layers, e.g., a silicon oxide layer, a doped porous silicon oxide, an aluminum oxide, a carbon doped silicon oxide, other electrically insulating layer. In alternate embodiments, the insulator can comprise organic materials, inorganic materials, or both. In an embodiment the second partial structure 503 can be exposed to an insulator gap fill processing. In an embodiment the second partial structure 503 can include a polishing step on the insulator. In an embodiment the polishing step on the oxide can be stopped on a bottom electrode of the selector 504 (not shown). In an embodiment the second partial structure 503 can have the pre- pattemed bitline 510 deposited.

[0074] In an embodiment, the pre-pattemed bitline 510 can include a conductive material. In an embodiment, the conductive materials used for the pre-patterned bitline 510 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the pre- pattemed bitline 510 can include a metallic material. In an embodiment, the pre-pattemed bitline 510 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the pre-pattemed bitline 510 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the pre-pattemed bitline 510 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the pre-pattemed bitline 510 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the pre-patterned bitline 510 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0075] In an embodiment the diagram 500 can further include a third partial structure 505 that can represent an aspect of the fabrication of the portion of the memory array. In an embodiment the third partial structure 505 can include a post-patterned bitline 512. In an embodiment the post-pattern bitline 512 can be fabricated using a column etch and/or lithography steps. In an embodiment the etch can stop on a bottom metal. In an embodiment the third partial structure 505 can be encapsulated for example with a nitride. In an embodiment the third partial structure 505 can be exposed to an oxide gap filling process.

[0076] In an embodiment the post-pattern bitline 512 can include a conductive material. In an embodiment, the conductive materials used for the post-pattern bitline 512 can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the post-pattern bitline 512 can include a metallic material. In an embodiment, the post-pattern bitline 512 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the post-pattern bitline 512 can comprise a semi- metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the post-pattern bitline 512 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the post-pattern bitline 512 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the post-pattern bitline 512 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0077] FIG. 6 shows an example diagram 600 of a processing flow for the fabrication of a portion of the memory array in accordance with one or more example embodiments of the disclosure. At block 602, electronics can be provided. In an embodiment the electronics can include decoders such as wordline decoders and/orbitline decoders, driving circuitry, wordline and/or bitline buffers and/or memory controllers and processors. In an embodiment the wordline and/or bitline decoders can serve to select a given wordline and/or bitline to store a bit or bits of information on a memory arrays. In an embodiment the wordline and/or bitline buffers can serve to store data that is in the memory arrays, for example, during read and/or write operations. In an embodiment the memory controller can serve to select one or more of the memory arrays for operation while disabling a portion of other memory arrays such as memory arrays. In an embodiment the electronics can include a processor that is communicatively coupled to the memory arrays and/or the memory controller not shown. In an embodiment the electronics can include a portion of on-chip electronics. In another embodiment the electronics can exist off chip.

[0078] At block 604, wordlines can be provided that can be electronically coupled or connected to the electronics. In an embodiment the wordlines can include a conductive material. In an embodiment, the conductive materials used for the wordlines can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the wordlines can include a metallic material. In an embodiment, the wordlines can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the wordlines can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the wordlines can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallic s, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the wordlines can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the wordlines may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0079] At block 606, selectors can be deposited on the wordlines. In an embodiment, the selectors can be used in connection with a memory arrays having a three-dimensional lattice like architecture, such as an x-point memory array, or a cross-point memory array. In an embodiment, the selector can include an IMT or IMT-like device, and/or a diode or diode-like device. In an embodiment, the IMT or IMT-like device can include an oxide material, for example, VO2, T13O5, T12O3, LaCoCb, NbCk, SmNiCb, and the like. In an embodiment, the selector can include chalcogenide-based alloys and can include Te, Se, or S. In an embodiment, the selector can be based on oxide materials when one of the electrodes contain silver.

[0080] At block 608, memory devices can be deposited on the selectors. In an embodiment, in such memory architectures, a selector and a memory device can be located at the intersection of each wordline and bitline. In an embodiment, a memory device used for each memory element in connection with the selector described herein can include transistor-based memory devices or negative-resistance memory devices. In an embodiment, the memory device used for each memory element in connection with the selector described herein can include an spin transfer torque memory (STTM) device, or the like.

[0081] At block 610, bitlines can be deposited on the memory devices. In an embodiment the bitlines can include a conductive material. In an embodiment, the conductive materials used for the bitlines can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the bitlines can include a metallic material. In an embodiment, the bitlines can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the bitlines can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the bitlines can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the bitlines can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the bitlines may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like. [0082] FIG. 7 depicts an example of a system 700 according to one or more embodiments of the disclosure. In an embodiment, the memory arrays discussed herein can be used in connection with system700. In one embodiment, system 700 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 700 can include a system on a chip (SOC) system.

[0083] In one embodiment, system 700 includes multiple processors including processor 710 and processor N 705, where processor N 705 has logic similar or identical to the logic of processor 710. In one embodiment, processor 710 has one or more processing cores (represented here by processing core 1 712 and processing core N 712N, where 712N represents the Nth processor core inside processor 710, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 7). In some embodiments, processing core 712 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 710 has a cache memory 716 to cache instructions and/or data for system 700. Cache memory 716 may be organized into a hierarchical structure including one or more levels of cache memory.

[0084] In some embodiments, processor 710 includes a memory controller (MC) 714, which is configured to perform functions that enable the processor 710 to access and communicate with memory 730 that includes a volatile memory 732 and/or a non-volatile memory 734. In some embodiments, processor 710 can be coupled with memory 730 and chipset 720. Processor 710 may also be coupled to a wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna antenna 778 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0085] In some embodiments, volatile memory 732 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 734 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0086] Memory device 730 stores information and instructions to be executed by processor 710. In one embodiment, memory 730 may also store temporary variables or other intermediate information while processor 710 is executing instructions. In the illustrated embodiment, chipset 720 connects with processor 710 via Point-to-Point (PtP or P-P) interface 717 and P-P interface 722. Chipset 720 enables processor 710 to connect to other elements in system 700. In some embodiments of the disclosure, P-P interface 717 and P-P interface 722 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0087] In some embodiments, chipset 720 can be configured to communicate with processor 710, the processor N 705, display device 740, and other devices 772, 776, 774, 760, 762, 764, 766, 777, etc. Chipset 720 may also be coupled to the wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals.

[0088] Chipset 720 connects to display device 740 via interface 726. Display 740 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 710 and chipset 720 are integrated into a single SOC. In addition, chipset 720 connects to bus 750 and/or bus 755 that interconnect various elements 774, 760, 762, 764, and 766. Bus 750 and bus 755 may be interconnected via a bus bridge 772. In one embodiment, chipset 720 couples with a non-volatile memory 760, a mass storage device(s) 762, a keyboard/mouse 764, and a network interface 766 via interface 724 and/or 704, smart TV 776, consumer electronics 777, etc.

[0089] In one embodiment, mass storage device(s) 762 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 766 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [0090] While the modules shown in FIG. 7 are depicted as separate blocks within the system 700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although Volatile Memory 732, Nonvolatile Memory 734 and cache memory 716 are depicted as a separate block within processor 710, cache memory 716 or selected elements thereof can be incorporated into processor core 712.

[0091] It is noted that the system 700 described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor devices, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The devices (for example, the devices described in connection with any of FIGS. 1-6), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0092] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0093] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0094] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0095] Example 1 may include a memory array, comprising: a first memory array comprising a plurality of first memory elements, the plurality of first memory elements comprising: first memory devices, first selectors, first bitlines, and first wordlines; and a second memory array comprising a plurality of second memory elements, the plurality of second memory elements comprising: second memory devices, second selectors, second bitlines, and second wordlines, wherein the first memory array is electronically coupled to the second memory array.

[0096] Example 2 may include the memory array of example 1 and/or some other example herein, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising: third memory devices, third selectors, third bitlines, and third wordlines; wherein the third memory array is electronically coupled to the first memory array and the second memory array. [0097] Example 3 may include the memory array of example 1 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in an interconnect layer.

[0098] Example 4 may include the memory array of example 1 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[0099] Example 5 may include the memory array of example 2 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

[00100] Example 6 may include the memory array of example 2 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00101] Example 7 may include the memory array of example 1 and/or some other example herein, wherein the first memory devices comprise first electronics including one or more of a bitline decoder, a wordline decoder, or an amplifier.

[00102] Example 8 may include the memory array of example 1 and/or some other example herein, wherein the first memory devices include memory devices fabricated using back-end- of-line (BEOL) processing.

[00103] Example 9 may include the memory array of example 1 and/or some other example herein, wherein the first memory devices include at least one of a resistive random-access memory (RRAM), a conductive-bridging RAM (CBRAM), a phase change memory (PCM), perpendicular magnetic tunneling junction (pMJT) memory, spin-transfer torque memory (STTM) memory, or a negative differential resistance (NDR) memory.

[00104] Example 10 may include the memory array of example 1 and/or some other example herein, wherein the first selectors include a diode device.

[00105] Example 11 may include a device including a memory array, the memory array comprising: a first memory array comprising a plurality of first memory elements, the plurality of first memory elements comprising: first memory devices, first selectors, first bitlines, and first wordlines; a second memory array comprising a plurality of second memory elements, the plurality of second memory elements comprising: second memory devices, second selectors, second bitlines, and second wordlines, wherein the first memory array is electronically coupled to the second memory array.

[00106] Example 12 may include the device of example 11 and/or some other example herein, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising:

third memory devices, third selectors, third bitlines, and third wordlines;

wherein the third memory array is electronically coupled to the first memory array and the second memory array.

[00107] Example 13 may include the device of example 11 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in an interconnect layer.

[00108] Example 14 may include the device of example 11 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00109] Example 15 may include the device of example 11 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

[00110] Example 16 may include the device of example 11 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00111] Example 17 may include the device of example 11 and/or some other example herein, wherein the first memory devices comprise first electronics including one or more of a bitline decoder, a wordline decoder, or an amplifier.

[00112] Example 18 may include the device of example 11 and/or some other example herein, wherein the first memory devices include memory devices fabricated using back-end-of-line (BEOL) processing. [00113] Example 19 may include the device of example 11 and/or some other example herein, wherein the first memory devices include at least one of a resistive random-access memory (RRAM), a conductive-bridging RAM (CBRAM), a phase change memory (PCM), perpendicular magnetic tunneling junction (pMJT) memory, spin-transfer torque memory (STTM) memory, or a negative differential resistance (NDR) memory.

[00114] Example 20 may include an integrated circuit including a memory array, the memory array comprising: a first memory array comprising a plurality of first memory elements, the plurality of first memory elements comprising: first memory devices, first selectors, first bitlines, and first wordlines; and a second memory array comprising a plurality of second memory elements, the plurality of second memory elements comprising: second memory devices, second selectors, second bitlines, and second wordlines; wherein the first memory array is electronically coupled to the second memory array.

[00115] Example 21 may include the integrated circuit of example 20 and/or some other example herein, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising: third memory devices; third selectors; third bitlines; and third wordlines; wherein the third memory array is electronically coupled to the first memory array and the second memory array.

[00116] Example 22 may include the integrated circuit of example 21 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

[00117] Example 23 may include the integrated circuit of example 21 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00118] Example 24 may include the integrated circuit of example 20 and/or some other example herein, wherein the first selectors include a diode device.

[00119] Example 25 may include the integrated circuit of example 20 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in an interconnect layer. [00120] Example 26 may include the integrated circuit of example 20 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00121] Example 27 may include the integrated circuit of example 20 and/or some other example herein, wherein the first memory devices comprise first electronics including one or more of a bitline decoder, a wordline decoder, or an amplifier.

[00122] Example 28 may include the integrated circuit of example 20 and/or some other example herein, wherein the first memory devices include memory devices fabricated using back-end-of-line (BEOL) processing.

[00123] Example 29 may include the integrated circuit of example 20 and/or some other example herein, wherein the first memory devices include at least one of a resistive random- access memory (RRAM), a conductive -bridging RAM (CBRAM), a phase change memory (PCM), perpendicular magnetic tunneling junction (pMJT) memory, spin-transfer torque memory (STTM) memory, or a negative differential resistance (NDR) memory.

[00124] Example 30 may include the integrated circuit of example 20 and/or some other example herein, wherein the first selectors include a diode device.

[00125] Example 31 may include an electronic device comprising: a memory array, comprising: a first memory array comprising a plurality of first memory elements, the plurality of first memory elements comprising: first memory devices, first selectors, first bitlines, and first wordlines; and a second memory array comprising a plurality of second memory elements, the plurality of second memory elements comprising: second memory devices, second selectors, second bitlines, and second wordlines, wherein the first memory array is electronically coupled to the second memory array.

[00126] Example 32 may include the electronic device of example 31 and/or some other example herein, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising: third memory devices, third selectors, third bitlines, and third wordlines;

[00127] Example 33 may include the electronic device of example 31 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in an interconnect layer. [00128] Example 34 may include the electronic device of example 31 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00129] Example 35 may include the electronic device of example 32 and/or some other example herein, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

[00130] Example 36 may include the electronic device of example 32 and/or some other example herein, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

[00131] Example 37 may include the electronic device of example 31 and/or some other example herein, wherein the first memory devices comprise first electronics including one or more of a bitline decoder, a wordline decoder, or an amplifier.

[00132] Example 38 may include the electronic device of example 31 and/or some other example herein, wherein the first memory devices include memory devices fabricated using back-end-of-line (BEOL) processing.

[00133] Example 39 may include the electronic device of example 31 and/or some other example herein, wherein the first memory devices include at least one of a resistive random- access memory (RRAM), a conductive -bridging RAM (CBRAM), a phase change memory (PCM), perpendicular magnetic tunneling junction (pMJT) memory, spin-transfer torque memory (STTM) memory, or a negative differential resistance (NDR) memory.

[00134] Example 40 may include the electronic device of example 31 and/or some other example herein, wherein the first selectors include a diode device.

[00135] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. [00136] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[00137] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[00138] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and the performance of any incorporated methods and processes. The patentable scope of certain embodiments of the disclosure is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

CLAIMS That which is claimed is:

1. A memory array, comprising:

a first memory array comprising a plurality of first memory elements, the plurality of first memory elements comprising:

first memory devices, first selectors, first bitlines, and first wordlines; and

a second memory array comprising a plurality of second memory elements, the plurality of second memory elements comprising:

second memory devices, second selectors, second bitlines, and second wordlines, wherein the first memory array is electronically coupled to the second memory array.

2. The memory array of claim 1, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising:

third memory devices, third selectors, third bitlines, and third wordlines;

3. The memory array of claim 1, wherein the first memory array and the second memory array are arranged horizontally, both in an interconnect layer.

4. The memory array of claim 1, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

5. The memory array of claim 2, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

6. The memory array of claim 2, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

7. The memory array of any one of claims 1 or 2, wherein the first memory devices comprise first electronics including one or more of a bitline decoder, a wordline decoder, or an amplifier.

8. The memory array of any one of claims 1 or 2, wherein the first memory devices include memory devices fabricated using back-end-of-line (BEOL) processing.

9. The memory array of any one of claims 1 or 2, wherein the first memory devices include at least one of a resistive random-access memory (RRAM), a conductive -bridging RAM (CBRAM), a phase change memory (PCM), perpendicular magnetic tunneling junction (pMJT) memory, spin-transfer torque memory (STTM) memory, or a negative differential resistance (NDR) memory.

10. The memory array of any one of claims 1 or 2, wherein the first selectors include a diode device.

11. A device including a memory array, the memory array comprising:

first memory devices, first selectors, first bitlines, and first wordlines;

12. The device of claim 11, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising:

third memory devices, third selectors, third bitlines, and third wordlines;

13. The device of claim 11, wherein the first memory array and the second memory array are arranged horizontally, both in an interconnect layer.

14. The device of claim 11, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

15. The device of claim 12, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

16. The device of claim 12, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.

17. The device of any one of claims 11 or 12, wherein the first memory devices comprise first electronics including one or more of a bitline decoder, a wordline decoder, or an amplifier.

18. The device of any one of claims 11 or 12, wherein the first memory devices include memory devices fabricated using back-end-of-line (BEOL) processing.

19. The device of any one of claims 11 or 12, wherein the first memory devices include at least one of a resistive random-access memory (RRAM), a conductive -bridging RAM (CBRAM), a phase change memory (PCM), perpendicular magnetic tunneling junction (pMJT) memory, spin-transfer torque memory (STTM) memory, or a negative differential resistance (NDR) memory.

20. An integrated circuit including a memory array, the memory array comprising:

first memory devices, first selectors, first bitlines, and first wordlines; and a second memory array comprising a plurality of second memory elements, the plurality of second memory elements comprising:

second memory devices, second selectors, second bitlines, and second wordlines;

wherein the first memory array is electronically coupled to the second memory array.

21. The integrated circuit of claim 20, further comprising a third memory array, the third memory array comprising a plurality of third memory elements, the plurality of third memory elements comprising:

third memory devices; third selectors; third bitlines; and third wordlines;

22. The integrated circuit of claim 21, wherein the first memory array is in a first interconnect layer and the second memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer, and the third memory array and the first memory array are arranged horizontally, both in the first interconnect layer.

23. The integrated circuit of claim 21, wherein the first memory array and the second memory array are arranged horizontally, both in a first interconnect layer, wherein the first memory array is in the first interconnect layer and the third memory array is in a second interconnect layer, wherein the first interconnect layer is on the second interconnect layer.