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WO2019125384A1 - Mémoire basée sur un couplage spin-orbite avec aimant isolant - Google Patents

Mémoire basée sur un couplage spin-orbite avec aimant isolant Download PDF

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Publication number
WO2019125384A1
WO2019125384A1 PCT/US2017/067087 US2017067087W WO2019125384A1 WO 2019125384 A1 WO2019125384 A1 WO 2019125384A1 US 2017067087 W US2017067087 W US 2017067087W WO 2019125384 A1 WO2019125384 A1 WO 2019125384A1
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Prior art keywords
magnet
interconnect
magnetic
spin
adjacent
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Inventor
Tanay GOSAVI
Chia-Ching Lin
Ashish Verma PENUMATCHA
Sasikanth Manipatruni
Gary A. ALLEN
Ian A. Young
Dmitri E. Nikonov
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1677—Verifying circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • Embedded memory with state retention can enable energy and computational efficiency.
  • spin transfer torque based magnetic random access memory suffer from the problem of high voltage and high write current during the programming (e.g., writing) of a bit-cell.
  • large write current e.g., greater than 100 mA
  • voltage e.g., greater than 0.7 V
  • Limited write current also leads to high write error rates or slow switching times (e.g., exceeding 20 ns) in MTJ based MRAM.
  • the presence of a large current flowing through a tunnel barrier leads to reliability issues in magnetic tunnel junctions.
  • Fig. 1A illustrates a magnetization response to an applied magnetic field for a ferromagnet.
  • Fig. IB illustrates a magnetization response to an applied magnetic field for a paramagnet.
  • Fig. 2A illustrates a three-dimensional (3D) view of a device having an out-of- plane magnetic tunnel junction (MTJ) stack directly coupled to a spin orbit coupling (SOC) interconnect.
  • MTJ out-of- plane magnetic tunnel junction
  • SOC spin orbit coupling
  • Fig. 2B illustrates a top view of a cross-section of the device of Fig. 2A.
  • Fig. 3 illustrates a cross-section of the spin orbit coupling (SOC) interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current.
  • SOC spin orbit coupling
  • Fig. 4A illustrates a plot showing write energy-delay conditions for one transistor and one magnetic tunnel junction (MTJ) with spin Hall effect (SHE) material compared to traditional MTJs.
  • MTJ magnetic tunnel junction
  • SHE spin Hall effect
  • Fig. 4B illustrates a plot comparing reliable write times for spin Hall MRAM and spin torque MRAM.
  • Fig. 5A illustrates a 3D view of a device having an MTJ with magnets having perpendicular magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, according to some embodiments of the disclosure.
  • Fig. 5B illustrates a top view of the device of Fig. 5A, in accordance with some embodiments of the disclosure.
  • Fig. 6A illustrates a 3D view of a device having an MTJ with magnets having in-plane magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, according to some embodiments of the disclosure.
  • Fig. 6B illustrates a top view of the device of Fig. 6A, in accordance with some embodiments of the disclosure.
  • Fig. 7A illustrates a 3D view of a cross-point device having an MTJ with magnets having perpendicular magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, and wherein a read port is positioned for a cross-point architecture, according to some embodiments of the disclosure.
  • Fig. 7B illustrates a top view of the device of Fig. 7A, in accordance with some embodiments of the disclosure.
  • Fig. 8A illustrates a 3D view of a cross-point device having an MTJ with magnets having in-plane magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, and wherein a read port is positioned for a cross-point architecture, according to some embodiments of the disclosure.
  • Fig. 8B illustrates a top view of the device of Fig. 8A, in accordance with some embodiments of the disclosure.
  • Fig. 9A illustrates a plot showing spin polarization capturing switching of the composite magnet, according to some embodiments of the disclosure.
  • Fig. 9B illustrates a magnetization plot associated with Fig. 9A, according to some embodiments of the disclosure.
  • Fig. 9C illustrates a plot showing spin polarization capturing switching of a composite magnet using traditional spin orbit material, according to some embodiments of the disclosure.
  • Fig. 9D illustrates a magnetization plot associated with Fig. 9C, according to some embodiments of the disclosure.
  • Fig. 10 illustrates a cross-section of a die layout having the device of Fig. 5A formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure.
  • Fig. 11 illustrates a cross-section of a die layout having the device of Fig. 5A formed in metal 2 (M2) and metal 1 (Ml) layer regions, according to some embodiments of the disclosure.
  • Fig. 12 illustrates a plot showing improvement in energy-delay product using the device of Fig. 5A compared to the device of Fig. 2A, in accordance with some embodiments of the disclosure.
  • FIG. 13 illustrates a flowchart of a method of forming any one of devices of
  • Fig. 14 illustrates a smart device or a computer system or a SoC (System-on-
  • Chip with a magnetic junction (e.g., devices of Figs. 5-8), according to some embodiments of the disclosure.
  • an apparatus which comprises: a magnetic junction having a layer (or structure) comprising an unpinned magnet; a layer (or structure) comprising an insulating or semi-insulating magnet, the layer (structure) being adjacent to the magnet junction; and an interconnect adjacent to the layer (structure).
  • the layer comprises a material which includes one or more of: Gd, Ga, Y, Co, Fe, Ni, or O. In some embodiments, the layer comprises a material which includes one or more of: Gd x Ga y O z (Gadolinium Gallium Garnet (GGG)) Y a Fe b O c (Yttrium Iron Garnet (YIG)), TmdFe e Of (Thulium Iron Garnet (TIG)) C02O3, Fe203, Co2Fe0 4 , Ni2Fe0 4 , M doped Gd x Ga y O z , or M doped Y a Fe b O c where, x, y, z, a, b, c, d, e, and f are numbers, and where M includes one of: B, Al, Si, or Cu.
  • GGG Gadolinium Gallium Garnet
  • YIG Yttrium Iron Garnet
  • TmdFe e Of Thulium
  • the apparatus comprises a second layer (or structure) between the layer and the magnetic junction, wherein the second layer comprises one of Ta or W.
  • the second layer extends away from the magnetic junction, wherein the apparatus comprises a third layer (e.g., a coupling layer or a coupling structure) adjacent to the second layer and away from the magnetic junction, wherein the third layer comprises a metal to provide a read port or contact.
  • the metal of the third layer comprises Ta or W.
  • a magnetic state is read via the magnetic junction where the insulating magnet is dipole/exchange bias coupled to other magnetic layers, which will have high tunneling magneto-resistance (TMR) in the tunneling junction.
  • TMR tunneling magneto-resistance
  • the coupling layer is used for the reading electrode.
  • a read electrode is formed on the coupling layer.
  • the read electrode on the coupling layer is in a cross-point architecture.
  • the magnets of the magnetic junction and the insulating or semi-insulating magnet are perpendicular magnets.
  • the magnets have perpendicular magnetic anisotropy.
  • the magnets of the magnetic junction and the insulating or semi-insulating magnet are in plane magnets.
  • the magnets have in-plane anisotropy.
  • the magnets of the magnetic junction are ferromagnets.
  • the magnets of the magnetic junction are paramagnets.
  • the term“free” or“unfixed” here with reference to a magnet refers to a magnet whose magnetization direction can change along its easy axis upon application of an external field or force (e.g., Oersted field, spin torque, etc.).
  • the term“fixed” or “pinned” here with reference to a magnet refers to a magnet whose magnetization direction is pinned or fixed along an axis and which may not change due to application of an external field (e.g., electrical field, Oersted field, spin torque,).
  • perpendicularly magnetized magnet refers to a magnet having a magnetization which is substantially perpendicular to a plane of the magnet or a device.
  • an in-plane magnet refers to a magnet that has magnetization in a direction substantially along the plane of the magnet.
  • a magnet with a magnetization which is in an x or y direction and is in a range of 0 (or 180 degrees) +/- 20 degrees relative to an x-y plane of a device.
  • a device may generally refer to an apparatus according to the context of the usage of that term.
  • a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc.
  • a device is a three dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system.
  • the plane of the device may also be the plane of an apparatus which comprises the device.
  • the out-of-plane magnetization switching enables perpendicular magnet anisotropy (PMA) based magnetic devices (e.g., MRAM and logic) comprising spin orbit effects that generate perpendicular spin currents.
  • PMA perpendicular magnet anisotropy
  • MRAM magnetic random access memory
  • GSOE giant spin orbit effects
  • the perpendicular magnet switch results in lower write error rates which enable faster MRAM (e.g., write time of less than 10 ns).
  • the perpendicular magnet switch of some embodiments decouple write and read paths to enable faster read latencies.
  • the perpendicular magnet switch of some embodiments uses significantly smaller read current through the MTJ and provides improved reliability of the tunneling oxide and MTJs. For example, less than 10 mA compared to 100 mA for nominal write is used by the perpendicular magnet switch of some embodiments.
  • insulating or semi-insulating magnet layer adjacent to the spin orbit coupling interconnect and the magnetic junction allows for faster switching because the magnetization saturation (Ms) is reduced while magnetic anisotropy increases.
  • the insulating or semi insulating magnet based on garnets may reduce leakage current from spin orbit coupling electrodes and have Ms, which aids in reducing the switching energy and increasing the switching efficiency of the MRAM bit.
  • Another advantage is that the insulating or semi-insulating magnet may not have to be patterned as closely and can be used as an etch stop layer to protect the spin orbit coupling electrode. As such, the fabrication process can be relaxed and made simpler because separate processes for forming an etch stop layer may be removed. Other technical effects will be evident from the various embodiments and figures.
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • Coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of “a,” “an,” and “the” include plural references.
  • the meaning of “in” includes “in” and “on.”
  • the term“scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area.
  • the term“scaling” generally also refers to downsizing layout and devices within the same technology node.
  • the term“scaling” may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.
  • the terms “substantially,”“close,”“approximately,”“near,” and“about,” generally refer to being within +/- 10% of a target value.
  • phrases“A and/or B” and“A or B” mean (A), (B), or (A and B).
  • phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the terms“left. ‘right, ’ front,”“back,’ ‘top,”“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
  • spin spin and“magnetic moment” are used equivalently. More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron).
  • Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet (FM)
  • the plot shows magnetization response to an applied magnetic field for ferromagnet 101.
  • the x-axis of plot 100 is magnetic field ⁇ ’ while the y-axis is magnetization‘m’.
  • the relationship between ⁇ ’ and‘m’ is not linear and results in a hysteresis loop as shown by curves 102 and 103.
  • the maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively.
  • saturated magnetization configurations 104 and 106 FM 101 has stable magnetizations.
  • FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields.
  • the magnetization of FM 101 in configuration 105 can be either in the +x direction or the -x direction for an in-plane FM.
  • changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming, resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.
  • Fig. IB illustrates magnetization plot 120 for paramagnet 121.
  • Plot 120 shows the magnetization response to an applied magnetic field for paramagnet 121.
  • the x-axis of plot 120 is magnetic field ⁇ ’ while the y-axis is magnetization‘m’.
  • a paramagnet as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it.
  • Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields.
  • the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122.
  • paramagnet 121 comprises a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCL (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy 2 0 (dysprosium oxide), Erbium (Er), EnCL (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd 2 0 3 ), FeO and Fe 2 0 3 (Iron oxide), Neodymium (Nd), Nd 2 0 3 (Neodymium oxide), K0 2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), Sm 2 0 3 (samarium oxide), Terbium (Tb), Tb 2 .
  • the magnet can be either a EM or a paramagnet.
  • Fig. 2A illustrates a three-dimensional (3D) view 200 of a device (also referred to as device 200) having an out-of-plane magnetic tunnel junction (MTJ) stack directly coupled to a spin orbit coupling (SOC) interconnect.
  • Fig. 2B illustrates a top view 220 of a cross-section of the device of Fig. 2A.
  • the stack of layers having MTJ 221 is coupled to an electrode 222 formed of spin Hall effect (SHE) or SOC material, where the SHE material converts charge current Iw (or write current) to spin polarized current Is.
  • SHE spin Hall effect
  • Device 200 forms a three terminal memory cell with SHE induced write mechanism and MTJ based read-out.
  • Device 200 comprises MTJ 221, SHE Interconnect or electrode 222, and non-magnetic metal(s) 223a/b.
  • MTJ 221 comprises layers 22la, 22lb, and 22lc.
  • layers (or structures) 22la and 22lc are ferromagnetic layers.
  • layer 22 lb is a metal or a tunneling dielectric.
  • layer 22lb is metal (e.g., Al or its oxide) and when the junction is a tunneling junction, then layer 22lb is a dielectric (e.g. MgO).
  • layer 22lb is a dielectric (e.g. MgO).
  • One or both ends along the horizontal direction of SHE Interconnect 222 is formed of non-magnetic metals 223a/b. Additional layers 22ld, 22le, 22lf, and 22lg can also be stacked on top of layer 22lc. In some embodiments, layer 22lg is a non-magnetic metal electrode.
  • the stack of layers 22la, 22lb, 22lc, 22ld, 22le, 22lf, and 22lg are formed of materials which include: Co x Fe y B z , MgO, Co x Fe y B z , Ru, Co x Fe y B z , IrMn, and Ru, respectively, where‘x,’‘y,’ and‘z’ are fractions of elements in the alloys.
  • Other materials may also be used to form MTJ 221.
  • MTJ 221 stack comprises free magnetic layer 22 la,
  • MgO tunneling oxide 22lb a fixed magnetic layer 22lc/d/e which is a combination of CoFe, Ru, and CoFe layers, respectively, referred to as Synthetic Anti-Ferromagnet (SAF), and an Anti-Ferromagnet (AFM) layer 22 lf.
  • SAF Synthetic Anti-Ferromagnet
  • AFM Anti-Ferromagnet
  • magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around the free magnetic layer such that a stray dipole field will not control the free magnetic layer 22 la.
  • the free and fixed magnetic layers are formed of CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them).
  • FM 221a/c are formed from Heusler alloys.
  • Heusler alloys are ferromagnetic metal alloys based on a Heusler phase. Heusler phases are intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloys are a result of a double-exchange mechanism between neighboring magnetic ions.
  • the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, Ni 2 MnAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, Pd 2 MnAl, Pd 2 MnIn, Pd 2 MnSn, Pd 2 MnSb,
  • fixed magnet layer 22 lc is magnet with perpendicular magnetic anisotropy (PMA).
  • PMA perpendicular magnetic anisotropy
  • fixed magnet structure 22lc has a magnetization pointing along the z-direction and is perpendicular to the x-y plane of the device 200.
  • the magnet with PMA is formed of a stack of materials, wherein the materials for the stack are selected from a group consisting of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn x Ga y ; Materials with Llo symmetry; and materials with tetragonal crystal structure.
  • the magnet with PMA is formed of a single layer of one or more materials. In some embodiments, the single layer is formed of MnGa.
  • Llo is a crystallographic derivative structure of a FCC (face centered cubic lattice) structure and has two of the faces occupied by one type of atom and the comer and the other face occupied with the second type of atom.
  • the magnetization vector usually is along the [0 0 1] axis of the crystal.
  • materials with Llo symmetry include CoPt and FePt.
  • materials with tetragonal crystal structure and magnetic moment are Heusler alloys such as CoFeAl, MnGe, MnGeGa, and MnGa.
  • SHE Interconnect 222 (or the write electrode) includes 3D materials such as one or more of b-Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling.
  • 3D materials such as one or more of b-Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling.
  • SHE interconnect 222 comprises a spin orbit 2D material which includes one or more of: graphene, BiSe 2 , B1S2, RiSeG ' e 2 T1S2, WS 2 , M0S2, TiSe2, WSe 2 , MoSe2, B2S3, Sb 2 S 3 , Ta 2 S, Re 2 S 7 , LaCPS 2 , LaOAsS 2 , ScOBiS 2 , GaOBiS 2 , AIOB1S2, LaOSbS 2 , BiOBiS 2 , YOB1S2, InOBiS 2 , LaOBiSe 2 , TiOBiS 2 , CeOBiS 2 , PrOBiS 2 , NdOBiS 2 , LaOBiS 2 , or SrFBiS 2 .
  • a spin orbit 2D material which includes one or more of: graphene, BiSe 2 , B1S2, RiSeG ' e 2 T1S2, WS 2 , M0
  • the SHE interconnect 222 comprises spin orbit material which includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material. In some embodiments, the SHE interconnect 222 comprises a spin orbit material which includes materials that exhibit Rashba-Bychkov effect.
  • SHE Interconnect 222 transitions into high conductivity non-magnetic metal(s) 223a/b to reduce the resistance of SHE Interconnect 222.
  • the non-magnetic metal(s) 223a/b include one or more of: Cu, Co, a-Ta, Al, CuSi, or NiSi.
  • the magnetization direction of fixed magnetic layer 22 lc is perpendicular relative to the magnetization direction of free magnetic layer 22 la (e.g., magnetization directions of the free and fixed magnetic layers are not parallel, rather they are orthogonal).
  • magnetization direction of free magnetic layer 22 la is along the x-y plane of device 200 while the magnetization direction of fixed magnetic layer 22 lc is perpendicular to the plane of the device.
  • magnetization direction of fixed magnetic layer 22 la is the plane of the device, while the magnetization direction of free magnetic layer 22 lc is perpendicular to the plane of the device.
  • the thickness of a ferromagnetic layer may determine its equilibrium magnetization direction. For example, when the thickness of the ferromagnetic layer 22la/c is above a certain threshold (depending on the material of the magnet, e.g. approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane. Likewise, when the thickness of the ferromagnetic layer 22la/c is below a certain threshold (depending on the material of the magnet), then the ferromagnetic layer 22la/c exhibits magnetization direction which is perpendicular to the plane of the magnetic layer. [0060] Other factors may also determine the direction of magnetization.
  • factors such as surface anisotropy (depending on the adjacent layers or a multi-layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic lattice), BCC (body centered cubic lattice), or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.
  • FCC face centered cubic lattice
  • BCC body centered cubic lattice
  • Llo-type of crystals where Llo is a type of crystal class which exhibits perpendicular magnetizations
  • the applied current / is converted into spin current I s by SHE
  • the magnetic cell is written by applying a charge current via SHE
  • the direction of the magnetic writing in free magnet layer 22 la is decided by the direction of the applied charge current.
  • Positive currents e.g., currents flowing in the -i-y direction
  • the injected spin current in turn produces spin torque to align the free magnet 22 la (coupled to the SHE layer 222 of SHE material) in the +X direction.
  • Negative currents e.g., currents flowing in the -y direction
  • the injected spin current in-tum produces spin torque to align the free magnet 22la (coupled to the SHE material of layer 222) in the -x direction.
  • the directions of spin polarization and thus of the free layer magnetization alignment are reversed compared to the above.
  • Fig. 3 illustrates a cross-section 300 of the spin orbit coupling interconnect
  • the vector of spin current I s I f — / j, points in the direction of transferred magnetic moment and has the magnitude of the difference of currents with spin along and opposite to the spin polarization direction
  • z is the unit vector perpendicular to the interface
  • P SHE is the spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current
  • w is the width of the magnet
  • t is the thickness of the SHE
  • S f is the spin flip length in SHE Interconnect 222
  • 6 SHE i s the spin Hall angle for SHE Interconnect 222 to free ferromagnetic layer interface.
  • the injected spin angular momentum responsible for the spin torque given by:
  • the generated spin up and down currents 301/302 (e.g., ] s ) are described as a vector cross-product given by:
  • Is Q SHE (J C X z ) . . . (3)
  • This spin to charge conversion is based on Tunnel Magneto Resistance (TMR) which is highly limited in the signal strength generated.
  • TMR Tunnel Magneto Resistance
  • the TMR based spin to charge conversion has low efficiency (e.g., less than one).
  • perpendicularly magnetized free magnet refers to a magnet having magnetization which is perpendicular to the plane of the magnet as opposed to in-plane magnet that has magnetization in a direction along the plane of the magnet.
  • Fig. 4A illustrates a plot 420 showing write energy-delay conditions for one transistor and one magnetic tunnel junction (MTJ) with spin Hall effect (SHE) material compared to traditional MTJs.
  • x-axis is energy per write operation in femto-Joules (fj) while the y-axis is delay in nanoseconds (ns).
  • the energy-delay trajectory of SHE and MTJ devices are compared for in-plane magnet switching as the applied write voltage is varied.
  • the energy-delay relationship (for in-plane switching) can be written as:
  • R wr ue is the write resistance of the device (resistance of SHE electrode or resistance of MTJ-P or MTJ-AP, where MTJ-P is a MTJ with parallel magnetizations while MTJ-AP is an MTJ with anti-parallel magnetizations, m 0 is vacuum permeability, e is the electron charge.
  • the equation shows that the energy at a given delay is directly proportional to the square of M Ve
  • Plot 420 shows five curves 421, 422, 423, 424, and 425.
  • Curves 421 and 422 show write energy-delay conditions using traditional MTJ devices without SHE material.
  • curve 421 shows the write energy-delay condition caused by switching a magnet from anti-parallel (AP) to parallel (P) state
  • curve 422 shows the write energy-delay condition caused by switching a magnet from P to AP state
  • Curves 422, 423, and 424 show write energy-delay conditions of an MTJ with SHE material.
  • write energy-delay conditions of an MTJ with SHE material is much lower than write energy- delay conditions of an MTJ without SHE material. While write energy-delay of an MTJ with SHE material improves over a traditional MTJ without SHE material, further improvement in write energy-delay is desired.
  • Fig. 4B illustrates a plot 430 comparing reliable write times for spin Hall
  • Waveform 431 is the write time for in-plane MTJ
  • waveform 432 is the write time for PMA MTJ
  • waveform 434 is the write time for spin Hall MTJ. All the cases considered in Fig. 4B assume a 30 X 60 nm magnet with 40 kT energy barrier and 3.5 nm SHE electrode thicknesses.
  • the energy-delay trajectories of the devices are obtained assuming a voltage sweep from 0 V to 0.7 V in accordance to voltage restrictions of scaled CMOS.
  • the energy- delay trajectory of the SHE-MTJ devices exhibits broadly two operating regions A) Region 1 where the energy-delay product is approximately constant ), an d
  • the energy-delay trajectory of the STT-MTJ (spin transfer torque MTJ) devices is limited with a minimum delay of 1 ns for in-plane devices at 0.7 V maximum applied voltage, the switching energy for P-AP and AP-P are in the range of 1 pj/write.
  • the energy-delay trajectory of SHE-MTJ (in-plane anisotropy) devices can enable switching times as low as 20 ps (b-W with 0.7 V, 20 fj/bit) or switching energy as small as 2 fj (b-W with 0.1 V, 1.5 ns switching time).
  • Fig. 5A illustrates a 3D view 500 of a device having an MTJ with magnets having perpendicular magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, according to some embodiments of the disclosure.
  • the device comprises a perpendicular insulating or semi-insulating magnet 501, coupling metal or interconnect 502, and read port 503, in addition to the layers discussed with reference to Fig. 2 A.
  • perpendicular insulating or semi-insulating magnet 501 is in contact with a Spin orbit torque (SOT) electrode 222.
  • SOT Spin orbit torque
  • a magnetic state is read via the MTJ where the perpendicular insulating or semi-insulating magnet 501 is dipole/exchange bias coupled to other magnetic layers or structures (e.g., layer 22la), which will have high TMR in the tunneling junction.
  • the coupling layer 502 is usually a conductive metal which is used for the reading electrode 503.
  • the perpendicular insulating or semi- insulating magnet 501 reduces leakage current from SOC electrode 122 and have low Ms, which aids in reducing the switching energy and increasing the switching efficiency of an MRAM bit. Another advantage is that the perpendicular insulating or semi-insulating magnet 501 may not have to be pattered as closely and can be used a etch stop layer to protect SOC electrode 122.
  • the perpendicular insulating or semi-insulating magnet 501 comprises a material which includes one or more of: Gd, Ga, Y, Co, Fe, Ni, or O.
  • the perpendicular insulating or semi-insulating magnet 501 comprises a material which includes one or more of: Gd x Ga y O z , Y a Fe b O c , Tm d Fe e O f , C02O3, Fe ⁇ Os, Co 2 Fe0 4 , Ni 2 Fe0 4 , M doped Gd x Ga y O z , or M doped Y a Fe b O c where, x, y, z, a, b, c, d, e, and f are numbers, and where M includes one of: B, Al, Si, or Cu.
  • the coupling layer 502 between the perpendicular insulating or semi-insulating magnet 501 and the free magnet layer 22 la of the magnetic junction wherein the coupling layer comprises one of Ru, Ir, Al, Cu, Ag, or Ta.
  • the perpendicular insulating or semi-insulating magnet 501 has a thickness tl in a range of 1 nm to 6 nm.
  • the SOC interconnect or electrode 222 has a thickness in a range of 1 nm to 6 nm.
  • Fig. 5B illustrates a top view 520 of the device of Fig. 5A along cross-section AA’, in accordance with some embodiments of the disclosure.
  • Fig. 6A illustrates a 3D view 600 of a device having an MTJ with magnets having in-plane magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, according to some embodiments of the disclosure.
  • the device of Fig. 6A is similar to device of Fig. 5A but for using in-plane magnets for fixed magnet 62lc, free magnet 62la, and insulating or semi-insulating magnet 601.
  • the technical effect of the insulating or semi-insulating magnet 601 is same as the technical effect of the perpendicular insulating or semi-insulating magnet 501, in accordance with various embodiments.
  • the perpendicular insulating or semi- insulating magnet 601 has a thickness tl in a range of 1 nm to 6 nm.
  • Fig. 6B illustrates a top view 620 of the device of Fig. 6A along cross-section AA’ in accordance with some embodiments of the disclosure.
  • Fig. 7A illustrates a 3D view 700 of a cross-point device having an MTJ with magnets having perpendicular magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, and wherein a read port is positioned for a cross-point architecture, according to some embodiments of the disclosure.
  • the coupling layer 502 is replaced with coupling layer 702 which has the same material choice as those described with reference to coupling layer 502.
  • coupling layer 702 extends orthogonal to the direction of insulating or semi-insulating magnet 501.
  • a read port 703 is formed on top or below, but coupled to, coupling layer 702. This configuration allows for cross- point architecture of memory cells comprising MTJs.
  • the overall technical effect and operation of the device of Fig. 7A is the same as that of Fig. 5A.
  • Fig. 7B illustrates a top view 720 of the device of Fig. 7A along cross-section AA’ in accordance with some embodiments of the disclosure.
  • Fig. 8A illustrates a 3D view 800 of a cross-point device having an MTJ with magnets having in-plane magnetizations, wherein an insulating or semi-insulating magnet is positioned between the MTJ and the SOC interconnect, and wherein a read port is positioned for a cross-point architecture, according to some embodiments of the disclosure.
  • the device of Fig. 8A is similar to device of Fig. 7A but for using in-plane magnets for fixed magnet 62lc, free magnet 62la, and insulating or semi-insulating magnet 601.
  • the technical effect of the insulating or semi-insulating magnet 601 is same as the technical effect of the perpendicular insulating or semi-insulating magnet 501, in accordance with various embodiments.
  • the perpendicular insulating or semi-insulating magnet 801 has a thickness tl in a range of 1 nm to 6 nm.
  • Fig. 8B illustrates a top view 820 of the device of Fig. 8A along cross-section AA’ in accordance with some embodiments of the disclosure.
  • Fig. 9A illustrates a plot 900 showing spin polarization capturing switching of magnet 22 la, according to some embodiments of the disclosure.
  • Fig. 9B illustrates a magnetization plot 920 associated with Fig. 9A, according to some embodiments of the disclosure.
  • Plot 900 shows switching of spin orbit torque device with PMA.
  • waveforms 901, 902, and 902 represent the magnetization projections on axes x, y, and z, respectively.
  • the magnet starts with z-magnetization of -1.
  • Positive spin orbit torque (SOT) is applied from 5 ns (nanoseconds) to 50 ns. It leads to switching z-magnetization to 1.
  • negative spin orbit torque is applied between 120 ns and 160 ns. It leads to switching z- magnetization to 1. This illustrates change of magnetization in response to write charge current of certain polarity.
  • Fig. 9C illustrates a plot 930 showing spin polarization capturing switching of magnet 22 la using traditional spin orbit material, according to some embodiments of the disclosure.
  • Fig. 9D illustrates a magnetization plot 940 associated with Fig. 9C, according to some embodiments of the disclosure.
  • waveforms 931, 932, and 932 represent the magnetization projections on axes x, y, and z, respectively.
  • SOT negative spin orbit torque
  • z-magnetization remains close to -1. This illustrates the persistence of magnetization in response to write charge current of opposite polarity.
  • Fig. 10 illustrates a cross-section 1000 of a die layout having the device of
  • Cross-section 1000 illustrates an active region having a transistor MN comprising diffusion region 1001, a gate terminal 1002, drain terminal 1004, and source terminal 1003.
  • the source terminal 1003 is coupled to SL (source line) via poly or via, where the SL is formed on Metal 0 (M0).
  • the drain terminal 1004 is coupled to MOa (also metal 0) through via 1005.
  • the drain terminal 1004 is coupled to spin Hall angle electrode 122 through Via 0-1 (e.g., via connecting metal 0 to metal 1 layers), metal 1 (Ml), Via 1-2 (e.g., via connecting metal 1 to metal 2 layers), and Metal 2 (M2).
  • the magnetic junction (e.g., MTJ 1021 or spin valve) is formed in the metal 3 (M3) region.
  • MTJ 1021 (or spin valve) can be according to any one of MTJs described with reference to Figs. 5-8.
  • the perpendicular free magnet layer of the magnetic junction couples to spin Hall electrode 222/1022 via insulating or semi-insulating magnet 1023 (same as one of magnets 501 or 601).
  • the fixed magnet layer of magnetic junction couples to the bit-line (BL) via spin Hall electrode 222 with through Via 3- 4 (e.g., via connecting metal 4 region to metal 4 (M4)).
  • bit- line is formed on M4.
  • n-type transistor MN is formed in the frontend of the die while the spin Hall electrode 222/1022 and the insulating or semi-insulating magnet 1023 are located in the backend of the die.
  • the term“backend” generally refers to a section of a die which is opposite of a“frontend” and where an IC (integrated circuit) package couples to IC die bumps.
  • high level metal layers e.g., metal layer 6 and above in a ten metal stack die
  • vias that are closer to a die package are considered part of the backend of the die.
  • the term“frontend” generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten metal stack die example).
  • the spin Hall electrode 222 and the fixed magnet 1023 are located in the backend metal layers or via layers for example in Via 3.
  • the electrical connectivity to the device is obtained in layers M0 and M4 or Ml and M5 or any set of two parallel interconnects.
  • Fig. 11 illustrates a cross-section 1100 of a die layout having the device of
  • Fig. 5A formed in metal 2 (M2) and metal 1 (Ml) layer regions, according to some embodiments of the disclosure.
  • the magnetic junction e.g., MTJ 1021 or spin valve
  • the spin Hall electrode 222/1022 and the additional insulating or semi- insulating magnet 1023 is formed is in the metal 1 region.
  • Fig. 12 illustrates a plot 1200 showing improvement in energy-delay product using the device of Fig. 5A compared to the device of Fig. 2A, in accordance with some embodiments of the disclosure.
  • x-axis is Write Energy (in fj) and y-axis is Delay (in ns).
  • two of the energy-delay trajectories are compared as write voltage is varied— 1201 which is the energy-delay trajectory of device 200 and 1202 is the energy delay trajectory of device 500.
  • Plot 1200 illustrates that device(s) 500/520/600/620 provides a shorter (i.e., improved) energy-delay product than device 200.
  • Fig. 13 illustrates a flowchart 1300 of a method of forming any one of devices of Figs. 5-8, according to some embodiments of the disclosure. While the blocks (or operations) are illustrated in a certain order, the order can be modified. For example, some blocks can be performed before others, and some blocks can be performed together (e.g., simultaneously).
  • a first structure is formed comprising a magnet with unfixed perpendicular magnetic anisotropy (PMA), wherein the first structure has an anisotropy axis perpendicular to a plane of a device.
  • a second structure is formed comprising one of a dielectric or metal, the second structure being adjacent to the first structure.
  • a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures.
  • the first, second, and third structures form a magnetic junction.
  • a fourth structure comprising an insulating or semi- insulating magnet, the fourth structure being adjacent to the magnet junction.
  • an interconnect is formed adjacent to the fourth structure.
  • the method of forming the interconnect comprises forming a material exhibiting spin orbit coupling.
  • the method of forming the fourth structure comprises forming a material which includes one or more of: Gd, Ga, Y, Co, Fe, Ni, or O.
  • the method of forming the fourth structure comprises forming a material which includes one or more of: Gd, Ga, O, U, Fe, Tm, Co, Ni, M, B, Al, Si, or Cu.
  • the method comprises forming a fifth structure between the fourth structure and the first structure of the magnetic junction, wherein the fifth structure comprises one of Ta or W. In some embodiments, the fifth structure away from the magnetic junction, wherein the method comprises forming a sixth structure is extended and is adjacent to the fifth structure and away from the magnetic junction, wherein the sixth structure comprises a metal to provide a read port or contact.
  • the metal of the sixth structure comprises Ta or W.
  • the fourth structure has a thickness in a range of 1 nm to 6 nm, and wherein the interconnect has a thickness in a range of 1 nm to 6 nm.
  • the dielectric comprises: Mg and O, and wherein the metal of the second structure includes Al.
  • the magnets of the first and third structures comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, or Ge.
  • the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, or Ge.
  • the interconnect generates spin Hall effect (SHE).
  • the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups.
  • the interconnect comprises spin orbit material which includes one or more of: graphene, Ti, S, W, Mo, Se, B, Sb, Ta, Re, La, C, P, La, As, Sc, Bi, O, Ga, A1, Y, In, Pr, Ce, Nd, Sr, or F.
  • the interconnect comprises spin orbit material includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material.
  • the interconnect comprises spin orbit material which includes materials that exhibit Rashba-Bychkov effect.
  • the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).
  • the magnet of the third structure is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, O, Dy, Er, Eu, Gd, Fe, Nd,
  • the magnet of the third structure is a paramagnet which comprises dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.
  • Fig. 14 illustrates a smart device or a computer system or a SoC (System-on-
  • Chip with a magnetic junction coupled to insulating or semi-insulating magnet for faster switching, according to some embodiments of the disclosure.
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals.
  • the transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device on the other hand, has asymmetric Source and Drain terminals.
  • BJT PNP/NPN Bi-polar junction transistors
  • BiCMOS BiCMOS
  • CMOS complementary metal oxide semiconductor
  • Fig. 14 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used.
  • computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.
  • computing device 1600 includes first processor 1610 with one or more devices according to any one of devices of Figs. 5-8, according to some embodiments discussed.
  • Other blocks of the computing device 1600 may also include one or more devices according to any one of devices of Figs. 5-8, according to some embodiments.
  • the various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 1610 can include one or more physical devices, such as microprocessors, application processors,
  • microcontrollers programmable logic devices, or other processing means.
  • the processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 1600 includes audio subsystem
  • Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.
  • computing device 1600 comprises display subsystem
  • Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600.
  • Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display.
  • display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • computing device 1600 comprises I/O controller 1640.
  • I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1640 can interact with audio subsystem
  • display subsystem 1630 For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.
  • I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation.
  • Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.
  • Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein).
  • the machine-readable medium e.g., memory 1660
  • embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • BIOS a computer program
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • computing device 1600 comprises connectivity 1670.
  • Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices.
  • the computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1670 can include multiple different types of connectivity.
  • the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674.
  • Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • computing device 1600 comprises peripheral connections 1680.
  • Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections.
  • the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from” 1684) connected to it.
  • the computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600.
  • a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.
  • the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • Example 1 An apparatus comprising: a magnetic junction including: a first structure comprising a magnet with unfixed perpendicular magnetic anisotropy (PMA) relative to a plane of a device; a second structure comprising one of a dielectric or metal, the second structure being adjacent to the first structure; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an insulative or semi-insulative magnet, the fourth structure being adjacent to the magnet junction; and an interconnect adjacent to the fourth structure.
  • PMA perpendicular magnetic anisotropy
  • Example 2 The apparatus of example 1, wherein the interconnect comprises a material exhibiting spin orbit coupling.
  • Example 3 The apparatus according to any one of preceding examples, wherein the fourth structure comprises a material which includes one or more of: Gd, Ga, Y, Co, Fe, Ni, or O.
  • Example 4 The apparatus of example 1, wherein the fourth structure comprises a material which includes one or more of: Gd, Ga, O, U, Fe, Tm, Co, Ni, M, B, Al, Si, or Cu.
  • Example 5 The apparatus of example 1 comprises a fifth structure between the fourth structure and the first structure of the magnetic junction, wherein the fifth structure comprises one of Ta or W.
  • Example 6 The apparatus of example 5, wherein the fifth structure extends away from the magnetic junction, wherein the apparatus comprises a sixth structure adjacent to the fifth structure and away from the magnetic junction, and wherein the sixth structure comprises a metal to provide a read port or contact.
  • Example 7 The apparatus of example 6, wherein the metal of the sixth structure comprises Ta or W.
  • Example 8 The apparatus of example 1, wherein the fourth structure has a thickness in a range of 1 nm to 6 nm, and wherein the interconnect has a thickness in a range of 1 nm to 6 nm.
  • Example 9 The apparatus according to any one of preceding examples, wherein the dielectric comprises: Mg and O, and wherein the metal of the second structure includes Al.
  • Example 10 The apparatus according to any one of examples 1 to 3, wherein the magnets of the first and third structures comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, or Ge.
  • a Heusler alloy Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG)
  • YIG Yttrium Iron Garnet
  • Example 11 The apparatus according to any one of preceding examples, wherein the interconnect is to generate spin Hall effect (SHE).
  • SHE spin Hall effect
  • Example 12 The apparatus according to any one of preceding examples, wherein the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups, graphene, Se, Te, W, Ti, Mo, Sb, S, Re, La, C, P, La, O, As, Ga, Al, Y, In, Ce, Pr, Nd, Sr, or F.
  • b-Tantalum b-Ta
  • Ta b-Tungsten
  • W Platinum
  • Pt Platinum
  • Cu Copper
  • Example 13 The apparatus of example 1, wherein the interconnect comprises spin orbit material which includes one or more of: graphene, Ti, S, W, Mo, Se, B, Sb, Ta, Re, La, C, P, La, As, Sc, Bi, O, Ga, Al, Y, In, Pr, Ce, Nd, Sr, or F.
  • spin orbit material which includes one or more of: graphene, Ti, S, W, Mo, Se, B, Sb, Ta, Re, La, C, P, La, As, Sc, Bi, O, Ga, Al, Y, In, Pr, Ce, Nd, Sr, or F.
  • Example 14 The apparatus of example 1, wherein the interconnect comprises spin orbit material includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material.
  • Example 15 The apparatus of example 1, wherein the interconnect comprises spin orbit material which includes materials that exhibit Rashba-Bychkov effect.
  • Example 16 The apparatus according to any one of preceding examples, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).
  • the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).
  • Example 17 The apparatus of example 1, wherein the magnet of the third structure is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, O, Dy, Er, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V. [00128]
  • Example 18 The apparatus of example 1, wherein the magnet of the third structure is a paramagnet which comprises dopants which include one or more of: Ce, Cr,
  • Example 19 A system comprising: a memory; a processor coupled to the memory, the processor having a spin wave switch, which comprises an apparatus according to any one of apparatus examples 1 to 18; and a wireless interface to allow the processor to communicate with another device.
  • Example 20 An apparatus comprising: a magnetic junction having a structure comprising an unpinned magnet; a structure comprising an insulative or semi-insulative magnet, the structure being adjacent to the magnet junction; and an interconnect adjacent to the structure.
  • Example 21 The apparatus of example 20, wherein the structure comprises a material which includes one or more of: Gd, Ga, Y, Co, Fe, Ni, or O.
  • Example 22 The apparatus of example 20, wherein the structure comprises a material which includes one or more of: Gd, Ga, O, U, Fe, Tm, Co, Ni, M, B, Al, Si, or Cu.
  • Example 23 The apparatus of example 20 comprises a second structure between the structure and the magnetic junction, wherein the second structure comprises one of Ta or W.
  • Example 24 The apparatus of example 23, wherein the second structure extends away from the magnetic junction, wherein the apparatus comprises a third structure adjacent to the second structure and away from the magnetic junction, and wherein the third structure comprises a metal to provide a read port or contact.
  • Example 25 The apparatus of example 24, wherein the metal of the third structure comprises Ta or W.
  • Example 26 A system comprising: a memory; a processor coupled to the memory, the processor having a spin wave switch, which comprises an apparatus according to any one of apparatus examples 20 to 25; and a wireless interface to allow the processor to communicate with another device.
  • Example 27 A method comprising: forming a magnetic junction including: forming a first structure comprising a magnet with unfixed perpendicular magnetic anisotropy (PMA), wherein the first structure has an anisotropy axis perpendicular to a plane of a device; forming a second structure comprising one of a dielectric or metal, the second structure being adjacent to the first structure; and forming a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; forming a fourth structure comprising an insulative or semi-insulative magnet, the fourth structure being adjacent to the magnet junction; and forming an interconnect adjacent to the fourth structure.
  • PMA perpendicular magnetic anisotropy
  • Example 28 The method of example 27, wherein forming the interconnect comprises forming a material exhibiting spin orbit coupling.
  • Example 29 The method of examples 27 or 28, wherein forming the fourth structure comprises forming a material which includes one or more of: Gd, Ga, Y, Co, Fe, Ni, or O.
  • Example 30 The method of examples 27 or 28, wherein forming the fourth structure comprises forming a material which includes one or more of: Gd, Ga, O, U, Fe, Tm, Co, Ni, M, B, Al, Si, or Cu.
  • Example 31 The method of examples 27 or 28 comprises forming a fifth structure between the fourth structure and the first structure of the magnetic junction, and wherein the fifth structure comprises one of Ta or W.
  • Example 32 The method of example 31 comprises extending the fifth structure away from the magnetic junction, wherein the method comprises forming a sixth structure adjacent to the fifth structure and away from the magnetic junction, and wherein the sixth structure comprises a metal to provide a read port or contact.
  • Example 33 The method of example 32, wherein the metal of the sixth structure comprises Ta or W.
  • Example 34 The method of examples 27 or 28, wherein the fourth structure has a thickness in a range of 1 nm to 6 nm, and wherein the interconnect has a thickness in a range of 1 nm to 6 nm.
  • Example 35 The method of examples 27 or 28, wherein the dielectric comprises: Mg and O, and wherein the metal of the second structure includes Al.
  • Example 36 The method of examples 27 or 28, wherein the magnets of the first and third structures comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn,
  • Example 37 The method of example 27 comprises generating spin Hall effect (SHE) by the interconnect.
  • Example 38 The method according to any one of preceding method examples, wherein the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b- Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups.
  • the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b- Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups.
  • Example 39 The method of example 27, wherein the interconnect comprises spin orbit material which includes one or more of: graphene, Ti, S, W, Mo, Se, B, Sb, Ta, Re, La, C, P, La, As, Sc, Bi, O, Ga, Al, Y, In, Pr, Ce, Nd, Sr, or F.
  • spin orbit material which includes one or more of: graphene, Ti, S, W, Mo, Se, B, Sb, Ta, Re, La, C, P, La, As, Sc, Bi, O, Ga, Al, Y, In, Pr, Ce, Nd, Sr, or F.
  • Example 40 The method of example 27, wherein the interconnect comprises spin orbit material includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material.
  • Example 41 The method of example 27, wherein the interconnect comprises spin orbit material which includes materials that exhibit Rashba-Bychkov effect.
  • Example 42 The method according to any one of preceding method examples, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).
  • the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).
  • Example 43 The method of example 27, wherein the magnet of the third structure is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, O, Dy, Er, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V.
  • Example 44 The method of example 27, wherein the magnet of the third structure is a paramagnet which comprises dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention concerne un appareil comprenant : une jonction magnétique comportant une structure comprenant un aimant non fixé ; une structure comprenant un aimant isolant ou semi-isolant, la structure étant adjacente à la jonction magnétique ; et une interconnexion adjacente à la structure.
PCT/US2017/067087 2017-12-18 2017-12-18 Mémoire basée sur un couplage spin-orbite avec aimant isolant Ceased WO2019125384A1 (fr)

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CN113838967A (zh) * 2021-08-30 2021-12-24 电子科技大学 一种合金/磁绝缘体自旋异质结及其制备方法和应用
TWI818402B (zh) * 2021-01-04 2023-10-11 台灣積體電路製造股份有限公司 記憶體元件及其製造方法

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