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WO2019114834A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2019114834A1
WO2019114834A1 PCT/CN2018/121313 CN2018121313W WO2019114834A1 WO 2019114834 A1 WO2019114834 A1 WO 2019114834A1 CN 2018121313 W CN2018121313 W CN 2018121313W WO 2019114834 A1 WO2019114834 A1 WO 2019114834A1
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Prior art keywords
pattern
insulating layer
gate
region
metal pattern
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French (fr)
Inventor
李海旭
汪建国
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority claimed from CN201711345541.8A external-priority patent/CN107910302A/zh
Priority claimed from CN201821680371.9U external-priority patent/CN208848909U/zh
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/621,773 priority Critical patent/US11177293B2/en
Publication of WO2019114834A1 publication Critical patent/WO2019114834A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same, and a display device including the array substrate.
  • AMOLED (Active Matrix Organic Light Emitting Diode) technology is the development trend of Mobile products.
  • a TFT Thin Film Transistor
  • Ioff leakage current
  • a TFT using an oxide semiconductor can reduce leakage current.
  • the mobility of carriers of the oxide semiconductor is small, it is sometimes difficult to form a driving circuit built in the display device by using a TFT using an oxide semiconductor.
  • the LTPS Low Temperature Poly-Si
  • LTPO LTPS+Oxide, a combination of low-temperature polysilicon and oxide semiconductor
  • Oxide TFT has certain advantages in sensor application of LTPS+Oxide technology because of its low leakage current. Therefore, the development of the LTPO process has high value and significance.
  • the present disclosure provides a method of fabricating an array substrate capable of effectively preventing the oxide semiconductor layer from being corroded by hydrofluoric acid at least in the case of process complexity.
  • a method of fabricating an array substrate including a substrate, the substrate including a first region and a second region, and the manufacturing method includes:
  • the first source and the first drain are respectively connected to the first semiconductor pattern through the first via, and the second source and the second drain respectively pass through the first Two via holes are connected to the second semiconductor pattern.
  • the first gate pattern is disposed in the same layer as the second gate pattern, and wherein the second insulating layer covers the first gate pattern and the second gate pattern .
  • the manufacturing method further includes forming a first gate insulating layer on the second semiconductor pattern, wherein the second gate pattern is on the first gate insulating layer, and wherein The third insulating layer covers the second semiconductor pattern, the first metal pattern, the second metal pattern, and the third metal pattern, the first gate insulating layer, and the second gate pattern.
  • an array substrate comprising:
  • the substrate including a first region and a second region
  • first gate pattern and a second gate pattern isolated from each other, respectively disposed in the first region and the second region;
  • a second metal pattern and a third metal pattern are located in the second region and are respectively overlapped with the second semiconductor pattern
  • a third insulating layer covering at least the second semiconductor pattern, the first metal pattern, the second metal pattern, and the third metal pattern
  • the first source and the first drain are respectively connected to the first semiconductor pattern through the first via, and the second source and the second drain respectively pass through the first Two via holes are connected to the second semiconductor pattern.
  • the first gate pattern is disposed in the same layer as the second gate pattern, and wherein the second insulating layer covers the first gate pattern and the second gate Polar pattern.
  • the array substrate further includes a first gate insulating layer on the second semiconductor pattern, wherein the second gate pattern is on the first gate insulating layer, and wherein The third insulating layer covers the second semiconductor pattern, the first metal pattern, the second metal pattern, and the third metal pattern, the first gate insulating layer, and the second gate pattern.
  • a display device including the above array substrate.
  • FIG. 1 is a process flow diagram of a method of fabricating an array substrate of the present disclosure
  • FIG. 2 to FIG. 5 are schematic cross-sectional views showing the steps of the method for fabricating the array substrate of the present disclosure
  • FIG. 6 is a schematic view showing an array substrate in the prior art
  • Figure 7 is a schematic view showing a specific embodiment of the array substrate of the present disclosure.
  • FIG. 8 is a flow chart showing a method of fabricating a specific embodiment of the array substrate of the present disclosure
  • 9-18 are schematic cross-sectional views showing the fabrication process of the array substrate of the present disclosure.
  • first region and the second region mentioned in the present disclosure are not limited to only the substrate itself, but may also include a range of regions in the vertical direction thereof.
  • a method for fabricating an array substrate of the present disclosure includes:
  • Step S101 The array substrate includes a substrate, the substrate includes a first region and a second region, and the first semiconductor pattern is formed in the first region;
  • Step S102 forming a first insulating layer covering at least the first semiconductor pattern
  • Step S103 forming a first gate pattern and a second gate pattern isolated from each other in the first region and the second region, respectively, by a film forming process;
  • Step S104 forming a second insulating layer covering the first gate pattern and the second gate pattern
  • Step S105 forming a second semiconductor pattern in the second region
  • Step S106 forming a first metal pattern in the first region and forming a second metal pattern and a third metal pattern respectively overlapping the second semiconductor pattern in the second region by a film forming process;
  • Step S107 forming a third insulating layer covering the second semiconductor pattern, the first metal pattern, the second metal pattern, and the third metal pattern;
  • Step S108 forming a first via hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer in the first region, and forming a second via hole penetrating the third insulating layer in the second region;
  • Step S109 forming a first source and a first drain, a second source, and a second drain, wherein the first source and the first drain are respectively connected to the first semiconductor pattern through the first via, and the second The source and the second drain are respectively connected to the second semiconductor pattern through the second via.
  • the array substrate includes a substrate S.
  • the material of the substrate S may be quartz glass, alkali-free glass, and silicon wafer, polyimide or plastic.
  • the substrate S has a plurality of first regions 100 and a plurality of second regions 200 (only one of which is shown in the drawing) to respectively form different types of TFTs in the two regions, for example, an oxide semiconductor TFT as a pixel in the display region
  • the switching element, and the LTPS TFT serves as the driving element of the driving circuit.
  • the first patterning process forms a first semiconductor pattern 101 in the first region 100 of the substrate S.
  • the first semiconductor pattern 101 is an active layer of the TFT corresponding to the first region 100, and the material thereof may be polysilicon.
  • the corresponding TFT is an LTPS TFT.
  • the light shielding pattern and the insulating layer may be formed before the first semiconductor pattern 101 of the first region 100 of the substrate S is formed.
  • the light-shielding pattern may utilize amorphous silicon or a dark resin or a metal material to prevent light incident from the substrate side from affecting the operational characteristics of the semiconductor device.
  • the formation of the first semiconductor pattern 101 may include the steps of forming amorphous silicon (a-Si) in the first region 100 of the substrate S, and then irradiating the amorphous silicon with an excimer laser to convert the amorphous silicon into polycrystalline silicon.
  • a-Si amorphous silicon
  • a stack of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer may be formed on the substrate S, thereby preventing impurities contained in the substrate S from contaminating the first semiconductor. Pattern 101.
  • the first insulating layer 110 is formed thereon.
  • the first insulating layer 110 covers at least the first semiconductor pattern 101, and may further cover the first region 100, and may further cover the second region 200.
  • the material of the first insulating layer 110 may be a silicon oxide (SiOx) layer, which may be formed by a CVD (Chemical Vapor Deposition) method using TEOS (tetraethoxysilane) as a raw material, and the CVD method may be, for example, a low pressure chemical vapor deposition method. Thermal vapor deposition, catalytic chemical vapor deposition, plasma enhanced chemical vapor deposition, and the like.
  • the first gate pattern 111 and the second gate pattern 112 are formed in the first region 100 and the second region 200 by the same mask and the same material by one film forming process
  • the patterns 112 are isolated from each other.
  • the first gate pattern 111 and the second gate pattern 112 are formed of an Al alloy, Cr, Mo, W, or a laminated film of the above, and serve as gate electrodes of the TFTs in the two regions, respectively.
  • the first gate pattern 111 and the second gate pattern 112 may be formed by plating, including but not limited to vacuum evaporation, magnetron sputtering, ion sputtering, and the like.
  • the first gate pattern 111 is formed on the first insulating layer 110 and directly above the first semiconductor pattern 101. If the first insulating layer 110 also covers the second region 200, the second gate pattern 112 may be formed on the first insulating layer 110. If the first insulating layer 110 covers only the first region 100, the second gate pattern 112 It may be formed directly on the second region 200 of the substrate S.
  • the second insulating layer 120 is formed thereon.
  • the second insulating layer 120 completely covers the first gate pattern 111 and the second gate pattern 112 while also covering the first insulating layer 110 and the substrate S.
  • the material of the second insulating layer 120 is a laminate of a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer is located below and the silicon oxide layer is located above so that the silicon oxide layer and the oxide layer The semiconductor layer is in contact.
  • the raw material and formation method of the silicon oxide layer can be the same as above.
  • the source gas for forming the silicon nitride layer as the nitrogen source gas, NH3, NH2H2N, N2 or the like can be used, and NH3 and N2 are preferable.
  • the silicon source gas SiH4, Si2H6, SiCl4, SiHCl3, SiH2Cl2, SiH3Cl3, or the like can be used.
  • SiF4 or the like is preferably SiH4.
  • the silicon nitride layer can also be formed by a chemical vapor deposition method (CVD).
  • the surface of the polysilicon semiconductor pattern exposed through the via hole needs to be subjected to hydrofluoric acid cleaning, and after the hydrofluoric acid cleaning. It is necessary to make the source/drain within less than half an hour. Otherwise, the surface of the polysilicon after cleaning will be exposed to water vapor or the air will oxidize and re-form the surface oxide, which will affect the lap joint and reduce the cleaning effect.
  • the second semiconductor pattern 102 usually an oxide semiconductor layer, such as IGZO
  • Dry Etch dry etching
  • the second semiconductor pattern 102 is formed in the second region 200.
  • the second semiconductor pattern 102 is an active layer of the TFT corresponding to the second region 200, and the material thereof may be a metal oxide.
  • the TFT corresponding to the second region 200 is an oxide semiconductor TFT.
  • the material of the second semiconductor pattern 102 may be indium zinc oxide (IZO), indium-tin-zinc Oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc oxide.
  • IZO indium zinc oxide
  • ITZO indium-tin-zinc Oxide
  • IGO indium gallium oxide
  • IWO Indium tungsten Oxide
  • ZnO zinc oxide
  • SnO tin oxide
  • GZO gallium zinc oxide
  • Zinc- Any of Tin Oxide, ZTO may be a combination of the foregoing various materials.
  • the second semiconductor pattern 102 may be formed by plating, including but not limited to vacuum evaporation, magnetron sputtering, ion sputtering, and the like.
  • plating including but not limited to vacuum evaporation, magnetron sputtering, ion sputtering, and the like.
  • the second semiconductor pattern 102 may be formed directly on the second insulating layer 120 and directly above the second gate pattern 112. As shown in FIG. 3, after the second semiconductor pattern 102 is formed, the first metal pattern 121 is formed in the first region 100 by the same mask and the same material by a single film forming process, and the second metal pattern 122 is formed in the second region 200. And the third metal pattern 123, and the second metal pattern 122 and the third metal pattern 123 are respectively overlapped with the second semiconductor pattern 102 while the second metal pattern 122 and the third metal pattern 123 are not in contact with each other.
  • the material of the first metal pattern 121, the second metal pattern 122, and the third metal pattern 123 may be a metal that does not react with HF at a normal temperature or reacts extremely slowly, such as Mo, which may be formed by plating.
  • the first metal pattern 121 is located on the second insulating layer 120 of the first region 100, and can serve as a trace for connecting different functions of the polysilicon unit, for example, as a connection between the switching TFT and the driving TFT; Corresponding to the gate pattern 111, it functions as a storage capacitor to keep the pixel display of the light-emitting unit.
  • the first gate pattern as the gate of the LTPS TFT is located at a different position from the same layer as the first gate pattern of the capacitor.
  • the second metal pattern 122 and the third metal pattern 123 are respectively formed on and connected to the two sides of the second semiconductor pattern 102.
  • the second metal pattern 122 and the third metal pattern may be overlapped in consideration of the stability of the connection.
  • a portion of each of 123 is located on the side of the second semiconductor pattern 102 while another portion of the second semiconductor pattern 102 is positioned over the second semiconductor pattern 102 to form a stable connection structure without easily breaking the circuit.
  • a third insulating layer 130 is formed thereon, and the third insulating layer 130 has the first metal pattern 121 and the second The metal pattern 122, the third metal pattern 123, and the second semiconductor pattern 102 are completely covered.
  • the third insulating layer 130 has good covering properties and insulating effects, and may be an interlayer dielectric layer, such as a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, etc., wherein the silicon oxide layer,
  • the raw material and formation method of the silicon oxide layer can be the same as above.
  • the third insulating layer 130 is formed, it is etched to form a plurality of first vias 131 and a plurality of second vias 132. As shown in FIG. 4, two first vias 131 are formed in the first region 100.
  • the first semiconductor pattern 101 is exposed through the insulating layer 110 , the second insulating layer 120 , and the third insulating layer 130 .
  • the second vias 132 are formed in the second region 200 and penetrate the third insulating layer 130 . Thereby, the second metal pattern 122 and the third metal pattern 123 are exposed.
  • the formation of the first via 131 and the second via 132 can be simultaneously performed by dry etching in the same exposure process, and the dry etching can be performed using a CF system (CF4) or a CHF system (CHF3).
  • CF4 CF4
  • CHF3 CHF system
  • the LTPS may be subjected to a hydrogenation process to fill the interface state, the intergranular boundary state, and the oxide layer defect with hydrogen atoms, and generally, a plasma hydrogenation method or a solid state diffusion method may be employed. Or a hydrogen ion implantation method or the like to carry out a hydrogenation process.
  • the material of the first insulating layer is usually silicon oxide, and an oxygen atmosphere easily oxidizes the polysilicon during the etching process
  • the first via hole 131 and the second via hole 132 are subjected to hydrofluoric acid cleaning to
  • the silicon oxide and the polymer on the surface of the polysilicon (p-Si) in the first via 131 are removed, and the insulator silicon oxide and the polymer are prevented from affecting the bonding and contact between the subsequent source/drain and the polysilicon, thereby ensuring the device characteristics of the LTPS.
  • the hydrofluoric acid does not contact the second semiconductor pattern 102 during the hydrofluoric acid cleaning, and does not react, and hydrogen
  • the corrosion of the second metal pattern 122 and the third metal pattern 123 by the hydrofluoric acid is also limited, and the corrosion of the oxide semiconductor is not caused by the corrosion of the second semiconductor pattern 102. Therefore, the hydrofluoric acid can be prevented from corroding the oxide semiconductor and causing damage. It does not affect the performance of the oxide semiconductor TFT.
  • the first source electrode 141S and the first drain electrode 141D are formed on the first region 100
  • the second source electrode 142S and the second drain electrode 142D are formed on the second region 200.
  • the low resistivity is the requirement of the TFT for the source and drain electrodes.
  • the good ohmic contact between the source and drain electrodes and the semiconductor layer is another important requirement of the TFT for the source and drain electrode materials, which can reduce the resistance between the drain and the source. Prevents current crowding effects.
  • the first source 141S, the first drain 141D, the second source 142S, and the second drain 142D may be simultaneously formed by a single film forming process, and the material thereof may be metal Ti, ITO, etc., and the metal Ti material not only has an IGZO layer but also It has better adhesion and can reduce the contact resistance with the active layer, while the ITO material has a lower resistivity, can form a better ohmic contact with the IGZO active layer, and has better transparency.
  • a portion of the first source 141S and the first drain 141D are formed on the third insulating layer 130, and are respectively connected to the first semiconductor pattern 101 through the two first vias 131; the second source 142S is connected to the second metal pattern 122 through a second via 132, and the second drain 142D is connected to the third metal pattern 123 through another second via 132, and the second metal pattern 122 and the third metal pattern 123 are respectively.
  • the second semiconductor pattern 102 is overlapped with the second semiconductor pattern 102 to achieve electrical connection between the second source 142S and the second drain 142D and the second semiconductor pattern 102.
  • a passivation layer (not shown) may be further formed on the third insulating layer 130 to cover the source and drain electrodes, and then the subsequent process may be smoothly performed.
  • an oxide semiconductor TFT is used for the display region and an LTPS TFT is used for the peripheral driving circuit.
  • an oxide semiconductor TFT may be added to the peripheral circuit to add to the display region.
  • LTPS TFT may be added to the peripheral circuit to add to the display region.
  • the array substrate of the present disclosure includes:
  • the substrate S includes a first region 100 and a second region 200;
  • the first semiconductor pattern 101 is located in the first region 100;
  • the first insulating layer 110 covers at least the first semiconductor pattern 101;
  • the first gate pattern 111 and the second gate pattern 112 are separated from each other, respectively disposed in the first region 100 and the second region 200;
  • a second insulating layer 120 covering the first gate pattern 111 and the second gate pattern 112;
  • the first metal pattern 121 is located on the second insulating layer 120 of the first region 100;
  • the second metal pattern 122 and the third metal pattern 123 are located in the second region 200 and overlap the second semiconductor pattern 102 respectively;
  • the third insulating layer 130 covers the second semiconductor pattern 102, the first metal pattern 121, the second metal pattern 122, and the third metal pattern 123;
  • the first via hole 131 is located in the first region 100 and penetrates through the first insulating layer 110, the second insulating layer 120 and the third insulating layer 130;
  • a second via 132 located in the second region 200 and through the third insulating layer 130;
  • a first source 141S and a first drain 141D are located on the third insulating layer 130 of the first region 100;
  • the second source 142S and the second drain 142D are located on the third insulating layer 130 of the second region 200;
  • the first source 141S and the first drain 141D are respectively connected to the first semiconductor pattern 101 through the first via 131, and the second source 142S and the second drain 142D pass through the second via 132 and the second semiconductor, respectively.
  • the pattern 102 is connected.
  • the materials of the first metal pattern 121, the second metal pattern 122, and the third metal pattern 123 are the same and can be formed by a single film forming process.
  • the manufacturing method of the present disclosure can realize the one-time patterning process by changing the position of the film layer of the oxide semiconductor in the array substrate and providing the lap joint structure on both sides thereof, and effectively protecting the oxide semiconductor layer by the lap joint structure.
  • the normal operation of the hydrofluoric acid cleaning after the via hole avoids the influence of the hydrofluoric acid on the oxide semiconductor layer, and simplifies the production process, thereby reducing the production cost.
  • the LTPS TFT and the oxide semiconductor TFT can be simultaneously formed by a common process, and thus various combinations of the LTPS TFT and the oxide semiconductor TFT can be used, whereby excellent image quality and reduction in work can be obtained.
  • a consumable organic electroluminescent display device By using the manufacturing method of the present disclosure, the LTPS TFT and the oxide semiconductor TFT can be simultaneously formed by a common process, and thus various combinations of the LTPS TFT and the oxide semiconductor TFT can be used, whereby excellent image quality and reduction in work can be obtained.
  • a consumable organic electroluminescent display device is a consumable organic electroluminescent display device.
  • the first via 602' of the low temperature polysilicon thin film transistor and the second pass of the oxide thin film transistor are The hole 702' is typically formed using a one-shot etch process, but since the depth of the first via 602' is deeper than the depth of the second via 702', when the second via 702' has been etched, the first via 602 'There is still a part of the unetched finish, and it is necessary to extend the etching time so that the first via 602' can reach the polysilicon semiconductor layer 601', expose the polysilicon semiconductor layer 601', and in the process of continuing the etching, the second pass Continued etching of the oxide semiconductor 701' in the hole 702' causes the oxide semiconductor 701' to be completely etched away in the subsequent etching time, thereby causing abnormal performance of the oxide thin film transistor.
  • the low temperature polysilicon thin film transistor needs to be cleaned with hydrofluoric acid (HF) after the first via hole 602' is formed, the oxide layer on the surface of the polysilicon (p-Si) is removed, and the source and drain electrodes are deposited. To ensure that the source and drain form a good ohmic contact with the polysilicon semiconductor layer, but when the array substrate is cleaned by HF, HF reacts with the oxide semiconductor layer 701' to cause the oxide semiconductor 701' to be etched away.
  • HF hydrofluoric acid
  • the performance of the oxide thin film transistor is abnormal, and if the barrier layer is formed at the second via hole 702' before the HF cleaning, the HF cleaning is removed, which also causes the process to be complicated and the cost to be increased.
  • the current process limitation of the array substrate causes the gate 703' and the gate insulating layer 704' of the oxide semiconductor to be formed by a single process, resulting in a shorter width of the gate insulating layer 704' in the oxide semiconductor layer.
  • the array substrate includes a substrate S and a low temperature polysilicon thin film transistor (LTPS TFT) and an oxide thin film transistor (Oxide TFT) formed on the substrate S, wherein the oxide thin film transistor is a top gate structure.
  • the oxide thin film transistor includes a second semiconductor pattern 670, a second gate pattern 693, a second source drain, and a second via 712. The area of the second semiconductor pattern 670 corresponding to the second via 712 is covered with a conductive protection portion, and the second source drain is connected to the conductive protection portion through the second via 712.
  • the area of the second semiconductor pattern 670 corresponding to the second via 712 is covered with a conductive protection portion, and the orthographic projection of the conductive protection portion on the substrate S covers the second via 712 on the substrate.
  • the orthographic projection on S i.e., the orthographic projection of the conductive guard on the substrate S overlaps the orthographic projection of the second via 712 on the substrate S.
  • the low temperature polysilicon thin film transistor includes a first semiconductor pattern 620, a first via 711, a first source drain connected to the first semiconductor pattern 620 through the first via 711, and a first gate formed over the first semiconductor pattern 620 The pattern 640 and the first metal pattern 691.
  • the array substrate includes a conductive protection portion formed on the second semiconductor pattern 670, and the conductive protection portion includes a second metal pattern 692 and a third metal pattern 694 respectively located at two ends of the second semiconductor pattern, and in a specific example, the second source and drain electrodes
  • the second source 723 and the second drain 724 may be respectively connected to the second metal pattern 692 and the third metal pattern 694 through the second via 712, and the conductive protection portion may be The electrical connection between the second source 723 and the second drain 724 and the second semiconductor pattern is realized, so that the oxide thin film transistor operates normally, and the first via 711 and the second via 712 can be prevented from being formed when the first via 711 and the second via 712 are formed.
  • the second semiconductor pattern 670 is damaged when the hole is subjected to hydrofluoric acid cleaning, and the second semiconductor pattern 670 is protected by the conductive protection portion to function as an etch barrier, so that the first via 711 and the second via can be enabled.
  • 712 is realized by one process, and the formation of the first via 711 and the second via 712 can be patterned by using only one mask, which can reduce the number of masks used, reduce the process flow of the array substrate, and simplify the process. ,cut costs.
  • the present disclosure provides a conductive protection portion on a region corresponding to the second via hole on the active layer of the oxide thin film transistor, and the active layer is effectively protected by the conductive protection portion, so that the second pattern can be realized after the patterning process is performed.
  • the normal operation of the hydrofluoric acid cleaning of the hole 712 and the first via 711 avoids the influence of hydrofluoric acid on the active layer of the oxide thin film transistor, and the oxide thin film transistor adopts a top gate structure, and the conductive protection portion can be oxidized.
  • the second gate pattern of the thin film transistor is disposed in the same layer and can be formed by one patterning process to reduce the number of process steps.
  • the substrate S includes a first region 600 and a second region 700
  • a low temperature polysilicon thin film transistor can be formed in the first region 600 of the substrate S
  • an oxide thin film transistor can be formed in the second region 700.
  • the first semiconductor pattern 620 is formed in the first region 600 and the second semiconductor pattern 670 is formed in the second region 700.
  • the material of the first semiconductor pattern 620 may be polysilicon for use as an active region of a low temperature polysilicon thin film transistor, and the material of the second semiconductor pattern 670 is an oxide, which may serve as an active region of the oxide thin film transistor.
  • the material of the oxide may be a combination of one or more of indium tin zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium tungsten oxide, zinc oxide, tin oxide, gallium zinc oxide, and zinc tin oxide.
  • the oxide thin film transistor can be used as a switching element of a pixel in a display area of a display panel, and a low temperature polysilicon thin film transistor can be used as a driving element of a driving circuit.
  • a first gate insulating layer 680 is further formed on the second semiconductor pattern 670.
  • the first gate insulating layer 680 can be formed by a single patterning process to make the first gate
  • the width W of the insulating layer 680 is wider than the width of the second gate pattern disposed on the first gate insulating layer 680, thereby avoiding a short channel effect due to the small width W of the first gate insulating layer 680.
  • the second gate pattern 693 and the material of the conductive protection portion may be selected from the same metal material, such as a combination of one or more of Al, Cr, Mo, and W.
  • the second gate pattern 693 and the conductive protection portion can be formed by one patterning process, which can save process steps and simplify the process of fabricating the array substrate.
  • the low temperature polysilicon thin film transistor may include a first semiconductor pattern, a first source drain connected to the first semiconductor pattern through a first via, and a first formed over the first semiconductor pattern a gate pattern and a first metal pattern.
  • a first metal pattern 691 is further formed on the first gate pattern 640.
  • the first metal pattern 691 can serve as a pixel electrode for controlling pixel display.
  • the first metal pattern 691 can be selected from the same metal material as the conductive protection portion, that is, the material of the first metal pattern 691 can be selected from a metal such as Al, Cr, Mo or W. Or a combination of multiples.
  • the first metal pattern 691 can be disposed in the same layer as the second gate pattern 693 and the conductive protection portion, and is formed by one patterning process to save process steps and simplify the array substrate fabrication process.
  • the array substrate of the present disclosure can simultaneously form a low-temperature polysilicon thin film transistor and an oxide thin film transistor by a more simplified process, and thus various combinations of a low-temperature polysilicon thin film transistor and an oxide thin film transistor can be used, thereby being able to obtain excellent image quality and can be reduced A low power organic electroluminescent display device.
  • a method for fabricating an array substrate is disclosed in the embodiment, and the method includes:
  • S602 Form a first insulating layer 630 covering at least the first semiconductor pattern 620.
  • S604 Form a second insulating layer 650 covering the first gate pattern 640.
  • S605 Forming a second semiconductor pattern 670 on the second insulating layer 650 of the second region 700.
  • S607 forming a first metal pattern 691 in the first region 600 by one patterning process, forming a second metal pattern 692 and a third metal pattern 694 respectively located at two ends of the second semiconductor pattern 670 in the second region 700, and being located at the first gate A second gate pattern 693 on the insulating layer 680.
  • S608 Form a third insulating layer 710 covering the first metal pattern 691, the second metal pattern 692, the third metal pattern 694, and the second gate pattern 693.
  • S610 forming a first source 721 and a first drain 722 connected to the first semiconductor pattern 620 through the first via 711, and forming a connection between the second metal pattern 692 and the third metal pattern 694 through the second via 712 The second source 723 and the second drain 724.
  • FIGS. 9 to 18 are cross-sectional views showing a process of fabricating the array substrate in the present embodiment.
  • a first semiconductor pattern 620 is formed in the first region 600 of the substrate S.
  • the material of the substrate S of the array substrate may be quartz glass, alkali-free glass, and silicon wafer, polyimide or plastic.
  • the substrate S may have a plurality of first regions 600 and a plurality of second regions 700 (only one of which is shown in the figure) for enabling formation of different types of transistors, such as oxide thin film transistors, in the two regions, respectively.
  • a switching element of a pixel in the display area is displayed, and a low temperature polysilicon thin film transistor is used as a driving element of the driving circuit.
  • the material of the first semiconductor pattern 620 is polysilicon.
  • the polysilicon semiconductor pattern is formed by first forming amorphous silicon (a-Si) in the first region 600 of the substrate S, and then irradiating the amorphous silicon with an excimer laser, thereby converting the amorphous silicon into polycrystalline silicon.
  • a flexible layer 611 may be formed on the substrate S, and the material of the flexible layer 611 may be polyimide (PI), when the array substrate is completed.
  • the substrate S can be removed to form a flexible display.
  • the flexible layer 611 may not be provided, which is not limited by the disclosure.
  • a fifth insulating layer 612 and a first buffer layer 613 may be disposed, and the insulating layer and the buffer layer may function as an insulator and prevent impurities in the substrate S from contaminating the first semiconductor pattern 620.
  • the material of the insulating layer and the buffer layer may be a commonly used transparent insulating material such as silicon nitride or silicon oxide.
  • a first insulating layer 630 covering at least the first semiconductor pattern 620 is formed on the first semiconductor pattern 620.
  • the first insulating layer 630 covers at least the first semiconductor pattern 620 , and may also cover the first region 600 , and may further cover the second region 700 .
  • the material of the first insulating layer 630 may be silicon nitride (Si3N4) or tetraethoxysilane (TEOS), and may be formed by chemical vapor deposition (CVD), and the CVD method may be performed by low pressure chemical vapor deposition.
  • a method such as a thermal vapor deposition method, a catalytic chemical vapor deposition method, or a plasma enhanced chemical vapor deposition method is not limited in the present disclosure.
  • a first gate pattern 640 is formed on the first insulating layer 630 of the first region 600.
  • the position of the first gate pattern 640 corresponds to the first semiconductor pattern 620 as the gate of the polysilicon transistor.
  • the material of the first gate pattern 640 may be formed by one or more of Al, Cr, Mo, or W. When a plurality of metals are used, the first gate pattern 640 is formed by a laminated film or the like of each metal.
  • the first gate pattern 640 may be formed by coating, including but not limited to a vacuum deposition process, a magnetron sputtering coating, an ion sputtering coating, or the like.
  • a second insulating layer 650 covering the first gate pattern 640 is formed on the first gate pattern 640.
  • the second insulating layer 650 covers at least the first gate pattern 640 and may further cover the first region 600 and may further cover the second region 700.
  • a second buffer layer 660 may further be formed on the second insulating layer 650.
  • the material of the second insulating layer 650 may be selected from silicon nitride
  • the material of the second buffer layer 660 may be selected from silicon oxide
  • the second buffer layer 660 formed of silicon oxide is in direct contact with the oxide thin film transistor.
  • the method of forming the second insulating layer 650 and the second buffer layer 660 is similar to the method of forming the first insulating layer 630.
  • the source gas for forming the silicon nitride layer as the nitrogen source gas, NH3, NH2H2N or N2 or the like, preferably NH3 and N2 may be used, and as the silicon source gas, SiH4, Si2H6, SiCl4, SiHCl3, SiH2Cl2, SiH3Cl3 or SiF4 or the like is preferably SiH4.
  • the silicon nitride layer can also be formed by a chemical vapor deposition method (CVD).
  • the surface of the polysilicon semiconductor pattern exposed through the via hole needs to be subjected to hydrofluoric acid cleaning, and at the same time, hydrofluoric acid is used. After cleaning, it is necessary to make the source/drain within less than half an hour. Otherwise, the surface of the polysilicon after cleaning will be exposed to water vapor or the air will oxidize and re-form the surface oxide, which will affect the lap joint and reduce the cleaning effect.
  • a second semiconductor pattern 670 (usually an oxide semiconductor layer, such as IGZO), and then perform dry etching and punching, followed by hydrofluoric acid cleaning and source and drain. Deposition. Therefore, after the first gate insulating layer 680 is formed, the second semiconductor pattern 670 is formed in the second region 700.
  • the second semiconductor pattern 670 is an active layer of a transistor corresponding to the second region, and the material thereof may be a metal oxide.
  • the transistor corresponding to the second region 700 is an oxide thin film transistor.
  • a second semiconductor pattern 670 is formed on the second insulating layer 650 of the second region 700.
  • the material of the second semiconductor pattern 670 may be selected from indium zinc oxide (IZO), indium-tin-zinc Oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc oxide. (indium gallium zinc oxide, IGZO), Indium tungsten Oxide (IWO), zinc oxide (ZnO), tin oxide (SnO), gallium zinc oxide (Gallium-Zinc Oxide, GZO), zinc tin oxide (Zinc- Any of Tin Oxide, ZTO), a combination of the foregoing various materials may also be used.
  • the second semiconductor pattern 670 may be formed by plating, including but not limited to vacuum evaporation, magnetron sputtering, ion sputtering, and the like.
  • plating including but not limited to vacuum evaporation, magnetron sputtering, ion sputtering, and the like.
  • a first gate insulating layer 680 is formed on the second semiconductor pattern 670.
  • the first gate insulating layer 680 partially covers the second semiconductor pattern 670, and the first gate insulating layer 680 is disposed at the center of the second semiconductor pattern 670 to leave a second via 712 in the region on both sides, so that the second semiconductor
  • the pattern 670 can be connected to the second source 723 and the second drain 724.
  • the first gate insulating layer 680 is formed by one patterning process, and the width W of the first gate insulating layer 680 can be controlled by the shape of the mask, so that the first gate insulating layer 680 can be made by providing a mask. The width W is appropriately increased, and the second semiconductor pattern 670 can be protected from the short channel effect when the second semiconductor pattern 670 is conductorized.
  • a first metal pattern 691 is formed in the first region 600 by one patterning process, and a second metal pattern 692 and a third metal pattern 694 respectively located at both ends of the second semiconductor pattern 670 are formed in the second region 700, and A second gate pattern 693 on the first gate insulating layer 680.
  • the materials of the first metal pattern 691, the second metal pattern 692, the third metal pattern 694, and the second gate pattern 693 may be selected from metals that do not react or react very slowly with hydrofluoric acid (HF) at normal temperature, such as Mo. .
  • the first metal pattern 691 is located on the second insulating layer 650 of the first region 600, and can serve as a trace for connecting different functions of the low temperature polysilicon thin film transistor, for example, as a connection between the switching transistor and the driving transistor;
  • the first gate pattern 640 corresponds to a storage capacitor and keeps the pixel display of the light-emitting unit.
  • the second metal pattern 692 and the third metal pattern 694 are respectively formed on and connected to the two sides of the second semiconductor pattern 670.
  • the second metal pattern 692 and the third metal pattern may be overlapped in consideration of the stability of the connection.
  • a portion of each of 694 is located on the side of the second semiconductor pattern 670 while the other portion is located above the second semiconductor pattern 670 to form a stable connection structure without easily breaking the circuit.
  • a third insulating layer 710 covering the first metal pattern 691, the second metal pattern 692, the third metal pattern 694, and the second gate pattern 693 is further formed.
  • a first via 711 penetrating through the first insulating layer 630, the second insulating layer 650, and the third insulating layer 710 is formed in the first region 600, in the second region 700.
  • a second via 712 is formed through the third insulating layer 710.
  • the first via 711 exposes the first semiconductor pattern 620
  • the second via 712 exposes the second metal pattern 692 and the third metal pattern 694.
  • the first via 711 and the second via 712 may be formed by one patterning process, and the process may be simultaneously performed by dry etching. Among them, the dry etching can be carried out by using a CF system (CF4) or a CHF system (CHF3).
  • the depth of the first via 711 is much larger than The second via 712, during the dry etching, the second via 712 has been etched to expose the second metal pattern 692 and the second metal pattern 694, and the first via 711 still has a portion that is not etched. When it is removed, etching is continued to enable the first via 711 to expose the first semiconductor pattern. At this time, the second metal pattern 692 and the third metal pattern 694 can block the etching, preventing the second semiconductor pattern 670 from being etched away, and destroying the active layer of the oxide thin film transistor.
  • the LTPS may be subjected to a hydrogenation process to fill the interface state, the intergranular boundary state, and the oxide layer defect with hydrogen atoms, and generally, a plasma hydrogenation method or a solid state diffusion method may be employed. Or a hydrogen ion implantation method or the like to carry out a hydrogenation process.
  • the material of the first insulating layer 630 is usually silicon oxide, and an oxygen atmosphere easily oxidizes the polysilicon during the etching process, after the hydrogenation process, the first via hole 711 needs to be subjected to hydrofluoric acid cleaning to remove the first via hole.
  • the silicon oxide and polymer on the surface of polycrystalline silicon (p-Si) in 711 prevent silicon oxide and polymer from affecting the subsequent source/drain overlap and contact with polysilicon, thereby ensuring the device characteristics of LTPS.
  • the hydrofluoric acid does not contact the second semiconductor pattern 670 during the hydrofluoric acid cleaning, and does not react, and at the same time, hydrogen
  • the corrosion of the second metal pattern 692 and the third metal pattern 694 by the hydrofluoric acid is also limited, and the corrosion is completely prevented from contacting the second semiconductor pattern 670, so that the hydrofluoric acid can be prevented from corroding the oxide semiconductor and causing damage. Does not affect the performance of the oxide thin film transistor.
  • a first source 721 and a first drain 722 are formed on the first region 600, and a second source 723 and a second drain 724 are formed on the second region 700.
  • Low resistivity is the requirement of the source to the drain electrode of the transistor.
  • the good ohmic contact between the source and drain electrodes and the semiconductor layer is another important requirement of the transistor for the source and drain electrode materials, which can reduce the resistance between the drain and the source. Prevents current crowding effects.
  • the first source 721, the first drain 722, the second source 723, and the second drain 724 can be simultaneously formed by one patterning process, and the material thereof can be metal Ti, ITO, etc., and the metal Ti material is not only compared with the IGZO layer. Good adhesion, and can reduce the contact resistance with the active layer, while the ITO material has a lower resistivity, can also form a better ohmic contact with the IGZO active layer, and has better transparency.
  • a portion of the first source 721 and the first drain 722 are formed on the third insulating layer 710 and are respectively connected to the first semiconductor pattern 620 through the two first vias 711; the second source 723 passes through a second pass
  • the hole 712 is connected to the second metal pattern 692, the second drain 724 is connected to the third metal pattern 694 through the other second via 712, and the second metal pattern 692 and the third metal pattern 694 are respectively associated with the second semiconductor pattern 670.
  • the electrical connection between the second source 723 and the second drain 724 and the second semiconductor pattern 670 is achieved.
  • a passivation layer may be further formed on the third insulating layer 710 to cover the source and drain electrodes, and then the subsequent process may be smoothly performed.
  • an oxide thin film transistor is used for the display region and a low-temperature polysilicon thin film transistor is used for the peripheral driving circuit.
  • an oxide thin film transistor may be added to the peripheral circuit for display.
  • a low temperature polysilicon thin film transistor is added to the region.
  • the embodiment further discloses a display device including the array substrate of the embodiment.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart watch, and the like.
  • the display device of the present disclosure also has a structure such as a frame of a conventional display device, and the structure is a conventional technical means in the art, and details are not described herein again.
  • the active layer is effectively protected by the conductive protection portion, and the hydrofluoric acid can be realized after the via patterning process is performed.
  • the normal cleaning process avoids the influence of hydrofluoric acid on the active layer of the oxide thin film transistor, and simplifies the fabrication process, thereby reducing the production cost.
  • the oxide thin film transistor adopts a top gate structure, and the conductive protection portion can be oxidized.
  • the second gate pattern of the thin film transistor is disposed in the same layer and can be formed by one patterning process to reduce the number of process steps.
  • the display device of the present disclosure includes the above array substrate, and the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of the present disclosure also has a structure such as a frame of a conventional display device.

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Abstract

一种阵列基板及其制造方法以及显示装置。该制造方法包括：在衬底（S）上形成第一半导体图案（101）和第一绝缘层(110)；形成彼此隔离的第一栅极图案(111)和第二栅极图案(112)；形成第二绝缘层(120)；形成第二半导体图案(102)；形成第一金属图案(121)以及分别与第二半导体图案(102)搭接的第二金属图案(122)和第三金属图案(123)；形成第三绝缘层(130)；形成第一过孔(131)、第二过孔(132)、第一源漏极(141S，141D)、第二源漏极（142S，142D），其中，第一源漏极(141S，141D)分别通过第一过孔(131)与第一半导体图案（101）连接，第二源漏极（142S，142D）分别通过第二过孔(132)与第二半导体图案连接(102)。本制造方法可实现一次构图工艺制作过孔后氢氟酸清洗的正常进行，避免了氢氟酸对氧化物半导体层的影响，同时简化了制作流程，进而降低生产成本。

Description

阵列基板及其制造方法和显示装置
相关申请的交叉引用
本申请要求于2017年12月15日提交的中国专利申请第201711345541.8号和2018年10月17日提交的中国专利申请第201821680371.9号的优先权，其全部内容通过引用结合在本文中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制造方法以及包括该阵列基板的显示装置。
背景技术
AMOLED(有源矩阵有机发光二极管)技术是Mobile产品的发展趋势。作为像素的开关使用的TFT(薄膜晶体管)，需要漏电流(Ioff)尽可能小，而利用氧化物半导体的TFT能够减小漏电流。但是，氧化物半导体的载流子的迁移率小，因此有时难以用使用了氧化物半导体的TFT来形成内置于显示装置内的驱动电路。另一方面，由于LTPS(Low Temperature Poly-Si：低温多晶硅)TFT的载流子迁移率大，因此能够通过使用了LTPS的TFT来形成驱动电路。然而，在将LTPS用作像素中的开关TFT的情况下，LTPS的漏电流大。
LTPO(LTPS+Oxide，即低温多晶硅与氧化物半导体的组合)技术结合了LTPS TFT和Oxide TFT这两种TFT各自的优势，在Mobile AMOLED产品的高PPI、低功耗、高画质等方面具备一定的技术优势。另外，由于Oxide TFT具有漏电流低的优点，在LTPS+Oxide技术的传感器应用上也有一定的优点。因此LTPO工艺的开发具有较高的价值和意义。
发明内容
本公开提供一种在阵列基板的制造方法，至少能够在工艺复杂度的情况下有效避免氧化物半导体层被氢氟酸腐蚀。
为实现上述目的，本公开采取如下技术方案。
根据本公开的第一方面，提供了一种阵列基板的制造方法，所述阵列基板包括衬底，所述衬底包括第一区域和第二区域，所述制造方法包括：
在所述第一区域形成第一半导体图案；
形成至少覆盖所述第一半导体图案的第一绝缘层；
分别在所述第一区域和所述第二区域形成彼此隔离的第一栅极图案和第二栅极图案；
形成至少覆盖所述第一栅极图案的第二绝缘层；
在所述第二区域形成第二半导体图案；
通过一次成膜工艺，在所述第一区域形成第一金属图案，在所述第二区域形成分别与所述第二半导体图案搭接的第二金属图案和第三金属图案；
形成至少覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案的第三绝缘层；
在所述第一区域形成贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的第一过孔，在所述第二区域形成贯穿所述第三绝缘层的第二过孔；以及
形成第一源极和第一漏极、第二源极和第二漏极，
其中，所述第一源极和所述第一漏极分别通过所述第一过孔与所述第一半导体图案连接，所述第二源极和所述第二漏极分别通过所述第二过孔与所述第二半导体图案连接。
在一些实施例中，所述第一栅极图案与所述第二栅极图案同层设置，并且其中，所述第二绝缘层覆盖所述第一栅极图案和所述第二栅极图案。
在另一些实施例中，该制造方法还包括在所述第二半导体图案上形成第一栅绝缘层，其中，所述第二栅极图案位于所述第一栅绝缘层上，并且其中，所述第三绝缘层覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案、所述第一栅绝缘层和所述第二栅极图案。
根据本公开的第二方面，提供一种阵列基板，包括：
衬底，所述衬底包括第一区域和第二区域；
第一半导体图案，位于所述第一区域；
第一绝缘层，至少覆盖所述第一半导体图案；
彼此隔离的第一栅极图案和第二栅极图案，分别设置于所述第一区域和所述第二区域；
第二绝缘层，至少覆盖所述第一栅极图案；
第一金属图案，位于所述第一区域的所述第二绝缘层上；
第二半导体图案，位于所述第二区域的所述第二绝缘层上；
第二金属图案和第三金属图案，位于所述第二区域并分别与所述第二半导体图案搭接；
第三绝缘层，至少覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案；
第一过孔，位于所述第一区域并贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层；
第二过孔，位于所述第二区域并贯穿所述第三绝缘层；
第一源极和第一漏极，位于所述第一区域的所述第三绝缘层上；以及
第二源极和第二漏极，位于所述第二区域的所述第三绝缘层上；
其中，所述第一源极和所述第一漏极分别通过所述第一过孔与所述第一半导体图案连接，所述第二源极和所述第二漏极分别通过所述第二过孔与所述第二半导体图案连接。
在一些实施例中，其中，所述第一栅极图案与所述第二栅极图案同层设置，并且其中，所述第二绝缘层覆盖所述第一栅极图案和所述第二栅极图案。
在另一些实施例中，该阵列基板还包括位于所述第二半导体图案上的第一栅绝缘层，其 中，所述第二栅极图案位于所述第一栅绝缘层上，并且其中，所述第三绝缘层覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案、所述第一栅绝缘层和所述第二栅极图案。
根据本公开的第四方面，提供一种显示装置，所述显示装置包括上述阵列基板。
附图说明
图1为本公开的阵列基板的制造方法的工艺流程图；
图2-图5为本公开的阵列基板的制造方法的工序剖面示意图；
图6示出现有技术中阵列基板的示意图；
图7示出本公开阵列基板一个具体实施例的示意图；
图8示出本公开阵列基板一个具体实施例的制作方法的流程图；
图9-18示出本公开阵列基板的制作过程的剖面示意图。
其中，附图标记说明如下：
S：衬底，100：第一区域，200：第二区域，101：第一半导体图案，102：第二半导体图案，110：第一绝缘层，111：第一栅极图案，112：第二栅极图案，120：第二绝缘层，121：第一金属图案，122：第二金属图案，123：第三金属图案，130：第三绝缘层，131：第一过孔，132：第二过孔，141S：第一源极，141D：第一漏极，142S：第二源极，142D：第二漏极，600：第一区域，700：第二区域，611：柔性层，612：第五绝缘层，613：第一缓冲层，620：第一半导体图案，670：第二半导体图案，630：第一绝缘层，680：第一栅绝缘层，640：第一栅极图案，693：第二栅极图案，650：第二绝缘层，660：第二缓冲层，691：第一金属图案，692：第二金属图案，694：第三金属图案，710：第三绝缘层，711：第一过孔，712：第二过孔，721：第一源极，722：第一漏极，723：第二源极，724：第二漏极。
具体实施方式
发明人发现，对于LTPS和氧化物半导体而言，由于材料的性质不同，将其形成于同一基板上会出现工艺不兼容等问题。在相关技术制备LTPS TFT的过程中，需要制作贯穿多层绝缘层的过孔，以使源漏电极与多晶硅半导体层连接。在制作过孔后，由于多晶硅层中对应位置暴露在空气中，会使其表面发生氧化，因此需要实施氢氟酸(HF)清洗，以在形成源漏电极前去除其表面氧化物。然而，如果在氢氟酸清洗过程中氢氟酸接触到氧化物半导体，将会导致氢氟酸腐蚀氧化物半导体而造成损伤，从而影响Oxide TFT的性能。
下面根据具体实施例对本公开的技术方案做进一步说明。本公开的保护范围不限于以下实施例，列举这些实例仅出于示例性目的而不以任何方式限制本公开。
需了解的是，在此公开的附图并未必按照实际装置及元件的比例绘示。在附图中可能夸大实施例的形状与厚度以便清楚表现出本公开实施例的特征。此外，附图中的结构及装置是以示意的方式绘示，以便清楚表现出本公开实施例的特征。
还需了解的是，本公开中所提到的第一区域和第二区域不仅仅局限于衬底自身，还可包括其垂直方向上的区域范围。
图1为本公开的阵列基板的制造方法的工艺流程图，如图1所示，本公开的阵列基板的制造方法包括：
步骤S101：阵列基板包括衬底，衬底包括第一区域和第二区域，在第一区域形成第一半导体图案；
步骤S102：形成至少覆盖第一半导体图案的第一绝缘层；
步骤S103：通过一次成膜工艺，分别在第一区域和第二区域形成彼此隔离的第一栅极图案和第二栅极图案；
步骤S104：形成覆盖第一栅极图案和第二栅极图案的第二绝缘层；
步骤S105：在第二区域形成第二半导体图案；
步骤S106：通过一次成膜工艺，在第一区域形成第一金属图案，在第二区域形成分别与第二半导体图案搭接的第二金属图案和第三金属图案；
步骤S107：形成覆盖第二半导体图案、第一金属图案、第二金属图案和第三金属图案的第三绝缘层；
步骤S108：在第一区域形成贯穿第一绝缘层、第二绝缘层和第三绝缘层的第一过孔，在第二区域形成贯穿第三绝缘层的第二过孔；以及
步骤S109：形成第一源极和第一漏极、第二源极和第二漏极，其中，第一源极和第一漏极分别通过第一过孔与第一半导体图案连接，第二源极和第二漏极分别通过第二过孔与第二半导体图案连接。
图2-图5为本公开一个实施方式的阵列基板的制造方法的工序剖面示意图。如图2所示，阵列基板包括衬底S，衬底S的材料可以为石英玻璃、无碱玻璃以及硅片、聚酰亚胺或塑料等。衬底S具有多个第一区域100和多个第二区域200(图中仅示出各一个)，以在两个区域中分别形成不同类型的TFT，例如氧化物半导体TFT作为显示区域中像素的开关元件，而LTPS TFT作为驱动电路的驱动元件。
首先构图工艺在衬底S的第一区域100形成第一半导体图案101，第一半导体图案101是作为第一区域100所对应TFT的有源层，其材料可为多晶硅，此时第一区域100所对应的TFT为LTPS TFT。
可以理解的是，在衬底S的第一区域100形成第一半导体图案101之前，可以先形成遮光图案以及绝缘层。其中遮光图案可以利用非晶硅或者深色树脂或者金属材料，从而避免从衬底侧入射的光线影响半导体器件的工作特性。
第一半导体图案101的形成可包括以下步骤：在衬底S的第一区域100形成非晶硅(a-Si)，之后对非晶硅照射准分子激光，从而将非晶硅转化为多晶硅。
在形成第一半导体图案101之前，还可先在衬底S上形成氮化硅(SiNx)层和氧化硅(SiOx)层的叠层，从而防止衬底S中所含的杂质污染第一半导体图案101。
形成第一半导体图案101后，在其上形成第一绝缘层110。第一绝缘层110至少覆盖第 一半导体图案101，可进一步覆盖第一区域100，还可进一步覆盖第二区域200。第一绝缘层110的材料可为氧化硅(SiOx)层，其可以TEOS(四乙氧基硅烷)为原料而利用CVD(化学气相沉积)法所形成，CVD法可例如低压化学气相沉积法、热气相沉积法、催化化学气相沉积法、等离子增强化学气相沉积法等。
通过一次成膜工艺，利用同一掩模和相同材料分别在第一区域100和第二区域200形成第一栅极图案111和第二栅极图案112，第一栅极图案111和第二栅极图案112彼此隔离。第一栅极图案111和第二栅极图案112由Al合金、Cr、Mo、W或者上述这些的层叠膜等形成，分别作为两个区域中TFT的栅极。第一栅极图案111和第二栅极图案112可通过镀膜的方式形成，包括但不限于真空蒸镀、磁控溅射镀膜、离子溅射镀膜等。
第一栅极图案111形成于第一绝缘层110上且处于第一半导体图案101的正上方。若第一绝缘层110也覆盖了第二区域200，第二栅极图案112可形成于第一绝缘层110上，若第一绝缘层110仅覆盖第一区域100，则第二栅极图案112可直接形成在衬底S的第二区域200上。
形成第一栅极图案111和第二栅极图案112后，在其上形成第二绝缘层120。第二绝缘层120将第一栅极图案111和第二栅极图案112完全覆盖，同时也将第一绝缘层110以及衬底S覆盖。
为保证氧化物半导体TFT的性能，第二绝缘层120的材料为氮化硅层和氧化硅层的叠层，其中氮化硅层位于下方而氧化硅层位于上方从而使氧化硅层与氧化物半导体层接触。
氧化硅层的原料及形成方法可与上文相同。就形成氮化硅层的原料气体而言，作为氮源气体，可使用NH3、NH2H2N、N2等，优选NH3和N2，作为硅源气体，可使用SiH4、Si2H6、SiCl4、SiHCl3、SiH2Cl2、SiH3Cl3、SiF4等，优选SiH4。氮化硅层也可通过化学气相沉积方法(CVD)形成。
需要说明的是，对于LTPS TFT，由于在制作源漏电极与有源层连接的过孔后，需要对多晶硅半导体图案通过过孔暴露出的表面进行氢氟酸清洗，同时，氢氟酸清洗后需要在小于半小时之内做制作源/漏极，否则清洗后的多晶硅表面接触水汽或者空气会氧化而重新形成表面氧化物，对搭接造成影响，降低清洗效果。为了进一步节约工艺流程，降低制作成本，需要先制做第二半导体图案102(通常为氧化物半导体层，例如IGZO)然后进行干刻蚀(Dry Etch)打孔，之后依次进行氢氟酸清洗和源/漏极沉积。
因此，形成第二绝缘层120后，在第二区域200形成第二半导体图案102，第二半导体图案102是作为第二区域200所对应TFT的有源层，其材料可为金属氧化物，此时第二区域200所对应的TFT为氧化物半导体TFT。
第二半导体图案102的材料可为氧化铟锌(indium zinc oxide,IZO)、氧化铟锡锌(Indium-Tin-Zinc Oxide,ITZO)、氧化铟镓(indium gallium oxide,IGO)、氧化铟镓锌(indium gallium zinc oxide,IGZO)、氧化铟钨(Indium tungsten Oxide,IWO)、氧化锌(ZnO)、氧化锡(SnO)、氧化镓锌(Gallium-Zinc Oxide,GZO)、氧化锌锡(Zinc-Tin Oxide,ZTO)中的任一种，可以为前述多种材料的组合。
第二半导体图案102可通过镀膜的方式形成，包括但不限于真空蒸镀、磁控溅射镀膜、离子溅射镀膜等。以IGZO为例，可采用直流磁控溅射制备，其中靶材的原子比为In2O3-Ga2O3-ZnO＝1∶1∶1(摩尔比)，通过调节氧气流量、沉积功率，气体流量等参数来获得满足应用要求的IGZO薄膜。
第二半导体图案102可直接形成于第二绝缘层120上，且处于第二栅极图案112的正上方。如图3所示，形成第二半导体图案102后，通过一次成膜工艺，利用同一掩模和相同原料在第一区域100形成第一金属图案121，在第二区域200形成第二金属图案122和第三金属图案123，并且第二金属图案122和第三金属图案123分别与第二半导体图案102搭接，同时第二金属图案122和第三金属图案123之间不接触。
第一金属图案121、第二金属图案122和第三金属图案123的材料可为常温下不与HF反应或反应极慢的金属，例如Mo，其可通过镀膜的方式形成。
第一金属图案121是位于第一区域100的第二绝缘层120上，其可充当走线，连接起不同作用的多晶硅单元，例如可作为连接开关TFT及驱动TFT的连线；也可第一栅极图案111相对应，起到存储电容作用，保持发光单元像素显示。作为LTPS TFT栅极的第一栅极图案与作为电容的第一栅极图案位于同一层的不同位置。
第二金属图案122和第三金属图案123分别形成于第二半导体图案102的两侧并与其连接，考虑到连接的稳定性，可以采用搭接的方式使第二金属图案122和第三金属图案123各自的一部分位于第二半导体图案102的侧边同时各自的另一部分位于第二半导体图案102之上，以形成稳固的连接结构，不会轻易断路。
如图4所示，形成第一金属图案121、第二金属图案122和第三金属图案123后，在其上形成第三绝缘层130，第三绝缘层130将第一金属图案121、第二金属图案122、第三金属图案123以及第二半导体图案102完全覆盖。
第三绝缘层130具有良好的覆盖特性和绝缘效果，可为层间介电层，例如氮化硅层、氧化硅层、氮化硅层和氧化硅层的叠层等，其中氧化硅层、氧化硅层的原料及形成方法可与上文相同。
形成第三绝缘层130后，对其进行蚀刻以形成多个第一过孔131和多个第二过孔132，如图4所示，两个第一过孔131形成于第一区域100，其贯穿一绝缘层110、第二绝缘层120和第三绝缘层130，从而使第一半导体图案101暴露出来；两个第二过孔132形成于第二区域200，其贯穿第三绝缘层130，从而使第二金属图案122和第三金属图案123暴露出来。
第一过孔131和第二过孔132的形成可在同一次曝光工艺中利用干式蚀刻同时进行，干式蚀刻可使用CF系(CF4)、或者CHF系(CHF3)的气体来进行。
形成第一过孔131和第二过孔132后，可对LTPS进行氢化工艺，以氢原子填补界面态、晶粒间界态及氧化层缺陷等，通常可采用等离子体氢化法、固态扩散法或氢离子注入法等来实施氢化工艺。
由于第一绝缘层的材料通常为氧化硅，并且刻蚀过程中有氧气气氛容易氧化多晶硅，因此在氢化工艺后，需要对第一过孔131和第二过孔132进行氢氟酸清洗，以去除第一过孔131 中多晶硅(p-Si)表面的氧化硅及聚合物，防止绝缘体氧化硅及聚合物影响后续源/漏极与多晶硅的搭接及接触，以此来保证LTPS的器件特性。由于第二过孔132仅暴露第二金属图案122和第三金属图案123，因此在进行氢氟酸清洗时，氢氟酸与第二半导体图案102不会接触，也不会进行反应，同时氢氟酸对第二金属图案122和第三金属图案123的腐蚀也很有限，不会出现将其腐蚀完全而接触第二半导体图案102的情况，因此可避免氢氟酸腐蚀氧化物半导体而造成损伤，不会影响氧化物半导体TFT的性能。如图5所示，氢氟酸清洗之后，在第一区域100上形成第一源极141S和第一漏极141D，在第二区域200上形成第二源极142S和第二漏极142D。
低电阻率是TFT对源漏电极的要求，除此之外，源漏电极与半导体层形成良好的欧姆接触是TFT对于源漏电极材料另一个重要要求，它可以降低漏源之间的电阻，防止产生电流拥挤效应。
第一源极141S、第一漏极141D、第二源极142S和第二漏极142D可利用一次成膜工艺同时形成，其材料可为金属Ti、ITO等，金属Ti材料不仅与IGZO层有较好的粘附能力，并且能够减少与有源层的接触电阻，而ITO材料具有较低的电阻率，还能与IGZO有源层形成较好的欧姆接触，并且具有较好的透明度。
如图5所示，第一源极141S和第一漏极141D的一部分形成于第三绝缘层130上，并分别通过两个第一过孔131与第一半导体图案101连接；第二源极142S通过一个第二过孔132与第二金属图案122连接，第二漏极142D通过另一个第二过孔132与第三金属图案123连接，而第二金属图案122和第三金属图案123分别与第二半导体图案102搭接，从而实现第二源极142S和第二漏极142D与第二半导体图案102的电性连接。
形成源漏电极后，可以在第三绝缘层130上进一步形成钝化层(图中未示出)并使其覆盖源漏电极，之后可顺利进行后续工艺。
在以上说明中，以将氧化物半导体TFT用于显示区域、将LTPS TFT用于周边驱动电路的形式进行了说明，但根据制品规格，也可以向周边电路添加氧化物半导体TFT，向显示区域添加LTPS TFT。
如图5所示，本公开的阵列基板包括：
衬底S，衬底S包括第一区域100和第二区域200；
第一半导体图案101，位于第一区域100；
第一绝缘层110，至少覆盖第一半导体图案101；
彼此隔离的第一栅极图案111和第二栅极图案112，分别设置于第一区域100和第二区域200；
第二绝缘层120，覆盖第一栅极图案111和第二栅极图案112；
第一金属图案121，位于第一区域100的第二绝缘层120上；
第二半导体图案102，位于第二区域200的第二绝缘层120上；
第二金属图案122和第三金属图案123，位于第二区域200并分别与第二半导体图案102搭接；
第三绝缘层130，覆盖第二半导体图案102、第一金属图案121、第二金属图案122和第三金属图案123；
第一过孔131，位于第一区域100并贯穿第一绝缘层110、第二绝缘层120和第三绝缘层130；
第二过孔132，位于第二区域200并贯穿第三绝缘层130；
第一源极141S和第一漏极141D，位于第一区域100的第三绝缘层130上；以及
第二源极142S和第二漏极142D，位于第二区域200的第三绝缘层130上；
其中，第一源极141S和第一漏极141D分别通过第一过孔131与第一半导体图案101连接，第二源极142S和第二漏极142D分别通过第二过孔132与第二半导体图案102连接。
其中，第一金属图案121、第二金属图案122和第三金属图案123的材料相同，可通过一次成膜工艺形成。
由上可知，本公开的制造方法通过改变阵列基板中氧化物半导体的膜层位置并在其两侧设置搭接结构，利用搭接结构对氧化物半导体层进行有效保护，可实现一次构图工艺制作过孔后氢氟酸清洗的正常进行，避免了氢氟酸对氧化物半导体层的影响，同时简化了制作流程，进而降低生产成本。
通过使用本公开的制造方法，能够通过共通的工艺同时形成LTPS TFT和氧化物半导体TFT，因此能够使用LTPS TFT和氧化物半导体TFT的各种组合，从而能够获得图像品质优异、且能够减小功耗的有机电致发光显示装置。
下面描述本公开的一些示例性可替代实施例。
如图6所示，现有技术中，一方面，LTPO阵列基板中为了减少掩膜板的使用，简化工艺流程，低温多晶硅薄膜晶体管的第一过孔602’和氧化物薄膜晶体管的第二过孔702’通常采用一次曝光刻蚀工艺形成，但是由于第一过孔602’的深度比第二过孔702’的深度更深，当第二过孔702’已经刻蚀完成，第一过孔602’仍有一部分未刻蚀完成，需要延长刻蚀时间以使第一过孔602’能够到达多晶硅半导体层601’，将多晶硅半导体层601’暴露出来，在继续刻蚀的过程中，第二过孔702’中继续刻蚀氧化物半导体701’，会导致氧化物半导体701’在后续的刻蚀时间中完全被刻蚀掉，进而导致氧化物薄膜晶体管的性能异常。而如果第一过孔602’和第二过孔702’通过两次工艺分别形成，则会增加掩膜板的使用数量，增大工艺复杂度，进而增加阵列基板的制作成本。另一方面，低温多晶硅薄膜晶体管在第一过孔602’形成后需要先用氢氟酸(HF)进行清洗，去除多晶硅(p-Si)表面的氧化层，再进行源极和漏极的沉积，以保证源极和漏极与多晶硅半导体层形成良好的欧姆接触，但是在采用HF对阵列基板进行清洗时，HF会与氧化物半导体层701’发生反应导致氧化物半导体701’被刻蚀掉，导致氧化物薄膜晶体管的性能异常，而如果在HF清洗之前先在第二过孔702’处形成阻挡层，HF清洗之后再去掉，同样会导致工艺复杂，成本增加。还一方面，目前阵列基板的工艺限制，导致氧化物半导体的栅极703’和栅极绝缘层704’通常通过一次工艺形成，导致栅极绝缘层704’的宽度较短，在氧化物半导体层701’导体化时，由于没有足够的栅极绝缘层704’保护，氧化物半导体沟道的有效长度会减小，会出现短沟道效 应，导致氧化物薄膜晶体管的特性不稳定。
如图7所示，根据本公开的一个方面，公开了阵列基板的一个具体实施例。本实施例中，阵列基板包括衬底S以及形成在衬底S上的低温多晶硅薄膜晶体管(LTPS TFT)和氧化物薄膜晶体管(Oxide TFT)，其中氧化物薄膜晶体管为顶栅结构。氧化物薄膜晶体管包括第二半导体图案670、第二栅极图案693、第二源漏极和第二过孔712。第二半导体图案670对应所述第二过孔712的区域覆盖有导电保护部，第二源漏极通过第二过孔712与所述导电保护部连接。其中，第二半导体图案670对应所述第二过孔712的区域覆盖有导电保护部，表示导电保护部在所述衬底S上的正投影覆盖所述第二过孔712在所述衬底S上的正投影，即导电保护部在衬底S上的正投影与第二过孔712在衬底S上的正投影交叠。低温多晶硅薄膜晶体管包括第一半导体图案620、第一过孔711、通过第一过孔711与第一半导体图案620连接的第一源漏极以及形成在第一半导体图案620上方的第一栅极图案640和第一金属图案691。
阵列基板包括形成在第二半导体图案670上的导电保护部，导电保护部包括分别位于第二半导体图案两端的第二金属图案692和第三金属图案694，在具体例子中，第二源漏极可包括第二源极723和第二漏极724，第二源极723和第二漏极724通过第二过孔712与第二金属图案692和第三金属图案694分别连接，导电保护部可实现第二源极723和第二漏极724与第二半导体图案的电连接，使氧化物薄膜晶体管正常工作，也能够防止形成第一过孔711和第二过孔712时、对两个过孔进行氢氟酸清洗时对第二半导体图案670造成损伤，通过导电保护部对第二半导体图案670进行保护，起到刻蚀阻挡的作用，从而能够使第一过孔711和第二过孔712通过一次工艺实现，第一过孔711和第二过孔712的形成可只用一个掩膜板进行图案化，能够减少掩膜板的使用数量，减少阵列基板的工艺流程，简化工艺，降低成本。本公开通过在氧化物薄膜晶体管的有源层上对应第二过孔的区域设置导电保护部，利用导电保护部对有源层进行有效保护，可实现一次构图工艺制作过孔后对第二过孔712和第一过孔711的氢氟酸清洗的正常进行，避免了氢氟酸对氧化物薄膜晶体管的有源层的影响，同时氧化物薄膜晶体管采用顶栅结构，导电保护部可与氧化物薄膜晶体管的第二栅极图案同层设置，可通过一次构图工艺形成以减少工艺步骤。
在一种实施方式中，衬底S包括第一区域600和第二区域700，可在衬底S的第一区域600形成低温多晶硅薄膜晶体管，在第二区域700形成氧化物薄膜晶体管。其中，在第一区域600形成第一半导体图案620，在第二区域700形成第二半导体图案670。
第一半导体图案620的材料可为多晶硅，用于作为低温多晶硅薄膜晶体管的有源区，第二半导体图案670的材料为氧化物，可作为氧化物薄膜晶体管的有源区。所述氧化物的材料可为氧化铟锡锌、氧化铟镓、氧化铟镓锌、氧化铟钨、氧化锌、氧化锡、氧化镓锌、氧化锌锡中的一种或多种的组合。在可选地实施方式中，氧化物薄膜晶体管可作为显示面板显示区域中像素的开关元件，而低温多晶硅薄膜晶体管可作为驱动电路的驱动元件。
在一种实施方式中，第二半导体图案670上进一步形成有第一栅绝缘层680。本公开中，由于导电保护部的设置，可减少阵列基板制作过程中的掩膜板的使用数量，从而本公开中， 第一栅绝缘层680可通过一次单独的构图工艺形成，使第一栅绝缘层680的宽度W更宽，大于设置于第一栅绝缘层680上第二栅极图案的宽度，从而避免由于第一栅绝缘层680的宽度W小而导致的短沟道效应。
在一种实施方式中，第二栅极图案693与导电保护部的材料可选用相同的金属材料，例如Al、Cr、Mo和W中的一种或多种的组合。在选用相同的金属材料时，第二栅极图案693和导电保护部可通过一次构图工艺形成，可节省工艺步骤，简化阵列基板制作流程。
在一种实施方式中，低温多晶硅薄膜晶体管可包括第一半导体图案、通过第一过孔与所述第一半导体图案连接的第一源漏极以及形成于所述第一半导体图案上方的第一栅极图案和第一金属图案。
第一栅极图案640上进一步形成有第一金属图案691，可选地，第一金属图案691可作为像素电极，用于控制像素显示。
在一种实施方式中，第一金属图案691可选用与导电保护部相同的金属材料，即同样的，第一金属图案691的材料可选用例如Al、Cr、Mo或W等金属中的一种或多种的组合。第一金属图案691可与第二栅极图案693和导电保护部同层设置，通过一次构图工艺形成，以节省工艺步骤，简化阵列基板制作流程。
本公开的阵列基板能够通过更简化的工艺同时形成低温多晶硅薄膜晶体管和氧化物薄膜晶体管，因此能够使用低温多晶硅薄膜晶体管和氧化物薄膜晶体管的各种组合，从而能够获得图像品质优异、且能够减小功耗的有机电致发光显示装置。
如图8所示，本实施例中还公开了阵列基板的制作方法，该方法包括：
S601：在衬底S的第一区域600形成第一半导体图案620。
S602：形成至少覆盖第一半导体图案620的第一绝缘层630。
S603：在第一区域600的第一绝缘层630上形成第一栅极图案640。
S604：形成覆盖第一栅极图案640的第二绝缘层650。
S605：在第二区域700的第二绝缘层650上形成第二半导体图案670。
S606：在第二半导体图案670上形成第一栅绝缘层680；
S607：通过一次构图工艺，在第一区域600形成第一金属图案691，在第二区域700形成分别位于第二半导体图案670两端的第二金属图案692和第三金属图案694以及位于第一栅绝缘层680上的第二栅极图案693。
S608：形成覆盖第一金属图案691、第二金属图案692、第三金属图案694和第二栅极图案693的第三绝缘层710。
S609：在第一区域600形成贯穿第一绝缘层630、第二绝缘层650和第三绝缘层710的第一过孔711，在第二区域700形成贯穿第三绝缘层710的第二过孔712；以及
S610：形成通过第一过孔711与第一半导体图案620连接的第一源极721和第一漏极722，形成通过第二过孔712与第二金属图案692和第三金属图案694分别连接的第二源极723和第二漏极724。
具体的，图9-图18示出本实施例中阵列基板的制作过程的剖面图。
如图9所示，在衬底S的第一区域600形成第一半导体图案620。其中，阵列基板的衬底S的材料可以是石英玻璃、无碱玻璃以及硅片、聚酰亚胺或塑料等。衬底S可具有多个第一区域600和多个第二区域700(图中仅示出各一个)，以用于能够在两个区域中分别形成不同类型的晶体管，例如氧化物薄膜晶体管作为显示区域中像素的开关元件，而低温多晶硅薄膜晶体管作为驱动电路的驱动元件。
可选地，第一半导体图案620的材料为多晶硅。其中，多晶硅半导体图案的形成可先在衬底S的第一区域600形成非晶硅(a-Si)，之后对非晶硅照射准分子激光，从而可将非晶硅转化为多晶硅。
在可选地实施方式中，在形成第一半导体图案620之前，可在衬底S上先形成柔性层611，该柔性层611的材料可选用聚酰亚胺(PI)，当阵列基板完成后，可将衬底S去除，以制成柔性显示屏。在其他实施方式中，当显示装置并非柔性显示装置时，可不设置柔性层611，本公开对此并不作限定。
在设置第一半导体图案620前，还可设置第五绝缘层612以及第一缓冲层613，绝缘层和缓冲层可起到绝缘的作用以及防止衬底S中的杂质污染第一半导体图案620。绝缘层和缓冲层的材料可选用氮化硅或氧化硅等常用的透明绝缘材料。
如图5所示，在第一半导体图案620上形成至少覆盖第一半导体图案620的第一绝缘层630。其中，第一绝缘层630至少覆盖第一半导体图案620，还可覆盖第一区域600，还可进一步覆盖第二区域700。第一绝缘层630的材料可以是氮化硅(Si3N4)，也可以是四乙氧基硅烷(TEOS)，并可利用化学气相沉积法(CVD)形成，CVD法可采用低压化学气相沉积法、热气相沉积法、催化化学气相沉积法、等离子增强化学气相沉积法等方法，本公开对此并不作限定。
如图6所示，在第一区域600的第一绝缘层630上形成第一栅极图案640。其中，第一栅极图案640的位置与第一半导体图案620对应，作为多晶硅晶体管的栅极。第一栅极图案640的材料可选用Al、Cr、Mo或W中的一种或多种形成，当采用多种金属时，通过各个金属的层叠膜等形成第一栅极图案640。第一栅极图案640可通过镀膜的方式形成，包括但不限于真空蒸镀、磁控溅射镀膜、离子溅射镀膜等镀膜工艺。
如图7所示，在第一栅极图案640上形成覆盖第一栅极图案640的第二绝缘层650。第二绝缘层650至少覆盖第一栅极图案640，并可进一步覆盖第一区域600，还可进一步覆盖第二区域700。为了保证氧化物薄膜晶体管的性能，第二绝缘层650上进一步还可形成第二缓冲层660。其中，第二绝缘层650的材料可选用氮化硅，第二缓冲层660的材料可选用氧化硅，由氧化硅形成的第二缓冲层660与氧化物薄膜晶体管直接接触。
第二绝缘层650和第二缓冲层660的形成方法与第一绝缘层630的形成方法类似。就形成氮化硅层的原料气体而言，作为氮源气体，可使用NH3、NH2H2N或N2等，优选NH3和N2，作为硅源气体，可使用SiH4、Si2H6、SiCl4、SiHCl3、SiH2Cl2、SiH3Cl3或SiF4等，优选SiH4。氮化硅层也可通过化学气相沉积方法(CVD)形成。
需要说明的是，对于低温多晶硅薄膜晶体管，由于在制作源漏电极与有源层连接的过孔 后，需要对多晶硅半导体图案通过过孔暴露出的表面进行氢氟酸清洗，同时，氢氟酸清洗后需要在小于半小时之内制作源/漏极，否则清洗后的多晶硅表面接触水汽或者空气会氧化而重新形成表面氧化物，对搭接造成影响，降低清洗效果。为了进一步节约工艺流程，降低制作成本，需要先制作第二半导体图案670(通常为氧化物半导体层，例如IGZO)，然后进行干刻蚀打孔，之后依次进行氢氟酸清洗和源、漏极沉积。因此，形成第一栅绝缘层680后，在第二区域700形成第二半导体图案670，第二半导体图案670是作为第二区域所对应晶体管的有源层，其材料可为金属氧化物，此时第二区域700所对应的晶体管为氧化物薄膜晶体管。
如图8所示，在第二区域700的第二绝缘层650上形成第二半导体图案670。第二半导体图案670的材料可选用氧化铟锌(indium zinc oxide,IZO)、氧化铟锡锌(Indium-Tin-Zinc Oxide,ITZO)、氧化铟镓(indium gallium oxide,IGO)、氧化铟镓锌(indium gallium zinc oxide,IGZO)、氧化铟钨(Indium tungsten Oxide,IWO)、氧化锌(ZnO)、氧化锡(SnO)、氧化镓锌(Gallium-Zinc Oxide,GZO)、氧化锌锡(Zinc-Tin Oxide,ZTO)中的任一种，也可以选用前述多种材料的组合。第二半导体图案670可通过镀膜的方式形成，包括但不限于真空蒸镀、磁控溅射镀膜、离子溅射镀膜等。以IGZO为例，可采用直流磁控溅射制备，其中靶材的原子比为In2O3-Ga2O3-ZnO＝1∶1∶1(摩尔比)，通过调节氧气流量、沉积功率、气体流量等参数来获得满足应用要求的IGZO薄膜。
如图9所示，在第二半导体图案670上形成第一栅绝缘层680。其中，第一栅绝缘层680部分覆盖第二半导体图案670，第一栅绝缘层680设置在第二半导体图案670的中央，以留出两侧的区域设置第二过孔712，使第二半导体图案670可与第二源极723和第二漏极724连接。本公开中，第一栅绝缘层680通过一次构图工艺形成，可通过掩膜板的形状控制第一栅绝缘层680的宽度W，从而可通过设置掩膜板，使第一栅绝缘层680的宽度W适当增大，在第二半导体图案670导体化的时候能够对第二半导体图案670进行保护，防止短沟道效应。
如图10所示，通过一次构图工艺，在第一区域600形成第一金属图案691，在第二区域700形成分别位于第二半导体图案670两端的第二金属图案692和第三金属图案694以及位于第一栅绝缘层680上的第二栅极图案693。其中，第一金属图案691、第二金属图案692、第三金属图案694和第二栅极图案693的材料可选择常温下不与氢氟酸(HF)反应或反应极慢的金属，例如Mo。
第一金属图案691位于第一区域600的第二绝缘层650上，其可充当走线，连接起不同作用的低温多晶硅薄膜晶体管，例如可作为连接开关晶体管及驱动晶体管的连线；也可与第一栅极图案640相对应，起到存储电容的作用，保持发光单元像素显示。
第二金属图案692和第三金属图案694分别形成于第二半导体图案670的两侧并与其连接，考虑到连接的稳定性，可以采用搭接的方式使第二金属图案692和第三金属图案694各自的一部分位于第二半导体图案670的侧边，同时各自的另一部分位于第二半导体图案670之上，以形成稳固的连接结构，不会轻易断路。
如图11所示，进一步形成覆盖第一金属图案691、第二金属图案692、第三金属图案694 和第二栅极图案693的第三绝缘层710。
如图12所示，形成第三绝缘层710后，在第一区域600形成贯穿第一绝缘层630、第二绝缘层650和第三绝缘层710的第一过孔711，在第二区域700形成贯穿第三绝缘层710的第二过孔712。第一过孔711将第一半导体图案620暴露出来，第二过孔712将第二金属图案692和第三金属图案694暴露出来。本公开的阵列基板中，第一过孔711和第二过孔712可通过一次构图工艺形成，工艺可选用干式刻蚀的方法同时进行。其中，干式刻蚀可选用CF系(CF4)、或者CHF系(CHF3)的气体来进行。
由于第一过孔711贯穿第一绝缘层630、第二绝缘层650和第三绝缘层710，而第二过孔712仅贯穿第三绝缘层710，从而第一过孔711的深度远远大于第二过孔712，在干式刻蚀的过程中，第二过孔712已经刻蚀至暴露出第二金属图案692和第二金属图案694时，第一过孔711仍有一部分没有刻蚀掉，需继续刻蚀以使第一过孔711能够暴露出第一半导体图案。此时，第二金属图案692和第三金属图案694能够阻挡刻蚀，防止第二半导体图案670被刻蚀掉，破坏氧化物薄膜晶体管的有源层。
形成第一过孔711和第二过孔712后，可对LTPS进行氢化工艺，以氢原子填补界面态、晶粒间界态及氧化层缺陷等，通常可采用等离子体氢化法、固态扩散法或氢离子注入法等来实施氢化工艺。
由于第一绝缘层630的材料通常为氧化硅，并且刻蚀过程中有氧气气氛容易氧化多晶硅，因此在氢化工艺后，需要对第一过孔711进行氢氟酸清洗，以去除第一过孔711中多晶硅(p-Si)表面的氧化硅及聚合物，防止氧化硅及聚合物影响后续源/漏极与多晶硅的搭接及接触，以此来保证LTPS的器件特性。由于第二过孔712仅暴露第二金属图案692和第三金属图案694，因此在进行氢氟酸清洗时，氢氟酸与第二半导体图案670不会接触，也不会进行反应，同时氢氟酸对第二金属图案692和第三金属图案694的腐蚀也很有限，不会出现将其腐蚀完全而接触第二半导体图案670的情况，因此可避免氢氟酸腐蚀氧化物半导体而造成损伤，不会影响氧化物薄膜晶体管的性能。
如图18所示，氢氟酸清洗之后，在第一区域600上形成第一源极721和第一漏极722，在第二区域700上形成第二源极723和第二漏极724。低电阻率是晶体管对源漏电极的要求，除此之外，源漏电极与半导体层形成良好的欧姆接触是晶体管对于源漏电极材料另一个重要要求，它可以降低漏源之间的电阻，防止产生电流拥挤效应。
第一源极721、第一漏极722、第二源极723和第二漏极724可利用一次构图工艺同时形成，其材料可为金属Ti、ITO等，金属Ti材料不仅与IGZO层有较好的粘附能力，并且能够减少与有源层的接触电阻，而ITO材料具有较低的电阻率，还能与IGZO有源层形成较好的欧姆接触，并且具有较好的透明度。
第一源极721和第一漏极722的一部分形成于第三绝缘层710上，并分别通过两个第一过孔711与第一半导体图案620连接；第二源极723通过一个第二过孔712与第二金属图案692连接，第二漏极724通过另一个第二过孔712与第三金属图案694连接，而第二金属图案692和第三金属图案694分别与第二半导体图案670搭接，从而实现第二源极723和第二 漏极724与第二半导体图案670的电性连接。
形成源漏电极后，可以在第三绝缘层710上进一步形成钝化层并使其覆盖源漏电极，之后可顺利进行后续工艺。
在以上说明中，以将氧化物薄膜晶体管用于显示区域、将低温多晶硅薄膜晶体管用于周边驱动电路的形式进行了说明，但根据制品规格，也可以向周边电路添加氧化物薄膜晶体管，向显示区域添加低温多晶硅薄膜晶体管。
基于相同原理，本实施例还公开了一种显示装置，该显示装置包括本实施例的阵列基板。其中，该显示装置可为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表等任何具有显示功能的产品或部件。当然，本公开的显示装置还具有常规的显示装置的外框等结构，该结构为本领域常规技术手段，在此不再赘述。
本实施例通过在氧化物薄膜晶体管的有源层上对应第二过孔的区域设置导电保护部，利用导电保护部对有源层进行有效保护，可实现一次构图工艺制作过孔后氢氟酸清洗的正常进行，避免了氢氟酸对氧化物薄膜晶体管的有源层的影响，同时简化了制作流程，进而降低生产成本，同时，氧化物薄膜晶体管采用顶栅结构，导电保护部可与氧化物薄膜晶体管的第二栅极图案同层设置，可通过一次构图工艺形成以减少工艺步骤。
本公开的显示装置包括上述阵列基板，该显示装置可为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本公开的显示装置还具有常规的显示装置的外框等结构。
本领域技术人员应当注意的是，本公开所描述的实施方式仅仅是示范性的，可在本公开的范围内作出各种其他替换、改变和改进。因而，本公开不限于上述实施方式，而仅由权利要求限定。

Claims (20)

  1. 一种阵列基板的制造方法，所述阵列基板包括衬底，所述衬底包括第一区域和第二区域，所述制造方法包括：
    在所述第一区域形成第一半导体图案；
    形成至少覆盖所述第一半导体图案的第一绝缘层；
    分别在所述第一区域和所述第二区域形成彼此隔离的第一栅极图案和第二栅极图案；
    形成至少覆盖所述第一栅极图案的第二绝缘层；
    在所述第二区域形成第二半导体图案；
    通过一次成膜工艺，在所述第一区域形成第一金属图案，在所述第二区域形成分别与所述第二半导体图案搭接的第二金属图案和第三金属图案；
    形成至少覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案的第三绝缘层；
    在所述第一区域形成贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的第一过孔，在所述第二区域形成贯穿所述第三绝缘层的第二过孔；以及
    形成第一源极和第一漏极、第二源极和第二漏极，
    其中，所述第一源极和所述第一漏极分别通过所述第一过孔与所述第一半导体图案连接，所述第二源极和所述第二漏极分别通过所述第二过孔与所述第二半导体图案连接。
  2. 如权利要求1所述的阵列基板的制造方法，其中，所述第一栅极图案与所述第二栅极图案同层设置，并且其中，所述第二绝缘层覆盖所述第一栅极图案和所述第二栅极图案。
  3. 如权利要求1所述的阵列基板的制造方法，还包括在所述第二半导体图案上形成第一栅绝缘层，其中，所述第二栅极图案位于所述第一栅绝缘层上，并且其中，所述第三绝缘层覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案、所述第一栅绝缘层和所述第二栅极图案。
  4. 如权利要求2或3所述的阵列基板的制造方法，其中，所述第一半导体图案的材料为多晶硅，其中，所述第二半导体图案的材料为氧化铟锌、氧化铟锡锌、氧化铟镓、氧化铟镓锌、氧化铟钨、氧化锌、氧化锡、氧化镓锌、氧化锌锡中的一种或多种的组合。
  5. 如权利要求2或3所述的阵列基板的制造方法，其中，所述第二源极通过所述第二过孔与所述第二金属图案连接，所述第二漏极通过所述第二过孔与所述第三金属图案连接。
  6. 如权利要求5所述的阵列基板的制造方法，其中，形成所述第一过孔和所述第二过孔的工艺包括：
    在同一次曝光工艺中，形成所述第一过孔和所述第二过孔；以及
    对所述第一过孔和所述第二过孔进行氢氟酸清洗。
  7. 一种阵列基板，包括：
    衬底，所述衬底包括第一区域和第二区域；
    第一半导体图案，位于所述第一区域；
    第一绝缘层，至少覆盖所述第一半导体图案；
    彼此隔离的第一栅极图案和第二栅极图案，分别设置于所述第一区域和所述第二区域；
    第二绝缘层，至少覆盖所述第一栅极图案；
    第一金属图案，位于所述第一区域的所述第二绝缘层上；
    第二半导体图案，位于所述第二区域的所述第二绝缘层上；
    第二金属图案和第三金属图案，位于所述第二区域并分别与所述第二半导体图案搭接；
    第三绝缘层，至少覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案；
    第一过孔，位于所述第一区域并贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层；
    第二过孔，位于所述第二区域并贯穿所述第三绝缘层；
    第一源极和第一漏极，以及
    第二源极和第二漏极；
    其中，所述第一源极和所述第一漏极分别通过所述第一过孔与所述第一半导体图案连接，所述第二源极和所述第二漏极分别通过所述第二过孔与所述第二半导体图案连接。
  8. 如权利要求7所述的阵列基板，其中，所述第一栅极图案与所述第二栅极图案同层设置，并且其中，所述第二绝缘层覆盖所述第一栅极图案和所述第二栅极图案。
  9. 如权利要求8所述的阵列基板，其中，所述第一半导体图案的材料为多晶硅，其中，所述第二半导体图案的材料为氧化铟锡锌、氧化铟镓、氧化铟镓锌、氧化铟钨、氧化锌、氧化锡、氧化镓锌、氧化锌锡中的一种或多种的组合。
  10. 如权利要求7所述的阵列基板，其中，所述第二源极通过所述第二过孔与所述第二金属图案连接，所述第二漏极通过所述第二过孔与所述第三金属图案连接。
  11. 如权利要求7所述的阵列基板，其中，所述第一金属图案、所述第二金属图案和所述第三金属图案的材料相同。
  12. 如权利要求6所述的阵列基板，还包括位于所述第二半导体图案上的第一栅绝缘层，其中，所述第二栅极图案位于所述第一栅绝缘层上，并且其中，所述第三绝缘层覆盖所述第二半导体图案、所述第一金属图案、所述第二金属图案和所述第三金属图案、所述第一栅绝缘层和所述第二栅极图案。
  13. 根据权利要求12所述的阵列基板，其中，所述第二金属图案和所述第三金属图案在所述衬底上的正投影覆盖所述第二过孔在所述衬底上的正投影。
  14. 根据权利要求12所述的阵列基板，其中，所述第二金属图案和所述第三金属图案 与所述第二栅极图案同层设置。
  15. 根据权利要求12所述的阵列基板，其中，所述第一栅绝缘层的宽度大于所述第二栅极图案的宽度。
  16. 根据权利要求12所述的阵列基板，其中，所述第一半导体图案、所述第一过孔、通过所述第一过孔与所述第一半导体图案连接的所述第一源极和所述第一漏极以及形成于所述第一半导体图案上方的所述第一栅极图案和所述第一金属图案组成低温多晶硅薄膜晶体管。
  17. 根据权利要求16所述的阵列基板，其中，所述第一金属图案与所述第二金属图案和所述第三金属图案和所述第二栅极图案同层设置。
  18. 根据权利要求16所述的阵列基板，其中，所述第一金属图案与所述第二金属图案和所述第三金属图案和所述第二栅极图案的材料相同。
  19. 根据权利要求12所述的阵列基板，其中，所述第二半导体图案的材料为氧化铟锡锌、氧化铟镓、氧化铟镓锌、氧化铟钨、氧化锌、氧化锡、氧化镓锌、氧化锌锡中的一种或多种的组合。
  20. 一种显示装置，其中，所述显示装置包括如权利要求6至19中任一项所述的阵列基板。
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