WO2019102392A1

WO2019102392A1 - Method and system for frequency compression

Info

Publication number: WO2019102392A1
Application number: PCT/IB2018/059220
Authority: WO
Inventors: Frederik Viljoen MINNAAR
Original assignee: Council for Scientific and Industrial Research CSIR
Current assignee: Council for Scientific and Industrial Research CSIR
Priority date: 2017-11-22
Filing date: 2018-11-22
Publication date: 2019-05-31
Anticipated expiration: 2020-05-22
Also published as: ZA202005163B; NL2019958B1

Abstract

The invention relates to a method and system compression of a wide frequency range into a lower and narrower range. In particular, the invention relates to a method for frequency band compression of signals, wherein the method comprises receiving an input signal having a frequency within a first frequency band; and processing the received input signal digitally by way of at least one digital frequency divider to generate an output signal, wherein the output signal falls within a second frequency band which is narrower than the first frequency band. The invention extends to a system comprising a receiver; and a digital frequency divider coupled thereto, wherein the digital frequency divider is configured to process the received input signal digitally to generate an output signal of a lower frequency than the received input signal, wherein the output signal falls within a second frequency band being narrower than the first frequency band.

Description

METHOD AND SYSTEM FOR FREQUENCY COMPRESSION

FIELD OF INVENTION

THIS INVENTION relates to methods and systems for frequency compression, particularly to methods and systems for compression of a wide frequency range into lower and narrower ranges that are more manageable, for example, for use, though not necessarily exclusively, in electronic warfare applications, as well as wideband frequency/phase modulated communication applications.

BACKGROUND OF THE INVENTION

Most Radar Warning (RW), Electronic Countermeasures (ECM), and Electronic Intelligence (ELINT) systems employ wide instantaneous bandwidth subsystems with the main objective to provide situational awareness, and measurement of emitter identifier attributes such as angle of arrival, signal form, frequency, timing and such, and allow for intelligent and fast response against or in cooperation of such emitter. Examples of such subsystems referred to above may be in the form of instantaneous frequency measurement (IFM) systems, and phase detectors to measure phase from an antenna array to determine angle of arrival of a signal to identify threats, map the electronic battlefield and eventually implement deceptive countermeasures.

Another application may be found in the field of wideband frequency or phase coded communication in the military or commercial fields such as internet and cellphone networks where the available frequency spectrum is rapidly becoming exhausted.

Due to the wide frequency ranges encountered by the aforementioned systems, the processing of received signals, for example, by the aforementioned subsystems is often computationally and resource exhaustive. Moreover, a problem exists with similar component behavior over increasingly large bandwidth, which problem poses reduced options in the design of systems as described above, particularly with respect to available elements to use in the design, extreme increase in cost, and end user restrictions for such elements, reliability and additional care to ensure operation over, and match between such elements.

One approach to be able to process signals received in such wide frequency bandwidths is by the compression of incoming frequencies into a reduced more manageable frequency range by way of analogue frequency dividers or prescalers. Resultant scaled signals from these frequency dividers are then further processed by less expensive means. A scheme of this type is described in US 4,859,934 A. However, such analogue prescalers are unpractical since it relies on resonant properties of such analogue prescalers, which restricts the usable input frequency range of such analogue prescalers to only an integer fraction of input frequency, for example, at a ratio of 2:1 .

The Inventor is also aware of prior art technologies such as those disclosed in EP 1560 335 A2 which is related to frequency synthesizers which use mixer elements to translate frequencies to other frequencies of the same bandwidth.

Another prior art technology is described in US 5,640,694 and relates to wideband signal receivers. In this prior art document, a receiver selects a smaller portion of a wide band and translates it to a common intermediate frequency band. This problematically leaves the receiver blind to the majority of the wide input band while processing only the smaller selection thereof which of course results in valuable data lost. Moreover, EP 2905 902 A1 relates to the simplified synthesis of digital frequencies and transmitter signals to the relatively narrow high power transmitter frequency band.

Apart from the problem/s associated with analogue prescalers mentioned above, the Inventor has noted that none of the prior art mentioned above discloses compression of a frequency band from a wideband to a more manageable narrow band in the manner contemplated herein.

It is therefore an object of the present invention at least to address the aforementioned problems and/or shortcomings of the aforementioned prior art and to provide a means to facilitate compression of an entire wide frequency band to a more narrower frequency band.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, there is provided a method for frequency band compression of signals, wherein the method comprises: receiving an input signal having a frequency within a first frequency band; forcing the at least one digital frequency divider to a predetermined phase state; and processing the received input signal digitally by way of at least one digital frequency divider, at the predetermined phase state, to generate an output signal, wherein the output signal falls within a second frequency band which is narrower than the first frequency band

The step of forcing the at least one frequency divider to a predetermined phase state may comprise one or both of resetting the at least one digital frequency divider, and switching the at least one digital frequency divider to an ON state. In particular, in the case of the latter, the method may comprise briefly switching the at least one frequency divider briefly OFF and then ON. This step may be advantageously taken so as to avoid the phase ambiguity normally resultant of such digital prescaling action. In particular, in digital circuit design this step may not be important but when used as part of an analogue phase detector or IFM the usual random "wakeup" phase state of the digital frequency divider must be avoided or overcome in order to ensure unambiguous measurements. It follows that the step of forcing the at least one frequency divider to a predetermined phase state may be important to the phase measurement functionality described herein.

This would of course be of importance in, for example, EW, applications but not necessarily so in prior art applications such as frequency synthesizers, etc. and schemes that merely seeks to avoid complexity in transmission signals.

As will be elaborated below, when the output of two independent frequency divided signals are compared and the phase states of each signal is ambiguous, then the compared phase at the outputs is also ambiguous. This is an inherent problem when using these technologies together as will be described below. Moreover, digital frequency dividers were not designed to be used in the analogue world and the forcing of the same to a predetermined or“known” state makes it work in the case where the processed signals phase state is vital to its desired performance.

The method may comprise synchronizing the phase state of the at least one digital frequency divider with a leading edge of the received input signal. The step of forcing the at least one frequency divider to a predetermined phase state may be triggered immediately prior to receipt of the leading edge of the received input signal by the at least one digital frequency divider.

The method may comprise generating a trigger signal and transmitting the same to the at least one digital frequency divider. The trigger signal may be configured to force the at least one digital frequency divider to a predetermined phase state.

The method may comprise preventing compressing of the received input signal by the at least one digital frequency divider until the trigger signal is generated and transmitted. It will be appreciated that this step may be advantageously taken so as to avoid the digital prescaling circuitry to assume a random phase state by the time that the signal of interest arrives for processing thereby.

According to a second aspect of the invention, there is provided a system for frequency band compression of signals, wherein the system comprises: a receiver module configured to receive an input signal having a frequency within a first frequency band; at least one digital frequency divider communicatively coupled to the receiver module, wherein the at least one digital frequency divider is configured to process the received input signal digitally to generate an output signal of a lower frequency than the received input signal, wherein the output signal falls within a second frequency band which is narrower than the first frequency band; and a conditioning arrangement comprising a trigger module configured to force the at least one digital frequency divider to a predetermined phase prior to operation of the at least one digital frequency divider.

The conditioning arrangement may be communicatively coupled to one or both of the receiver module and the at least one digital frequency divider.

The trigger module may be configured to force the at least one frequency divider to a predetermined phase state by one or both of resetting the at least one digital frequency divider, and switching the at least one digital frequency divider to an ON state. In particular, the trigger module may be configured, in the case of the latter, to first switch the at least one digital frequency divider OFF state (briefly) then to the ON state.

The trigger module may be configured to synchronize the phase state of the at least one digital frequency divider with a leading edge of the received input signal such that the at least one frequency divider is forced to a predetermined phase state by the trigger module immediately prior to the receipt of the leading edge of the received signal by the at least one digital frequency divider.

The trigger module may be configured to generate a trigger signal and transmitting the same to the at least one digital frequency divider, wherein the trigger signal is configured to force the at least one digital frequency divider to a predetermined phase state. The conditioning arrangement may comprise an input gate switch communicatively coupled to the receiver module, trigger module and the at least one digital frequency divider, wherein the input gate switch is operable by the trigger signal to allow the received input signal to be transmitted from the receiver module to the at least one digital frequency divider.

It will be understood that for the purposes of clarity the term“band” may be used interchangeably with the term“bandwidth” being a range of frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a high level schematic illustration of a system in accordance with an example embodiment of the invention;

Figure 2 shows a low level schematic illustration of a system in accordance with an example embodiment of the invention;

Figure 3 shows a flow diagram of a method in accordance with an example embodiment of the invention; and

Figure 4 shows an example timing diagram illustrating operation of the system in accordance with an example embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of an embodiment of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure may be practiced without these specific details. Referring to Figures 1 and 2 of the drawings, a system for frequency band compression of received signals is generally indicated by reference numeral 10. The system 10 typically finds application in instantaneous bandwidth subsystems found for example, in Radar Warning (RW), Electronic Countermeasures (ECM), and Electronic Intelligence (ELI NT) systems, or collectively referred to as Electronic Warfare (EW) systems. However, it will be appreciated by those skilled in the field of invention that nothing precludes the use of the system 10 and the principles referred to herein in other systems, not related to EW, for example, wideband communication applications, such as cellphone or internet networking systems.

In any event, the system 10 typically comprises a receiver module 12, a conditioning arrangement 14, and a digital frequency divider or prescaler 16 communicatively coupled, for example, in a hardwired fashion. The receiver module 12 may be in the form of an electrical interface configured to receive input signal of a frequency in a first frequency range, for example in a traditional wideband EW band of 2 - 18 GHz. The input signal may be an electromagnetic signal wirelessly received by the module 12 via a suitable wireless antennas or detectors (not shown), as will be understood by those skilled in the art. It will be appreciated that the system 10 may receive and process a time multiplexed plurality of input signals in a continuous fashion modulated in phase and/or frequency or not but for ease of explanation, reference will be made herein to the system 10 receiving and processing a single input signal.

The conditioning arrangement 14 is communicatively and operatively interposed between the receiver module 12 and the digital frequency divider 16. The digital frequency divider or digital prescaler 16 may be a conventional digital n-times digital divider 16 making use of digital gate technology which must be capable to process an input signal frequency range of at least that of the receiver module 12. It will be noted that for brevity reference herein to“digital frequency divider” and “prescaler” will be understood to refer to the same thing. Though one divider 16 is illustrated, it will be understood that in some example embodiments (not described further), a plurality of digital dividers 16 may be utilized, for example, in a cascaded fashion to achieve frequency band compression as described herein. However, in other example embodiments the divider 16 is a suitable programmable digital frequency diver 16. It will be appreciated that in the case of multiple cascaded digital prescaler devices, all of the devices must be simultaneously reset to a known phase state at the triggering command or in response to receipt of the trigger signal generated as described herein.

The digital divider 16 may be configured to effectively receive an input signal and process the same to output an output signal having a lower frequency and in a reduced frequency band than the input frequency band. To this end, the divider 16 may be configured to digitally divide the frequency of the received input signal by a predetermined value, n. Differently defined, the divider 16 may be configured to compress/down convert/down scale a received input signal in the first frequency band to an output signal having a lower frequency in the second lower or compressed frequency band.

The predetermined value, n, may be an integer value selected based on the desired compressed second frequency band. For example, if the first frequency band is between 2 and 18 GHz and the desired compressed second frequency band is between 1 and 9 GHz, then the predetermined value associated with the digital frequency divider 16 is an integer value n of 2, i.e., n = 2.

This is convenient because steps of measuring signal parameters from a 2-18 GHz frequency range is significantly more difficult than a 1 - 9 GHz range.

Despite the benefits mentioned, it will be understood by those skilled in the art that digital frequency dividers 16 suffer from digital memory and uncertain phase status causing random phase error when separately prescaled output signals therefrom are phase compared. In the absence of an input signal, digital frequency dividers tend to be sensitive to spurious input signals such as noise even when an input port thereof is properly terminated. In this condition, the digital divider either oscillates at some natural frequency, or assumes a phase state in an unpredictable way so that the state of the prescaler 16 is uncertain when the input signal arrives at the input port thereof.

By way of background, and as alluded to above, n-times digital prescalers can assume any of 2tt/h radiants of phase states whenever the input signal arrives at the input port thereof, emulating a number of n phase offset ambiguities to the prescaled output signal. Independently prescaled signals can therefore not be phase compared unless these ambiguities can either be avoided or resolved.

In this regard, though there may be similar but different circuitry that addresses the same problem, by way of example of a suitable solution the simple the conditioning arrangement 14 seeks to address the drawbacks associated with the use of digital prescalers. Though it is described collectively for ease of description, the arrangement 14 is comprised of a trigger module 18 and a noise-and spurious input gate switch as illustrated in Figure 2. In this regard, it will be noted that though not illustrated and/or described in great detail, it will be understood by those skilled in the field of invention that the system 10 and/or the components associated therewith may comprise suitable electronic components and/or circuitry, for example, driver and biasing circuitry, as the case may be to realise the system 10 as described herein. Moreover, unless specifically indicated (e.g., the digital prescaler 16), certain components making up the system 10 may be digital, analogue, or a combination thereof. The trigger module 18 is coupled to the prescaler 16, for example, via a suitable hardwired connection and is configured to force the digital frequency divider 16 to a predetermined phase state (a known state) prior to operation of the frequency divider 16. To this end, the trigger module 18 comprises suitable electronic components (e.g., resistor/s, capacitor/s, comparator/s, gate/s, etc.) configured to generate a trigger signal or also referred to as a“prescaler reset signal” or“divider reset signal” which is used to operate or control the prescaler 16 to reset, power OFF/ON, or the like prior to the processing of a received input signal by the prescaler 16. It will be understood that the trigger module 18 generates the“divider reset” signal in Figure 4 using a suitable NAND gate fast enough to meet the demand of the very fast rise and fall times as well as the short time that it remains in the“divider reset” state.

The NAND gate produces a digital output by comparison of the states of the NAND gate’s two input ports. The NAND gate produces a digital high or“1” output in all cases except for the case where both the input signals to the NAND gate are high or “1”, in which case the output of the NAND gate will be low or“0”. The two inputs of the NAND gate are fed with the same clock signal, except for the one input of the NAND gate having a digital inverter to ensure that the two input signals to the NAND gate are different in the steady state. The combination of the resistor R and capacitor C shown in Figure 2 effectively delays the signal with a time constant RC equal to the "divider reset" time, which delay causes a transitional situation whereby the fast NAND gate input signals are both high or "1 ", causing the NAND gate to generate the short "divider reset" signal immediately after the clock rising edge. It will be noted that an output from the trigger module 14 supplying the generated trigger signal may be connected to a suitable power/reset/clear pin associated with the prescaler 16.

The clock rising edge shown as an upwards arrow in the first graph of Figure 4, drives the trigger module 14 to generate the short "divider reset" signal in the second graph. The third graph shows a system related indication of when the output of the frequency dividing prescaler 16 output performs a correct output function, taking into account the frequency divider "reset" and "OFF" state when it is inoperative, and also accounting for a 5 ns (by example, in Figure 4) latency whereby the prescaler 16 performs the internal prescaling of the signal leading edge and present it to the output, whereafter the function continues until the following leading edge of the clock. As will be appreciated by those skilled in the field of invention, the "divider reset" and latency times are to be determined in a practical manner or by calculation, and depends purely on the specific properties of the prescaler 16 used. The clock rate and "divider reset" and latency times must be designed for to allow acceptable prescaler data throughput as required by the greater system.

It will be noted that an external clock synchronizes measurement updated with the leading edge of the clock, in this case 20ns (Figure 4). Though not illustrated, in some example embodiments, the clock referred to may form part of the system 10 described herein. In any event, the prescaler 16 is reset by the trigger module 14 which generates the trigger signal or also referred to as a prescaler reset signal, to reset the prescaler 16 in a predetermined state within 2ns just after the clock rise time. At the same time the switch 20 isolates any possible input noise and other spurious input that may confuse the prescaler 16 at the time of reset, so that the prescaler 16 is in a known phase state at the end of the 2ns period. Assuming that the clock is properly synchronized with an input signal, the prescaler 16 will then perform the frequency division with some latency, shown in the bottom graph of Figure 4, which latency is shown to be 5ns by way of example. By way of further example, two or more independently prescaled signals from different antenna elements will then be synchronized in phase and true phase interferometry may be performed.

The input gate switch 20 is communicatively coupled to the receiver module 12, trigger module 14, and the digital frequency divider 16. The input gate switch 20 is a normally closed switch operatively connected to the input port of the prescaler 16. The input gate switch 20 is operable, or in other words controllable, by the trigger signal generated by the trigger module 14 to open from a normally closed condition so as to isolate the received input port of the prescaler 16 from the receiver module 12 to the digital prescaler 16 at the same time as the prescaler 16 is being forced to a predetermined known state by way of the trigger signal.

Reference is now made to Figure 3 of the drawings where a block flow diagram of a method in accordance with the invention is generally indicated by reference numeral 30. Though reference will be made to Figures 1 , 2, and 4 in the explanation of the method 30, it will be noted that the method 30 may be applied to other systems not described herein.

The method 30 may proceed in a subsystem forming part of a system in an EW or communications applications as described above. The method 30 comprises, the step of receiving, at block 32 via the module 12, an input electromagnetic signal having a first frequency in a first frequency range.

The method 30 comprises forcing the digital prescaler 16, at block 34 via the module 14, to a predetermined phase state by generating and transmitting a trigger signal to the prescaler 16 to reset/power OFF/ON/clear the prescaler 16 in a manner as described above. The method 30 simultaneously comprises, also at block 34, transmitting the generated trigger signal to the input gate switch 20 provided at the input port of the prescaler 16 so as to open the same. In this way, the received input port is isolated from the prescaler 36 for processing as described in step 36 below. This triggering step to reset the prescaler into a known phase state must be very short in comparison to the desired signal duration, typically consuming the rise and settling time of the signal only.

The method 30 then comprises processing the received input signal digitally, at block 36 by way of the digital prescaler 16, to generate an output signal of a lower frequency than the received input signal, wherein the output signal falls within a second frequency band which is narrower than the first frequency band. With reference to Figure 2, with the input frequency in a first frequency range of between 2 to18 Ghz, the prescaler 16 is preconfigured to divide the input frequency of incoming signals by an integer value n of 4 so as to realise a second frequency range of 0.5 - 4.5 GHz, i.e. (2 to 18 Ghz)/ (n = 4), wherein the second frequency range is lower and more compressed than the first frequency range by a factor of 4.

The output signals from the prescaler 16 are then further processed with conventional components. In this way, the system as described herein compresses input signals to a manageable frequency range which reduced hardware complexity, size, and cost of processing equipment. In this way, labour associated in construction, repair, and calibration of a wide range of analogue application is reduced. It will be appreciated that another application of the invention as disclosed herein may be found in the field of wideband frequency or phase coded communication in the military or commercial fields such as internet and cellphone networks where the available frequency spectrum is rapidly becoming exhausted.

The present invention effectively allows compression of the entire extreme wide band to a more manageable narrow frequency band so that all of the band can be processed at the same time.

By using digital prescalers as described herein, one is able to compress analogue signals and overcome the limitation of having to rely on the resonant properties of the analogue prescalers, effectively enabling the present invention cope with input bandwidths of approximately 36:1 and more, such as needed for the modern electronic warfare band of 0.5 to 18 GHz. This enables a single receiver to comfortably compress the entire electronic warfare band into as little as 1 GHz for instantaneous and simultaneous processing. Moreover, it will be noted that the Inventor realizes that commercially available prescalers or frequency dividers were developed and may be found widely on the open market for the purpose of, for instance, frequency synthesizer instrumentation or phase locked loop elements where the initial phase state of the divided frequency is unimportant. However, it is important to note that the invention described herein relates to cases where the initial phase state of the divided frequency or band of frequencies is vital to the successful operation, and must be forced to be predetermined and consistent, in order to for instance compare phase to another channel of signals without ambiguity, such as for instance in phase comparison components.

Claims

1 . A method for frequency band compression of signals, wherein the method comprises: receiving an input signal having a frequency within a first frequency band ; forcing the at least one digital frequency divider to a predetermined phase state; and processing the received input signal digitally by way of at least one digital frequency divider, at the predetermined phase state, to generate an output signal, wherein the output signal falls within a second frequency band which is narrower than the first frequency band.

2. A method as claimed in claim 1 , wherein the step of forcing the at least one frequency divider to a predetermined phase state comprises one or both of resetting the at least one digital frequency divider, and switching the at least one digital frequency divider first to an OFF state and then to an ON state.

3. A method as claimed in either claim 1 or 2, wherein the method comprises synchronizing the phase state of the at least one digital frequency divider with a leading edge of the received input signal, wherein the step of forcing the at least one frequency divider to a predetermined phase state is triggered immediately prior to receipt of the leading edge of the received input signal by the at least one digital frequency divider.

4. A method as claimed in any one of claims 1 to 3, wherein the method comprises generating a trigger signal and transmitting the same to the at least one digital frequency divider, wherein the trigger signal is configured to force the at least one digital frequency divider to a predetermined phase state.

5. A method as claimed in claim 4, wherein the method comprises preventing processing of the received input signal by the at least one digital frequency divider until the trigger signal is generated and transmitted.

6. A system for frequency band compression of signals, wherein the system comprises: a receiver module configured to receive an input signal having a frequency within a first frequency band; at least one digital frequency divider communicatively coupled to the receiver module, wherein the at least one digital frequency divider is configured to process the received input signal digitally to generate an output signal of a lower frequency than the received input signal, wherein the output signal falls within a second frequency band which is narrower than the first frequency band; and a conditioning arrangement comprising a trigger module configured to force the at least one digital frequency divider to a predetermined phase prior to operation of the at least one digital frequency divider.

7. A system as claimed in claim 6, wherein the conditioning arrangement is communicatively coupled to one or both of the receiver module and the at least one digital frequency divider.

8. A system as claimed in claim 7, wherein the trigger module is configured to force the at least one frequency divider to a predetermined phase state by one or both of resetting the at least one digital frequency divider, and switching the at least one digital frequency divider first to an OFF state then to an ON state.

9. A system as claimed in any one of claims 6 to 8, wherein the trigger module is configured to synchronize the phase state of the at least one digital frequency divider with a leading edge of the received input signal such that the at least one frequency divider is forced to a predetermined phase state by the trigger module immediately prior to the receipt of the leading edge of the received signal by the at least one digital frequency divider.

10. A system as claimed in any one of claims 6 to 9, wherein the trigger module is configured to generate a trigger signal and transmitting the same to the at least one digital frequency divider, wherein the trigger signal is configured to force the at least one digital frequency divider to a predetermined phase state.

1 1 . A system as claimed in claim 10, wherein the conditioning arrangement comprises an input gate switch communicatively coupled to the receiver module, trigger module and the at least one digital frequency divider, wherein the input gate switch is operable by the trigger signal to allow the received input signal to be transmitted from the receiver module to the at least one digital frequency divider.

12. A system as claimed in any one of claims 6 to 1 1 , wherein the at least one digital frequency divider is configured to divide the frequency of the received input signal by a predetermined integer value.