WO2019188174A1 - Information processing device - Google Patents

Abstract

This information processing device is provided with: a process execution unit (102) that executes a process on the basis of data stored in a local memory and a global memory; and an address conversion unit (101) that executes an address conversion process for converting the address of an access destination in response to the process execution performed by the process execution unit (102).

Description

Information processing device Cross-reference of related applications

This application is based on Japanese Patent Application No. 2018-068428 filed on March 30, 2018, and claims the benefit of its priority. Which is incorporated herein by reference.

The present disclosure relates to an information processing apparatus that can access both a local memory that it occupies and a global memory that is shared with other information processing apparatuses.

As an information processing apparatus that can access both a local memory owned by itself and a global memory shared with other information processing apparatuses, an apparatus described in Patent Document 1 is disclosed. In the following Patent Document 1, the computer unit includes a heterogeneous mixing unit of a central processing unit (CPU) and a graphic processing unit (GPU). The system creates a subbuffer from the parent buffer for each of the plurality of heterogeneous computer units. If the subbuffer is not associated with the same computer unit as the parent buffer, the system copies the data from the subbuffer to the memory of that computer unit. The system further tracks updates to the data and forwards these updates to the subbuffer.

Special table 2013-528861 gazette

In Patent Document 1, a parent buffer and a sub buffer are associated with each other, and the parent buffer and the sub buffer are updated so as to be synchronized. If data is frequently written and read between the local memory and the global memory in this way, the data transfer time between the local memory and the global memory becomes a bottleneck, which affects the processing speed.

The present disclosure provides an information processing apparatus capable of accessing both a local memory owned by itself and a global memory shared with another information processing apparatus and capable of further speeding up the processing. The purpose is to do.

The present disclosure is an information processing apparatus capable of accessing both a local memory owned by itself and a global memory shared with another information processing apparatus, and performs processing based on data stored in the local memory and the global memory. And an address conversion unit for executing an address conversion process for converting the address of the access destination with respect to the execution of the process of the process execution unit.

Because the address conversion process that converts the address of the access destination for the execution of the process of the process execution unit is executed, only the data required by the process execution unit can be accessed, and the processing can be further speeded up. It becomes.

FIG. 1 is a diagram for explaining parallel processing which is a premise of the present embodiment. FIG. 2 is a diagram showing a system configuration example for executing the parallel processing shown in FIG. FIG. 3 is a diagram illustrating a graph structure for illustrating an example of processing according to the present embodiment. FIG. 4 is a diagram for explaining processing of the accelerator according to the present embodiment. FIG. 5 is a diagram for explaining a write state of the local memory and the global memory. FIG. 6 is a diagram for explaining a write state of the local memory and the global memory. FIG. 7 is a diagram for explaining processing of an accelerator as a comparative example. FIG. 8 is a diagram for explaining a write state of the local memory and the global memory in the comparative example.

Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate the understanding of the description, the same constituent elements in the drawings will be denoted by the same reference numerals as much as possible, and redundant description will be omitted.

FIG. 1A shows a program code having a graph structure, FIG. 1B shows a thread state, and FIG. 1C shows a state of parallel processing.

As shown in FIG. 1A, the program to be processed in this embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.

1) When automatic vectorization and graph structure extraction are performed on the program code shown in FIG. 1A by a compiler, a large number of threads as shown in FIG. 1B can be generated.

1) Parallel execution as shown in FIG. 1C can be performed on a large number of threads shown in FIG. 1B by dynamic register placement and thread scheduling by hardware. By dynamically allocating register resources during execution, a plurality of threads can be executed in parallel for different instruction streams.

Next, a system configuration example including an accelerator 10 that performs dynamic register allocation and thread scheduling will be described with reference to FIG.

The accelerator 10 constitutes an information processing system together with the host CPU 12 and the global memory 14. The host CPU 12 is an arithmetic unit that mainly performs data processing. The host CPU 12 supports the OS.

The global memory 14 has three memory areas, buf0, buf1, and buf2. The global memory 14 reads and writes data according to accesses from the CPU 12 and the accelerator 10.

The accelerator 10 is positioned as an individual master provided to cope with the heavy computation load of the host CPU 12. The accelerator 10 includes an address conversion unit 101, an execution core 102, and a local memory 103.

The address conversion unit 101 is a part that executes an address conversion process for converting the address of the access destination with respect to the execution of the process of the execution core 102 that is the process execution unit. When the data required for processing by the execution core 102 that is the processing execution unit is not stored in the local memory 103, the address conversion unit 101 transfers the execution core 102 that is the processing execution unit from the global memory 14 to the local memory 103. The address conversion process is executed so that the data is transferred. The address conversion unit 101 monitors a situation in which the host CPU 12 that is another information processing apparatus accesses the global memory 14, and when there is no data required for the global memory 14, On the other hand, an address conversion process is executed so that data is transferred from the local memory 103 to the global memory 14.

The execution core 102 corresponds to the processing execution unit of the present disclosure, and is a part that executes processing based on data stored in the local memory 103 and the global memory 14.

The local memory 103 has three memory areas, buf0, buf1, and buf2. The local memory 103 accepts only access from the execution core 102, and reads and writes data.

As described above, the accelerator 10 according to the present embodiment is an information processing apparatus according to the present disclosure, and is used for both the local memory 103 owned by the accelerator 10 and the global memory 14 shared with the host CPU 12 that is another information processing apparatus. Execution of the processing of the execution core 102, which is a process execution unit that can be accessed and executes processing based on the data stored in the local memory and the global memory, and the execution core 102 that is the processing execution unit And an address conversion unit 101 that executes an address conversion process for converting an access destination address.

Subsequently, processing of the accelerator 10 will be described with reference to FIGS. 3, 4, 5, and 6. FIG. 3 is a diagram illustrating a graph structure of a program used for explanation. In the example shown in FIG. 3, the processing of Graph1 is executed using the data stored in buf0, and the result is stored in buf1. Subsequently, the processing of Graph2 is executed using the data stored in buf1, and the result is stored in buf2. The description will be continued on the premise of such processing.

FIG. 4 is a sequence diagram when the processing as shown in FIG. 3 is executed. FIG. 5 is a diagram showing the status of the global memory 14 and the local memory 103 when the processing shown in FIG. 4 is performed.

As shown in FIG. 4, the host CPU 12 instructs the accelerator 10 to execute Graph 1 (step S001). As shown in FIG. 5A, at this time, no data is stored in the local memory 103, and data001 is stored in buf 0 of the global memory 14.

In response to the execution instruction in step S001, the address conversion unit 101 determines whether buf0 data is stored in the local memory 103 (step S101). If buf0 data is stored in the local memory 103, the process proceeds to step S104. If buf0 data is not stored in the local memory 103, the process proceeds to step S102.

As shown in FIG. 5A, at this time, if data is not stored in the local memory 103, the process of step S102 is executed. In step S <b> 102, the address conversion unit 101 outputs an instruction to read the buf <b> 0 data from the global memory 14 and write it to the local memory 103 to the execution core 102.

In response to this instruction, the execution core 102 reads the data of buf0 from the global memory 14 and writes it in the local memory 103 (step S201). As shown in FIG. 5B, data001 is also stored in buf0 of the local memory 103.

Subsequently, an execution instruction for Graph1 is output from the address conversion unit 101 to the execution core 102 (step S103). In response to this instruction, the execution core 102 executes the process of Graph1 (step S202). The execution core 102 writes the execution result in buf1 (step S203). As a result of this writing, data002 is stored in buf1 of the local memory 103 as shown in FIG.

The completion notification of Graph1 is transmitted from the execution core 102 to the host CPU 12 (step S204). At this stage, as shown in FIG. 5C, no data is written in buf1 of the global memory 14.

The address conversion unit 101 monitors the memory access status of the host CPU 12 (step S104). Since the host CPU 12 recognizes that Graph1 has been completed by the notification in step S204, the host CPU 12 may read the buf1 that is the execution result of Graph1 from the global memory 14 and perform the next process (step S002).

The address conversion unit 101 detects the processing of the CPU 12 in step S002 and determines whether buf1 is stored in the global memory 14 (step S105). If buf1 is stored in the global memory 14, no special action is taken. If buf1 is not stored in the global memory 14, the CPU 12 performs read delay processing (step S107). This process delays the process in which the CPU 12 reads data from the global memory 14 until the process of the execution core 102 described later is completed.

The address conversion unit 101 outputs an instruction to write buf1 from the local memory 103 to the global memory 14 to the execution core 102 (step S106). In response to this instruction, the execution core 102 executes a process of writing buf1 of the local memory 103 into the global memory 14 (step S205). As a result of this writing, data002 is stored in buf1 of the global memory 14 as shown in FIG.

The writing from the local memory 103 to the global memory 14 only when such a need arises is executed even when the processing proceeds to Graph2. FIG. 6 shows the data write status of the local memory 103 and the global memory 14 in that case.

6 (A) and 6 (B) are in the same situation as FIG. 5 (A) and FIG. 5 (B). Here, when execution of Graph 2 is instructed from the CPU 12, the execution core 102 executes Graph 2, and writes the resulting data 003 of buf 2 only in the local memory 103.

Since the CPU 12 recognizes that the Graph 2 has been completed by the notification, the buf 2 that is the execution result of the Graph 2 may be read from the global memory 14 to perform the next process. The address conversion unit 101 recognizes this action, and the execution core 102 writes buf2 from the local memory 103 to the global memory 14. As shown in FIG. 6D, since buf1 that is not required by the CPU 12 is not scraped to the global memory 14, useless access to the memory can be reduced.

For comparison, an example in which address translation is not performed will be described with reference to FIGS. As shown in FIG. 7, the host CPU instructs the accelerator to execute Graph1 (step S051). As shown in FIG. 8A, at this time, no data is stored in the local memory, and data001 is stored in buf0 of the global memory.

The execution core reads buf0 from the global memory and writes it to the local memory (step S251). At this stage, as shown in FIG. 8B, data is written to buf1 of the local memory.

The execution core executes Graph1 (step S252). The execution core writes buf1 as the execution result of Graph1 to the local memory (step S253). The execution core writes buf1 into the global memory (step S254). At this stage, as shown in FIG. 8C, data is written to buf1 of the global memory.

The execution core transmits a Graph1 completion notification to the host CPU (step S255). The host CPU reads buf1 from the global memory (step S052).

When the execution core executes Graph2, buf2 is immediately written to the global memory when execution is completed, and the state shown in FIG.

As is apparent from a comparison between FIG. 6 which is a memory writing example of this embodiment and FIG. 8 which is a memory writing example of a comparative example, in this embodiment, the local memory 103 is transferred to the global memory 14 only when necessary. Since writing is performed, the processing can be further speeded up.

The embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Those in which those skilled in the art appropriately modify the design of these specific examples are also included in the scope of the present disclosure as long as they have the features of the present disclosure. Each element included in each of the specific examples described above and their arrangement, conditions, shape, and the like are not limited to those illustrated, and can be changed as appropriate. Each element included in each of the specific examples described above can be appropriately combined as long as no technical contradiction occurs.

Claims (3)

An information processing apparatus capable of accessing both a local memory owned by itself and a global memory shared with another information processing apparatus,
A process execution unit (102) for executing a process based on data stored in the local memory and the global memory;
An information conversion apparatus comprising: an address conversion unit (101) that executes an address conversion process for converting an access destination address with respect to execution of the process of the process execution unit. The information processing apparatus according to claim 1,
The address conversion unit is configured to transfer the data to the process execution unit from the global memory to the local memory when data required for the process execution unit is not stored in the local memory. An information processing apparatus that executes processing. An information processing apparatus according to claim 2,
The address conversion unit monitors a situation in which another information processing apparatus accesses the global memory, and when there is no data required in the global memory, the global address is transmitted from the local memory to the processing execution unit. An information processing apparatus that executes the address conversion process so as to transfer data to a memory.

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