WO2019188172A1 - Information processing device - Google Patents

Abstract

Provided is an information processing device comprising: an execution recognition part (141) for recognizing whether it is necessary to commence a check execution mode for executing a plurality of fault sensing execution instructions with regard to a plurality of execution pipes; and an instruction output part (142) for executing the check execution mode with regard to the plurality of execution pipes if the commencement of the check execution mode has been recognized by the execution recognition part (141). The instruction output part (142) is for executing the check execution mode for a number of times greater than or equal to the number of the execution pipe installations, and executes the check execution mode such that each of the plurality of fault sensing execution instructions is executed in different execution pipes.

Description

Information processing device Cross-reference of related applications

This application is based on Japanese Patent Application No. 2018-068426 filed on March 30, 2018, and claims the benefit of its priority. Which is incorporated herein by reference.

The present disclosure relates to an information processing apparatus including a thread scheduler that assigns processing to a plurality of processing execution hardware having the same configuration.

As an invention for ensuring the functional safety of a processor element which is a plurality of processing execution hardware, the one described in Patent Document 1 below is disclosed. In the following Patent Document 1, when the same data processing is executed by a plurality of processor elements to realize the functional safety of the processor elements, the safety measure is determined by determining the mismatch of the access requests issued from the plurality of processor elements. A bus interface unit that performs processing and performs control to start access processing that responds to the access request when they match is adopted.

Japanese Patent Laying-Open No. 2015-153282

Requirement for functional safety is that processing is executed repeatedly with different hardware resources, and the result is compared to confirm the presence of hardware failure. Duplicate execution requires failure detection by changing execution timing and execution hardware resources. Conventionally, a plurality of processing execution hardware having the same configuration is executed by executing different types of software to detect a failure, and when a failure is detected, the same software is repeatedly executed and the results are compared. ing.

However, in an information processing apparatus including a thread scheduler that assigns processing to a plurality of processing execution hardware having the same configuration, even if different types of software are executed, not all processing execution hardware necessarily executes the processing. It is also assumed that only a part of the processing execution hardware executes the processing.

An object of the present disclosure is to provide an information processing apparatus including a thread scheduler that assigns processing to a plurality of processing execution hardware having the same configuration, which can ensure functional safety. .

The present disclosure is an information processing apparatus including a thread scheduler that assigns processing to a plurality of processing execution hardware having the same configuration, and starts a check execution mode that executes a plurality of failure detection execution instructions for the plurality of processing execution hardware An execution recognition unit that recognizes necessity, and an instruction output unit that executes the check execution mode for a plurality of processing execution hardware when the execution recognition unit recognizes the start of the check execution mode. Yes. The instruction output unit executes the execution of the check execution mode at least as many times as the number of the plurality of processing execution hardware installed, and each of the plurality of failure detection execution instructions is executed on different processing execution hardware. Execute check execution mode.

By executing the check execution mode at least as many times as the number of installed multiple process execution hardware, and executing the check execution mode so that each of the plurality of failure detection execution instructions is executed in different process execution hardware, Since the failure detection command can be executed at different times without biasing the plurality of processing execution hardware provided, functional safety can be reliably ensured.

FIG. 1 is a diagram for explaining parallel processing which is a premise of the present embodiment. FIG. 2 is a diagram showing a system configuration example for executing the parallel processing shown in FIG. FIG. 3 is a diagram illustrating a configuration example of the DFP used in FIG. FIG. 4 is a diagram for explaining the function of the scheduler. FIG. 5 is a diagram for explaining the function of the scheduler. FIG. 6 is a diagram for explaining the function of the scheduler. FIG. 7 is a diagram for explaining the function of the scheduler. FIG. 8 is a diagram for explaining the function of the scheduler. FIG. 9 is a diagram for explaining the function of the scheduler. FIG. 10 is a diagram for explaining the function of the scheduler. FIG. 11 is a diagram for explaining the function of the scheduler.

Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate the understanding of the description, the same constituent elements in the drawings will be denoted by the same reference numerals as much as possible, and redundant description will be omitted.

FIG. 1A shows a program code having a graph structure, FIG. 1B shows a thread state, and FIG. 1C shows a state of parallel processing.

As shown in FIG. 1A, the program to be processed in this embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.

1) When automatic vectorization and graph structure extraction are performed on the program code shown in FIG. 1A by a compiler, a large number of threads as shown in FIG. 1B can be generated.

1) Parallel execution as shown in FIG. 1C can be performed on a large number of threads shown in FIG. 1B by dynamic register placement and thread scheduling by hardware. By dynamically allocating register resources during execution, a plurality of threads can be executed in parallel for different instruction streams.

Next, a data processing system 2, which is a system configuration example including a DFP (Data Flow Processor) 10 as an accelerator for performing dynamic register placement and thread scheduling, will be described with reference to FIG. The DFP 10 corresponds to the information processing apparatus of the present disclosure.

The data processing system 2 includes a DFP 10, an event handler 20, a host CPU 21, a ROM 22, a RAM 23, an external interface 24, and a system bus 25. The host CPU 21 is an arithmetic unit that mainly performs data processing. The host CPU 21 supports the OS. The event handler 20 is a part that generates an interrupt process.

ROM 22 is a read-only memory. The RAM 23 is a read / write memory. The external interface 24 is an interface for exchanging information with the outside of the data processing system 2. The system bus 25 is for transmitting and receiving information between the DFP 10, the host CPU 21, the ROM 22, the RAM 23, and the external interface 24.

The DFP 10 is positioned as an individual master provided to cope with the heavy computation load of the host CPU 21. The DFP 10 is configured to support the interrupt generated by the event handler 20.

Next, the DFP 10 will be described with reference to FIG. As shown in FIG. 3, the DFP 10 includes a command unit 12, a thread scheduler 14, an execution core 16, and a memory subsystem 18.

The command unit 12 is configured to be able to communicate information with the config interface. The command unit 12 also functions as a command buffer.

The thread scheduler 14 is a part that schedules processing of a large number of threads as exemplified in FIG. The thread scheduler 14 can perform scheduling across threads.

The execution core 16 has four processing elements, PE # 0, PE # 1, PE # 2, and PE # 3. The execution core 16 has a number of pipelines that can be scheduled independently.

The memory subsystem 18 includes an arbiter 181, an L1 cache 18a, and an L2 cache 18b. The memory subsystem 18 is configured to allow information communication between the system bus interface and the ROM interface.

Subsequently, the thread scheduler 14 included in the information processing apparatus of the present disclosure will be described with reference to FIG. A program code (PC) and an instruction code are supplied to the thread scheduler 14. In the present embodiment, the parity corresponding to the program code and instruction code is generated and input to the thread scheduler 14 by the hardware in the previous stage of the thread scheduler 14. The schedule mode corresponding to the parity is also input from the previous hardware of the thread scheduler 14.

The thread scheduler 14 outputs instruction execution to the execution pipe 0 and the execution pipe 1 according to the parity and the schedule mode. An example will be described with reference to FIG. When the parity is 0 and the schedule mode is 0, execution of the first instruction is started in the execution pipe 1. Subsequently, the second instruction executes an instruction in execution pipe 0, the third instruction executes an instruction in execution pipe 0, the fourth instruction executes an instruction in execution pipe 1, and the fifth instruction in execution pipe 1. An instruction is executed, the sixth instruction executes an instruction in the execution pipe 1, the seventh instruction executes an instruction in the execution pipe 0, and the eighth instruction executes an instruction in the execution pipe 1.

Next, when the parity is 1 and the schedule mode is 1, the first instruction is executed by the execution pipe 0. Subsequently, the second instruction executes an instruction in execution pipe 0, the third instruction executes an instruction in execution pipe 0, the fourth instruction executes an instruction in execution pipe 0, and the fifth instruction in execution pipe 0 An instruction is executed, the sixth instruction executes an instruction on the execution pipe 0, the seventh instruction executes an instruction on the execution pipe 1, and the eighth instruction executes an instruction on the execution pipe 0.

In this way, by executing an instruction in one instruction string in one of a pair of execution pipes, and selecting the execution pipe so that the next instruction string is in reverse phase to the execution pipe executed in the previous instruction string, It is possible to execute instructions with different execution times without deviation.

The thread scheduler 14 includes an execution recognition unit 141 and an instruction output unit 142 as functional components. The execution recognition unit 141 is a part that recognizes whether it is necessary to start a check execution mode for executing a plurality of failure detection execution instructions for an execution pipe that is a plurality of process execution hardware. In the example described with reference to FIG. 4, when an instruction code, parity, and schedule mode are input, the execution recognition unit 141 recognizes the necessity for starting the check time mode.

The instruction output unit 142 is a part that executes the check execution mode for an execution pipe that is a plurality of processing execution hardwares when the execution recognition unit 141 recognizes the start of the check execution mode. The instruction output unit 142 executes the check execution mode at least as many times as the number of installed processing execution hardware, and each of the plurality of failure detection execution instructions is executed by different processing execution hardware. Execute check execution mode.

In the example shown in FIG. 4, since two execution pipes which are processing execution hardware are provided, the instruction sequence is executed twice. In the first instruction, the execution pipe 1 is executed in the first execution (schedule mode 0), and the execution pipe 0 is executed in the second execution (schedule mode 1). Subsequent instructions are also executed alternately by the execution pipe 0 and the execution pipe 1.

In this way, the execution of the check execution mode is performed at least as many times as the number of pieces of processing execution hardware installed, and the check execution mode is executed so that each of the plurality of failure detection execution instructions is executed on different processing execution hardware. By doing so, the failure detection command can be executed at different times without biasing the plurality of processing execution hardware provided, so that functional safety can be ensured reliably.

In the example shown in FIG. 4, a pair of execution pipes 0 and 1 are provided for one thread scheduler 14, and a plurality of failure detection execution instructions are executed on the execution pipe 0 and the execution pipe 1. However, the thread scheduler is not limited to one, and the execution pipes are not limited to a pair.

In the example shown in FIG. 6, a pair of thread scheduler 14A and thread scheduler 14B are provided. For the thread scheduler 14A and the thread scheduler 14B, the distributor 50 distributes a program code (PC), an instruction code, a parity, and a schedule mode.

The thread scheduler 14A outputs instruction execution to the execution pipe 0 and the execution pipe 1 according to the parity and the schedule mode. The thread scheduler 14B outputs instruction execution to the execution pipe 2 and the execution pipe 3 according to the parity and the schedule mode.

An example will be described with reference to FIG. When the parity is 0 and the schedule mode is 0, execution of the first instruction starts in the execution pipe 3. Subsequently, the second instruction executes an instruction in the execution pipe 1, the third instruction executes an instruction in the execution pipe 2, the fourth instruction executes an instruction in the execution pipe 0, and the fifth instruction in the execution pipe 1. An instruction is executed, the sixth instruction executes an instruction in the execution pipe 3, the seventh instruction executes an instruction in the execution pipe 0, and the eighth instruction executes an instruction in the execution pipe 2.

Next, when the parity is 1 and the schedule mode is 1, the first instruction is executed by the execution pipe 0. Subsequently, the second instruction executes the instruction in the execution pipe 3, the third instruction executes the instruction in the execution pipe 1, the fourth instruction executes the instruction in the execution pipe 2, and the fifth instruction in the execution pipe 2. An instruction is executed, the sixth instruction executes an instruction in the execution pipe 1, the seventh instruction executes an instruction in the execution pipe 3, and the eighth instruction executes an instruction in the execution pipe 0.

In this way, instructions are executed in one instruction sequence on one of the pair of execution schedulers carried by one of the thread schedulers 14A and 14B. In the next instruction sequence, by selecting one of the execution pipes carried by the thread scheduler having the opposite phase to that of the thread scheduler that executed the previous instruction sequence, it is possible to execute the instruction with the execution time shifted without deviation.

As a variation of a program unit for generating a parity, as described above, a program code and an instruction code generated for each instruction can be considered. In this case, a parity generation unit is provided as hardware.

As another variation for generating parity, as shown in FIG. 8, a program binary having a thread selection flag at the time of testing is conceivable. In this case, a parity generation unit as hardware is unnecessary. As another variation for generating the parity, a parity such as a base address of data set in the program code or the instruction code may be used.

As shown in FIG. 9, the instruction output unit 142 refers to a schedule history 51 that is an execution history of instructions for a plurality of processing execution hardware before starting execution of the check execution mode, and performs check execution including the execution history. The mode can be executed. The schedule history 51 which is an instruction execution history has an instruction history including an instruction canceled by speculative execution, thereby having an instruction history that does not affect the system. Therefore, even in the cancel operation, a test in which the execution pipe is divided can be performed.

As shown in FIG. 10, the instruction output unit 142 is an execution pipe that is an execution result history that is a result of execution of an instruction that affects a plurality of processing execution hardware before the execution of the check execution mode is started. With reference to the history 52, the check execution mode can be executed including the execution result history. By using the execution pipe history 52 which is an execution result history that is a result of execution of an instruction affecting the processing execution hardware, it is not necessary to hold an execution cancellation history, and the execution pipe history 52 table is compact. Can be.

As shown in FIG. 11, a test mode register 55 can be provided separately from the DFP 10. The test mode register 55 outputs a test mode signal to the DFP 10. The execution recognition unit 141 can recognize the necessity of starting the check execution mode by receiving this test mode signal.

The embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Those in which those skilled in the art appropriately modify the design of these specific examples are also included in the scope of the present disclosure as long as they have the features of the present disclosure. Each element included in each of the specific examples described above and their arrangement, conditions, shape, and the like are not limited to those illustrated, and can be changed as appropriate. Each element included in each of the specific examples described above can be appropriately combined as long as no technical contradiction occurs.

Claims (3)

An information processing apparatus including a thread scheduler that assigns processing to a plurality of processing execution hardware having the same configuration,
An execution recognition unit (141) for recognizing the necessity of starting a check execution mode for executing a plurality of failure detection execution instructions for the plurality of processing execution hardware;
An instruction output unit (142) for executing the check execution mode with respect to the plurality of processing execution hardware when the execution recognition unit recognizes the start of the check execution mode;
The instruction output unit performs the execution of the check execution mode at least as many times as the number of the plurality of process execution hardware installed, and each of the plurality of failure detection execution instructions is different in the process execution hardware. An information processing apparatus that executes the check execution mode to be executed. The information processing apparatus according to claim 1,
The information output apparatus, wherein the instruction output unit refers to an execution history of instructions for the plurality of processing execution hardware before starting execution of the check execution mode, and executes the check execution mode including the execution history. An information processing apparatus according to claim 2,
The instruction output unit refers to an execution result history that is a result of execution of an instruction that affects the plurality of process execution hardware before starting execution of the check execution mode, and includes the execution result history. An information processing apparatus that executes the check execution mode.

Images