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WO2019168036A1 - Procédé de production de dispositif de mémorisation non volatil - Google Patents

Procédé de production de dispositif de mémorisation non volatil Download PDF

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Publication number
WO2019168036A1
WO2019168036A1 PCT/JP2019/007581 JP2019007581W WO2019168036A1 WO 2019168036 A1 WO2019168036 A1 WO 2019168036A1 JP 2019007581 W JP2019007581 W JP 2019007581W WO 2019168036 A1 WO2019168036 A1 WO 2019168036A1
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WO
WIPO (PCT)
Prior art keywords
hole
layer
conductive layer
etching
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/007581
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English (en)
Japanese (ja)
Inventor
和雄 吉備
高橋　彰宏
坂本　渉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
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Tokyo Electron Ltd
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Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of WO2019168036A1 publication Critical patent/WO2019168036A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Definitions

  • the disclosed technology relates to a method for manufacturing a nonvolatile memory device.
  • a NAND flash memory is known as a small and large capacity non-volatile storage device.
  • a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
  • a contact with a conductive layer functioning as a word line of each memory cell In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell.
  • etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
  • the insulating layer and the sacrificial layer are alternately stacked, and the end portion is formed in a stepped shape in the stacking direction of the multilayer film.
  • a step of forming a first hole penetrating the end portion, and a part of each of the sacrificial layers on the inner side wall of the first hole is radially inward of the first hole from the insulating layer.
  • Remove the part covering the upper surface of the convex part And filling the first hole with a conductive material in a state where the upper surface of the convex portion of the conductive layer disposed in the uppermost layer in the first hole is exposed from the insulating film. Including the step of.
  • a contact with a conductive layer in each layer can be appropriately formed in a NAND flash memory having a stacked structure.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 3 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 4 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 5 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 6 is a diagram for explaining the etching of each insulating layer in more detail.
  • FIG. 7 is a diagram for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND
  • FIG. 8 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 9 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 10 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 11 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 12 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory 10 according to the present embodiment.
  • a NAND flash memory 10 shown in FIG. 1 is a NAND flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged.
  • the NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating film 16, and a plurality of contact plugs 18.
  • the stacking direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction
  • the direction perpendicular to the paper surface of FIG. 1 is defined as the X direction in the plane of each layer, and parallel to the paper surface of FIG. Is defined as the Y direction.
  • the substrate 12 is a substrate formed of a semiconductor such as silicon.
  • the multilayer film 14 has a structure in which the conductive layers 22 and the insulating layers 24 are alternately stacked and the end portions are formed in a stepped shape.
  • a plurality of pairs of the conductive layer 22 and the insulating layer 24 respectively correspond to a plurality of memory cells arranged three-dimensionally in the Z direction.
  • Each conductive layer 22 functions as a word line of each memory cell, for example.
  • Each conductive layer 22 is made of a metal such as W, for example.
  • each insulating layer 24 functions as an interlayer insulating film that insulates between the conductive layers 22 adjacent in the Z direction.
  • Each insulating layer 24 is, for example, a silicon oxide film.
  • each pair of the conductive layer 22 and the insulating layer 24 is not covered with another pair disposed in the upper layer.
  • the insulating film 16 is formed on the multilayer film 14 so as to cover the multilayer film 14.
  • the insulating film 16 functions as an interlayer insulating film that insulates between the multilayer film 14 and a wiring layer disposed on the insulating film 16.
  • the insulating film 16 is, for example, a silicon oxide film.
  • the multilayer film 14 and the insulating film 16 are formed with a plurality of contact holes CH penetrating the end of the multilayer film 14 in the Z direction.
  • the plurality of contact holes CH are formed at one time by etching, for example, and reach the substrate 12.
  • each contact hole CH is formed by etching, in the multilayer film 14, each conductive layer 22 is not used as an etch stop layer.
  • each conductive layer 22 protrudes inward in the radial direction of the contact hole CH from each insulating layer 24.
  • an insulating film 32 is formed along the inner wall of each contact hole CH.
  • the insulating film 32 is, for example, a silicon oxide film.
  • the insulating film 32 has an opening 32a at a position corresponding to the upper surface of the convex portion protruding in the radial direction of the contact hole CH of the conductive layer 22 disposed in the uppermost layer in each contact hole CH.
  • the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in each contact hole CH is exposed from the opening 32 a of the insulating film 32.
  • Each contact plug 18 is disposed in each contact hole CH.
  • Each contact plug 18 is made of a metal such as W, for example.
  • Each contact plug 18 is in contact with the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH through the opening 32 a of the insulating film 32.
  • each contact plug 18 is electrically insulated from the other conductive layer 22 other than the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH by the insulating film 32.
  • each contact plug 18 is in contact with the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH. It is electrically insulated from the conductive layer 22 by the insulating film 32.
  • each conductive layer 22 is not used as an etch stop layer in the multilayer film 14. Therefore, it is possible to electrically connect each contact plug 18 to the uppermost conductive layer 22 in the corresponding contact hole CH without using the conductive layer 22 in each layer as an etch stop layer. Become. As a result, in the NAND flash memory 10 having the stacked structure, the contact with the conductive layer 22 in each layer is appropriately formed.
  • FIG. 2 is a flowchart showing an example of a method for manufacturing the NAND flash memory 10 according to the present embodiment.
  • 3 to 5 and FIGS. 7 to 12 are views for explaining an example of the manufacturing method of the NAND flash memory 10 according to the present embodiment.
  • the sacrificial layers 52 and the insulating layers 54 are alternately stacked, and the multi-layer film 44 whose end portions are formed in a step shape, and the insulating film 46 that covers the multi-layer film 44, Is formed on the substrate 42.
  • the sacrificial layer 52 is made of, for example, SiN.
  • the insulating layer 54 is made of a material for forming the insulating layer 24 such as SiO 2 .
  • the stacking direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction, and the direction perpendicular to the paper surface of FIG. 3 is defined as the X direction and the direction parallel to the paper surface of FIG. It is defined as
  • a plurality of contact holes CH ′ penetrating the end portions of the multilayer film 14 in the Z direction are formed in the multilayer film 44 and the insulating film 46.
  • the plurality of contact holes CH ′ are collectively formed by anisotropic etching such as RIE (Reactive Ion Etching) and reach the substrate 42.
  • the contact hole CH ′ is an example of a first hole.
  • An etching method of the contact hole CH ′ is, for example, dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as an etching apparatus. Specific conditions for etching at this time are as follows.
  • each sacrificial layer 52 is more radial in the contact hole CH ′ than the respective insulating layer 54 on the inner wall of each contact hole CH ′.
  • Each insulating layer 54 is etched so as to protrude inward.
  • each sacrificial layer 52 is formed with a convex portion 52a that protrudes radially inward of the contact hole CH ′ from the respective insulating layer 54.
  • the insulating film 46 is etched in the radial direction of the contact hole CH ′ together with the respective insulating layers 54.
  • etching gas mixed gas of CF 4 , Ar and O 2
  • Etching temperature 100-300 °C ⁇
  • Etching time 1 to 300 min
  • Etching power 500 to 3000 W at a frequency of 13 to 60 MHz
  • FIG. 6 is a diagram for explaining the etching of each insulating layer 54 in more detail.
  • FIG. 6 corresponds to a schematic plan view when each contact hole CH ′ is viewed from the Z-axis direction.
  • the cross-sectional area of the portion surrounded by each insulating layer 54 of the contact hole CH ′ is A1
  • the cross-sectional area of the portion surrounded by each sacrificial layer 52 of the contact hole CH ′ is A2.
  • each insulating layer 54 is etched until the difference (A1-A2) between the cross-sectional area A1 and the cross-sectional area A2 becomes equal to or larger than the cross-sectional area A2.
  • an insulating film 62 is deposited along the inner wall of each contact hole CH ′.
  • the insulating film 62 is deposited along the convex part 52a of each sacrificial layer 52 on the inner side wall of each contact hole CH ′.
  • the insulating film 62 is made of a material for forming the insulating film 32 such as SiO 2 .
  • the insulating film 62 is deposited along the inner wall of each contact hole CH ′ by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). Specific conditions applied to the deposition of the insulating film 62 are as follows.
  • the insulating film 62 can also be formed by using a PVD (Physical Vapor Deposition) method or spin coating.
  • the formation temperature of the CVD method can be set to 300 to 1200 ° C., and O 3 can be used instead of O 2 .
  • Perhydropolysilazane can be used as a raw material, but in that case, the insulating film 62 can be formed by a spin coating method.
  • the organic material 48 is filled in the contact hole CH ′ in which the insulating film 62 is deposited.
  • the organic material 48 is, for example, SOC (spin on carbon).
  • the organic material 48 is filled by, for example, CVD or coating.
  • each sacrificial layer 52 is replaced with a conductive layer 72 in a state where the insulating film 62 is deposited along the inner wall of each contact hole CH ′.
  • each sacrificial layer 52 is removed by isotropic etching such as wet etching, for example.
  • the conductive layer 72 is disposed by filling the space obtained by removing the respective sacrificial layers 52 with a metal material.
  • the metal material filled in the space obtained by removing each sacrificial layer 52 is a metal material for forming the conductive layer 22 such as W (tungsten).
  • each conductive layer 72 is formed with a convex portion 72a protruding in the radial direction of the contact hole CH ′ from the respective insulating layer 54.
  • the convex portions 72a of the respective conductive layers 72 are arranged at the positions where the convex portions 52a of the respective sacrifice layers 52 were arranged. Specific conditions of the wet etching at this time are as follows.
  • ⁇ Etching temperature 200-350 °C ⁇ Etching time: 30 ⁇ 180min
  • a well-known technique using a raw material such as WF 6 or W (CO) 6 in addition to tungsten can be used.
  • the organic material 48 is removed.
  • the organic material 48 is removed by, for example, ashing.
  • Step S108 of FIG. 2 and FIG. 11 the protrusion protruding in the radial direction of the contact hole CH ′ of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ of the insulating film 62.
  • a portion covering the upper surface of the portion 72a is removed by etching.
  • an opening 62a is formed in the insulating film 62. From the opening 62a of the insulating film 62, the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ is formed. Exposed.
  • the etching method at this time is dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as an etching apparatus.
  • Specific conditions for etching at this time are as follows.
  • Gas flow rate: CF 4 / Ar / O 2 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm ⁇
  • Etching time 1 to 300 min
  • Etching power 500 to 3000 W at a frequency of 13 to 60 MHz
  • a metal material 78 is filled therein.
  • the metal material 78 and the upper surface of the convex part 72a of the electroconductive layer 72 arrange
  • the metal material 78 and the conductive layer 72 other than the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ are electrically insulated from each other by the insulating film 62.
  • the metal material 78 is a metal material for forming the contact plug 18 such as W (tungsten).
  • the metal material 78 is an example of a conductive material.
  • the substrate 42 functions as the substrate 12
  • the conductive layer 72 functions as the conductive layer 22
  • the insulating layer 54 functions as the insulating layer 24, and the insulating film 46 functions as the insulating film 16.
  • the metal material 78 functions as the contact plug 18, the insulating film 62 functions as the insulating film 32
  • the contact hole CH ′ functions as the contact hole CH.
  • a well-known technique using a raw material such as WF 6 or W (CO) 6 in addition to tungsten can be used.
  • the upper surface of the convex portion 72 a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ is exposed from the insulating film 32.
  • the metal material 78 is filled in each contact hole CH ′.
  • the metal material 78 comes into contact with the upper surface of the protrusion 72 a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′, and is electrically insulated from the other conductive layer 72 by the insulating film 62.
  • each contact hole CH ′ is formed by etching, each conductive layer 72 is not used as an etch stop layer.
  • each insulating layer 54 has a cross-sectional area A1 of a portion surrounded by each insulating layer 54 of the contact hole CH ′ and a cross-sectional area A2 of a portion surrounded by each sacrificial layer 52. Etching is performed until the difference (A1-A2) becomes equal to or larger than the cross-sectional area A2. As a result, a sufficient surface area of the upper surface of the convex portion 52a of each sacrificial layer 52 is ensured. Therefore, when each sacrificial layer 52 is replaced with the conductive layer 72, a contact for forming the contact with the conductive layer 72 is formed. A sufficient surface area is secured.
  • the surface area for forming a contact with the conductive layer 72 corresponds to, for example, the surface area of the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′. As a result, the contact resistance corresponding to the contact with the conductive layer 72 is reduced.
  • the contact hole CH ′ penetrating the end of the multilayer film 44 in the Z direction is formed in the multilayer film 44 as an example, but the disclosed technique is not limited to this.
  • the contact hole CH ′ is formed in the multilayer film 44 at the same time as another contact hole penetrating another part different from the end of the multilayer film 44 in the Z direction. You may do it.
  • the other contact hole is, for example, a memory hole for arranging a plurality of memory cells three-dimensionally.
  • the other contact hole is an example of a second hole.
  • Multilayer film 52 Sacrificial layer 54 Insulating layer 62 Insulating film 72 Conductive layer 72a Convex part 78 Metal material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un procédé de production d'un dispositif de mémorisation non volatil (10). Le procédé de production comprend : une étape consistant à ménager un premier trou (CH') dans un film multicouche (44) qui a été formé par stratification alternée de couches d'isolation (54) et de couches sacrificielles (52) et qui comporte des parties d'extrémité en forme d'escalier ; une étape consistant à graver les couches d'isolation au niveau d'une paroi intérieure du premier trou de sorte qu'une partie de chacune des couches sacrificielles fasse plus saillie dans la direction radiale à l'intérieur du premier trou que les couches d'isolation ; une étape consistant à déposer un film isolant (62) le long de la paroi intérieure du premier trou ; une étape consistant à remplacer les couches sacrificielles par des couches conductrices (72) ; une étape consistant à retirer la partie du film isolant qui recouvre une surface supérieure d'une partie en saillie (72a) de la couche conductrice supérieure à l'intérieur du premier trou ; et une étape consistant à remplir l'intérieur du premier trou avec un matériau conducteur (78).
PCT/JP2019/007581 2018-03-02 2019-02-27 Procédé de production de dispositif de mémorisation non volatil Ceased WO2019168036A1 (fr)

Applications Claiming Priority (2)

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JP2018037229 2018-03-02
JP2018-037229 2018-03-02

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WO2019168036A1 true WO2019168036A1 (fr) 2019-09-06

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170098658A1 (en) * 2015-10-06 2017-04-06 Kabushiki Kaisha Toshiba Semiconductor memory device
US20180240811A1 (en) * 2017-02-21 2018-08-23 Samsung Electronics Co., Ltd. Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures
JP2018163981A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170098658A1 (en) * 2015-10-06 2017-04-06 Kabushiki Kaisha Toshiba Semiconductor memory device
US20180240811A1 (en) * 2017-02-21 2018-08-23 Samsung Electronics Co., Ltd. Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures
JP2018163981A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置およびその製造方法

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