WO2019163784A1 - Method for manufacturing solar cell - Google Patents

Abstract

The present invention includes: a step for forming a p-type semiconductor layer (13p) on one primary surface (11S) of a crystal substrate (11); a step for laminating, on the p-type semiconductor layer (13p), a lift-off layer (LF) mainly composed of an oxide; and a step for selectively removing the p-type semiconductor layer (13p) and the lift-off layer (LF), wherein, in the step for selectively removing the p-type semiconductor layer (13p) and the lift-off layer (LF), wet-etching is carried out using at least two different types of etching solutions so that the etching surface area of the p-type semiconductor layer (13p) is equal to or less than the etching surface area of the lift-off layer (LF) as seen from the one primary surface side in a direction perpendicular to the surface of the crystal substrate (11).

Description

Manufacturing method of solar cell

The technology disclosed herein belongs to a technical field related to a solar cell manufacturing method.

A general solar cell is a double-sided electrode type in which electrodes are arranged on both surfaces (light-receiving surface / back surface) of a semiconductor substrate. Recently, as a solar cell having no shielding loss due to an electrode, as shown in Patent Document 1 A back contact (back electrode) type solar cell in which an electrode is disposed only on the back surface has been developed.

In the back contact type solar cell, a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer must be formed on the back surface with high accuracy, and the manufacturing method becomes complicated as compared with a double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, as shown in Patent Document 1, a semiconductor layer pattern forming technique by a lift-off method can be cited. That is, development of a patterning technique for forming a semiconductor layer pattern by removing the lift-off layer and removing the semiconductor layer formed on the lift-off layer has been underway.

JP 2013-120863 A

However, in the method described in Patent Document 1, if the lift-off layer and the semiconductor layer are similar in solubility, even an unintended layer may be removed, and patterning accuracy or productivity may not be increased. There is.

The technology disclosed herein has been made in view of such a point, and an object thereof is to efficiently manufacture a high-performance back contact solar cell.

In order to solve the above problems, the technique disclosed herein includes a step of forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate; A step of laminating a lift-off layer mainly composed of an oxide on the first semiconductor layer; a step of selectively removing the first semiconductor layer and the lift-off layer by etching; and the first semiconductor layer and the Forming a second conductive type second semiconductor layer on the one main surface including the lift-off layer; and removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer In the step of selectively removing the first semiconductor layer and the lift-off layer, the etching area of the first semiconductor layer when viewed from the one main surface side in the direction perpendicular to the surface of the semiconductor substrate is Said To be less than the etching area of Futoofu layer, removing the first semiconductor layer and the lift-off layer by wet etching using two or more different etchants, it has a structure that.

According to the technology disclosed here, a high-performance back contact solar cell is efficiently manufactured.

1 is a schematic cross-sectional view partially showing a solar cell according to an exemplary embodiment. It is a top view which shows the back side main surface of the crystal substrate which comprises a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross section which shows one process of the manufacturing method of a solar cell. It is the top view which looked at the state at the time of completion | finish of the process of FIG. 7 from the back main surface side of the orthogonal | vertical direction of a crystal substrate. FIG. 9 is a diagram corresponding to FIG. 8 illustrating a modification of the present embodiment. FIG. 10 is a diagram corresponding to FIG. 9 showing a modification of the present embodiment.

Exemplary embodiments will be described with reference to the drawings.

FIG. 1 is a partial cross-sectional view of a solar cell (cell) according to this embodiment. As shown in FIG. 1, the solar cell 10 according to the present embodiment uses a crystal substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the main surface on which light is incident is referred to as a front-side main surface 11SU, and the opposite main surface is referred to as a back-side main surface 11SB. For convenience, the front main surface 11SU has a light receiving side that is more positively received than the back main surface 11SB and a non-light receiving side that is not actively receiving light.

The solar cell 10 according to this embodiment is a so-called heterojunction crystal silicon solar cell, and is a back contact type (back electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode). Layer 18).

Hereinafter, for convenience, members corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be suffixed with “p” or “n”. In addition, since the conductivity types are different such as p-type and n-type, one conductivity type may be referred to as “first conductivity type” and the other conductivity type may be referred to as “second conductivity type”.

The crystal substrate 11 may be a semiconductor substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon. Hereinafter, a single crystal silicon substrate will be described as an example.

Even if the conductivity type of the crystal substrate 11 is an n-type single crystal silicon substrate into which an impurity (for example, phosphorus (P) atom) that introduces electrons into silicon atoms is introduced, holes are introduced into the silicon atoms. A p-type single crystal silicon substrate into which impurities to be introduced (for example, boron (B) atoms) are introduced may be used. Hereinafter, an n-type single crystal substrate that is said to have a long carrier life will be described as an example.

The crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S from the viewpoint of confining received light. You may have. Note that the texture structure TX (uneven surface) is obtained by, for example, anisotropic etching applying the difference between the etching rate of the crystal substrate 11 with the (100) plane orientation and the etching rate of the (111) plane orientation. Can be formed.

The thickness of the crystal substrate 11 may be 250 μm or less. Note that the measurement direction when measuring the thickness is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate independent of the texture structure TX). Hereinafter, this vertical direction, that is, the direction in which the thickness is measured is defined as a perpendicular direction.

The size of the unevenness in the texture structure TX can be defined by the number of vertices, for example. In the present embodiment, from the viewpoint of light capturing performance and productivity, the number of vertices is preferably in the range of 50000 / mm 2 or more and 100000 / mm 2 or less, particularly 70000 / mm 2 or more and 85000 / It is preferable that it is below mm2.

When the thickness of the crystal substrate 11 is 250 μm or less, the amount of silicon used can be reduced, so that it becomes easy to secure the silicon substrate and the cost can be reduced. In addition, the back contact structure that collects holes and electrons generated by photoexcitation in the silicon substrate only on the back side is preferable from the viewpoint of the free path of each exciton.

On the other hand, when the thickness of the crystal substrate 11 is excessively small, the mechanical strength is reduced, or external light (sunlight) is not sufficiently absorbed, and the short-circuit current density is reduced. For this reason, the thickness of the crystal substrate 11 is preferably 50 μm or more, and more preferably 70 μm or more. When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the convex vertices in the light-receiving side and the back surface side. Is done.

The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers the both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11. Note that “intrinsic (i-type)” is not limited to complete intrinsicity including no conductive impurities, but is “weak” including a small amount of n-type impurities or p-type impurities within a range in which a silicon-based layer can function as an intrinsic layer. Also included are layers that are substantially intrinsic of “n-type” or “weak p-type”.

In addition, the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as necessary.

The material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon thin film, or a hydrogenated amorphous silicon thin film (a-Si: H thin film) containing silicon and hydrogen. Also good. Here, the term “amorphous” means a structure having a long period and no order. That is, it includes not only complete disorder but also one having a short period of order.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, the deterioration of the conversion characteristics caused by the increase in resistance can be suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma CVD (plasma enhanced chemical vapor deposition) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing the diffusion of impurities into the single crystal silicon. Further, in the case of the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile effective in recovering carriers.

The conditions for forming a thin film by plasma CVD include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high frequency power density of 0.003 W / cm ^{2 to} 0.5 W / It may be cm ² or less.

As the raw material gas used for forming the thin film, in the case of the intrinsic semiconductor layer 12, a silicon-containing gas such as monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ), or those gases and hydrogen (H _2). ) May be mixed.

Note that a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ), or monogermane (GeH ₄ ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN _X). ) Or a silicon compound such as silicon germanium (SIGe), the energy gap of the thin film may be changed as appropriate.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. N-type semiconductor layer 13n is formed on the other part of the back main surface of crystal substrate 11 with intrinsic semiconductor layer 12n interposed. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.

The thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, the deterioration of the conversion characteristics caused by the increase in resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated via the intrinsic semiconductor layer 12. The The width of the conductive semiconductor layer 13 may be not less than 50 μm and not more than 3000 μm, and may be not less than 80 μm and not more than 500 μm. The widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are the lengths of a part of each patterned layer, unless otherwise specified. It means the length in the direction orthogonal to the extending direction.

In the solar cell 10 of the present embodiment, a part of the intrinsic semiconductor layer 12n and a part of the n-type semiconductor layer 13n are formed on the p-type semiconductor layer 13p. The portions of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n formed on the p-type semiconductor layer 13p are configured such that the edges in the width direction are substantially flush.

When photoexcitons (carriers) generated in the crystal substrate 11 are taken out through the conductive semiconductor layer 13, holes have an effective mass larger than electrons. For this reason, from the viewpoint of reducing transport loss, the p-type semiconductor layer 13p may be narrower than the n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be not less than 0.5 times and not more than 0.9 times the width of the n-type semiconductor layer 13n, and is not less than 0.6 times and not more than 0.8 times. Also good.

The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron or the like) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and may be formed of an amorphous silicon layer similarly to the p-type semiconductor layer 13p.

As a source gas for the conductive semiconductor layer 13, a silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or a mixed gas of a silicon-based gas and hydrogen (H ₂ ) may be used. As the dopant gas, diborane (B ₂ H ₆ ) or the like is used for forming the p-type semiconductor layer 13p, and phosphine (PH ₃ ) or the like is used for forming the n-type semiconductor layer. Moreover, since the addition amount of impurities such as boron (B) or phosphorus (P) may be small, a mixed gas obtained by diluting a dopant gas with a raw material gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, different types such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ), or monogermane (GeH ₄ ) are used. The p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be alloyed by adding a gas containing these elements.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light. For example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), zinc oxide (ZnO), or oxide titanium (TiO _X) can be mentioned. Moreover, as a formation method of the low reflection layer 14, you may apply with the resin material which disperse | distributed the nanoparticle of oxides, such as a zinc oxide or a titanium oxide, for example.

The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n. The electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged so as to be separated from each other, thereby preventing a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

Further, the electrode layer 15 may be formed of only a metal having high conductivity. Further, from the viewpoint of electrical connection between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the semiconductor layers 13p and 13n of the metal that is the electrode material, The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.

In the present embodiment, the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18. Further, as shown in the plan view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-teeth shape, an electrode layer formed on the comb back portion May be referred to as a bus bar portion, and an electrode layer formed on the comb tooth portion may be referred to as a finger portion.

The transparent electrode layer 17 is not particularly restricted but includes materials such as zinc (ZnO) or indium oxide _(InO X), or various metal oxides in indium oxide, such as titanium oxide _(TiO X), tin oxide ( Examples thereof include a transparent conductive oxide to which SnO _X ), tungsten oxide (WO _X ), molybdenum oxide (MoO _X ), or the like is added in an amount of 1 wt% to 10 wt%.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. As a method for forming a transparent electrode layer suitable for this thickness, for example, a physical organic vapor deposition (PVD: physical vapor deposition) method such as a sputtering method, or a metal organic using a reaction between an organic metal compound and oxygen or water. The chemical vapor deposition method (MOCVD: Metal-Organic-Chemical-Vapor-Deposition) method etc. are mentioned.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. Examples of a method for forming the metal electrode layer 18 suitable for this thickness include a printing method in which a material paste is printed by inkjet or screen printing, or a plating method. However, the present invention is not limited to this, and when a vacuum process is employed, vapor deposition or sputtering may be employed.

Further, the width of the comb tooth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb tooth portions. However, the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion. Further, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as leakage between the metal electrode layers 18 is prevented.

In this embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back side main surface 11SB of the crystal substrate 11, and the passivation and conductive properties of each bonding surface are stacked. A predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels at the type semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17.

Examples of the annealing process according to the present embodiment include an annealing process in which the crystal substrate 11 on which each of the above layers is formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less. In this case, the atmosphere in the oven may be air, and more effective annealing can be performed by using hydrogen or nitrogen. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.

[Method for manufacturing solar cell]
Hereinafter, a method for manufacturing the solar cell 10 according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.

Next, as shown in FIG. 4, for example, an intrinsic semiconductor layer 12 </ b> U is formed on the front main surface 11 </ b> SU of the crystal substrate 11. Subsequently, the low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. For the low reflection layer 14, silicon nitride (SiN _x ) or silicon oxide (SiO _x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of light confinement.

Next, as shown in FIG. 5, an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back main surface 11SB of the crystal substrate 11. Subsequently, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. As a result, the p-type semiconductor layer 13p is formed on the back-side main surface 11SB which is one main surface of the crystal substrate 11. As described above, in this embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is performed before one of the crystal substrates (semiconductor substrates) 11 is formed before the p-type semiconductor layer 13p is formed. A step of forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on the principal surface (back side principal surface) 11S.

Thereafter, a lift-off layer LF is formed on the formed p-type semiconductor layer 13p. In the present embodiment, the lift-off layer LF is composed mainly of an oxide. Specifically, the lift-off layer LF is mainly composed of an oxide of an element selected from one or more of indium (In), zinc (Zn), tin (SnO), aluminum (Al), and silicon (Si). It is configured as. The lift-off layer LF need not be an oxide (for example, indium oxide (InO _x )) of one of the above elements. For example, indium-tin composite oxide, indium-aluminum composite oxide, indium-silicon Complex oxides, zinc-silicon complex oxides, zinc-tin complex oxides, zinc-aluminum complex oxides, ternary types such as aluminum-silicon complex oxides, indium-zinc-tin complex oxides, zinc-tin -A quaternary type such as a silicon composite oxide can be selected.

The lift-off layer LF can be formed by a vacuum process, in particular, a CVD method or a sputtering method. In these methods, the film quality such as density can be controlled without largely changing the composition by the flow rate ratio and pressure of the source gas, the voltage during plasma discharge, and the like. Furthermore, the etching characteristics in the film thickness direction can be adjusted by changing the film forming conditions in the film thickness direction. Further, the structure of the oxide formed by the vacuum process is not particularly limited, and examples thereof include a structure including a physical or chemical void (defect) inside the layer. When the lift-off layer LF is formed by a vacuum process, the growing particles grow so as to be stacked almost perpendicular to the film formation surface. In this case, a large number of particles formed of the grown particles may be generated, and voids may be generated between the particles. In the case of the lift-off layer LF including such voids, the etching solution may easily enter the layer, and thus the etching rate may be increased. For this reason, the lift-off time mentioned later can be shortened.

Next, as shown in FIGS. 6 and 7, the lift-off layer LF and the p-type semiconductor layer 13 p are patterned on the back main surface 11 SB of the crystal substrate 11. As a result, a non-forming region NA in which the p-type semiconductor layer 13p is not formed is generated. On the other hand, the lift-off layer LF and the p-type semiconductor layer 13p remain in a region that is not etched on the back side main surface 11SB of the crystal substrate 11.

6 and 7, the area melted by the etching of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p (hereinafter referred to as an etching area) when viewed from the back main surface 11SB side in the direction perpendicular to the crystal substrate 11 is obtained. Then, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF are removed by wet etching using two or more kinds of different etchants so as to be equal to or less than the etching area of the lift-off layer LF. More specifically, the intrinsic semiconductor layer 12p is formed such that the width of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is equal to or greater than the width of the lift-off layer LF when viewed from the back main surface 11SB side in the direction perpendicular to the crystal substrate 11. The p-type semiconductor layer 13p and the lift-off layer LF are removed.

In the actual process, as shown in FIG. 6, the lift-off layer is selectively removed by wet etching using the first etching solution, and then the intrinsic semiconductor layer 12 and the p-type semiconductor layer are formed as shown in FIG. Then, it is selectively removed by wet etching using a second etching solution.

Such a patterning step can be realized by photolithography, for example, by forming a resist film (not shown) having a predetermined pattern on the lift-off layer LF and etching a region masked by the formed resist film. . As shown in FIGS. 6 and 7, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF are patterned to form a non-formation region NA in a partial region of the back-side main surface 11SB of the crystal substrate 11. That is, an exposed region of the back side main surface 11SB is generated. Details of the non-forming area NA will be described later.

As the first etching solution used in the step shown in FIG. 6, for example, a strong acid etching solution such as hydrochloric acid or nitric acid is used. On the other hand, as the second etching solution used in the step shown in FIG. 7, for example, a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, ozone / hydrofluoric acid solution) is used.

In addition, the ozone / hydrofluoric acid solution as the second etching solution etches not only the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p but also the lift-off layer LF. For this reason, in the state after the step shown in FIG. 7, the edge portion in the width direction of the lift-off layer LF recedes compared to the state after the step shown in FIG. 6. As a result, the end edge portion of the lift-off layer LF is set back from the end edge portion of the p-type semiconductor layer 13p. As a result, as shown in FIG. 11, the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are equal to or greater than the width of the lift-off layer LF when viewed from the back main surface 11SB side in the direction perpendicular to the crystal substrate 11.

Next, as shown in FIG. 8, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed on the back main surface 11SB of the crystal substrate 11 including the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p. Sequentially formed. As described above, in the present embodiment, the step of forming the n-type semiconductor layer (second semiconductor layer) 13n includes the lift-off layer of the crystal substrate (semiconductor substrate) 11 before the n-type semiconductor layer 13n is formed. A step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back side main surface) 11S including the LF and the p-type semiconductor layer. Thereby, the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-forming region NA, the surface and side surfaces (end faces) of the lift-off layer LF, the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor. It is formed so as to cover the side surface (end surface) of the layer 12p. Here, in order to form the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n in a state where the edge of the lift-off layer LF is set back from the edge of the p-type semiconductor layer 13p, as shown in FIG. A part of the semiconductor layer 12n and a part of the n-type semiconductor layer 13n are formed directly on the p-type semiconductor layer 13p.

Next, as shown in FIG. 9, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the lift-off layer LF are removed from the crystal substrate 11 by removing the lift-off layer LF stacked using an etching solution ( Lift off). Here, it is not necessary to dissolve the second intrinsic semiconductor layer and the second conductivity type semiconductor layer covering the lift-off layer LF, and the lift-off layer is peeled off from the crystal substrate at the same time. As an etching solution used for this patterning, it is preferable to use a solvent that dissolves the lift-off layer LF and does not dissolve each intrinsic semiconductor layer 12 and the conductive semiconductor layer 13. For example, when the lift-off layer LF is mainly composed of a metal oxide such as indium oxide (InO _x ) or zinc oxide (ZnO), an acidic liquid such as hydrochloric acid is used, and the lift-off layer LF is composed of silicon oxide (SiO _x ) Is the main component, hydrofluoric acid is used.

Next, as shown in FIG. 10, the transparent electrode layer is formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, sputtering using a mask. 17 (17p, 17n) is formed. The transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire surface of the back main surface 11SB without using a mask, and then the transparent conductive film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography. Alternatively, etching may be performed to leave the conductive oxide film.

Thereafter, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 by using, for example, a mesh screen (not shown) having an opening.

Through the above steps, the back junction solar cell 10 is formed.

(Summary and effect)
The following can be said from the manufacturing method of the solar cell 10 described above.

First, in the step shown in FIG. 9, when the lift-off layer LF is removed with an etching solution, the intrinsic semiconductor layer 12 n and the n-type semiconductor layer 13 n deposited on the lift-off layer LF are also removed from the crystal substrate 11 at the same time. (So-called lift-off). This step does not require the resist coating step and the development step used in the photolithography method as compared with the case of using the photolithography method in the step shown in FIG. For this reason, the n-type semiconductor layer 13n is easily patterned.

The lift-off layer LF is composed mainly of an oxide. In the step of patterning the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF, the intrinsic semiconductor is seen from the back side of the crystal substrate 11 in the direction perpendicular to the plane. The intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off are formed by wet etching using two or more different etching solutions so that the etching area of the layer 12p and the p-type semiconductor layer 13p is equal to or less than the etching area of the lift-off layer LF. Layer LF is removed. In this way, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed by etching so that the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is equal to or less than the etching area of the lift-off layer LF. The exposure of the crystal substrate 11 is prevented.

That is, if the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is larger than the etching area of the lift-off layer LF when viewed from the back side in the direction perpendicular to the crystal substrate 11, the intrinsic semiconductor layer 12p and the p-type The semiconductor layer 13p is in a state where the semiconductor layer 13p is retracted from the lift-off layer LF (side-cut state). In this state, when the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed, the lift-off layer LF functions as a mask, and the side surfaces of the intrinsic semiconductor layer 12n on the non-formation region NA and the intrinsic semiconductor layers 12p and p A gap is generated between the side surface of the type semiconductor layer 13p. Then, when the lift-off layer LF, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are removed, the crystal substrate 11 is interposed between the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n. The back main surface 11SB is exposed. If the back side main surface 11SB of the crystal substrate 11 is exposed, the effective area where holes and electrons can be collected is reduced by the exposed area, so that the performance of the solar cell is deteriorated.

On the other hand, when the lift-off layer LF is composed mainly of an oxide as in this embodiment, the etching characteristics of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the etching characteristics of the lift-off layer LF are obtained. to differ greatly. The etching solution for etching the lift-off layer LF is different from the etching solution for etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, thereby controlling the etching area of each layer, particularly the intrinsic semiconductor layer. Patterning accuracy in the width direction of the 12p and the p-type semiconductor layer 13p is increased. As a result, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p becomes equal to or less than the etching area of the lift-off layer LF. As a result, the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the side surface of the lift-off layer LF are flush with each other, or the lift-off layer LF seems to recede from the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. It becomes a state. If the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the intrinsic semiconductor layer 12n is formed so as to be in contact with at least the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. Exposure of the substrate 11 is suppressed. Therefore, deterioration of the performance of the solar cell is suppressed, and a high-performance solar cell can be manufactured.

Therefore, according to this embodiment, a high-performance back contact solar cell can be efficiently manufactured.

As described above, in order to control the etching area of each layer, the etching rate of the first etching solution used in the process of FIG. 6 is expressed by the following relational expression (1):
Etching rate of intrinsic semiconductor layer 12p ≦ etching rate of p-type semiconductor layer 13p << etching rate of lift-off layer LF (1)
And the etching rate of the second etchant used in the step shown in FIG. 7 is expressed by the following relational expression (2):
Etching rate of intrinsic semiconductor layer 12p ≦ etching rate of p-type semiconductor layer 13p ≦ etching rate of lift-off layer LF (2)
It is preferable to satisfy.

If the first etching solution satisfies the relational expression (1), the lift-off layer LF can be selectively and quickly dissolved in the step shown in FIG. When the second etching solution satisfies the relational expression (2), when the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are dissolved in the step shown in FIG. 7, the lift-off layer LF is also dissolved together. For this reason, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p does not become larger than the etching area of the lift-off layer LF, and the side cut of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p hardly occurs.

The above relational expressions (1) and (2) can be satisfied depending on the type of etching solution or the concentration of the etching solution.

The thickness of the lift-off layer LF is preferably 20 nm or more and 500 nm or less, and particularly preferably 50 nm or more and 250 nm or less. That is, if the lift-off layer LF is too thick, there is a concern that the etching in the step of FIG. 6 is insufficient or the productivity is lowered. Further, if the lift-off layer LF is too thick, a reverse-tapered undercut may occur in the lift-off layer LF due to side etching. When reverse-tapered undercut occurs in the lift-off layer LF, the width of the lift-off layer LF becomes narrower as compared with the surface of the lift-off layer LF as it approaches the p-type semiconductor layer 13p. For this reason, in the state after etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the edge portions of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are the farthest from the p-type semiconductor layer 13p in the lift-off layer LF. It will be in the state where it retreated rather than the end edge part of this part. When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, as described above, the lift-off layer LF functions as a mask, and the side surface of the intrinsic semiconductor layer 12n on the non-formation region NA A gap is formed between the side surfaces of the semiconductor layer 12p and the p-type semiconductor layer 13p, and the crystal substrate 11 is finally exposed. Therefore, the film thickness of the lift-off layer LF needs to be a film thickness that can prevent the reverse tapered undercut as described above. On the other hand, if the film thickness is too thin, the lift-off layer LF may be completely removed (lifted off) when the lift-off layer LF is patterned in the process shown in FIG. Become. Accordingly, the thickness of the lift-off layer LF is particularly preferably 20 nm or more and 500 nm or less.

Further, the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back main surface 11SB of the crystal substrate 11 has a texture structure TX. It is preferable that a texture structure reflecting the above (second texture structure) is included.

When the conductive semiconductor layer 13 has the texture structure TX on the surface, the etching solution easily penetrates into the semiconductor layer 13 due to the unevenness of the texture structure TX. For this reason, the conductive semiconductor layer 13 is easily removed, that is, easily patterned.

In the present embodiment, the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front-side main surface 11SU and the back-side main surface 11SB. May be provided. That is, when the texture structure TX is provided on the front main surface 11SU, the effect of capturing received light and the effect of confinement are enhanced. On the other hand, when the texture structure TX is provided on the back main surface 11SB, the light capturing effect is improved and the patterning of the conductive semiconductor layer 13 is facilitated. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. In the present embodiment, the texture structure TX of both the main surfaces 11S has the same pattern. However, the present invention is not limited to this, and the size of the unevenness of the texture structure TX is changed between the front-side main surface 11SU and the back-side main surface 11SB. Also good.

The technology disclosed herein is not limited to the above-described embodiment, and can be substituted without departing from the scope of the claims.

For example, in the above-described embodiment, in the step shown in FIG. 7, the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are larger than the width of the lift-off layer LF when viewed from the back side in the direction perpendicular to the crystal substrate 11. Thus, although the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are patterned, the width of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is substantially the same as the width of the lift-off layer LF (not limited to this) (actual Alternatively, patterning (etching) may be performed so that the lift-off layer LF has a slightly smaller width. That is, when the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are substantially the same as the width of the lift-off layer LF, the edge portion of the lift-off layer LF and the edge portion of the p-type semiconductor layer 13p are located at substantially the same position. To do. When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n do not run directly on the p-type semiconductor layer 13p, as shown in FIG. It is formed. As a result, by removing the lift-off layer LF, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n deposited on the lift-off layer LF are removed from the crystal substrate 11, as shown in FIG. 13n is not formed on the p-type semiconductor layer 13p, but is separated from the p-type semiconductor layer 13p via the intrinsic semiconductor layer 12n in the width direction. In the case where the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are formed in this way, the separation groove is formed at the boundary between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from the viewpoint of suppressing the occurrence of leakage. Is preferably formed.

In the above-described embodiment, the semiconductor layer used in the process shown in FIG. 5 is the p-type semiconductor layer 13p. However, the semiconductor layer is not limited to this and may be the n-type semiconductor layer 13n. The conductivity type of the crystal substrate 11 is not particularly limited, and may be p-type or n-type.

The above-described embodiments are merely examples, and the scope of the technology of the present disclosure should not be interpreted in a limited manner. The scope of the technology of the present disclosure is defined by the scope of the claims, and all modifications and changes belonging to the equivalent scope of the claims are within the scope of the technology of the present disclosure.

Hereinafter, the technology according to the present disclosure will be specifically described by way of examples. However, the technology according to the present disclosure is not limited to these examples. Examples 1 to 3 and Comparative Examples 1 and 2 were prepared as follows (see [Table 1]). In the following description, those having the same conditions in Examples 1 to 3 and Comparative Examples 1 and 2 are not particularly distinguished.

[Crystal substrate]
First, a single crystal silicon substrate having a thickness of 200 μm was employed as the crystal substrate. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramidal texture structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
The crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness: 8 nm) made of silicon was formed on both main surfaces of the introduced crystal substrate. The film forming conditions were a substrate temperature of 150 ° C., a pressure of 120 Pa, a SiH ₄ / H ₂ flow rate value of 3/10, and a power density of 0.011 W / cm ² .

[P-type semiconductor layer (first conductivity type semiconductor layer)]
A crystal substrate having an intrinsic semiconductor layer formed on both main surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon-based thin film (film thickness 10 nm) was formed on the intrinsic semiconductor layer on the back main surface. The film forming conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a SiH ₄ / B ₂ H ₆ flow ratio value of 1/3, and a power density of 0.01 W / cm ₂ . _The flow rate of B 2 _{H 6} gas _is the flow rate of the diluent gas B 2 _{H 6} was diluted by _{H 2} to 5000 ppm.

[Lift-off layer]
In Example 1, a lift-off layer containing indium-tin composite oxide as a main component was formed to a thickness of 100 nm on a p-type hydrogenated amorphous silicon-based thin film using a magnetron sputtering apparatus. . A mixed gas of argon and oxygen was introduced into the chamber of the apparatus using indium oxide containing 20% by weight of tin oxide as a target and the substrate temperature was 150 ° C., and the pressure in the chamber was set to 0.8 Pa. Was set to be. The mixing ratio of argon and oxygen was set so that oxygen would be 10% by volume, and film formation was performed at an electric power density of 0.4 W / cm ² using an AC power source.

In Example 2, a lift-off layer containing zinc-tin composite oxide as a main component was formed to a thickness of 100 nm on a p-type hydrogenated amorphous silicon-based thin film using a magnetron sputtering apparatus. . Zinc oxide containing 40% by weight of tin oxide was used as a target, and a mixed gas of argon and oxygen was introduced into the chamber of the apparatus at a substrate temperature of 150 ° C., and the pressure in the chamber was set to 0.8 Pa. Was set to be. The mixing ratio of argon and oxygen was set so that oxygen would be 5% by volume, and film formation was performed at an electric power density of 0.4 W / cm ² using an AC power source.

In Example 3, a lift-off layer containing silicon oxide (SiO _x ) as a main component was formed to a thickness of 150 nm on a p-type hydrogenated amorphous silicon thin film using a CVD apparatus. The film formation conditions were a substrate temperature of 150 ° C., a pressure of 0.9 kPa, a SiH ₄ / CO ₂ / H ₂ flow rate ratio of 1/10/750, and a power density of 0.15 W / cm ² .

In Comparative Example 1, a lift-off layer mainly composed of zinc-tin composite oxide was formed on a p-type hydrogenated amorphous silicon-based thin film so as to have a thickness of 100 nm. Zinc oxide containing 40% by weight of tin oxide was used as a target, and a mixed gas of argon and oxygen was introduced into the chamber of the apparatus at a substrate temperature of 150 ° C., and the pressure in the chamber was set to 0.8 Pa. Was set to be. The mixing ratio of argon and oxygen was set so that oxygen would be 5% by volume, and film formation was performed at an electric power density of 0.4 W / cm ² using an AC power source.

In Comparative Example 2, a lift-off layer mainly composed of copper was formed on the p-type hydrogenated amorphous silicon-based thin film so as to have a thickness of 200 nm. Argon was introduced into the chamber of the apparatus using copper as a target and the substrate temperature at 150 ° C., and the pressure in the chamber was set to 0.6 Pa. Film formation was performed at an electric power density of 0.4 W / cm ² using an AC power source.

[Patterning of lift-off layer and first conductivity type semiconductor layer]
First, for each of Examples 1 to 3 and Comparative Examples 1 and 2, a photosensitive resist film was formed on the back side main surface of the crystal substrate on which the lift-off layer was formed. This was exposed and developed by a photolithography method to expose regions for removing the lift-off layer, p-type semiconductor layer, and intrinsic semiconductor layer.

In Examples 1 and 2, after exposure and development, the substrate was immersed in 3% by weight hydrochloric acid to remove the lift-off layer in the exposed area. After rinsing with pure water, the p-type semiconductor layer and the intrinsic semiconductor layer in the exposed region were removed by dipping in an ozone / hydrofluoric acid solution in which 5.5 ppm by weight of hydrofluoric acid was mixed with 20 ppm of ozone.

In Example 3, after exposure / development, the substrate was immersed in 5% by weight hydrofluoric acid to remove the lift-off layer in the exposed region. After rinsing with pure water, the p-type semiconductor layer and the intrinsic semiconductor layer in the exposed region were removed by dipping in an ozone / hydrofluoric acid solution in which 5.5 ppm by weight of hydrofluoric acid was mixed with 20 ppm of ozone.

In Comparative Example 1, after exposure and development, the substrate was immersed in an ozone / hydrofluoric acid solution in which 20 ppm of ozone was mixed with 5.5% by weight of hydrofluoric acid, and the lift-off layer, p-type semiconductor layer, and intrinsic region in the exposed region were exposed. The semiconductor layer was removed.

In Comparative Example 2, after exposure and development, the substrate was immersed in a 7% by weight iron (III) chloride aqueous solution to remove the lift-off layer in the exposed region. After rinsing with pure water, the p-type semiconductor layer and the intrinsic semiconductor layer in the exposed region were removed by dipping in an ozone / hydrofluoric acid solution in which 5.5 ppm by weight of hydrofluoric acid was mixed with 20 ppm of ozone.

Hereinafter, this process is referred to as a patterning process.

[N-type semiconductor layer (second conductivity type semiconductor layer)]
After the patterning step, a crystal substrate in which the exposed back main surface is cleaned with hydrofluoric acid having a concentration of 2% by weight is introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness: 8 nm) is formed on the back main surface for the first time. The film was formed under the same film formation conditions as the semiconductor layer. Subsequently, an n-type hydrogenated amorphous silicon-based thin film (film thickness: 10 nm) was formed on the formed intrinsic semiconductor layer. The film forming conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a SiH ₄ / PH ₃ / H ₂ flow ratio value of 1/2, and a power density of 0.01 W / cm ² . The flow rate of the PH ₃ gas is the flow rate of the diluent gas PH ₃ is diluted by _{H 2} to 5000 ppm.

[Removal of lift-off layer and second conductivity type semiconductor layer]
In Examples 1 and 2, a crystal substrate on which an n-type semiconductor layer is formed is immersed in hydrochloric acid having a concentration of 3% by weight as an etching solution, and a lift-off layer, an n-type semiconductor layer covering the lift-off layer, and a lift-off layer And the intrinsic semiconductor layer between the n-type semiconductor layer and the n-type semiconductor layer were collectively removed.

In Example 3, a crystal substrate on which an n-type semiconductor layer is formed is immersed in hydrofluoric acid having a concentration of 5% by weight as an etchant, and a lift-off layer, an n-type semiconductor layer on the lift-off layer, and Intrinsic semiconductor layers between the lift-off layer and the n-type semiconductor layer were collectively removed.

In Comparative Example 1, as will be described in detail later, this step is not performed because the lift-off layer was etched excessively to the extent that it does not function as a lift-off layer.

In Comparative Example 2, the crystal substrate on which the n-type semiconductor layer was formed was immersed in iron chloride (III) having a concentration of 7% by weight as an etching solution, and the lift-off layer, the n-type semiconductor layer on the lift-off layer, In addition, the intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer was collectively removed.

Hereinafter, this process is referred to as a lift-off process.

[Electrode layer, low reflection layer]
Using a magnetron sputtering apparatus, an oxide film (film thickness: 100 nm) serving as a base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. Further, a silicon nitride layer was formed on the light receiving surface side of the crystal substrate as a low reflection layer. As the transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure in the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set such that the resistivity was the lowest (so-called bottom). In addition, film formation was performed at a power density of 0.4 W / cm ² using a DC power source.

Next, etching was performed by photolithography so as to leave only the transparent conductive oxide film on the conductive semiconductor layers (p-type semiconductor layer and n-type semiconductor layer), thereby forming a transparent electrode layer. The transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, a silver paste (manufactured by Fujikura Kasei Co., Ltd .: Dotite FA-333) was screen-printed on the transparent electrode layer without dilution, and a heat treatment was performed in an oven at a temperature of 150 ° C. for 60 minutes. Thereby, the metal electrode layer was formed.

Next, an evaluation method for a back contact type solar cell will be described. Refer to [Table 1] for the evaluation results.

[Evaluation of film thickness and etching properties]
The film thickness or etching state of the lift-off layer was evaluated using an optical microscope (BX51: Olympus Optical Co., Ltd.) and SEM (Field Emission Scanning Electron Microscope S4800: Hitachi High-Technologies Corporation). After the patterning step, etching is performed in accordance with the designed patterning removal region, and the p-type semiconductor layer is not etched more than the lift-off layer as viewed from the back main surface of the crystal substrate with an optical microscope (the p-type semiconductor layer is not etched). In the case where the edge portion is not receded from the edge portion of the lift-off layer), the mark is “◯”. In the case where the lift-off layer is excessively etched and the solar cell characteristics are adversely affected, the mark is “x”.

In the lift-off process, “○” was given when the lift-off layer was removed, and “x” was given when the lift-off layer remained. In Comparative Example 2, the lift-off layer was excessively removed in the patterning process, and evaluation after the lift-off process was impossible.

[Evaluation of conversion efficiency]
A solar simulator was used to irradiate AM (air mass) 1.5 standard sunlight with a light amount of 100 mW / cm ² to measure the conversion efficiency (Eff (%)) of the solar cell. The conversion efficiency (solar cell characteristics) of Example 1 was set to 1.00, and the relative values are shown in [Table 1].

Examples 1 to 3 were good in both pattern accuracy and solar cell characteristics.

In comparison between Example 2 and Comparative Example 1, it was found that even when the zinc-tin composite oxide was used as the lift-off layer, the etching in the patterning process was improved by using two types of etching solutions. That is, in the ozone / hydrofluoric acid necessary for etching the first conductivity type semiconductor layer (here, p-type semiconductor layer) and the intrinsic semiconductor layer, the lift-off layer is etched, and the etching liquid becomes the first conductivity type semiconductor layer and It takes time to reach the intrinsic semiconductor layer, during which the lift-off layer is excessively etched. On the other hand, when two types of etching solutions (here, hydrochloric acid and ozone / hydrofluoric acid) are used, the lift-off layer is first etched with hydrochloric acid, and then the first conductivity type semiconductor layer and the intrinsic semiconductor layer are formed with ozone / hydrofluoric acid. It can be etched. While the first conductive type semiconductor layer and the intrinsic semiconductor layer are removed with ozone / hydrofluoric acid, the lift-off layer is also etched, but the first conductive type semiconductor layer and the intrinsic semiconductor layer are considerably thinner than the lift-off layer. The etching time may be short, and the etching amount of the lift-off layer is very small. For this reason, the etching in a patterning process becomes favorable.

Further, comparing Examples 1 to 3 with Comparative Example 2, ozone / hydrofluoric acid is not only used for etching the first conductivity type semiconductor layer and the intrinsic semiconductor layer, but also for the lift-off layer in a small amount. It was found that the side cut of the conductive semiconductor layer and the intrinsic semiconductor layer is suppressed. That is, there are not a few crystal grain boundaries in the metal oxide lift-off layer. When the lift-off layer is not etched at all during the etching of the first conductivity type semiconductor layer and the intrinsic semiconductor layer, the etching solution passes through the crystal grain boundaries of the lift-off layer and the first conductivity type semiconductor layer and the intrinsic semiconductor layer. May be reached. On the other hand, the lift-off layer is also etched in a small amount during the etching of the first conductive type semiconductor layer and the intrinsic semiconductor layer, so that the edge portions of the first conductive type semiconductor layer and the intrinsic semiconductor layer recede by etching. When this is done, the edge of the lift-off layer also recedes by etching. For this reason, it is possible to suppress the etching solution from etching the first conductivity type semiconductor layer and the intrinsic semiconductor layer located under the lift-off layer through the crystal grain boundaries of the lift-off layer.

In summary, compared to the comparative example, the example obtained a result that the solar cell characteristics were improved by using a lift-off layer mainly composed of an oxide and performing wet etching using two kinds of etching solutions. . This is because each layer is etched as quickly as possible using two kinds of etching solutions, and when the first conductive type semiconductor layer and the intrinsic semiconductor layer are etched, a slight amount of the lift-off layer is etched with the etching solution. As a result, both the patterning process and the lift-off process are patterned uniformly and accurately, whereby an electrical contact (in series) with the arrangement of the first conductive type semiconductor layer and the second conductive type semiconductor layer or the electrode layer. This is thought to be due to better resistance rise suppression.

In particular, when the first conductivity type semiconductor layer and the intrinsic semiconductor layer are etched, the lift-off layer is etched in a small amount by the etching solution, thereby suppressing the side cut of the first conductivity type semiconductor layer and the intrinsic semiconductor layer. Therefore, it is considered that sufficient solar cell characteristics can be obtained.

10 Solar cell 11 Crystal substrate (semiconductor substrate)
12 Intrinsic Semiconductor Layer 13 Conductive Semiconductor Layer 13p P-type Semiconductor Layer [First Conductive First Semiconductor Layer / Second Conductive Second Semiconductor Layer]
13n n-type semiconductor layer [second conductivity type first semiconductor layer / first conductivity type second semiconductor layer]
15 Electrode layer 17 Transparent electrode layer 18 Metal electrode layer LF Lift-off layer

Claims (7)

Forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate;
Laminating a lift-off layer mainly composed of an oxide on the first semiconductor layer;
Selectively removing the first semiconductor layer and the lift-off layer by etching;
Forming a second semiconductor layer of a second conductivity type on the one main surface including the first semiconductor layer and the lift-off layer;
Removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer,
In the step of selectively removing the first semiconductor layer and the lift-off layer, an etching area of the first semiconductor layer as viewed from the one main surface side in a direction perpendicular to the surface of the semiconductor substrate is the lift-off layer. A method for manufacturing a solar cell, wherein the first semiconductor layer and the lift-off layer are removed by wet etching using two or more different etching solutions so as to be equal to or less than an etching area. 2. The method for manufacturing a solar cell according to claim 1, wherein the step of selectively removing the first semiconductor layer and the lift-off layer includes a lift-off layer removing step of removing the lift-off layer, and removing the first semiconductor layer. A first semiconductor layer removing step,
The manufacturing method of the solar cell from which the kind of etching liquid used at the said lift-off layer removal process differs from the kind of etching liquid used at the said 1st semiconductor layer removal process. In the manufacturing method of the solar cell of Claim 2,
When the etchant used in the lift-off layer removal step is a first etchant and the etchant used in the first semiconductor layer removal step is a second etchant,
The first etching solution has the following relational expression (1):
Satisfying the etching rate of the first semiconductor layer << the etching rate of the lift-off layer;
The second etching solution has the following relational expression (2):
The manufacturing method of the solar cell which satisfy | fills the etching rate of a 1st semiconductor layer <the etching rate of a lift-off layer. In the method for manufacturing a solar cell according to any one of claims 1 to 3,
The lift-off layer is a method for manufacturing a solar cell whose main component is an oxide of an element selected from indium, zinc, tin, aluminum, and silicon. In the method for producing a solar cell according to any one of claims 1 to 4,
In the step of laminating the lift-off layer, a method for manufacturing a solar cell, wherein the lift-off layer is formed to have a thickness of 20 nm to 500 nm. In the method for manufacturing a solar cell according to any one of claims 1 to 5,
The semiconductor substrate has a first texture structure on each of the two main surfaces,
The method for manufacturing a solar cell, wherein the first semiconductor layer and the second semiconductor layer formed on the one main surface of the semiconductor substrate include a second texture structure reflecting the first texture structure. The method for manufacturing a solar cell according to any one of claims 1 to 6,
In the step of selectively removing the first semiconductor layer and the lift-off layer, in the step of removing the second semiconductor layer, a part of the second semiconductor layer is formed on the first semiconductor layer. A method of manufacturing a solar cell, wherein etching is performed so that an edge portion of the lift-off layer is formed so as to recede from an edge portion of the first semiconductor layer.

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