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WO2019144754A1 - Procédé de réception de signal - Google Patents

Procédé de réception de signal Download PDF

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Publication number
WO2019144754A1
WO2019144754A1 PCT/CN2018/124202 CN2018124202W WO2019144754A1 WO 2019144754 A1 WO2019144754 A1 WO 2019144754A1 CN 2018124202 W CN2018124202 W CN 2018124202W WO 2019144754 A1 WO2019144754 A1 WO 2019144754A1
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WIPO (PCT)
Prior art keywords
signal
sampling
data
bit
clock
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Ceased
Application number
PCT/CN2018/124202
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English (en)
Chinese (zh)
Inventor
黄廉真
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Googol Technology (shenzhen) Ltd
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Googol Technology (shenzhen) Ltd
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Priority to DE112018006746.7T priority Critical patent/DE112018006746T5/de
Publication of WO2019144754A1 publication Critical patent/WO2019144754A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a signal receiving method.
  • a signal receiving method is provided.
  • a signal receiving method for receiving a data signal sent from a device comprising:
  • the counter When the signal edge of the first sampling signal is detected, the counter is cleared and the counting is restarted, and the counter is incremented every time the clock period of the local clock of the master device is passed;
  • the first sampling signal is collected to obtain a second sampling signal belonging to the local clock of the master device, and a sampling clock signal is generated at the same time, where n is an integer not less than zero, the collecting station
  • the frequency of the data signal sent by the slave device is four times the transmission rate of the data signal sent by the slave device;
  • Sampling is performed in the second sampling signal by using the sampling clock signal to obtain a sampling value, and when the sampling value conforms to a rule of a transmission protocol, the second sampling signal is received.
  • the step of collecting a data signal sent from the device to obtain a first sampling signal belonging to the local clock of the slave device includes:
  • the signal edge of the first sampled signal is one of a rising edge and a falling edge.
  • the transmission protocol is an asynchronous transceiving transmission protocol.
  • the transmission protocol is a controller area network bus protocol.
  • the sampling the clock signal is used to sample the second sampling signal to obtain a sampling value.
  • the step of receiving the second sampling signal includes: :
  • sampling clock signal uses the sampling clock signal to extract feature points of the transmission protocol in the second sampling signal and perform verification, and if the verification result is correct, determine a transmission sequence of one frame of data in the second sampling signal.
  • the second sampling signal is received when it is detected that the transmission sequence of the second sampling signal conforms to the rules of the transmission protocol.
  • the feature points include a start bit, an idle bit, and a stop bit.
  • the feature points include a start bit, a parity bit, and a stop bit.
  • the sampling signal is used to extract feature points of the transmission protocol in the second sampling signal and perform verification. If the verification result is correct, determine one of the second sampling signals.
  • the steps of the transmission sequence of the frame data include:
  • the method further includes:
  • the second sampling signal is continuously collected on the rising edge of the sampling clock signal to obtain the first sample value.
  • the sampling clock signal is a square wave.
  • the data format of the one frame of data includes a 1-bit start bit, a 5-bit data bit, a 1-bit parity bit, and a 1-bit, 1.5-bit or 2-bit end bit.
  • the method further includes: when the transmission sequence of the second sampling signal does not comply with a rule of a transmission protocol, reporting an application layer, and continuing to perform the rising edge of the sampling clock signal The second sampled signal is collected to obtain a first sampled value.
  • the counter when the signal edge of the first sampling signal is detected, the counter is cleared and restarted, and the counter is added every time a clock period of the local clock of the master device is passed.
  • the steps of one include:
  • a signal receiving method for receiving a data signal sent from a device comprising:
  • the counter When the signal edge of the first sampling signal is detected, the counter is cleared and the counting is restarted, and the counter is incremented every time the clock period of the local clock of the master device is passed;
  • the first sampling signal is collected to obtain a second sampling signal belonging to the local clock of the master device, and a sampling clock signal is generated at the same time, where n is an integer not less than zero, the collecting station
  • the frequency of the data signal sent by the slave device is four times the transmission rate of the data signal sent by the slave device;
  • sampling the second sampling signal by using the sampling clock signal to obtain a sampling value, and when the sampling value meets a rule of a transmission protocol, receiving the second sampling signal;
  • the step of collecting the data signal sent from the device to obtain the first sampling signal belonging to the local clock of the slave device includes:
  • the step of sampling the second sampling signal by using the sampling clock signal to obtain a sampling value includes:
  • the second sampling signal is received when it is detected that the transmission sequence of the second sampling signal conforms to the rules of the transmission protocol.
  • FIG. 1 is a schematic flow chart of a signal receiving method provided by an embodiment
  • step S140 in the signal receiving method in the embodiment shown in FIG. 1;
  • step S141 in the signal receiving method in the embodiment shown in FIG. 2;
  • step S120 is a schematic flow chart of one embodiment of step S120 in the signal receiving method in the embodiment shown in FIG. 1;
  • FIG. 5 is a timing diagram of one of the steps S110 to S130 in the signal receiving method in the embodiment shown in FIG. 1;
  • Fig. 6 is a timing chart showing one of the embodiments of step S140 in the signal receiving method in the embodiment shown in Fig. 1.
  • an embodiment provides a signal receiving method.
  • the signal receiving method is for receiving a data signal transmitted from a device.
  • the method includes:
  • Step S110 collecting a data signal sent from the device to obtain a first sampling signal belonging to the local clock of the slave device.
  • the I2C bus is a simple, bidirectional two-wire synchronous serial bus.
  • the external physical interface of I2C uses two logical signal lines, one transmission data (SDA) and one transmission clock (SCL), to realize communication between multiple devices through protocols.
  • SDA transmission data
  • SCL transmission clock
  • the master device the device that initiates the bus to transfer data and generate a clock to open the transmission
  • any addressed device is called a slave device.
  • the relationship between master and slave, transmit and receive on the bus is not constant, but depends on the direction of data transfer at this time.
  • the master device wants to send data to the slave device, the master device first addresses the slave device, then actively sends data to the slave device, and finally the master device terminates the data transfer; if the master device wants to receive the slave device's data, the master device first searches for the slave device. Address from the device. The master device then receives the data sent from the slave device and finally terminates the receiving process by the master device.
  • the slave device transmits a data signal with the slave device local clock to the master device, and the master device receives the data signal and performs acquisition, thereby obtaining a first sampled signal with the slave device local clock.
  • Step S120 when the signal edge of the first sampling signal is detected, the counter is cleared and restarted, and the counter is incremented every time the clock period of the local clock of the master device is passed.
  • the master device internally detects the obtained first sampling signal, and when the signal edge of the first sampling signal is detected, clears the counter count, and restarts counting from zero, and the counter encounters one master every time.
  • the count of the device's local clock is incremented by one.
  • the signal edge of the first sampled signal may be a rising edge or a falling edge, but only one of them may be selected.
  • Step S130 when the counter counts up to 2+4n, collecting the first sampling signal, obtaining a second sampling signal belonging to the local clock of the master device, and simultaneously generating a sampling clock signal, where n is an integer not less than zero, and collecting the The frequency of the data signal sent from the device is four times the transmission rate of the data signal transmitted from the device.
  • the first sampling signal is internally sampled by the master device, and the second sampling signal with the local clock of the master device is obtained after multiple sampling, and at the same time, the internal device is in the counter.
  • the sampling is performed, so the count is 2+4n as the sampling clock, and the sampling clock signal is generated.
  • the primary sampling device internally samples the first sampling signal, and on the other hand, the main device internally generates a square wave sampling clock signal, which is equivalent to the local device of the slave device.
  • the clock is synchronized with the local clock of the master device, thereby eliminating the accumulated error caused by the sampling, and after a plurality of times, the second sampling signal and the sampling clock signal with the local clock of the master device are obtained.
  • n is an integer not less than zero
  • the frequency of the data signal transmitted from the device is four times the transmission rate of the data signal transmitted from the device, and four times here may be other multiples, for example, five times, six times, etc. This allows more sampled signals to be acquired from the data signals sent from the device.
  • This step eliminates the problem of time deviation caused by the inconsistent clock frequencies of the master device and the slave device, and also solves the problem that the high-level and low-level durations of the transmitted data signals are not strictly equal.
  • Step S140 sampling the second sampling signal by using the sampling clock signal to obtain a sampling value, and when the sampling value conforms to the rule of the transmission protocol, receiving the second sampling signal.
  • the transmission protocol is an asynchronous transceiver transmission protocol.
  • the transmission protocol may be a CAN (Controller Area Network) protocol or an I2C protocol, and the transmission protocol is not limited to these, as long as the transmission protocol to which the signal receiving method can be applied.
  • this article uses the asynchronous Asynchronous Receiver/Transmitter (Uart) as an example.
  • step S140 includes:
  • Step S141 extracting feature points of the transmission protocol in the second sampling signal by using the sampling clock signal and performing verification, and if the verification result is correct, determining a transmission sequence of one frame of data in the second sampling signal.
  • the feature point includes a start bit, a parity bit, and a stop bit.
  • the feature point may be adjusted according to a transmission protocol.
  • the feature point may also include a start bit and a stop bit, and may also include a start bit, a stop bit, an idle bit, and the like.
  • step S141 includes:
  • Step S1411 collecting the second sampling signal on the rising edge of the sampling clock signal to obtain a first sampling value.
  • the sampling clock signal is a square wave.
  • the main sampling device internally samples the second sampling signal to obtain a sampling value for the second sampling signal.
  • Step S1412 When the first sampled value is zero, the position where the sampled value of the second sampled signal is zero is used as the start bit of one frame of data in the second sampled signal.
  • the data format of one frame of data includes a 1-bit start bit, a 5-bit data bit, a 1-bit parity bit, and a 1-bit, 1.5-bit or 2-bit end bit.
  • the start bit must be a logical "0" level that lasts one bit time, marking the beginning of a character transfer.
  • the data bit is the valid data bit of the transmitted character immediately after the start bit.
  • the low bit of the character is transmitted first, and the high bit of the character is transmitted after the transfer.
  • the data bits are several bits, which can be set by hardware or software. In general, the number of data bits can be between 5 and 8 bits.
  • the parity bit is only one bit and is used for odd or even parity, or no parity.
  • the stop bit is 1 bit, 1.5 bit or 2 bits and can be set by software. It must be a logic "1" level, marking the end of the transmission of a character.
  • the data format of the one frame of data may further include an idle bit, and the idle bit indicates that the line is in an idle state, and the line is at a logic "1" level.
  • the idle bit can be absent, and the efficiency of asynchronous transfer is the highest at this time.
  • the first The position of the sampled value in the second sampled signal is used as the start bit of one frame of data in the second sampled signal.
  • Step S1413 relocating the parity bit and the end bit of one frame of data, and sampling the parity bit and the end bit, respectively corresponding to obtaining the second sample value and the third sample value.
  • the master device internally determines the parity bit and the end bit after 5 bits from the start bit, and then samples the parity bit and the end bit, thereby obtaining respectively.
  • the first sample value and the end bit corresponding to the parity bit correspond to the obtained second sample value.
  • Step S1414 When both the second sample value and the third sample value conform to the rules of the transmission protocol, a transmission sequence of one frame of data in the second sampled signal is determined. For example, in the value of the second sampled value plus the number of bits of "1" in the data bit is even (even parity) or odd (odd check) match, when the third sample value is 1, just send and receive asynchronously
  • the logical "1" level of the stop bit of the transmission protocol matches, meaning the end of one character, thereby determining that the transmission sequence of one frame of data in the current second sampled signal is correct.
  • the second sampling signal is continuously collected on the rising edge of the sampling clock signal to obtain the first sampling value.
  • the value of the second sample value plus the number of bits of "1" in the data bit is not an odd number or the value of the second sample value is added to the data bit when the even parity is performed.
  • the number of 1" bits is not even, or if the third sample value is not 1, and does not match the logic "1" level of the stop bit of the asynchronous transceiver transmission protocol, it does not comply with the rules of the asynchronous transceiver transmission protocol.
  • the start bit that is initially determined is wrong, so when the main device internally encounters the next rising edge of the sampling clock signal, the second sampling signal is continuously collected, and a first sample value is obtained again.
  • Step S142 buffering a transmission sequence of one frame of data in the second sampling signal, and continuing to determine a transmission sequence of the next frame data in the second sampling signal until a transmission sequence of the second sampling signal is obtained.
  • the transmission sequence of one frame of the correct second sampling signal is buffered, and then the transmission sequence of the next frame data in the second sampling signal is determined according to the above method until the transmission sequence of the second sampling signal is obtained.
  • the first-in first-out method is adopted, that is, the instruction that enters first completes and retires, and then executes the next instruction.
  • Step S143 when it is detected that the transmission sequence of the second sampling signal conforms to the rule of the transmission protocol, the second sampling signal is received. Specifically, it is next detected whether the transmission sequence of the obtained second sampling signal is really correct. If the transmission sequence of the second sampling signal also satisfies the rule of the asynchronous transmission and reception transmission protocol, the obtained second sampling signal is correct. Then the master device receives the second sampling signal. In addition, the detection of the transmission sequence of the second sampled signal is ongoing to ensure the correctness of the transmission sequence of the second sampled signal.
  • the rules for asynchronous transmit and receive transport protocols may also include a level of "1" when there is no data transmission. Therefore, it can also be added to the monitoring rule of the asynchronous transceiving transmission protocol according to this feature, thereby detecting whether the transmission sequence of the transmitted second sampling signal is correct.
  • the application layer is reported, and the second sampling signal is continuously collected on the rising edge of the sampling clock signal to obtain a first sampling value.
  • the master device determines whether the transmission sequence of the obtained second sampling signal is really correct. If the transmission sequence of the second sampling signal does not satisfy the rule of the asynchronous transmission and reception transmission protocol, it is determined that the obtained second sampling signal is an error. On the one hand, the master device initializes and reports to the application layer. On the other hand, the master device then collects the second sampled signal on the next rising signal edge of the sampling clock signal, obtains the first sampled value again, and repeats the above steps.
  • the above signal receiving method first collects a data signal sent from the device to obtain a first sampling signal belonging to a local clock of the slave device, and when detecting a rising edge or a falling edge of the first sampling signal, clearing the counter and restarting counting,
  • the counter counts to 2+4n
  • the first sampling signal is collected, and the second sampling signal belonging to the local clock of the master device is obtained, thereby eliminating the time deviation problem caused by the inconsistent clock frequencies of the master device and the slave device, and counting up at the counter.
  • 2+4n as the sampling clock signal instead of the traditional 0+4n, also solves the problem that the high-level and low-level durations of the transmitted data signal are not strictly equal.
  • the sampling clock signal is used in the second sampling signal.
  • the method solves the problem that the line length transmission delay is introduced between the devices due to the existence of the transmission distance, thereby causing the sequence of the received data to be misaligned.
  • step S110 includes:
  • the data signal sent from the device is collected, the data signal is filtered, and the filtered data signal is output through the register to obtain a first sampling signal belonging to the local clock of the slave device.
  • the master device collects the data signal sent by the slave device, first filters some noise in the data signal through low-pass filtering, and then outputs the filtered data signal through the register, thereby reducing the appearance of the master device when collecting the data signal.
  • the probability of steady state also reduces the distortion of the signal transmission, and also obtains the first sampled signal with the local clock of the slave device.
  • step S120 includes:
  • Step S121 detecting and collecting a signal edge of the first sampling signal to generate a signal edge signal, wherein the signal edge is a rising edge or a falling edge.
  • the signal of the first sampling signal is detected to be edge-acquired, so that the signal edge is generated according to the acquired signal edge, and the signal edge can only be one of a rising edge or a falling edge of the first sampling signal.
  • Step S122 when the counter encounters the signal edge of the signal edge signal, the counter is cleared and restarts counting. Specifically, when the counter encounters a rising or falling edge of the signal edge when counting, the counter's count will all be cleared and recounted from zero.
  • FIG. 5 a timing diagram of a data signal sent by a master device to a slave device according to an embodiment of the signal receiving method.
  • the slave device transmits the data signal B_Tx with the slave device local clock to the master device, and the master device receives the data signal B_Tx and performs acquisition to obtain the data signal A_Rx. Then, some noise in the data signal A_Rx is filtered out by low-pass filtering, and the filtered data signal is output through the register to obtain a first sampling signal A_Rx_Filter with a slave local clock.
  • the acquisition is performed when the rising edge of the first sampling signal A_Rx_Filter is detected, thereby generating a signal edge positive_edge according to the collected rising edge.
  • the main device internally samples the first sampling signal A_Rx_Filter once, and after sampling a plurality of times, obtains the second sampling signal A_Rx_Filter_q with the local clock of the main device, and at the same time, the counter is internally in the counter.
  • the count of Cnt is 2+4n, sampling is performed, so the count is 2+4n as the sampling clock, and the sampling clock signal sample_clk is generated.
  • the second sampling signal A_Rx_Filter_q is collected on the rising edge of the sampling clock signal sample_clk to obtain a first sampling value.
  • the position where the sampled value of the second sampled signal A_Rx_Filter_q is zero is taken as the start bit Beg of one frame of data in the second sampled signal A_Rx_Filter_q.
  • the parity bit Check and the end bit End of one frame of data are repositioned, and the parity bit Check and the end bit End are sampled, and the second sample value and the third sample value are respectively obtained.
  • a transmission sequence of one frame of data in the second sampled signal A_Rx_Filter_q is determined.
  • the transmission sequence of one frame of data in the second sampling signal A_Rx_Filter_q is buffered, and the transmission sequence of the next frame data in the second sampling signal A_Rx_Filter_q is continuously determined until the transmission sequence of the second sampling signal A_Rx_Filter_q is obtained.
  • the second sampling signal A_Rx_Filter_q is received.
  • the application layer is reported, and the second sampling signal A_Rx_Filter_q is continuously collected on the rising edge of the sampling clock signal sample_clk to obtain a first sampling value.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un procédé de réception de signal pour recevoir un signal de données envoyé par un dispositif esclave. Le procédé consiste à : collecter un signal de données envoyé par un dispositif esclave pour obtenir un premier signal d'échantillonnage appartenant à une horloge locale du dispositif esclave ; lorsqu'un front de signal du premier signal d'échantillonnage est détecté, remettre un compteur à zéro et redémarrer le comptage ; lorsqu'une valeur de comptage du compteur atteint 2+4 n, collecter le premier signal d'échantillonnage pour obtenir un second signal d'échantillonnage appartenant à une horloge locale d'un dispositif maître, et générer un signal d'horloge d'échantillonnage, la fréquence à laquelle le signal de données envoyé par le dispositif esclave est collecté étant le quadruple de la vitesse de transmission à laquelle le signal de données est envoyé par le dispositif esclave ; et exécuter un échantillonnage dans le second signal d'échantillonnage à l'aide d'un signal d'horloge d'échantillonnage pour obtenir une valeur d'échantillonnage, et lorsque la valeur d'échantillonnage satisfait des règles d'un protocole de transmission, recevoir le second signal d'échantillonnage.
PCT/CN2018/124202 2018-01-25 2018-12-27 Procédé de réception de signal Ceased WO2019144754A1 (fr)

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CN201810074581.1A CN108390752B (zh) 2018-01-25 2018-01-25 信号接收方法

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CN108390752B (zh) * 2018-01-25 2020-12-22 固高科技(深圳)有限公司 信号接收方法
CN109885525B (zh) * 2019-03-19 2021-02-12 西安联飞智能装备研究院有限责任公司 Uart接收方法、装置、电子设备及可读存储介质
CN112165525B (zh) * 2020-09-28 2023-12-08 北京视界恒通科技有限公司 一种串行数据透传方法及装置
CN112653924A (zh) * 2020-12-15 2021-04-13 上海安路信息科技有限公司 Hdmi接收方法及装置
CN113656340B (zh) * 2021-08-20 2024-10-11 西安易朴通讯技术有限公司 I2c总线的通信控制方法、系统和装置
CN114885046B (zh) * 2022-07-12 2022-09-20 成都市易冲半导体有限公司 一种scp串行通信协议的可靠高效解析方法
CN120498623B (zh) * 2025-07-15 2025-12-16 北京方芯半导体有限公司 一种基于phy芯片的数据接收方法及装置

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