WO2019039311A1 - Solid-state image capture element, image capture device, and electronic apparatus - Google Patents

Abstract

The present invention relates to a solid-state image capture element, an image capture device and an electronic apparatus which, even in a configuration in which a pixel signal read mode is switched between a tracking mode of source (SF) and a differential mode, make it possible to increase the speed of reading pixels in differential mode. When a pixel signal of a first pixel and a second pixel forming a differential pair is read, phase data D of the first pixel and phase data P of the second pixel signal are simultaneously subject to A / D conversion using the slope of the same reference signal. The invention can be applied to an image capture device.

Description

Solid-state imaging device, imaging device, and electronic device

The present disclosure relates to a solid-state imaging device, an imaging device, and an electronic device, and in particular, a configuration that can be used properly in differential mode and source follower mode, and that speeds up readout of pixel signals in differential mode. The present invention relates to a solid-state imaging device, an imaging device, and an electronic device that can be realized.

Conventionally, in a complementary metal oxide semiconductor (CMOS) image sensor, charge voltage conversion of photoelectrons is performed in a floating diffusion (FD) region (floating diffusion region), and an amplification transistor in a pixel is also referred to as a source follower (hereinafter referred to as SF (Source Follower)). ) The circuit was configured to read out the signal of the pixel from the FD region. The signal read out from the pixel in this manner is processed by a column circuit having an AD (Analog Digital) converter or the like.

In order to reduce the input conversion noise in the column circuit, it is effective to amplify the signal in the pixel portion. Then, the read-out technique which comprises a differential amplifier, without increasing the number of transistors in a pixel is proposed (for example, refer patent document 1 and patent document 2).

In this way, in the readout circuit that amplifies the signal after amplifying the signal by configuring the differential amplifier in the pixel, it is possible to obtain high conversion efficiency when converting the received light into an electrical signal and reading it out. A low noise and high quality image can be obtained from the read pixel signal.

JP, 2008-271280, A JP 2003-259218 A

By the way, in the pixel amplifier circuit (pixel amplifier: hereinafter simply referred to as pixel amplifier) composed of the conventional SF circuit, the conversion efficiency is determined by the reciprocal of the floating diffusion capacitance, but the differential amplification type pixel amplifier The gain is large and the conversion efficiency can be significantly improved.

However, because the amplitude width (dynamic range) of the output voltage is narrow, it is provided in the differential mode in the dark, in the source follower mode in the bright, and in peripheral circuits except for special applications such as shooting in very dark places. It is desirable to switch and use a switch (hereinafter also referred to as SW).

However, in order to make the pixel capable of switching between the differential mode and the source follower (SF) mode with respect to the pixel only in the SF mode, the addition of the longitudinal wiring in the pixel and the current to the column readout circuit unit It is necessary to add a mirror circuit and to add a changeover switch circuit.

On the other hand, in conventional pixels, high-speed readout is known in which pixels in a plurality of rows are read out by SF readout at the same time by increasing in-pixel longitudinal interconnections serving as vertical signal lines.

On the other hand, in the case of a pixel configured to be able to switch between the conventional differential mode and the source follower (SF) mode, the same as when the conventional SF mode pixel is speeded up to two rows / one horizontal clock in parallel readout. Although the number of vertical wirings is required, the reading speed in SF mode is 1 row / 1 horizontal clock, and the reading speed in differential mode is 0.5 row / 1 horizontal clock.

The present disclosure has been made in view of such a situation, and in particular, high-speed pixel readout in differential mode is possible even for pixels that can be switched between differential mode and source follower (SF) mode. To achieve

A solid-state imaging device according to one aspect of the present disclosure includes a pixel array unit in which a pixel generating a pixel signal according to the amount of incident light is arranged, a first pixel and a second pixel arranged in the pixel array unit. Of the first pixel, the transfer state of the charge of the first pixel, the reset state of the second pixel, the transfer of the charge of the second pixel And an analog-to-digital converter for converting the output of each of the differential circuits in an analog-to-digital conversion state, the analog-to-digital converter transmitting the charge of the first pixel, and the second pixel A solid-state imaging device that simultaneously analog-digital converts the output of the differential circuit in the reset state.

The input voltage of the first pixel forming the differential circuit and the output of the differential circuit are shorted to supply the reset voltage to the input circuit of the second pixel, and the first pixel and the second pixel are supplied. It may further include a reset unit that discharges the input charge of the pixel of.

The analog-to-digital converter includes a reference signal generator that generates a reference signal by changing at a predetermined rate, a comparator that compares the reference signal with the output of the differential circuit, and the reference signal. It is possible to count an elapsed time from being stored, and to stop counting and include a counter that holds it as a count code based on the comparison result of the comparison unit, and the count code held in the counter And the analog-to-digital conversion of the output of the differential circuit based on the predetermined rate, and the reference signal generated by the reference signal generation unit with the reference signal generated at the same timing. The counter of the counter corresponding to the comparison result when the transferred state and the output of the differential circuit of each of the reset states of the second pixel are simultaneously compared. Based on Ntokodo, the state of transferring the charges of the first pixel, and the output of the differential circuit in the reset state of the second pixel may be adapted to analog-to-digital conversion at the same time.

The comparison unit and the counter are respectively provided for the first pixel and the second pixel, and in the comparison unit, the input terminal and the output terminal are shorted to offset the reset level. An auto-zero switch for performing an auto-zero operation can be included, and when the first pixel and the second pixel are reset by the reset unit, the comparison unit of the first pixel can be included. The auto-zero switch may perform an auto-zero operation, and the reference signal generator may multiply the reference signal by a first offset corresponding to the offset.

The reference signal generation unit, after multiplying the reference signal by the first offset, returns the reference signal to a reference voltage to generate the reference signal at a predetermined rate, and the counter of the first pixel is generated. Start counting the count code, and compare the output of the differential circuit in the reset state of the first pixel with the reference signal in the comparison unit of the first pixel, and the comparison result is inverted When doing so, the counter may stop counting the count code, and hold the count code as an output of the differential circuit in a reset state of the first pixel.

After the count code in the reset state of the first pixel is held in the counter of the first pixel, the auto zero switch is performed by the auto zero switch in the comparison unit of the second pixel, The reference signal generation unit may multiply the reference signal by a second offset.

The reference signal generation unit multiplies the reference signal by the second offset and then returns the reference voltage to generate the reference signal at the predetermined rate, and the counter of the first pixel After inverting the bit of the count code, the count is started, and the output of the differential circuit in a state in which the charge of the first pixel is transferred and the reference signal are started in the comparison unit of the first pixel. When the comparison result is inverted, the counter of the first pixel stops counting the count code, the count code is reset, the reset state of the first pixel, and the charge of the first pixel. Is held as the analog-to-digital conversion result which is the difference from the transferred state, the counter of the second pixel starts counting of the count code, and the comparator of the second pixel The output of the differential circuit in the set state is compared with the reference signal, and when the comparison result is inverted, the counter of the second pixel stops counting the count code, and the count code It can be made to hold as a reset state of 2 pixels.

After the counter of the second pixel holds the count code of the output of the differential circuit in the reset state of the second pixel and transfers the charge of the second pixel, The reference signal generation unit generates the reference signal at the predetermined rate by using the reference signal as the reference voltage and causing the counter of the second pixel to invert the count code and start counting. The comparison unit of the second pixel compares the output of the differential circuit in a state in which the charge of the second pixel is transferred with the reference signal, and when the comparison result is inverted, the second The pixel counter stops counting the count code, and the count code is converted to an analog-to-digital conversion result as a difference between the reset state of the second pixel and the state of transferring the charge of the second pixel. It can be made to be held Te.

A switch that switches the connection between a first amplification transistor that amplifies a pixel signal accompanying transfer of the charge of the first pixel and a second amplification transistor that amplifies the pixel signal accompanying transfer of the charge of the second pixel Can be further included, and by switching the connection to the switch, the first pixel and the second pixel can be formed by the first amplifier transistor and the second amplifier transistor. It is possible to form a source follower circuit that outputs each pixel signal with the pixel.

An imaging device according to one aspect of the present disclosure includes a pixel array portion in which pixels generating pixel signals according to the amount of incident light are disposed, a first pixel and a second pixel disposed in the pixel array portion. The differential circuit formed by the pixels, the reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, the charge of the second pixel is transferred And an analog-to-digital converter for converting the output of each of the differential circuits in an analog-to-digital converter, the analog-to-digital converter transmitting the charge of the first pixel, and the second pixel. It is an imaging device which carries out analog-digital conversion of the output of the differential circuit of a reset state simultaneously.

An electronic device according to one aspect of the present disclosure includes a pixel array unit in which pixels generating pixel signals according to the amount of incident light are disposed, a first pixel and a second pixel disposed in the pixel array unit. The differential circuit formed by the pixels, the reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, the charge of the second pixel is transferred And an analog-to-digital converter for converting the output of each of the differential circuits in an analog-to-digital converter, the analog-to-digital converter transmitting the charge of the first pixel, and the second pixel. It is an electronic device which simultaneously analog-digital converts the output of the differential circuit in a reset state.

In one aspect of the present disclosure, a pixel array portion in which a pixel generating a pixel signal is disposed in accordance with the light amount of incident light, and a first pixel and a second pixel disposed in the pixel array portion. The differential circuit to be formed, the reset state of the first pixel, the state of transferring the charge of the first pixel, the reset state of the second pixel, and the state of transferring the charge of the second pixel An analog-to-digital converter that converts the output of each differential circuit to analog-to-digital conversion, the state in which the charge of the first pixel is transferred, and the output of the differential circuit in a reset state of the second pixel Are simultaneously analog-digital converted.

According to one aspect of the present disclosure, it is possible to realize high-speed pixel readout in the differential mode even in a pixel configured to be able to switch between the differential mode and the source follower (SF) mode.

It is a figure explaining an example of composition of a 1st embodiment of a solid-state image sensing device of this indication. It is a figure explaining the structure of the unit pixel in the solid-state image sensor of FIG. It is a figure explaining the structural example of the differential mode in the pixel array part of FIG. 1, a column read-out circuit part, and a column signal processing part. It is a circuit diagram explaining the equivalent circuit of FIG. It is a figure explaining the structural example of the source follower mode in the pixel array part of FIG. 1, a column read-out circuit part, and a column signal processing part. It is a circuit diagram explaining the equivalent circuit of FIG. It is a timing chart explaining the operation when the solid-state image sensor of FIG. 1 is in the differential mode. It is a timing chart explaining operation | movement when the solid-state image sensor of FIG. 1 is a source follower mode. It is a figure explaining an example of composition of a 2nd embodiment of a solid-state image sensing device of this indication. It is a figure explaining the structural example of the differential mode in the pixel array part of FIG. 9, a column read-out circuit part, and a column signal processing part. It is a figure explaining the structural example of the source follower mode in the pixel array part of FIG. 9, a column read-out circuit part, and a column signal processing part. 10 is a timing chart illustrating an operation when the solid-state imaging device of FIG. 9 is in a differential mode. 10 is a timing chart illustrating an operation when the solid-state imaging device of FIG. 9 is in a source follower mode. It is a figure explaining an example of composition of a back irradiation type solid imaging device and a front irradiation type solid imaging device. It is a figure which shows the example of application to a back irradiation type solid-state image sensor. It is a block diagram showing an example of composition of an imaging device as electronic equipment to which composition of an imaging device of this indication is applied. It is a figure explaining the example of use of the imaging device to which the art of this indication is applied. It is a block diagram showing an example of rough composition of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the present specification and the drawings, components having substantially the same functional configuration will be assigned the same reference numerals and redundant description will be omitted.

Also, the description will be made in the following order.
1. First Embodiment Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Application example to electronic device 6. Usage example of imaging device Application example to mobile

<< 1. First Embodiment >>
In the solid-state imaging device of the present disclosure, in the configuration capable of switching between the source follower (SF) mode and the differential mode (hereinafter, also simply referred to as SF / differential mode switching pixel), It is possible to speed up pixel readout.

FIG. 1 is a diagram showing a configuration example of a first embodiment of a solid-state imaging device to which the technology of the present disclosure is applied.

The solid-state imaging device 11 shown in FIG. 1 is formed of a solid-state imaging device such as, for example, a complementary metal oxide semiconductor (CMOS) image sensor, and includes a system control unit 31, a vertical drive unit 32, a pixel array unit 33, a column readout circuit unit 34, and a column. A signal processing unit 35, a horizontal drive unit 36, a signal processing unit 37, and a data storage unit 38 are provided.

In the solid-state imaging device 11 of FIG. 1, for example, the system control unit 31 to the data storage unit 38 are formed on one semiconductor substrate, but some of them are formed on another semiconductor substrate or the like. You may do so.

The system control unit 31 is configured by a timing generator or the like that generates various timing signals, and based on various timing signals generated by the timing generator, the vertical drive unit 32, the column readout circuit unit 34, the column signal processing unit 35, And controls the drive of the horizontal drive unit 36.

The vertical drive unit 32 is, for example, a shift register, an address decoder, or the like, and is a pixel drive unit that drives each pixel of the pixel array unit 33 simultaneously in all pixels or in units of rows.

Although the specific configuration of the vertical driving unit 32 is not shown, the vertical driving unit 32 has a reading scanning system, a sweep scanning system, or a batch sweep system and a circuit for batch transfer. ing.

The vertical driving unit 32 is controlled by the system control unit 31, and in order to read out the pixel signal from the unit pixel 51, the unit pixel 51 of the pixel array unit 33 is selectively scanned in order by row.

In the case of row driving, that is, rolling shutter operation, with regard to sweeping, sweeping scanning is performed prior to the reading scanning with respect to the reading scanning with respect to the reading row on which reading scanning is performed by the reading scanning system.

Further, in the case of global exposure, that is, global shutter operation, batch sweep-out is performed prior to batch transfer by the time of the shutter speed. By this sweeping out, unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels 51 in the readout row.

Then, a so-called electronic shutter operation is performed by sweeping out (resetting) the unnecessary charge. Here, the electronic shutter operation is an operation of discharging unnecessary light charges accumulated in the photoelectric conversion element until immediately before and newly starting exposure (starting accumulation of light charges).

The signal read out by the readout operation by the readout scanning system corresponds to the light amount of the light incident on the unit pixel 51 after the readout operation immediately before that or the electronic shutter operation.

Furthermore, in the case of row driving, a period from the reading timing in the previous reading operation or the sweeping timing in the electronic shutter operation to the reading timing in the current reading operation is the photocharge storage time (exposure time) in the unit pixel 51 Become. In the case of global exposure, the time from batch sweep-out to batch transfer is the accumulation time (exposure time).

In addition, here, the vertical driving unit 32 and the pixel row including the unit pixels 51 are connected by various signal lines.

That is, for example, in a pixel row including unit pixels 51, a signal line SEL (FIG. 2) for setting unit pixels 51 in the pixel row to a selected state, and a signal line RST (FIG. 2) for resetting unit pixels 51. And a signal line TRG (FIG. 2) for transferring charge in the unit pixel 51.

Similarly, signal lines corresponding to the signal line SEL (FIG. 2), the signal line RST (FIG. 2), and the signal line TRG (FIG. 2) are connected to the other pixel rows. For example, in the pixel row consisting of the unit pixel 51 in the nth row, the signal line SEL (FIG. 2) for setting the unit pixel 51 in the pixel row in the nth row and the signal for resetting the unit pixel 51 A line RST (FIG. 2) and a signal line TRG (FIG. 2) for transferring charges in the unit pixel 51 are connected.

The signal lines SEL (FIG. 2), RST (FIG. 2), and TRG (FIG. 2) are provided for each pixel row of the unit pixel 51.

In the pixel array unit 33, a plurality of pixels are arranged in a matrix, and unit pixels 51 for mainly receiving light incident from a subject and performing photoelectric conversion to obtain a target pixel signal are arranged. There is.

As described above, in the effective pixel area of the pixel array section 33, a plurality of unit pixels 51 are two-dimensionally arranged in a matrix, that is, in an array.

Each unit pixel 51 photoelectrically converts light incident from a subject to generate photocharges of charge amounts according to the amount of incident light and accumulates the light charges internally, and is capable of outputting a signal according to the photocharges It is an effective unit pixel which has an element. In particular, in this example, the unit pixel 51 is a readout pixel that is a readout target of a pixel signal according to the light amount of light incident from the outside. The unit pixel 51 is provided with, for example, a photodiode as a photoelectric conversion element.

It is to be noted that in the pixel array section 33, other than the effective unit pixel, a dummy unit pixel having a structure not having a photodiode for performing photoelectric conversion and light reception surface shielded to block incident light from the outside. There may be a case where a light shielding unit pixel equivalent to the effective pixel includes a region in which the light shielding unit pixel is two-dimensionally arranged in a matrix.

Also, in the following, the unit pixel is appropriately referred to simply as a pixel, and the light charge of the charge amount according to the amount of incident light of light incident on the unit pixel is also referred to as charge as appropriate.

The column readout circuit unit 34 is a circuit (constant current source) 71 for supplying a constant current for each pixel column to at least a selected pixel row in the pixel array unit 33, and a current mirror circuit 72 constituting a high gain amplifier. , And readout mode switches SW1 to SW9 (FIG. 3) for switching these, and together with a transistor in a selected pixel in the pixel array unit 33, configure an amplifier, convert a photocharge signal into a voltage signal and Output to

The column readout circuit unit 34 constitutes a differential amplifier circuit together with the transistors in the selected pixel of the pixel array unit 33, and the differential amplifier circuit converts the signal of the photocharge into a voltage signal and outputs it to the vertical signal line.

The column signal processing unit 35 is, for example, a single slope type column AD converter including the comparator 91, the counter 92, the reference signal generation unit 93, and the like, and from the unit pixel 51 under control of the system control unit 31. The read out signal is subjected to AD conversion, and the obtained pixel signal is supplied to the signal processing unit 37. In addition, the column signal processing unit 35 executes, for example, CDS (Correlated Double Sampling; correlation double sampling) processing as noise removal processing, and removes pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors. .

The horizontal drive unit 36 is configured by a shift register, an address decoder, and the like, and is a horizontal drive unit that selects unit circuits corresponding to the pixel columns of the column signal processing unit 35 in order. The pixel signals subjected to the signal processing in the column signal processing unit 35 are sequentially output to the signal processing unit 37 by the selective scanning by the horizontal driving unit 36.

The signal processing unit 37 performs various signal processing such as addition processing on the pixel signal supplied from the column signal processing unit 35.

The data storage unit 38 temporarily stores data necessary for the signal processing in the signal processing unit 37.

The signal processing unit 37 and the data storage unit 38 are configured to be processed by software by an external signal processing unit provided on a substrate different from the solid-state imaging device 11, for example, a DSP (Digital Signal Processor) or another arithmetic device. Alternatively, it may be mounted on the same substrate as the solid-state imaging device 11.

<Basic configuration and function example of unit pixel>
Next, with reference to FIG. 2, a basic configuration and a function example of the unit pixel 51 will be described.

The unit pixel 51 shown in FIG. 2 includes a photodiode PD (Photodiode), a transfer transistor Trg-Tr, a reset transistor Rst-Tr, an amplification transistor Amp-Tr, a selection transistor Sel-Tr, and a floating diffusion region FD (hereinafter referred to simply as (Also referred to as FD).

Here, the transfer transistor Trg-Tr, the reset transistor Rst-Tr, the amplification transistor Amp-Tr, and the selection transistor Sel-Tr are nMOS transistors.

The photodiode PD is a photoelectric conversion element that generates an electric charge according to the light amount of incident light by photoelectrically converting light incident from the outside.

The transfer transistor Trg-Tr is provided between the photodiode PD and the FD, and transfers the charge obtained by photoelectric conversion in the photodiode PD and accumulated in the photodiode PD to the FD.

Here, the signal line TRG is connected to the gate of the transfer transistor Trg-Tr, and the transfer transistor Trg-Tr is a drive signal TRG_S that is a signal pulse supplied from the vertical drive unit 32 via the signal line TRG. Drive accordingly.

Specifically, when the transfer transistor Trg-Tr is turned on by the drive signal TRG_S, that is, when the drive signal TRG_S is brought to a high level which is a higher voltage level, the charge stored in the photodiode PD is transferred to the FD. Transfer to

The reset transistor Rst-Tr is provided between a predetermined power supply and the FD, and a signal line RST is connected to the gate of the reset transistor Rst-Tr. In particular, here, the drain of the reset transistor Rst-Tr is connected to a predetermined power supply via the signal line VRD. The source of the reset transistor Rst-Tr may be connected to the signal line VRD.

The reset transistor Rst-Tr is driven according to a drive signal RST_S which is a signal pulse supplied from the vertical drive unit 32 via the signal line RST.

Specifically, when the reset transistor Rst-Tr is turned on by the drive signal RST_S before and after signal readout from the unit pixel 51, that is, the drive signal RST_S is set to a high level which is a higher voltage level. And reset operation. That is, the reset transistor Rst-Tr resets the FD and the photodiode PD by discharging the charge stored in the FD and the photodiode PD to a predetermined power supply via the signal line VRD.

The drain of the amplification transistor Amp-Tr is connected to the source of the selection transistor Sel-Tr, and the source of the amplification transistor Amp-Tr is connected to the signal line VPX. Note that the drain of the amplification transistor Amp-Tr may be connected to the signal line VPX.

The gate of the amplification transistor Amp-Tr is connected to the FD. The amplification transistor Amp-Tr functions as an amplifier that receives the potential fluctuation of the FD connected to its own gate as an input signal, and the output voltage signal output from the amplification transistor Amp-Tr is transmitted through the selection transistor Sel-Tr. It is output to the vertical signal line VSL.

The output voltage signal output from the amplification transistor Amp-Tr in this manner is output to the column readout circuit unit 34 via the selection transistor Sel-Tr and the vertical signal line VSL.

The signal line VPX connected to the amplification transistor Amp-Tr is connected to the tail current sources Mn [2j], Mn [] at the time of reading out the signal from the unit pixel 51 in the differential amplifier circuit formed of one unit pixel 51. 2j-1] (see FIG. 3) is an in-phase node of the differential pair to be connected.

The drain of the selection transistor Sel-Tr is connected to the vertical signal line VSL, and the source of the selection transistor Sel-Tr is connected to the drain of the amplification transistor Amp-Tr. The source of the selection transistor Sel-Tr may be connected to the vertical signal line VSL.

Further, the selection transistor Sel-Tr is driven according to the drive signal SEL_S which is a signal pulse supplied from the vertical drive unit 32 via the signal line SEL.

Specifically, when the selection transistor Sel-Tr is turned on by the drive signal SEL_S at the time of reading out a signal from the unit pixel 51, that is, when the drive signal SEL_S is brought to a high level which is a higher voltage level, The vertical signal line VSL and the amplification transistor Amp-Tr are electrically connected, and the unit pixel 51 provided with itself is brought into a selected state. When the unit pixel 51 is selected, an output voltage signal output from the amplification transistor Amp-Tr is output to the vertical signal line VSL via the selection transistor Sel-Tr.

In the unit pixel 51 configured as described above, the reset transistor Rst-Tr that discharges the charge accumulated in the photodiodes PD and FD is an FD according to the drive signal RST_S supplied from the vertical drive unit 32 via the signal line RST. Turn on and off the discharge of the accumulated charge.

For example, when the drive signal RST_S of high level is supplied, the reset transistor Rst-Tr discharges the charge stored in the FD via the signal line VRD. That is, the FD is reset.

On the other hand, when the low level drive signal RST_S which is a voltage level lower than the high level, for example, is supplied, the reset transistor Rst-Tr electrically disconnects the FD and the signal line VRD. As a result, the FD is in a floating state.

On the other hand, the photodiode PD photoelectrically converts incident light from the outside, and generates and accumulates a charge according to the light amount of the incident light.

The transfer transistor Trg-Tr turns on / off the transfer of charge from the photodiode PD to the FD according to the drive signal TRG_S supplied from the vertical drive unit 32.

For example, when the drive signal TRG_S of high level is supplied, the transfer transistor Trg-Tr transfers the charge accumulated in the photodiode PD to the FD, and when the drive signal TRG_S of low level is supplied, the transfer transistor Trg-Tr is transferred to the FD Stop the transfer of charge.

While the transfer transistor Trg-Tr stops transferring the charge to the FD, the charge obtained by the photoelectric conversion is accumulated in the photodiode PD.

The floating diffusion region FD has a function of accumulating charge transferred from the photodiode PD through the transfer transistor Trg-Tr.

When the reset transistor Rst-Tr is turned off and the FD is in a floating state, the potential of the FD is modulated according to the charge amount of the charge stored in the FD.

The selection transistor Sel-Tr turns on / off the output of the output voltage signal from the amplification transistor Amp-Tr to the vertical signal line VSL in accordance with the drive signal SEL_S supplied from the vertical drive unit 32.

For example, when the drive signal SEL_S of high level is supplied, the selection transistor Sel-Tr outputs the output voltage signal to the vertical signal line VSL, and when the drive signal SEL_S of low level is supplied, the vertical direction of the output voltage signal is output. Stop the output to the signal line VSL.

As a result, in the vertical signal line VSL to which the plurality of unit pixels 51 are connected, only the output voltage signal output from the unit pixel 51 in the selected state can be extracted (read out).

The pixel configuration of the unit pixel 51 is not limited to the configuration shown in FIG. 2, and may be any pixel configuration, such as a pixel configuration capable of global shutter operation with memory and a pixel configuration of floating diffusion sharing type. Good. That is, the present technology is applicable to various pixel configurations.

<Configuration Example of Differential Mode of Basic Pixel Reading Unit>
Next, with reference to FIG. 3, a configuration example of the differential mode of the basic pixel readout unit in the solid-state imaging device of FIG. 1 will be described. Here, the basic pixel readout unit refers to a unit pixel pair of the same row and adjacent columns forming a differential pair and a unit pixel pair of adjacent rows for performing two-row parallel readout, and the basic pixel readout units are further divided into two in a matrix. A pixel array unit 33 is formed in a three-dimensional arrangement. Further, the basic pixel reading unit can also individually read unit pixel pairs in accordance with the operation of the switches SW1 to SW11 described later. Hereinafter, a mode in which 2-row parallel reading is performed in a unit pixel pair is referred to as a differential mode, and a mode in which reading is individually performed in a unit pixel pair is referred to as a source follower (SF) mode.

In FIG. 3, the switches SW1 to SW11 are shown as connected in the differential mode.

The column readout circuit unit 34 and the column signal processing unit 35 are configured, for example, as shown in FIG. In FIG. 3, the same reference numerals are given to configurations having the same functions as the configurations in FIG. 1 and FIG. 2, and the description thereof will be appropriately omitted. Further, FIG. 3 shows an example of a pair of unit pixels 51 in a predetermined column of the [2j-1] th column and the [2j] th column in the pixel array unit 33, and The unit pixel 51 [2j-1] and the unit pixel 51 [2j] are referred to, and the other configurations are referred to similarly.

In the example shown in FIG. 3, the unit pixel 51 [2j-1] and the unit pixel 51 [2j] are formed as a differential pair, and the unit pixel 51 [2j-1] and the unit pixel 51 [2j] The column readout circuit unit 34 and the differential amplifier circuit which is a differential amplifier are formed.

In particular, here, the unit pixel 51 [2j-1] is the reference side of the differential pair, that is, the positive input side, and the unit pixel 51 [2j] is the signal readout side of the differential pair, that is, the negative input side. It is assumed.

That is, the unit pixel 51 [2j-1] includes the photodiode PD [2j-1], the transfer transistor Trg-Tr [2j-1], the reset transistor Rst-Tr [2j-1], and the amplification transistor Amp-Tr [2j]. -1], selection transistor Sel-Tr [2j-1], and floating diffusion region FD [2j-1].

The photodiode PD [2j-1], the transfer transistor Trg-Tr [2j-1], the reset transistor Rst-Tr [2j-1], the amplification transistor Amp-Tr [2j-1], the selection transistor Sel-Tr [ 2j-1] and the floating diffusion region FD [2j-1] are the photodiode PD [2j] of the unit pixel 51 [2j], the transfer transistor Trg-Tr [2j], and the reset transistor Rst-Tr [2j-1]. It corresponds to the amplification transistor Amp-Tr [2j], the selection transistor Sel-Tr [2j], and the floating diffusion region FD [2j], and is arranged in the same connection relation.

The gate of the selection transistor Sel-Tr [2j-1] is connected to the signal line SEL2 [n], and the selection transistor Sel-Tr [2j-1] is connected to the vertical drive unit 32 via the signal line SEL2 [n]. It drives according to drive signal SEL2 [n] supplied from.

Similarly, the gate of the reset transistor Rst-Tr [2j-1] is connected to the signal line RST2 [n], and the reset transistor Rst-Tr [2j-1] is vertical via the signal line RST2 [n]. It drives according to drive signal RST2 [n] supplied from the drive part 32. FIG.

The gate of the transfer transistor Trg-Tr [2j-1] is connected to the signal line TRG [2], and the transfer transistor Trg-Tr [2j-1] is connected to the vertical drive unit 32 via the signal line TRG [2]. It drives according to drive signal TRG2 [n] supplied from.

Furthermore, in the unit pixel 51 [2j-1], the source of the amplification transistor Amp-Tr [2j-1] is connected to the signal line VPX [2j-1], and the drain of the selection transistor Sel-Tr [2j-1] Are connected to the vertical signal line VSL [2j-1]. The drain of the reset transistor Rst-Tr [2j-1] is connected to the signal line VRD [2j-1].

The drain of the amplification transistor Amp-Tr [2j-1] is connected to the signal line VPX [2j-1], the source of the selection transistor Sel-Tr [2j-1] is connected to the vertical signal line VSL, and the reset transistor The source of Rst-Tr [2j-1] may be connected to the signal line VRD [2j-1].

In addition, the column read out circuit unit 34 includes tail current sources Mn [2j-1] and Mn [2j] of the differential pair, a load transistor Mp-Tr [2j] serving as an output load of the differential pair, and a load transistor Mp-. A load transistor Mp-Tr [2j-1] which is a reference destination of the current mirror circuit 72 which copies a predetermined current to Tr [2j] is provided. The tail current sources Mn [2j-1] and Mn [2j] of the differential pair constitute a constant current source 71.

Here, the load transistor Mp-Tr [2j] and the load transistor Mp-Tr [2j-1] are pMOS transistors, and the load transistor Mp-Tr [2j] and the load transistor Mp-Tr [2j-1] make a current flow. A mirror circuit 72 is configured.

Furthermore, the column readout circuit unit 34 includes switches SW1 to SW9 that switch between the differential mode and the SF mode. The switches SW1 and SW2 are turned on in the differential mode and turned off in the SF mode. Also, the switch SW3 is turned off in the differential mode and turned on in the SF mode. The switches SW4 and SW5 are turned on in the differential mode and turned off in the SF mode. The switches SW6 and SW7 are turned off in the differential mode and turned on in the SF mode.

That is, in the differential mode, as shown in FIG. 3, the switches SW1, SW2, SW4, SW5, and SW9 are turned on and the switches SW3, SW6, SW7, and SW8 are turned off.

In the example of FIG. 3, the signal line VRD [2j-1] is a signal line for discharging the charge accumulated in the FD [2j-1] of the unit pixel 51 [2j-1].

The tail current sources Mn [2j-1] and Mn [2j] flow a constant current to the unit pixel 51 [2j-1] and the unit pixel 51 [2j] which are differential pairs.

Here, the switches SW4 and SW5 of the current sources Mn [2j-1] and Mn [2j] are unit pixel 51 [2j-1] by the signal lines VPX [2j-1] and VPX [2j] as the wiring in the pixel. And a source of the amplification transistor Amp-Tr [2j] of the unit pixel 51 [2j].

The drain of the load transistor Mp-Tr [2j] is electrically connected to the drain of the selection transistor Sel-Tr [2j] of the unit pixel 51 [2j] via the vertical signal line VSL [2j] which is an intra-pixel wiring. The source of the load transistor Mp-Tr [2j] is connected to the power supply of a predetermined voltage VDD.

In addition, the drain of the load transistor Mp-Tr [2j-1] is connected to the selection transistor Sel-Tr [2j-1 of the unit pixel [2j-1] through the vertical signal line VSL [2j-1] which is the wiring in the pixel. The source of the load transistor Mp-Tr [2j-1] is connected to the power supply of a predetermined voltage VDD.

Furthermore, the gate of the load transistor Mp-Tr [2j-1] is connected to the gate of the load transistor Mp-Tr [2j] and the drain of the load transistor Mp-Tr [2j-1], whereby the load transistor A current mirror circuit 72 is configured of Mp-Tr [2j-1] and load transistor Mp-Tr [2j].

Further, the signal line VRD [2j-1] is electrically connected to the drain of the reset transistor Rst-Tr [2j-1] of the unit pixel 51 [2j-1].

Furthermore, when the pixel array unit 33 and the column readout circuit unit 34 function in the differential mode, the FD [2j-1] of the unit pixel 51 [2j-1] is the positive input side of the differential amplifier circuit (input node The FD [2j] of the unit pixel 51 [2j] is the negative input side (input node) of the differential amplifier circuit. That is, the signal accumulated in FD [2 j-1] is a positive input, and the signal accumulated in FD [2 j] is a negative input. Then, the potential of the vertical signal line VSL [2j] is output, and is output to the column signal processing unit 35 from the output terminal Vout [2j]. The output terminal Vout [2j-1] outputs the potential of the vertical signal line VSL [2j-1] to the column signal processing unit 35.

Further, in the differential mode in FIG. 3, the vertical signal line VSL [2j] and the signal line VRD [2j] are electrically connected, and the input / output as a differential amplifier circuit at the time of resetting of the FD [2j]. By short-circuiting, it is possible to apply negative feedback and secure an operating point for stable operation as a differential amplifier circuit.

When the column readout circuit unit 34, the unit pixel 51 [2j], and the unit pixel 51 [2j-1] as described above function in the differential mode, for example, the number of pixel columns provided in the pixel array unit 33 ( The number of columns), that is, each pixel column, is provided in parallel.

The column signal processing unit 35 includes comparators 91 [2j-1], 91 [2j], counters 92 [2j-1], 92 [2j], a reference signal generator 93, and switches SW10 and SW11. The pixel signal read out from the column readout circuit unit 34 is converted from an analog signal to a digital signal and output.

The comparator 91 [2 j] compares the reference signal consisting of the ramp voltage supplied from the reference signal generation unit 93 to the positive input terminal with the read signal input from the output terminal Vout [2 j], and outputs the output terminal Vout. When the read signal input from [2j] exceeds the ramp voltage, it is output to the counter 92 [2j].

The counter 92 [2j] counts up the counter so as to correspond to the slope of the reference signal consisting of the ramp voltage generated by the reference signal generation unit 93, and digitizes the count code at the timing when the comparison result of the comparator 91 is inverted. A pixel signal consisting of a signal is held as it is.

The comparator 91 [2j-1] receives the ramp voltage supplied to the positive input terminal from the reference signal generator 93, the output terminal Vout [2j-1], or the read signal input from the output terminal Vout [2j]. And when the read signal input from the output terminal Vout [2j-1] or the output terminal Vout [2j] exceeds the lamp voltage, the counter 92 [2j-1] is output.

The switches SW10 and SW11 switch the connection to the negative input terminal of the comparator 91 [2j-1] to either the output terminal Vout [2j-1] or the output terminal Vout [2j-1]. In the differential mode, the switch SW10 is turned off and the switch SW11 is turned on. Also, in the SF mode, the switch SW10 is turned on and the switch SW11 is turned off.

The counter 92 [2j-1] counts up the counter so as to correspond to the slope of the reference signal consisting of the ramp voltage generated by the reference signal generation unit 93, and the count code at the timing when the comparison result of the comparator 91 is inverted. Are output as pixel signals consisting of digital signals.

With such a configuration, single-slope AD converters are configured by the comparators 91 [2j-1], 91 [2j] and the counters 92 [2j-1], 92 [2j].

The comparators 91 [2j-1] and 91 [2j] respectively have auto-zero switches AZSW1-1 and 1-2 and AZSW2-1 and 2-2, and are turned on when the auto-zero operation is performed. Be done.

FIG. 4 shows an equivalent circuit in the differential mode of the pixel array unit 33 and the column readout circuit unit 34 in FIG. As shown in FIG. 4, the differential readout circuit is configured by unit pixels 51 [2 j−1] and 51 [2 j], constant current source 71 and current mirror circuit 72, and unit pixel 51 [2 j −1]. , 51 [2j] form a unit pixel pair.

<Configuration Example of Basic Pixel Reading Unit in SF Mode>
Next, with reference to FIG. 5, a configuration example in the SF (source follower) mode of the basic pixel reading unit of the solid-state imaging device 11 of FIG. 1 will be described. The various circuit configurations are the same as those described with reference to FIG. 3 and thus the description thereof is omitted, and here, the operations of SW1 to SW11 will be described.

In the source follower mode, the switches SW6 to SW8 and SW10 are turned on, and the switches SW1 to SW5, SW9 and SW11 are turned off.

As a result, as shown in the equivalent circuit diagram of FIG. 6, the basic pixel readout units respectively correspond to the unit pixels 51 [2j-1] and 51 [2j], function as source follower circuits, and are independent of each other. Thus, the pixel signals are read out to the comparators 91 [2j-1] and 91 [2j].

<Pixel Reading Operation of Differential Mode in Basic Pixel Reading Unit of FIG. 3>
Next, with reference to the timing chart of FIG. 7, the pixel readout operation in the basic pixel readout unit of the differential mode of FIG. 3 will be described. Here, the n-th row pixel readout will be described.

FIG. 7 shows, from the top, the horizontal synchronization signal XHS, the drive signal SEL [n], the drive signal RST1 [n] of the unit pixel 51 [2j], and the drive signal RST2 [n] of the unit pixel 51 [2j-1]. , Drive signal TRG1 [n] of unit pixel 51 [2j], drive signal TRG2 [n] of unit pixel 51 [2j-1], control signal AZSW1 of auto-zero switch AZSW1-1, AZSW1-2, auto-zero switch AZSW2-1 , And the operation period of the counter 92 [2j] and the operation period of the counter 92 [2j-1] are indicated by the solid line waveforms, respectively.

Further, under the operation period of the counter 92 [2j] and the operation period of the counter 92 [2j-1], the internal node of the comparator 91 [2j-1] at the output terminal Vout [2j] and the output terminal Vout Internal nodes of the comparator 91 [2 j] in [2 j] are indicated by waveforms of one-dot chain line and two-dot chain line respectively, and reference corresponding to the internal nodes of the comparators 91 [2 j], 91 [2 j-1] The signal is shown as a bold waveform.

Furthermore, under the internal nodes of the comparators 91 [2 j] and 91 [2 j-1], the counter code of the counter 92 [2 j] and the counter code of the counter 92 [2 j-1] are indicated by solid waveforms. ing.

That is, at time t0, the horizontal synchronization signal XHS is input.

When the drive signal SEL [n] is switched from L level to H level from time t1 to t24, a tail current source from the source to the drain of the amplification transistors Amp-Tr [2j-1] and Amp-Tr [2j] A current is supplied from Mn [2j-1] and Mn [2j], and the potentials of the floating diffusion regions FD [2j-1] and FD [2j] of the selected unit pixel 51 [2j-1], 51 [2j] are selected. The voltage signals amplified to VSL [2j-1] and VSL [2j] are output as a differential amplifier circuit with an input voltage signal.

From time t2 to t5, the auto zero switches AZSW1-1 and 1-2 of the comparator 91 [2 j] are turned on to perform an auto zero operation, whereby each of the positive input terminal and the negative input terminal in the comparator 91 [2 j] is performed. Become almost the same voltage.

Further, in the period from time t3 to time t4, the H level is applied to the drive signals RST1 [n] and RST2 [n], and the floating diffusion region FD [2j] of the unit pixel 51 [2j], 51 [2j-1]. The charge stored in FD [2 j-1] is discharged, and the signal level is initialized (reset).

At this time, an output terminal Vout [2j] which is an output of the differential amplifier circuit is differentially amplified through VRD [2j] of unit pixel 51 [2j] and reset transistor Rst-Tr [2j] of unit pixel 51 [2j]. It is electrically connected to the floating diffusion region FD [2 j] of the unit pixel 51 [2 j] which is one of the inputs of the circuit.

As a result, since the differential amplifier circuit is negatively fed back to the floating diffusion region FD [2j] where the output Vout [2j] is one input side and is virtually grounded, it is externally fixed to the power supply Vrst. Another FD [2j-1], FD [2j], and power supply Vout [2j] have the same potential, and a so-called voltage follower circuit is formed.

During the period from time t4 to time t5, the reset signal RST [n] is applied to the L level, and the floating diffusion regions FD [2j-1] and FD [2j] of the unit pixels 51 [2j-1] and 51 [2j] are The signal lines VRD [2j-1] and VRD [2j] are electrically disconnected from each other to be in a floating state.

At this time, since the floating diffusion region FD [2j] of the unit pixel 51 [2j] and the floating diffusion region FD [2j-1] of the unit pixel 51 [2j-1] have substantially the same structure, the reset off time is Since the potential fluctuation (reset feedthrough) is also substantially the same, the potentials of the floating diffusion regions FD [2j-1] and FD [2j] behave substantially the same, and thus are canceled as an in-phase signal and the output of the differential amplifier circuit is reset. It will be in the state which does not change substantially from the power supply Vrst at the time of ON.

Further, as described above, the auto zero switches AZSW1-1 and AZSW1-2 of the comparator 91 [2 j] are turned on to perform an auto zero operation, whereby the positive input terminal and the negative input in the comparator 91 [2 j] The terminals have almost the same voltage.

At times t5 to t6, the reference signal generation unit 93 multiplies the reference voltage (for example, the GND level) by the offset VPOF1 and applies the reference signal to the positive input terminal of the comparator 91 [2j]. This is to make the distribution fall within the range of the slope signal of the P phase because the P phase level varies with a constant distribution for each pixel (column).

Next, at time t6, the reference signal generation unit 93 resets the reference signal to the reference voltage, and after securing a sufficient settling period, at time t7, the reference signal generation unit 93 generates a reference signal consisting of a lamp voltage Are outputted while raising at predetermined time intervals, and AD conversion is started.

Further, at time t7, the system control unit 31 puts only the counter 92 [2j] out of the counters 92 [2j] and 92 [2j-1] into a valid state. The counter 92 [2 j] counts the time from the transition start timing of the slope signal formed of the reference signal from the reference signal generation unit 93 to the inversion of the output of the comparator 91 [2 j].

That is, counter 92 [2j] counts time from time t7 to time t8 in FIG. 7 and holds data in a data holding unit (not shown) as a count code P1 of the P phase signal of unit pixel 51 [2j]. Do. The reference signal generator 93 raises the lamp voltage until time t9.

In the period from time t10 to time t13, the reference signal generation unit 93 applies the offset VPOF2 to the reference voltage. At this time, the auto zero switches AZSW2-1 and AZSW2-2 of the comparator 91 [2j-1] are turned on, and the auto zero operation of the comparator [2 j-1] is performed.

When the drive signal TRG1 [n] of the unit pixel 51 [2j] is applied in a pulse shape from time t11 to time t12, the charge accumulated in the photodiode PD [2j] of the unit pixel 51 [2j] is the transfer transistor Trg It is transferred to the floating diffusion region FD [2j] by -Tr [2j].

The potential of the floating diffusion region FD [2j] of the unit pixel 51 [2j] is modulated by the transferred charges, and this is input as a voltage signal to the gate of the amplification transistor Amp-Tr [2j] of the unit pixel 51 [2j]. A voltage signal corresponding to the accumulated charge amount is output to the output terminal Vout [2j] as the positive direction amplitude on the vertical signal line VSL [2j] on the unit pixel 51 [2j] side.

At this time, the reference signal generation unit 93 sets the reference signal to the state where the offset VPOF2 is applied to the reference signal, and turns on the auto zero switches AZSW2-1 and AZSW2-2 of the comparator 91 [2j-1]. By doing this, the auto zero operation of the comparator 91 [2j-1] is performed. Although the pixel signal of the unit pixel 51 [2j] is transferred and the output terminal Vout [2j] is oscillated from the power supply Vrst, this state becomes the reset level for the unit pixel 51 [2j-1].

During time t12 to t13, the counter 92 [2j] inverts all bits of the held count code P1 and holds it as a count code (−P1).

At time t13, the reference signal generation unit 93 resets the reference signal, and returns to the reference voltage from the state where the offset VPOF2 is applied.

At times t14 to t17 after resetting the reference signal to the reference voltage and securing a sufficient settling period, the counters 92 [2j] and 92 [2j-1] enable the count operation, and the reference signal generation unit 93 Generates a reference signal consisting of a ramp voltage to start AD conversion on the signal of the same output terminal Vout [2j].

At this time, the counter 92 [2j] starts counting from the start point of the slope signal transition of the reference signal generated by the reference signal generation unit 93 with the count code (-P1) as the initial value. When the output is inverted, the counting operation is stopped. In FIG. 7, at time t15, the output of the comparator 91 [2j] is inverted, so the counter 92 [2j] stops the count operation at time t15 and stores the count result.

At this time, the count code stored in the counter 92 [2j] is the count code (D1-P1) obtained by subtracting the P-phase count code P1 from the D-phase count code D1 and is output to the signal processing unit 37. It is held by the counter 92 [2j].

On the other hand, the comparator 91 [2j-1] performs the comparison operation on the basis of the operating point at which the auto-zero operation is performed from time t10 to t13, and the counter 92 [2j-1] The counting is started from the signal transition start time point, and when the output of the comparator 91 [2j-1] is inverted at time t16, the counting operation is stopped and the count code P2 of the P phase signal of the unit pixel 51 [2j-1] Store

At time t18, the reference signal generation unit 93 resets the reference signal to return to the reference voltage.

At time t19 to t20, when the drive signal TRG2 [n] of the unit pixel 51 [2j-1] is applied in a pulse shape, the signal is accumulated in the photodiode PD [2j-1] of the unit pixel 51 [2j-1]. The transferred charge is transferred to the floating diffusion region FD [2j-1] by the transfer transistor Trg-Tr [2j-1]. The potential of the floating diffusion region FD [2j-1] of the unit pixel 51 [2j-1] is modulated by the transferred charge, and this is the potential of the amplification transistor Amp-Tr [2j-1] of the unit pixel 51 [2j-1]. When a voltage signal is input to the gate, a voltage signal corresponding to the accumulated charge amount is output to the output terminal Vout [2j] as negative amplitude based on the voltage at time t16.

In the period from time t19 to t20, the count code P2 held by the counter 92 [2j-1] is inverted in all bits to be a count code (-P2).

From time t21 to t23, the counting operation of the counter 92 [2j-1] is enabled and AD conversion is performed. The counter 92 [2j-1] starts counting from the slope signal transition start time point of the reference signal generated by the reference signal generation unit 93 with the count code (-P2) as the initial value, and the comparator 91 [2j-1] At time t22 in FIG. 7, the count operation is stopped, and the count code (D2-P2) which is the difference between the D phase signal of unit pixel 51 [2j-1] and the P phase signal is obtained. .

The polarities of the digital codes of the pixel signals of the unit pixels 51 [2j] and 51 [2j-1] determined by the count code (D1-P1) and the count code (D2-P2) are mutually inverted. Therefore, the polarity and reference level (for example, the level at the time of dark imaging) are inverted by inverting the positive and negative of the count (D2-P2) by the signal processing unit 37 (or an external DSP (Digital Signal Processor)). Processing is needed. Thus, the CDS processing for removing noise is established by taking the difference between the read reset level and the signal level.

Further, according to the above processing, the P-phase signal of the unit pixel 51 [2j], the D-phase signal of the unit pixel 51 [2j], the P-phase signal of the pixel signal 51 [2j-1], 51 [2j-1] When detecting four types of D-phase signals of pixel signals, the D-phase signal of unit pixel 51 [2j] and the P-phase signal of pixel signals of 51 [2j-1] have the same slope signal transition As it can be determined by counting from the start point, it is possible to detect almost simultaneously.

As a result, four types of signals can be determined not by four transitions of the slope signal but by three transitions of the slope signal. Therefore, two pixels of the unit pixel 51 [2j] and 51 [2j-1] are obtained. It becomes possible to shorten the period required for reading out the pixel signal of the pixel signal, and it becomes possible to realize high-speed reading out of the pixel signal even in the differential mode.

<Pixel Reading Operation in SF Mode in Basic Pixel Reading Unit of FIG. 5>

Next, with reference to the timing chart of FIG. 8, the pixel readout operation in the basic pixel readout unit of the SF mode of FIG. 5 will be described. Here, the n-th row pixel readout will be described.

At time t0, the horizontal synchronization signal XHS is input.

When the drive signal SEL [n] is switched from the L level to the H level from time t101 to time t117, the loads from the source to the drain of the amplification transistors Amp-Tr [2j-1] and Amp-Tr [2j] are generated. A current is supplied from the tail current sources Mn [2j-1] and Mn [2j] to be a MOS circuit, and the floating diffusion region FD [2j-1] of the selected unit pixel 51 [2j-1], 51 [2j] , And a voltage signal amplified to VSL [2j-1] and VSL [2j] as a differential amplifier circuit using the potential of FD [2j] as an input voltage signal is output.

At time t102 to t105, the auto zero switches AZSW1-1, AZSW1-2, AZSW2-1, and AZSW2-2 of the comparators 91 [2j] and 91 [2j-1] are turned on to perform the auto zero operation, The respective positive input terminals and negative input terminals in the comparators 91 [2j] and 91 [2j-1] have substantially the same voltage.

Further, the reference signal generation unit 93 multiplies the reference voltage (for example, the GND level) by the offset VPOF1 and applies the reference signal to the positive input terminals of the comparators 91 [2j] and 91 [2j-1]. This is to make the distribution fall within the range of the slope signal of the P phase because the P phase level varies with a constant distribution for each pixel (column).

In the period from time t103 to t104, the H level is applied to the drive signals RST1 [n] and RST2 [n], and the floating diffusion regions FD [2j] and FD [of the unit pixels 51 [2j] and 51 [2j-1]. 2j-1] is discharged and the signal level is initialized (reset).

During the period from time t104 to time t105, the drive signal RST [n] is applied to the L level, and the floating diffusion regions FD [2j-1], FD [2j] of the unit pixels 51 [2j-1], 51 [2j] are The signal lines VRD [2j-1] and VRD [2j] are electrically disconnected from each other to be in a floating state.

At time t106, the reference signal generation unit 93 resets the reference signal to rise to the reference voltage, and after securing a sufficient settling period, at time t107, the reference signal generation unit 93 performs reference including the lamp voltage The signal is outputted while being dropped at a predetermined time interval, and AD conversion is started.

In addition, at times t107 to t109, the system control unit 31 puts the counters 92 [2j] and 92 [2j-1] into count effective states. The counters 92 [2j] and 92 [2j-1] output the comparators 91 [2j] and 91 [2j-1] from the transition start timing of the slope signal from the reference signal generation unit 93 which is the reference signal. Count the time to reverse.

That is, the counter 92 [2j] counts the time from time t107 to time t108 in FIG. 7 and sets the internal code as count codes P1 and P2 of P-phase signals of the unit pixels 51 [2j] and 51 [2j-1]. The data is held in a data holding unit (not shown). The reference signal generation unit 93 decreases the lamp voltage until time t109.

When drive signals TRG1 [n] and TRG2 [n] of unit pixels 51 [2j] and 51 [2j-1] are applied in a pulse shape from time t110 to time t111, unit pixels 51 [2j] and 51 [2j] are applied. The charges accumulated in the photodiodes PD [2j] and PD [2j-1] of the cell -1] are floated in the floating diffusion region FD [2j], by the transfer transistors Trg-Tr [2j] and Trg-Tr [2j-1], respectively. It is transferred to FD [2j-1].

The potential of the floating diffusion regions FD [2j] and FD [2j-1] of the unit pixel 51 [2j] and 51 [2j-1] is modulated by the transferred charge, and this is modulated by the unit pixel 51 [2j] and 51 [2j]. When the voltage signals are input to the gates of the respective amplification transistors Amp-Tr [2j] and Amp-Tr [2j-1] of -1], the vertical signal lines VSL [2j] and VSL [2j-1] are respectively input. A voltage signal corresponding to the accumulated charge amount is output.

At time t112, the counters 92 [2j] and 92 [2j-1] respectively invert the count codes P1 and P2 by all bits to obtain count codes (-P1) and (-P2).

From time t113 to t116, the system control unit 31 controls the counters 92 [2j] and 92 [2j-1] to put them in count enable states.

The counter 92 [2 j] performs counting operation for the time from the transition start timing of the slope signal formed of the reference signal generated by the reference signal generation unit 93 to the output of the comparator 91 [2 j] being inverted. In FIG. 8, the counter 92 [2j] counts up to the time from time t113 to time t114, and stores the count code D1-P1.

In addition, the counter 92 [2j-1] performs the counting operation only for the time from the transition start timing of the slope signal including the reference signal generated by the reference signal generation unit 93 to the inversion of the output of the comparator 91 [2j-1]. Do. In FIG. 8, the counter 92 [2j-1] counts up to the time from time t113 to t115, and stores the count code D2-P2.

In this manner, the counters 92 [2j] and 92 [2j-1] perform CDS processing for removing noise by taking the difference between the read reset level and the signal level, and the pixel from which the noise has been removed. Read out the signal.

The operation as described above can realize the operation in the SF mode.

In the pixel readout processing with reference to the timing charts in FIG. 7 and FIG. 8, with regard to the slope direction of the reference signal generated by the reference signal generation unit 93, the ramp voltage is boosted in the differential mode of FIG. Although an example of the slope signal to be used has been described, a step-down slope signal may be used. Further, in the source follower mode of FIG. 8, an example of the slope signal for stepping down the ramp voltage has been described, but a slope signal for boosting may be used.

That is, as described above, in the solid-state imaging device 11 of the present disclosure described with reference to FIGS. 3 and 5, switching between the differential mode and the SF mode is possible. Therefore, it is possible to use the differential mode in the dark to improve sensitivity and to use the SF mode in the bright to capture high resolution images. Further, in the SF mode, it becomes possible to realize normal pixel readout, and also in the differential mode, the D-phase signal of one unit pixel and the other unit pixel between the pixels forming a unit pixel pair. Since it is possible to read out the P-phase signal of the signal at substantially the same time, it is possible to speed up the reading of the pixel signal in the differential mode.

<< 2. Second embodiment >>
In the above, the example in which the comparator 91 and the counter 92 are provided in each column has been described, but the circuit scale is simplified by providing one each in two columns serving as a unit pixel pair, and the power consumption and the manufacturing cost May be reduced.

FIG. 9 is a diagram showing a configuration example of the second embodiment of the solid-state imaging device 11 to which the present technology is applied. In the configuration example of the solid-state imaging device of FIG. 9, the same reference numerals are given to configurations having the same functions as the configuration of the solid-state imaging device 11 of FIG.

That is, the solid-state imaging device of FIG. 9 differs from the solid-state imaging device of FIG. 1 in that in the column signal processing unit 35, one comparator 91 and one counter 92 are arranged in two columns.

As shown by the solid-state imaging device in FIG. 9, the circuit scale can be simplified by providing the comparators 91 and the counters 92 one by one in two rows, thereby reducing power consumption and manufacturing cost. It becomes possible.

<Configuration Example of Differential Mode of Basic Pixel Reading Unit>
Next, with reference to FIG. 10, a configuration example of the basic pixel readout unit in the differential mode in the solid-state imaging device of FIG. 9 will be described. The components having the same functions as the components in the configuration example in the differential mode of the basic pixel reading unit in FIG. 5 are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

That is, in the configuration example of the basic pixel readout unit of FIG. 10 in the differential mode, a point different from the configuration example of the basic pixel readout unit of FIG. 5 in the differential mode is that a total of two are provided for each unit pixel pair. The comparator 91 and the counter 92, which have been described above, are one in number.

That is, in the configuration example in the differential mode of the basic pixel readout unit of FIG. 10, the column signal processing unit 35 differs from the configuration example in the differential mode of the basic pixel readout unit of FIG. 1] and the counter 92 [2j-1] are omitted, only the comparator 91 [2j] and the counter 92 [2j] are provided, and the switches SW12 and SW13 are provided instead of the switches SW10 and SW11. That is the point.

The switch SW12 is turned on when in the differential mode, and the switch SW13 is turned off. Further, in the case of the SF mode, the switches SW12 and SW13 are switched on or off correspondingly when reading out with the unit pixels 51 [2j], 51 [2j-1] (see FIG. 11).

The comparator 91 [2j] and the counter 92 [2j] are one unit pixel pair, so the operation in the differential mode is different from the operation described with reference to the timing chart of FIG. The description will be made later with reference to the timing chart of FIG.

<Configuration Example of Basic Pixel Reading Unit in SF Mode>
Next, with reference to FIG. 11, a configuration example in the SF (source follower) mode of the basic pixel reading unit of the solid-state imaging device of FIG. 9 will be described. The various circuit configurations are the same as those described with reference to FIG. 10, and thus the description thereof is omitted. Here, the operations of the SW 12 and the SW 13 will be described.

In the source follower mode, when the pixel signal of the unit pixel 51 [2j] is read, the switch SW12 is turned on, the switch SW13 is turned off, and the pixel signal of the unit pixel 51 [2j-1] is read, The switch SW12 is turned off and the switch SW13 is turned on.

That is, in this case, the pixel signal of the unit pixel 51 [2j] and the pixel signal of the unit pixel 51 [2j-1] are alternately read out independently at different timings.

<Pixel Reading Operation of Differential Mode in Basic Pixel Reading Unit of FIG. 10>
Next, with reference to the timing chart of FIG. 12, the pixel readout operation in the basic pixel readout unit of the differential mode of FIG. 10 will be described. Here, the n-th row pixel readout will be described.

In FIG. 12, the AZSW2, the internal node of the comparator 91 [2j-1] at the output terminal Vout [2j], and the counter code of the counter 92 [2j-1] are not described, and the counter 92 [2j] A counter data transfer timing and a signal processing period are added to the lower part of the operation period.

At time t0, the horizontal synchronization signal XHS is input.

At time t201 to t223, when the drive signal SEL [n] is switched from L level to H level, a tail current source from the source to the drain of the amplification transistors Amp-Tr [2j-1] and Amp-Tr [2j]. A current is supplied from Mn [2j-1] and Mn [2j], and the potentials of the floating diffusion regions FD [2j-1] and FD [2j] of the selected unit pixel 51 [2j-1], 51 [2j] are selected. The voltage signals amplified to VSL [2j-1] and VSL [2j] are output as a differential amplifier circuit with an input voltage signal.

From time t202 to t205, the auto zero switches AZSW1-1 and AZSW1-2 of the comparator 91 [2 j] are turned on to perform an auto zero operation, whereby each of the positive input terminal and the negative input terminal in the comparator 91 [2 j] is performed. Become almost the same voltage.

Further, in the period from time t203 to t204, the H level is applied to the drive signals RST1 [n] and RST2 [n], and the floating diffusion region FD [2j] of the unit pixel 51 [2j], 51 [2j-1], The charge stored in FD [2 j-1] is discharged, and the signal level is initialized (reset).

At this time, an output terminal Vout [2j] which is an output of the differential amplifier circuit is differentially amplified through VRD [2j] of unit pixel 51 [2j] and reset transistor Rst-Tr [2j] of unit pixel 51 [2j]. It is electrically connected to the floating diffusion region FD [2 j] of the unit pixel 51 [2 j] which is one of the inputs of the circuit.

As a result, since the differential amplifier circuit is negatively fed back to the floating diffusion region FD [2j] where the output Vout [2j] is one input side and is virtually grounded, the external amplification is fixed to the power supply Vrst. One FD [2j-1], FD [2j], and power supply Vout [2j] have the same potential, and a so-called voltage follower circuit is formed.

During the period from time t204 to time t205, the reset signal RST [n] is applied to the L level, and the floating diffusion regions FD [2j-1], FD [2j] of the unit pixels 51 [2j-1], 51 [2j] are The signal lines VRD [2j-1] and VRD [2j] are electrically disconnected from each other to be in a floating state.

At this time, since the floating diffusion region FD [2j] of the unit pixel 51 [2j] and the floating diffusion region FD [2j-1] of the unit pixel 51 [2j-1] have substantially the same structure, the reset off time is Since the potential fluctuation (reset feedthrough) is also substantially the same, the potentials of the floating diffusion regions FD [2j-1] and FD [2j] behave substantially the same, and thus are canceled as an in-phase signal and the output of the differential amplifier circuit is reset. It will be in the state which does not substantially change from the power supply Vrst at the time of ON.

At this time, as described above, the auto zero switches AZSW1-1 and AZSW1-2 of the comparator 91 [2 j] are turned on and the auto zero operation is performed, whereby the positive input terminal and the negative electrode in the comparator 91 [2 j] The input terminals have almost the same voltage.

At times t205 to t206, the reference signal generation unit 93 multiplies the reference voltage (for example, GND level) by the offset VPOF1 and applies the reference signal to the positive input terminal of the comparator 91 [2j]. This is to make the distribution fall within the range of the slope signal of the P phase because the P phase level varies with a constant distribution for each pixel (column).

Next, at time t206, the reference signal generation unit 93 resets the reference signal to the reference voltage, and after securing a sufficient settling period, at time t207, the reference signal generation unit 93 generates a reference signal consisting of a lamp voltage. Are outputted while raising at predetermined time intervals, and AD conversion is started.

In addition, at time t207, the system control unit 31 puts only the counter 92 [2j] into a count effective state. The counter 92 [2j] counts time from the transition start timing of the slope signal from the reference signal generation unit 93 which is a reference signal to the time when the output of the comparator 91 [2j] is inverted.

That is, the counter 92 [2j] counts the time from time t207 to t208 in FIG. 12, and the internal data (not shown) as a count code (first signal) S1 of the P phase signal of the unit pixel 51 [2j]. Hold data in the holding unit. The reference signal generator 93 raises the lamp voltage until time t209.

When the drive signal TRG1 [n] of the unit pixel 51 [2j] is applied in a pulse shape in the period from time t210 to t211, the charge accumulated in the photodiode PD [2j] of the unit pixel 51 [2j] is transferred It is transferred to the floating diffusion region FD [2j] by the transistor Trg-Tr [2j].

The potential of the floating diffusion region FD [2j] of the unit pixel 51 [2j] is modulated by the transferred charges, and this is input as a voltage signal to the gate of the amplification transistor Amp-Tr [2j] of the unit pixel 51 [2j]. A voltage signal corresponding to the accumulated charge amount is output to the output terminal Vout [2j] as the positive direction amplitude on the vertical signal line VSL [2j] on the unit pixel 51 [2j] side. At this time, the counter 92 [2j] transfers the count code S1 to the signal processing unit 37, and resets the count code.

At time t212, the reference signal generation unit 93 resets the reference signal to return to the reference voltage.

At times t213 to t215 after resetting the reference signal to the reference voltage and securing a sufficient settling period, the counter 92 [2j] enables the counting operation, and the reference signal generation unit 93 performs the reference including the lamp voltage. The signal is boosted at predetermined time intervals, and AD conversion is started on the signal of the same output terminal Vout [2j].

At this time, the counter 92 [2j] starts counting from the start point of the slope signal transition of the reference signal generated by the reference signal generation unit 93, and stops the counting operation when the output of the comparator 91 [2j] is inverted. In FIG. 12, since the output of the comparator 91 [2j] is inverted at time t214, the counter 92 [2j] stops the count operation at time t215 and the count code which is the count result (second code Signal S2 is stored. The reference signal generation unit 93 boosts the voltage level boosted up to time t209 to a value obtained by adding only the voltage Vs2.

At this time, the count code S1 stored in the counter 92 [2j] is a D-phase signal of the unit pixel 51 [2j] and a P-phase signal of the unit pixel 51 [2j-1] at the same time. It is held in the counter 92 [2j] until it is output to 37.

At time t216, the reference signal generation unit 93 resets the reference signal to return to the reference voltage. At this time, the reference signal generation unit 93 resets the voltage reduced by the voltage Vs3 with respect to the reference voltage.

From time t217 to t218, when the drive signal TRG2 [n] of the unit pixel 51 [2j-1] is applied in a pulse shape, the pulse is accumulated in the photodiode PD [2j-1] of the unit pixel 51 [2j-1]. The transferred charge is transferred to the floating diffusion region FD [2j-1] by the transfer transistor Trg-Tr [2j-1]. The potential of the floating diffusion region FD [2j-1] of the unit pixel 51 [2j-1] is modulated by the transferred charge, and this is the potential of the amplification transistor Amp-Tr [2j-1] of the unit pixel 51 [2j-1]. When a voltage signal is input to the gate, a voltage signal corresponding to the accumulated charge amount is output to the output terminal Vout [2j] as negative amplitude based on the voltage at time t216. At this time, the counter 92 [2j] transfers the count S2 to the signal processing unit 37, and resets the count code.

At times t219 to t221, the counting operation of the counter 92 [2j] is enabled and AD conversion is performed. The counter 92 [2j] starts counting from the start point of the slope signal transition of the reference signal generated by the reference signal generation unit 93 from the initial value consisting of count 0, and the output of the comparator 91 [2j] is inverted. At time t220 in FIG. 12, the count operation is stopped, and a count code (third signal) S3 which is a D-phase signal of the unit pixel 51 [2j-1] is obtained.

At times t222 to t224, the counter 92 [2j] transfers the count S3 to the signal processing unit 37, and resets the count.

From time t225 to t226, the signal processing unit 37 realizes CDS by subtraction processing of the count code S2−count code S1, and a good unit pixel 51 [2 j from which the fixed pattern noise has been removed by the difference between the reset level and the signal level. Can be obtained. Further, the signal processing unit 37 realizes CDS by subtraction processing of the count code S3 to the count code S2, and the fixed pattern noise is removed by the difference between the reset level and the signal level. A pixel signal can be obtained.

Note that the signal processing unit 37 inverts the positive / negative of the count code S3−count code S2 and further adds digital processing to unite the polarity and reference level (for example, Dark imaging level) of the digital signal to the unit pixel 51 [2j]. Can be adjusted to

The voltages Vs2 and Vs3 are values provided to guarantee the signal range of the analog-to-digital converter, and it is desirable that the voltage range be equal to or higher than the signal range of the analog-to-digital converter. However, setting the voltages Vs2 and Vs3 large results in a large count code, so the count operation time of the counter 92 [2j] becomes long, the processing time decreases, and the power consumption increases.

Even if the circuit scale is simplified by providing the comparator 91 and the counter 92 in two rows by the above processing, a solid-state imaging device in which the comparator 91 and the counter 92 are provided in each row It is possible to realize readout of pixel signals in the differential mode at the same processing speed as in the above, and further to reduce power consumption and manufacturing cost.

<Pixel Readout in SF Mode in Basic Pixel Readout Unit of FIG. 11>
Next, with reference to the timing chart of FIG. 13, pixel readout in the SF mode in the basic pixel readout unit of FIG. 11 will be described.

In FIG. 13, the control signal AZSW2 of the auto-zero switch, the internal node of the comparator 91 [2j-1] at the output terminal Vout [2j], and the counter 92 [2j-1] with respect to the waveform diagram of FIG. The operation timing of the switches SW12 and SW13 is shown below the control signal AZSW1 of the auto zero switch.

That is, in the period from time t302 to t317 in the waveform diagram of FIG. 13, the switch SW12 is on and the period in which the switch SW13 is off, the pixel readout of the unit pixel 51 [2j] in the timing chart in FIG. A processing operation is performed. Further, in the period from time t318 to t333, when the switch SW12 is off and the switch SW13 is on, the pixel readout processing operation of the unit pixel 51 [2j-1] in the timing chart in FIG. Ru.

That is, the pixel readout operations of the unit pixel 51 [2j-1] and the unit pixel 51 [2j] are alternately performed at different timings.

Therefore, although the processing speed in the SF mode is twice that of the processing described with reference to FIG. 8, the SF mode and the differential mode can be switched and used, and in the differential mode, pixel readout Since the operation can be speeded up and the circuit scale can be reduced, power consumption and manufacturing cost can be reduced.

<< 3. Third Embodiment >>
<Surface-illuminated solid-state imaging device and back-illuminated solid-state imaging device>
Next, the solid-state imaging device 11 of FIGS. 1 and 9 of the present disclosure may be either a front-illuminated solid-state imaging device or a back-illuminated solid-state imaging device.

The back-illuminated solid-state imaging device is the configuration shown in the right part of FIG. In the back-illuminated solid-state imaging device, when the incident direction of light is from the upper side to the lower side in the figure, the on-chip lens 101 for condensing incident light in the pixel unit from the top on the photodiode PD A color filter 102 for transmitting light, a photoelectric conversion layer 103 provided with a photodiode PD for generating a pixel signal according to the light quantity of incident light by photoelectric conversion, a wiring layer 104 provided with a wiring, and a substrate 105 Ru.

Moreover, a front side illumination type solid-state imaging device is a structure shown by the left part of FIG. In the surface-illuminated solid-state imaging device, when the incident direction of light is from the upper side to the lower side in the figure, the on-chip lens 101 that condenses the incident light in the pixel unit from the top in the photodiode A color filter 102 for transmitting light, a wiring layer 104 provided with a wiring, a photoelectric conversion layer 103 provided with a photodiode PD for generating a pixel signal according to the light quantity of incident light by photoelectric conversion, and a substrate 105 Ru.

However, although the opening area D2 for incident light is provided in the front surface irradiation type wiring layer 104, the wiring is smaller than the rear surface irradiation type opening area D1 by providing the wiring. For this reason, the back-illuminated solid-state imaging device is more advantageous than the front-illuminated solid-state imaging device in terms of pixel characteristics such as sensitivity and full-well-capacity. On the other hand, the front side illumination type solid-state imaging device has a simpler manufacturing process than the back side illumination type solid-state imaging device, and therefore can be manufactured at low cost.

<< 4. Fourth Embodiment >>
<On the pixel structure of the solid-state imaging device>
By the way, in the solid-state imaging device having the configuration shown in FIG. 3, FIG. 5, FIG. 10, and FIG. 11, the differential amplifier circuit is formed for reading the pixel signal, and the wiring in the pixel is increased.

Therefore, it is possible to reduce the demerit such as the decrease in sensitivity if the present technology is applied to the back side illumination type solid state imaging device rather than the front side illumination type solid state imaging device.

Therefore, for example, pixel array circuits such as the system control unit 31, the vertical drive unit 32, the column readout circuit unit 34, the column signal processing unit 35, the horizontal drive unit 36, the signal processing unit 37, and the data storage unit 38 The substrate 33 may be stacked on another substrate.

That is, for example, when the present technology is applied to a general backside illumination type image sensor, as shown by an arrow W11 in FIG. 15, the pixel array unit 33 and the pixel periphery of the system control unit 31 etc. on a predetermined substrate BLK11. A circuit is formed. In FIG. 15, parts corresponding to the case in FIG. 1 are given the same reference numerals, and the description thereof will be omitted as appropriate.

Here, the pixel array portion 33 is formed at the central portion of the substrate BLK11, and pixel peripheral circuits such as the read load portion 22 are formed in the region R31 and the region R32 around the pixel array portion 33.

Then, the substrate BLK11 and the substrate BLK12, which is a silicon substrate for support, are bonded, that is, the substrate BLK11 is stacked on the substrate BLK12, and the solid-state imaging device illustrated in FIGS. 3, 5, 10, and 11 is obtained. One corresponding back-illuminated image sensor is used.

However, in the present technology, since a current mirror circuit 72 composed of a pMOS transistor and various changeover switches such as switches SW1 to SW13 are required to constitute a differential amplifier circuit, the area of the pixel peripheral circuit is large. Tend to

Therefore, an increase in area can be suppressed, for example, by using a stacked back side illumination type image sensor in which the pixel array unit 33 and the pixel peripheral circuit are provided on different substrates as indicated by an arrow W12.

That is, in the example shown by the arrow W12, the pixel array unit 33 is formed on the substrate BLK11, and pixel peripheral circuits such as the system control unit 31 are formed in the region R41 and the region R42 of the substrate BLK12.

Then, one stacked back-illuminated image sensor to which the present technology is applied, corresponding to the solid-state imaging device shown in FIG. 3, FIG. 5, FIG. 10, and FIG. Be done.

In such a laminated back-illuminated image sensor, the chip area of the image sensor itself can be reduced. In the multilayer back-illuminated image sensor, the substrate BLK11 in which the pixels are formed is manufactured by a pixel dedicated process, and the substrate BLK12 in which the pixel peripheral circuits are formed is dedicated to the pixel peripheral circuits without worrying about the formation of the pixels and the like. Can be manufactured by the process of From these things, cost reduction and performance enhancement of the solid-state imaging device 11 can be realized.

In the example shown by arrow W12, all the pixel peripheral circuits are formed on the substrate BLK12 side, but at least a part of the pixel peripheral circuits is formed on the substrate BLK12 side, and the remaining part of the pixel peripheral circuits is the substrate BLK11 It may be formed on the side.

<< 5. Application example to electronic device >>
The solid-state imaging device described above can be applied to various electronic devices such as an imaging device such as a digital still camera or a digital video camera, a mobile phone having an imaging function, or another device having an imaging function. .

FIG. 16 is a block diagram illustrating a configuration example of an imaging device as an electronic device to which the present technology is applied.

The imaging device 201 shown in FIG. 16 includes an optical system 202, a shutter device 203, a solid-state imaging device 204, a drive circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208, and can handle still images and moving images. It can be imaged.

The optical system 202 includes one or a plurality of lenses, guides light from a subject (incident light) to the solid-state imaging device 204, and forms an image on the light receiving surface of the solid-state imaging device 204.

The shutter device 203 is disposed between the optical system 202 and the solid-state imaging device 204, and controls the light irradiation period and the light shielding period to the solid-state imaging device 204 according to the control of the drive circuit 205.

The solid-state imaging device 204 is configured by a package including the solid-state imaging device described above. The solid-state imaging device 204 accumulates signal charges for a certain period according to the light focused on the light receiving surface via the optical system 202 and the shutter device 203. The signal charge stored in the solid-state imaging device 204 is transferred according to a drive signal (timing signal) supplied from the drive circuit 205.

The drive circuit 205 outputs a drive signal for controlling the transfer operation of the solid-state imaging device 204 and the shutter operation of the shutter device 203 to drive the solid-state imaging device 204 and the shutter device 203.

The signal processing circuit 206 performs various types of signal processing on the signal charge output from the solid-state imaging device 204. An image (image data) obtained by the signal processing circuit 206 performing signal processing is supplied to a monitor 207 and displayed, or supplied to a memory 208 and stored (recorded).

Also in the imaging device 201 configured in this manner, the above-described solid-state imaging device 11 of FIGS. 3, 5, 10, and 11 is applied to the optical system 202 and the solid-state imaging device 204 to obtain differential. It is possible to speed up the pixel readout speed in the differential mode with the configuration in which the mode and the SF mode are switched to operate.

<< 6. Example of use of image sensor >>
FIG. 17 is a view showing a use example using the solid-state imaging device 11 of FIGS. 3, 5, 10 and 11 described above.

The imaging device described above can be used, for example, in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

-A device that captures images for viewing, such as a digital camera or a portable device with a camera function-For safe driving such as automatic stop, recognition of driver's condition, etc. A device provided for traffic, such as an on-vehicle sensor for capturing images of the rear, surroundings, inside of a car, a monitoring camera for monitoring a traveling vehicle or a road, a distance measuring sensor for measuring distance between vehicles, etc. Devices used for home appliances such as TVs, refrigerators, air conditioners, etc. to perform imaging and device operation according to the gesture ・ Endoscopes, devices for performing blood vessel imaging by receiving infrared light, etc. Equipment provided for medical and healthcare use-Equipment provided for security, such as surveillance cameras for crime prevention, cameras for personal identification, etc.-Skin measuring equipment for photographing skin, photographing for scalp Beauty, such as a microscope Equipment provided for use-Equipment provided for sports use, such as action cameras and wearable cameras for sports applications, etc.-Used for agriculture, such as cameras for monitoring the condition of fields and crops apparatus

<< 7. Applications to mobiles >>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on any type of mobile object such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot May be

FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

Vehicle control system 12000 includes a plurality of electronic control units connected via communication network 12001. In the example shown in FIG. 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

The driveline control unit 12010 controls the operation of devices related to the driveline of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, and a steering angle of the vehicle. adjusting steering mechanism, and functions as a control device of the braking device or the like to generate a braking force of the vehicle.

Body system control unit 12020 controls the operation of the camera settings device to the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device of various lamps such as a headlamp, a back lamp, a brake lamp, a blinker or a fog lamp. In this case, the body system control unit 12020, the signal of the radio wave or various switches is transmitted from wireless controller to replace the key can be entered. Body system control unit 12020 receives an input of these radio or signal, the door lock device for a vehicle, the power window device, controls the lamp.

Outside vehicle information detection unit 12030 detects information outside the vehicle equipped with vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The out-of-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle, and receives the captured image. The external information detection unit 12030 may perform object detection processing or distance detection processing of a person, a vehicle, an obstacle, a sign, characters on a road surface, or the like based on the received image.

Imaging unit 12031 receives light, an optical sensor for outputting an electric signal corresponding to the received light amount of the light. The imaging unit 12031 can output an electric signal as an image or can output it as distance measurement information. The light image pickup unit 12031 is received may be a visible light, it may be invisible light such as infrared rays.

Vehicle information detection unit 12040 detects the vehicle information. For example, a driver state detection unit 12041 that detects a state of a driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera for imaging the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver does not go to sleep.

The microcomputer 12051 calculates a control target value of the driving force generation device, the steering mechanism or the braking device based on the information inside and outside the vehicle acquired by the outside information detecting unit 12030 or the in-vehicle information detecting unit 12040, and a drive system control unit A control command can be output to 12010. For example, the microcomputer 12051 is collision avoidance or cushioning of the vehicle, follow-up running based on inter-vehicle distance, vehicle speed maintained running, functions realized in the vehicle collision warning, or ADAS including lane departure warning of the vehicle (Advanced Driver Assistance System) It is possible to perform coordinated control aiming at

The microcomputer 12051, the driving force generating device on the basis of the information around the vehicle acquired by the outside information detection unit 12030 or vehicle information detection unit 12040, by controlling the steering mechanism or braking device, the driver automatic operation such that autonomously traveling without depending on the operation can be carried out cooperative control for the purpose of.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the external information detection unit 12030. For example, the microcomputer 12051 controls the headlamps in response to the preceding vehicle or the position where the oncoming vehicle is detected outside the vehicle information detection unit 12030, the cooperative control for the purpose of achieving the anti-glare such as switching the high beam to the low beam It can be carried out.

Audio and image output unit 12052 transmits, to the passenger or outside of the vehicle, at least one of the output signal of the voice and image to be output device to inform a visually or aurally information. In the example of FIG. 18, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as the output device. Display unit 12062, for example, may include at least one of the on-board display and head-up display.

FIG. 19 is a diagram illustrating an example of the installation position of the imaging unit 12031.

In FIG. 19, the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose of the vehicle 12100, a side mirror, a rear bumper, a back door, and an upper portion of a windshield of a vehicle interior. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle cabin mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 included in the side mirror mainly acquire an image of the side of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. Images in the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 19 shows an example of the imaging range of the imaging units 12101 to 12104. Imaging range 12111 indicates an imaging range of the imaging unit 12101 provided in the front nose, imaging range 12112,12113 are each an imaging range of the imaging unit 12102,12103 provided on the side mirror, an imaging range 12114 is The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's eye view of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging unit 12101 through 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging devices, or an imaging device having pixels for phase difference detection.

For example, the microcomputer 12051, based on the distance information obtained from to no imaging unit 12101 12104, and the distance to the three-dimensional object in to no imaging range 12111 in 12114, the temporal change of the distance (relative speed with respect to the vehicle 12100) In particular, it is possible to extract a three-dimensional object traveling at a predetermined speed (for example, 0 km / h or more) in substantially the same direction as the vehicle 12100 as a leading vehicle, in particular by finding the it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Automatic operation or the like for autonomously traveling without depending on the way of the driver operation can perform cooperative control for the purpose.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data relating to three-dimensional objects into two-dimensional vehicles such as two-wheeled vehicles, ordinary vehicles, large vehicles, classification and extracted, can be used for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to see. Then, the microcomputer 12051 determines a collision risk which indicates the risk of collision with the obstacle, when a situation that might collide with the collision risk set value or more, through an audio speaker 12061, a display portion 12062 By outputting a warning to the driver or performing forcible deceleration or avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.

At least one of the imaging unit 12101 to 12104, may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as an infrared camera, and pattern matching processing on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not The procedure is to determine Microcomputer 12051 is, determines that the pedestrian in the captured image of the imaging unit 12101 to 12104 is present, recognizing the pedestrian, the sound image output unit 12052 is rectangular outline for enhancement to the recognized pedestrian to superimpose, controls the display unit 12062. The audio image output unit 12052 is, an icon or the like indicating a pedestrian may control the display unit 12062 to display the desired position.

The example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 and the like among the configurations described above. Specifically, the solid-state imaging device 11 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the configuration can be used properly in the differential mode and the source follower mode, and speeding up of reading of pixel signals in the differential mode can be realized. It becomes possible.

The present disclosure can also have the following configurations.
<1> A pixel array unit in which pixels for generating pixel signals are arranged in accordance with the amount of incident light;
A differential circuit formed by the first pixel and the second pixel arranged in the pixel array unit;
The reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, and the state in which the charge of the second pixel is transferred And an analog-to-digital converter for analog-to-digital conversion of the output,
The analog-to-digital converter simultaneously performs analog-to-digital conversion on an output of the differential circuit in a state in which the charge of the first pixel is transferred and a reset state of the second pixel.
<2> An input portion of a first pixel forming the differential circuit, and an output of the differential circuit are short-circuited to supply a reset voltage to an input portion of a second pixel. The solid-state imaging device according to <1>, further including a reset unit that discharges the input charge of the second pixel.
<3> The analog-to-digital converter
A reference signal generation unit which generates a reference signal by changing it at a predetermined rate;
A comparison unit that compares the reference signal with the output of the differential circuit;
And a counter that counts an elapsed time after the reference signal is generated, and based on the comparison result of the comparison unit, stops counting and holds it as a count code.
The output of the differential circuit is analog-digital converted based on the count code held in the counter and the predetermined rate,
The state in which the charge of the first pixel is transferred by the reference signal generated by the reference signal generation unit at the same timing, and the output of the differential circuit in the reset state of the second pixel Of the first pixel and the output of the differential circuit in the reset state of the second pixel based on the count code of the counter according to the comparison result when the two are simultaneously compared. At the same time, it performs analog-to-digital conversion <2>.
<4> The comparison unit and the counter are provided for the first pixel and the second pixel, respectively.
The comparison unit includes an auto-zero switch for performing an auto-zero operation of shorting the input terminal and the output terminal to offset the reset level,
When the first pixel and the second pixel are reset by the reset unit, an auto-zero operation is performed by the auto-zero switch of the comparison unit of the first pixel,
The solid-state imaging device according to <3>, wherein the reference signal generation unit multiplies the reference signal by a first offset corresponding to the offset.
<5> The reference signal generation unit, after multiplying the reference signal by the first offset, returns the reference signal to a reference voltage, and generates the reference signal at a predetermined rate,
The first pixel counter starts counting a count code,
The comparison unit of the first pixel compares the output of the differential circuit in the reset state of the first pixel with the reference signal, and when the comparison result is inverted, the counter counts the count code. Is stopped, and the count code is held as an output of the differential circuit in a reset state of the first pixel. <4>.
<6> In the counter of the first pixel, after the count code in the reset state of the first pixel is held, the comparison unit of the second pixel performs an autozero operation by the autozero switch,
The solid-state imaging device according to <5>, wherein the reference signal generation unit applies a second offset to the reference signal.
<7> The reference signal generation unit multiplies the reference signal by a second offset, and then returns the reference voltage to the reference voltage to generate the reference signal at the predetermined rate,
The first pixel counter starts counting after inverting the bit of the count code,
The comparison unit of the first pixel compares the output of the differential circuit in a state in which the charge of the first pixel is transferred with the reference signal, and when the comparison result is inverted, the first pixel The counter stops counting the count code, and holds the count code as an analog-to-digital conversion result that is a difference between the reset state of the first pixel and the state of transferring the charge of the first pixel. ,
The second pixel counter starts counting the count code,
The comparator of the second pixel compares the output of the differential circuit in the reset state of the second pixel with the reference signal, and when the comparison result is inverted, the counter of the second pixel is The solid-state imaging device according to <6>, stopping counting of a count code and holding the count code as a reset state of the second pixel.
<8> The counter of the second pixel holds the count code of the output of the differential circuit in the reset state of the second pixel, and transfers the charge of the second pixel rear,
The reference signal generation unit generates the reference signal at the predetermined rate, using the reference signal as the reference voltage.
The second pixel counter starts counting after inverting bits of the count code,
The comparison unit of the second pixel compares the output of the differential circuit in a state in which the charge of the second pixel is transferred with the reference signal, and when the comparison result is inverted, the second pixel The counter stops counting the count code, and holds the count code as an analog-to-digital conversion result which is a difference between the reset state of the second pixel and the state of transferring the charge of the second pixel. The solid-state image sensor as described in <7>.
<9> A connection between a first amplification transistor that amplifies a pixel signal involved in transfer of the charge of the first pixel and a second amplification transistor that amplifies the pixel signal involved in the transfer of the charge of the second pixel Further includes a switch for switching
The switch is a source follower that outputs respective pixel signals of the first pixel and the second pixel by the first amplification transistor and the second amplification transistor by switching the connection. The solid-state imaging device according to any one of <1> to <8>, which forms a circuit.
<10> A pixel array unit in which pixels for generating pixel signals are disposed in accordance with the amount of incident light;
A differential circuit formed by the first pixel and the second pixel arranged in the pixel array unit;
The reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, and the state in which the charge of the second pixel is transferred And an analog-to-digital converter for analog-to-digital conversion of the output,
The analog-to-digital converter simultaneously performs analog-to-digital conversion on an output of the differential circuit in a state in which the charge of the first pixel is transferred and in a reset state of the second pixel.
<11> A pixel array unit in which pixels for generating pixel signals are disposed in accordance with the amount of incident light;
A differential circuit formed by the first pixel and the second pixel arranged in the pixel array unit;
The reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, and the state in which the charge of the second pixel is transferred And an analog-to-digital converter for analog-to-digital conversion of the output,
The electronic device according to claim 1, wherein the analog-to-digital converter simultaneously analog-digital converts an output of the differential circuit in a state in which the charge of the first pixel is transferred and a reset state of the second pixel.
<12> The comparison unit and the counter are provided in any one of the first pixel and the second pixel,
The comparison unit includes an auto-zero switch for performing an auto-zero operation of shorting the input terminal and the output terminal to offset the reset level,
When the first pixel and the second pixel are reset by the reset unit, the comparison unit performs an auto-zero operation by the auto-zero switch.
The solid-state imaging device according to <3>, wherein the reference signal generation unit applies the offset to the reference signal.
<13> The reference signal generation unit, after multiplying the reference signal by the offset, returns the reference signal to a reference voltage, and generates the reference signal at the predetermined rate,
The counter starts counting the count code,
The comparison section compares the output of the differential circuit in the reset state of the first pixel with the reference signal, and when the comparison result is inverted, the counter stops counting the count code, The solid-state imaging device according to <12>, wherein the count code is held as a first processing result.
<14> After the counter holds the output of the differential circuit in the reset state of the first pixel, the reference signal generation unit generates the reference signal at the predetermined rate from the reference voltage. ,
The counter starts counting the count code,
The comparison section compares the output of the differential circuit in a state in which the charge of the first pixel is transferred with the reference signal, and when the comparison result is inverted, the counter stops counting the count code. The solid-state imaging device according to <13>, wherein the count code is held as a second processing result.
<15> After the counter holds the second processing result and transfers the charge of the second pixel,
The reference signal generation unit offsets the reference signal by a predetermined voltage lower than the reference voltage, and generates the reference signal at the predetermined rate.
The counter starts counting the count code,
The comparison section compares the output of the differential circuit in a state in which the charge of the second pixel is transferred with the reference signal, and when the comparison result is inverted, the counter stops counting the count code. The solid-state imaging device according to <14>, wherein the count code is held as a third processing result.
<16> The information processing apparatus further includes a signal processing unit that performs signal processing on a count code to be the first processing result to the third processing result,
The signal processing unit
From the difference between the second processing result and the first processing result, an analog-to-digital conversion result is obtained which is the difference between the reset state of the first pixel and the state in which the charge of the first pixel is transferred.
From the difference between the third processing result and the second processing result, an analog-to-digital conversion result is obtained which is the difference between the reset state of the second pixel and the state in which the charge of the second pixel is transferred. The solid-state image sensor as described in 15>.

11 solid-state imaging device 31 system control unit 32 vertical drive unit 33 pixel array unit 34 column readout circuit unit 35 column signal processing unit 36 horizontal drive unit 37 signal processing unit 38 data storage unit 51, 51 [2 j], 51 [2 j -1] unit pixel, 71 constant current source, 72 current mirror circuit, 91, 91 [2 j], 91 [2 j -1] comparator, 92, 92 [2 j], 92 [2 j- 1] Counter

Claims (11)

A pixel array unit in which pixels that generate pixel signals are arranged according to the amount of incident light;
A differential circuit formed by the first pixel and the second pixel arranged in the pixel array unit;
The reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, and the state in which the charge of the second pixel is transferred And an analog-to-digital converter for analog-to-digital conversion of the output,
The analog-to-digital converter simultaneously performs analog-to-digital conversion on an output of the differential circuit in a state in which the charge of the first pixel is transferred and a reset state of the second pixel. The input voltage of the first pixel forming the differential circuit and the output of the differential circuit are shorted to supply the reset voltage to the input circuit of the second pixel, and the first pixel and the second pixel are supplied. The solid-state imaging device according to claim 1, further comprising a reset unit that discharges an input charge of the pixel. The analog-to-digital converter
A reference signal generation unit which generates a reference signal by changing it at a predetermined rate;
A comparison unit that compares the reference signal with the output of the differential circuit;
And a counter that counts an elapsed time after the reference signal is generated, and based on the comparison result of the comparison unit, stops counting and holds it as a count code.
The output of the differential circuit is analog-digital converted based on the count code held in the counter and the predetermined rate,
The state in which the charge of the first pixel is transferred by the reference signal generated by the reference signal generation unit at the same timing, and the output of the differential circuit in the reset state of the second pixel Of the first pixel and the output of the differential circuit in the reset state of the second pixel based on the count code of the counter according to the comparison result when the two are simultaneously compared. The solid-state imaging device according to claim 2, wherein analog-to-digital conversion is simultaneously performed. The comparison unit and the counter are provided for the first pixel and the second pixel, respectively.
The comparison unit includes an auto-zero switch for performing an auto-zero operation of shorting the input terminal and the output terminal to offset the reset level,
When the first pixel and the second pixel are reset by the reset unit, an auto-zero operation is performed by the auto-zero switch of the comparison unit of the first pixel,
The solid-state imaging device according to claim 3, wherein the reference signal generation unit multiplies the reference signal by a first offset corresponding to the offset. The reference signal generation unit, after multiplying the reference signal by the first offset, returns the reference signal to a reference voltage, and generates the reference signal at a predetermined rate.
The first pixel counter starts counting a count code,
The comparison unit of the first pixel compares the output of the differential circuit in the reset state of the first pixel with the reference signal, and when the comparison result is inverted, the counter counts the count code. The solid-state imaging device according to claim 4, wherein the count code is held as an output of the differential circuit in a reset state of the first pixel. After the count code in the reset state of the first pixel is held in the counter of the first pixel, the comparison unit of the second pixel performs an auto-zero operation by the auto-zero switch,
The solid-state imaging device according to claim 5, wherein the reference signal generation unit multiplies the reference signal by a second offset. The reference signal generation unit multiplies the reference signal by a second offset and then returns the reference voltage to the reference voltage to generate the reference signal at the predetermined rate.
The first pixel counter starts counting after inverting the bit of the count code,
The comparison unit of the first pixel compares the output of the differential circuit in a state in which the charge of the first pixel is transferred with the reference signal, and when the comparison result is inverted, the first pixel The counter stops counting the count code, and holds the count code as an analog-to-digital conversion result that is a difference between the reset state of the first pixel and the state of transferring the charge of the first pixel. ,
The second pixel counter starts counting the count code,
The comparator of the second pixel compares the output of the differential circuit in the reset state of the second pixel with the reference signal, and when the comparison result is inverted, the counter of the second pixel is The solid-state imaging device according to claim 6, wherein the counting of the count code is stopped, and the count code is held as a reset state of the second pixel. After the counter of the second pixel holds the count code of the output of the differential circuit in the reset state of the second pixel and transfers the charge of the second pixel,
The reference signal generation unit generates the reference signal at the predetermined rate, using the reference signal as the reference voltage.
The second pixel counter starts counting after inverting bits of the count code,
The comparison unit of the second pixel compares the output of the differential circuit in a state in which the charge of the second pixel is transferred with the reference signal, and when the comparison result is inverted, the second pixel The counter stops counting the count code, and holds the count code as an analog-to-digital conversion result which is a difference between the reset state of the second pixel and the state of transferring the charge of the second pixel. The solid-state imaging device according to claim 7. A switch that switches the connection between a first amplification transistor that amplifies a pixel signal accompanying transfer of the charge of the first pixel and a second amplification transistor that amplifies the pixel signal accompanying transfer of the charge of the second pixel Further include
The switch is a source follower that outputs respective pixel signals of the first pixel and the second pixel by the first amplification transistor and the second amplification transistor by switching the connection. The solid-state imaging device according to claim 1, which forms a circuit. A pixel array unit in which pixels that generate pixel signals are arranged according to the amount of incident light;
A differential circuit formed by the first pixel and the second pixel arranged in the pixel array unit;
The reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, and the state in which the charge of the second pixel is transferred And an analog-to-digital converter for analog-to-digital conversion of the output,
The analog-to-digital converter simultaneously performs analog-to-digital conversion on an output of the differential circuit in a state in which the charge of the first pixel is transferred and in a reset state of the second pixel. A pixel array unit in which pixels that generate pixel signals are arranged according to the amount of incident light;
A differential circuit formed by the first pixel and the second pixel arranged in the pixel array unit;
The reset state of the first pixel, the state in which the charge of the first pixel is transferred, the reset state of the second pixel, and the state in which the charge of the second pixel is transferred And an analog-to-digital converter for analog-to-digital conversion of the output,
The electronic device according to claim 1, wherein the analog-to-digital converter simultaneously analog-digital converts an output of the differential circuit in a state in which the charge of the first pixel is transferred and a reset state of the second pixel.

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