WO2019032114A1

WO2019032114A1 - Qubit devices with undercut conductive circuit elements

Info

Publication number: WO2019032114A1
Application number: PCT/US2017/046402
Authority: WO
Inventors: Roman CAUDILLO; Zachary R. YOSCOVITS; Hubert C. GEORGE; Ravi Pillarisetty; Nicole K. THOMAS; David J. MICHALAK; Jeanette M. ROBERTS; Kanwaljit SINGH; James S. CLARKE
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-08-11
Filing date: 2017-08-11
Publication date: 2019-02-14
Anticipated expiration: 2020-02-11

Abstract

Embodiments of the present disclosure propose quantum circuit assemblies, as well as methods of fabricating thereof, that include undercut conductive circuit elements. An exemplary quantum circuit assembly includes a plurality of qubits provided over or in a substrate and supporting circuitry in the form of a conductive circuit element for one or more of the plurality of qubits. The conductive circuit element includes a conductive line which is undercut in that a portion of the conductive line is suspended over the substrate, i.e. is separated from the substrate by a gap. Suspending portions of supporting circuitry of qubit devices over substrates by virtue of creating undercuts in conductive circuit elements of such devices allows reducing the combined areas of the substrate-superconductor interfaces and also moves the sharp angles of the conductive circuit elements further away from the substrate, which may reduce losses and improve coherence times of qubits.

Description

QUBIT DEVICES WITH UNDERCUT CONDUCTIVE CIRCUIT ELEMENTS

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to qubit devices which employ undercut conductive circuit elements and to methods of fabricating thereof.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

[0003] Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0004] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results.

Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit, according to some embodiments of the present disclosure. [0007] FIGS. 2A-2B provide schematic illustrations of an exemplary conductive circuit element without an undercut.

[0008] FIG. 3 provides a schematic illustration of an exemplary conductive circuit element with an undercut, according to some embodiments of the present disclosure.

[0009] FIG. 4 provides a flow chart of a SC bilayer stack method for fabricating quantum circuit assemblies with undercut conductive circuit elements, according to some embodiments of the present disclosure.

[0010] FIGS. 5A-5C are cross-sections illustrating various exemplary stages in the manufacture of a quantum circuit assembly with undercut conductive circuit elements using the SC bilayer stack method of FIG. 2, in accordance with some embodiments of the present disclosure.

[0011] FIGS. 6A-6C are cross-sections illustrating various exemplary stages in the manufacture of a quantum circuit assembly with undercut conductive circuit elements using the SC bilayer stack method of FIG. 2, in accordance with other embodiments of the present disclosure.

[0012] FIGS. 7A and 7B are top views of a wafer and dies that may include one or more of quantum circuit assemblies disclosed herein.

[0013] FIG. 8 is a cross-sectional side view of a device assembly that may include one or more of quantum circuit assemblies disclosed herein.

[0014] FIG. 9 is a block diagram of an exemplary quantum computing device that may include one or more of quantum circuit assemblies disclosed herein, in accordance with various embodiments.

Detailed Description

Overview

[0015] As briefly described above, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0016] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Therefore, both the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits.

[0017] As also briefly described above, protecting qubits from decoherence remains to be a challenge. For this reason, materials, structures, and fabrication methods used for building quantum circuits continuously focus on reducing spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be the dominant source of qubit decoherence, where, in general, as used in quantum mechanics, a two-level (also referred to as "two-state") system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states.

[0018] Ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, single trapped ion qubits, Silicon (Si) quantum dot qubits, photon polarization qubits, etc.

[0019] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer. Superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction. Josephson Junctions are integral building blocks in quantum circuits employing superconducting qubit devices, forming the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.

[0020] Another type of integral building blocks in superconducting qubit devices are resonators used to couple qubits together and to readout the state of qubits. In general, a resonator of a quantum circuit is a microwave transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions (i.e. a resonant microwave transmission line).

[0021] Conventionally, resonators of superconducting qubit devices have been implemented as coplanar waveguides (CPWs), which is a particular type of a microwave transmission line. However, employing a conventional CPW architecture for forming resonators may not be the most optimum for quantum computers because the interface area between the substrate and the superconductors (SCs) of which the resonators are made is likely to contribute to spurious TLS's which lead to qubit decoherence. Furthermore, substrate-superconductor interfaces of conductive quantum circuit elements other than resonators, such as e.g. non-resonant transmission lines, shunt capacitors, etc., may also contribute to spurious TLS's which lead to qubit decoherence in a similar manner.

[0022] Embodiments of the present disclosure propose quantum circuit assemblies, as well as methods of fabricating thereof, that could improve on one or more of the drawbacks described above. In one aspect of the present disclosure, a quantum circuit assembly including a plurality of qubits provided over or in a substrate and a conductive circuit element for one or more of the plurality of qubits is proposed. The conductive circuit element includes a conductive line which is undercut in that a portion of the conductive line is suspended over the substrate, i.e. is separated from the substrate by a gap.

[0023] The conductive circuit element may be an example of supporting circuitry for a

superconducting qubit quantum circuit assembly, where, in general, a distinction can be made between supporting circuitry elements which are electrically connected to one or more Josephson Junctions of a superconducting qubit, such as e.g. shunt capacitors, superconducting loops of a superconducting quantum interference device (SQUID), etc., referred to herein as "qubit supporting circuitry," and supporting circuitry elements which are capacitively or magnetically coupled to a qubit but are not directly electrically connected to Josephson Junctions, such as e.g. resonators, flux bias lines, microwave feed lines, etc., referred to herein as "chip supporting circuitry." The undercut conductive circuit element described herein may be used to implement any of these examples of supporting circuitry elements.

[0024] Suspending portions of supporting circuitry of a qubit device over the substrate by virtue of creating undercuts in conductive circuit elements allows reducing the combined areas of the substrate-superconductor interfaces and also moves the sharp angles/corners of the

conductive/superconductive material (i.e. areas of potentially higher electric field) further away from the lossy substrate, which should reduce coupling to the spurious TLS's due to the presence of the substrate and reduce loss in the microwave region. As a result, coherence times of qubits, in particular superconducting qubits, may be improved.

[0025] In order to provide substantially lossless connectivity to, from, and between the qubits, electrically conductive portions of various quantum circuit elements described herein (e.g. the undercut conductive circuit elements described herein) may be made from one or more superconductive materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconductive. In the following, unless specified otherwise, reference to an electrically conductive material or circuit element implies that a SC can be used, and vice versa (i.e. reference to a SC implies that a conductive material which is not superconductive may be used). Furthermore, materials described herein as

"superconductive/superconducting materials" may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions, e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate, but which may not exhibit such behavior at e.g. room temperatures.

[0026] While some descriptions are provided with reference to superconducting qubits, in particular to transmons, a particular class of superconducting qubits, at least some teachings of the present disclosure may be applicable to quantum circuit assembly implementations of any qubits, including superconducting qubits other than transmons and/or including qubits other than superconducting qubits, which may employ undercut conductive circuit elements as described herein to implement any conductive circuit elements of such quantum circuit assemblies, all of which implementations are within the scope of the present disclosure. For example, the undercut conductive circuit elements described herein may be used in hybrid semiconducting- superconducting quantum circuits.

[0027] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0028] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0029] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0030] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0031] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.

Furthermore, as used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious TLS's may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0032] Still further, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GHz, e.g. in 5-10 GHz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

Exemplary quantum circuit

[0033] FIG. 1 provides a schematic illustration of an exemplary quantum circuit 100 that may include any of the quantum circuit assemblies described herein.

[0034] As shown in FIG. 1, an exemplary quantum circuit 100 may include two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element). In case the quantum circuit 100 implements superconducting qubits (i.e. the qubits 102 are superconducting qubits), each of the

superconducting qubits 102 may include one or more Josephson Junctions 104 electrically connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit. For the example of a superconducting quantum circuit 100, the circuit elements 106 could be e.g. shunt capacitors, superconducting loops of a SQUID, electrodes for setting an overall capacitance of a qubit, or/and ports for capacitively coupling the qubit to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line or electromagnetically coupling the qubit to a flux bias line.

[0035] In general, a SQUID includes a pair of Josephson Junctions and a loop of a conductive, typically superconductive material (i.e. a superconducting loop), connecting the pair of Josephson Junctions. Applying magnetic field to the SQUID region of a superconducting qubit allows controlling a frequency of the qubit which, in turn, allows controlling whether the qubit interacts with other components of a quantum circuit, e.g. with other qubits. Applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct current (DC) or a pulse of current through an electrically conductive line generally referred to as a "flux bias line" (also known as a "flux line" or a "flux coil line"). By providing flux bias lines sufficiently close to SQUIDs, magnetic fields generated as a result of currents running through the flux bias lines extend to the SQUIDs, thus tuning qubit frequencies. [0036] Microwave drive lines (also known as "microwave lines" or "drive lines") are typically used to control the state of the qubits by providing a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.

[0037] As also shown in FIG. 1, an exemplary quantum circuit 100 typically includes a plurality of non-resonant transmission lines 108 and a plurality of resonators 110, e.g. coupling and readout resonators.

[0038] The non-resonant transmission lines 108 are typically used for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits. For example, for superconducting qubits, examples of the non-resonant transmission lines 108 include flux bias lines, microwave feed lines, and direct drive lines.

[0039] In general, a resonator 110 of a quantum circuit differs from a non-resonant microwave transmission line 108 in that a resonator is a transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions. In contrast, non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonators in the proximity of such non-resonant lines. Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible. For example, the ends of non-resonant transmission lines are typically engineered to have a specific impedance (e.g. substantially 50 Ohm) to minimize impedance mismatches to other circuit elements to which the lines are connected, in order to minimize the amount of reflected signal at transitions (e.g., transitions from the chip to the package, the package to the connector, etc.).

[0040] A resonator is made with fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line structure used to implement a resonator. In order to satisfy boundary conditions for resonance, each end of a transmission line that implements a resonator can be either a node, if it is shorted to ground (e.g. by being electrically connected to a ground plane of a transmission line structure that implements the resonator, or to any other ground potential), or an antinode, if it is capacitively or inductively coupled to another quantum circuit element. Thus, resonators 110 differ from non-resonant microwave transmission lines 108 in how these lines are terminated. A line used to route a signal on a substrate, i.e. one of the non-resonant transmission lines 108, typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to a quantum dot device or another bonding pad or another electrical connection to a load). In other words, non-resonant transmission lines 108 terminate with direct electrical connections to sources and loads. On the other hand, a transmission line resonator is typically composed of a piece of transmission line terminated with an open or short circuit. In this case, for a desired resonant frequency, transmission line length may e.g. be a multiple of a microwave wavelength divided by 4. However, other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above. For example, capacitive terminations may be used for resonators which are coupled to a line or another resonator by capacitors.

[0041] Besides line termination by capacitive or inductive coupling or a short circuit, in order to support resonant oscillations, transmission lines of the resonators 110 need to be of a specific length that can support such oscillations. That is why, often times, resonators 110 may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).

[0042] One type of the resonators 110 used with superconducting qubits are so-called coupling resonators (also known as "bus resonators"), which allow coupling different qubits together in order to realize quantum logic gates. A coupling resonator may be implemented as a microwave transmission line that includes capacitive or inductive connections to ground on both sides (e.g. a half wavelength resonator), which results in oscillations (resonance) within the transmission line. While the ends of a coupling resonator have open circuits to the ground, each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in sufficient proximity to the qubit. Because each side of a coupling resonator has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit, a necessary functionality for implementing logic gates.

[0043] Another type of the resonators 110 used with superconducting qubits are so-called readout resonators, which may be used to read the state(s) of qubits. In some embodiments, a

corresponding readout resonator may be provided for each qubit. A readout resonator is similar to a coupling resonator in that it may be implemented as a transmission line that includes a capacitive or an inductive connection to ground on one side. On the other side, a readout resonator may either have a capacitive connection to ground (for a half wavelength resonator) or may have a short circuit to the ground (for a quarter wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit. A readout resonator is coupled to a qubit by being in sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.

[0044] The circuit elements 106, the non-resonant transmission lines 108, and the resonators 110 may be considered, broadly, as "supporting circuitry" for the qubits 102 or/and the Josephson Junctions 104 (in case the qubits 102 are superconducting qubits), where, as described above, a further distinction could be made between "qubit supporting circuitry" in the form of the circuit elements 106 and "chip supporting circuitry" in the form of the non-resonant transmission lines 108 and the resonators 110. Further, any other connections for providing microwave or other electrical signals to different circuit elements and components of the quantum circuit 100, such as e.g.

connections between electrodes of various circuit components, or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, may be considered as being within the general category of "supporting circuitry." Still further, the term "supporting circuitry" may also be used to refer to elements providing electrical

interconnections to/from/between quantum circuit elements/components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non- quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog-to-digital converters, mixers, multiplexers, amplifiers, etc.

[0045] In the embodiments where the quantum circuit 100 implements qubits other than superconducting qubits, descriptions as provided above are still applicable except that the qubits 102 would not include Josephson Junctions 104.

[0046] At least some of the supporting circuitry in the quantum circuit 100 may be implemented as undercut conductive circuit elements as described herein.

[0047] In various embodiments, various conductive circuit elements of supporting circuitry included in a quantum circuit such as the quantum circuit 100 could have different shapes and layouts. In general, the term "line" as e.g. used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so. For example, some resonant or non-resonant transmission lines or parts thereof (e.g. conductor strips of resonant or non-resonant transmission lines) may comprise more curves, wiggles, and turns while other resonant or non-resonant transmission lines or parts thereof may comprise less curves, wiggles, and turns, and some transmission lines or parts thereof may comprise substantially straight lines.

[0048] In some embodiments, materials forming the various conductive circuit elements of supporting circuitry, and in particular the resonator structures described herein, may include niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and/or niobium titanium nitride (NbTiN), all of which are particular types of superconductors at qubit operating temperatures, as well as their alloys. However, in various embodiments, other suitable superconductors as well as non- superconducting conductors may be used as well, all of which may be referred to "conductive" or "electrically conductive" materials.

[0049] The qubits 102, the non-resonant transmission lines 108, and the resonators 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1).

[0050] In various embodiments, quantum circuits such as the one shown in FIG. 1 may be used to implement components associated with a quantum integrated circuit (IC). Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC. The quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a quantum system. Undercut conductive circuit elements

[0051] In order to highlight the advantages offered by novel quantum circuit assemblies with conductive circuit elements with undercuts as proposed herein, it would be helpful to first explain how various supporting circuitry is implemented in conventional quantum circuits.

[0052] FIGS. 2A-2B provide schematic illustrations of an exemplary conductive circuit element, namely a quantum circuit resonator, without an undercut.

[0053] As mentioned above, conventionally, quantum circuit resonators have been implemented as CPWs. FIGS. 2A and 2B provide, respectively, a perspective and a cross-section illustrations of an exemplary conventional CPW resonator 200. As shown in FIGS. 2A and 2B, the resonator 200 includes two ground planes 214 and 218 and a signal line 216 provided in the middle, between the two ground planes. The signal line 216 and the ground planes 214 and 218 all lie in the same plane over a dielectric substrate 212. FIG. 2A indicates a strip width W of the signal line 216, and slot spaces S between the signal line 216 and each of the ground planes 214 and 218. The strip width W and slot spaces 5 are parameters that define characteristics of a CPW transmission line, such as e.g. impedance of the transmission line and electromagnetic field distribution.

[0054] As described above, employing a conventional CPW architecture for forming resonators, or, in general, forming various supporting circuitry made of conductive, typically superconductive, materials directly on the dielectric substrate may not be the most optimum for quantum computers because the interface area between the substrate and the SCs of which conductive circuit elements of the supporting circuitry are made is likely to contribute to spurious TLS's which lead to qubit decoherence. This may be explained as follows.

[0055] One major source of loss and thus decoherence in superconducting qubits is thought to be attributable to spurious TLS's in the areas surrounding the qubits, in particular, TLS's in dielectric materials which are not highly crystalline, such as e.g. the substrates on which quantum circuits are often built. These TLS's are thought to be either an electron or an ion that can tunnel between two spatial states, which are caused either by defects in the crystal structure of the substrate or through polar impurities such as hydroxyl (OH- ) groups. One mechanism of how spurious TLS's can lead to decoherence in a qubit is based on the idea that, if the TLS's are in a close proximity to the qubit and are in resonance with the qubit (i.e. when the frequency of a spurious TLS is close to the frequency of a qubit), they can couple to it. When this happens, spurious TLS's and the qubit exchange energy in the form of photons emitted by the qubit and absorbed by the spurious TLS's and may be viewed as a spurious TLS-qubit system having a certain combined energy. When combined energy of such a TLS-qubit system decays through phonon emission from the spurious TLS's, the TLS-qubit system relaxes, leading to decoherence of the qubit. Spurious TLS's that lead to qubit decoherence by this mechanism may be present at the surface of superconductive materials (i.e. TLS's present at the superconductor-air interface) or/and at an interface between a substrate and superconductive materials of various conductive circuit elements of supporting circuitry. This problem is thought to be made even worse at areas of higher concentration of electromagnetic fields, which are typically areas around sharp corners/angles at metal/dielectric interfaces (i.e. at the interfaces of an electrically conductive materials of the supporting circuitry and the dielectric material of the substrate, or air.)

[0056] Embodiments of the present disclosure propose to improve on this issue by undercutting at least portions of conductive circuit elements, so that at least such portions are suspended over the substrate instead of being in contact, i.e. interfacing, with the substrate. These embodiments are based on an insight that the density of spurious TLS's at superconductor-substrate interfaces is higher than that at superconductor-vacuum interfaces and therefore, in general, minimizing superconductor-substrate interfaces may be beneficial for extending qubit coherence times.

Consequently, reducing the interface area between a substrate and bottom superconductive portions of supporting circuitry may reduce the total amount of spurious TLS's in close proximity to qubits and supporting circuitry and, thus, could improve on the decoherence problems of qubits.

[0057] Creating such undercuts may be particularly beneficial for resonators (i.e. a particular type of supporting circuitry) in that it may advantageously improve resonator quality factor. However, it may also be advantageous for various non-resonant conductive circuit elements such as e.g. flux bias lines, microwave feed lines, or any other conductive circuit elements of supporting circuitry as described herein. For example, creating undercuts as described herein for qubit supporting circuitry such as a shunt capacitor electrically connected to the Josephson Junctions of a transmon qubit may reduce the TLS's in closest proximity to the lis and qubit and thus increase the coherence times of the qubit.

[0058] FIG. 3 provides a schematic illustration of an exemplary conductive circuit element 300 with an undercut, according to some embodiments of the present disclosure. The conductive circuit element 300 may be provided over a substrate 312 and may include at least a signal line 316, which signal line 316 may be an example of a conductive line of a conductive circuit element of any of the supporting circuitry described herein. As shown in FIG. 3, the signal line 316 may include undercuts 330 on one or both sides of the signal line (FIG. 3 illustrates an embodiment with the undercuts 330 provided on both sides) in that portions along the signal line 316, along the entire length of the signal line 316 or at least along a portion of the entire length of the signal line 316, are not in contact with the substrate 312, but are suspended over the substrate.

[0059] The example of FIG. 3 further illustrates that the conductive circuit element 300 may further include two ground planes 314 and 318 arranged such that the signal line 316 is between the two ground planes 314, 318, but, in general, these ground planes are optional. The example of FIG. 3 also illustrates that each of the ground planes 314 and 318 also includes undercuts 330 on each side of each ground plane, but this implementation is also optional in that, in general, one or more of the ground planes 314, 318 may not include any undercuts at all, or may include undercuts only on one side. In the following, descriptions of the undercuts 330 provided with reference to the signal line 316 or, in general, with reference to a conductive line of a conductive circuit element, are applicable to the undercuts 330 which may be provided in any of the ground planes of the supporting circuitry.

[0060] In some embodiments, the exemplary conductive circuit element 300 shown in FIG. 3 could be a quantum circuit resonator or any non-resonant transmission line for a quantum circuit, e.g. any of the non-resonant transmission lines 108 or resonators 110 of the quantum circuit 100 described above. For example, when the conductive circuit element 300 includes the two ground planes 314 and 318 arranged such that the signal line 316 is between the two ground planes 314, 318, it becomes similar to the CPW resonator 200 shown in FIG. 2B. However, in contrast to FIG. 2B, at least the signal line 316 of the conductive circuit element 300 includes one or more undercuts 330.

[0061] In other embodiments, the exemplary conductive circuit element 300 shown in FIG. 3 could be any conductive circuit element of a quantum circuit, e.g. any of the circuit elements 106 of the quantum circuit 100 described above.

[0062] FIG. 3 illustrates that each undercut 330 may be formed by recessing the lower portion of the signal line 316 by a depth d_u (a dimension measured along the y-axis of the coordinate system as shown in FIG. 3; where subscript "u" stands for "undercut") with respect to sidewalls 332 of the upper portion of the signal line 316. Thus, the undercut depth d_u may be viewed as the width of the conductive line portion suspended over the substrate 312. In various embodiments, the undercut depth d_u may be between about 1 and 5000 nm, including all values and ranges therein, e.g.

between about 10 and 200 nm, or between about 20 and 100 nm. In various embodiments, the undercut depth d_u may be between about 1% and 40% of the total width w (i.e. the width of the upper portion which is not recessed; shown in FIG. 3) of a conductive line being undercut, including all values and ranges therein, e.g. between about 5 and 25 %, or between about 10 and 20 %. Thus, a width of the upper portion of the signal line 316 is greater than a width of the lower portion of the signal line. In other words, an area, in a plane parallel to the plane of the substrate 312, of the upper portion of the conductive circuit element 300 is greater than an area, also in a plane parallel to the plane of the substrate, of the lower portion of the conductive circuit element 300.

[0063] FIG. 3 further illustrates that, for each undercut 330, a distance between the substrate 312 and a portion of the signal line 316 suspended over the substrate 312 may be referred to as a dimension d_s (a dimension measured along the z-axis of the coordinate system as shown in FIG. 3; where subscript "s" stands for "suspended"). Thus, the dimension d_s may be viewed as the height of the undercut. In various embodiments, the undercut height d_s may be between about 5 and 200 nm, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 5 and 35 nm. In various embodiments, the undercut height d_s may be between about 1% and 50% of the total height h (shown in FIG. 3) of a conductive line being undercut, including all values and ranges therein, e.g. between about 3% and 25%, or between about 5% and 20%.

[0064] Suspending portions of the supporting circuitry over the substrate 312 by virtue of creating one or more undercuts 330 in at least one conductive line, such as e.g. the signal line 316, allows reducing the combined areas of the substrate-superconductor interface and also moves the sharp angles/corners of the superconductor (i.e. areas of higher electric field) further away from the lossy substrate, which should reduce coupling to the spurious TLS's due to the presence of the substrate 312 and reduce loss in the microwave region. As a result, coherence times of superconducting qubits may be improved.

[0065] A conductive circuit element with at least a conductive line having an undercut as described herein, such as e.g. the conductive circuit element 300 with the signal line 316 having at least one undercut 330, may be fabricated using various suitable techniques, all of which being within the scope of the present disclosure. One such exemplary technique is shown in FIG. 4 and described below.

[0066] FIG. 4 provides a flow chart of a SC bilayer stack method 400 for fabricating quantum circuit assemblies with undercut conductive circuit elements, according to some embodiments of the present disclosure. The method 400 is referred to as a "bilayer stack" method because it is based on the use of a stack of two layers of different conductive, preferably superconductive, materials.

[0067] Implementations of the present disclosure may be formed or carried out any substrate suitable for realizing quantum circuit assemblies described herein. In one implementation, the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0068] Various operations of the method 400 may be illustrated with reference to two exemplary embodiments discussed below, but the method 400 may be used to manufacture any suitable quantum circuit assemblies with conductive circuit elements having conductive lines with undercuts according to any embodiments of the present disclosure. FIGS. 5A-5C are cross-sections illustrating various example stages in the manufacture of a quantum circuit assembly using the SC bilayer stack method of FIG. 4 in accordance with a first embodiment of the present disclosure, while FIGS. 6A-6C are cross-sections illustrating various example stages in the manufacture of a quantum circuit assembly using the SC bilayer stack method of FIG. 4 in accordance with a second embodiment of the present disclosure. Each one of FIGS. 5A-5C and FIGS. 6A-6C illustrates a cross-sectional view of along the z-y plane (as indicated in these FIGS.), where same reference numerals refer to the same or analogous elements/materials shown. [0069] Although the operations of the method 400 are illustrated in FIG. 4 once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple quantum circuit assemblies as described herein substantially simultaneously. In another example, the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component in which one or more undercut conductive circuit elements are to be included.

[0070] In addition, the manufacturing method 400 may include other operations, not specifically shown in FIG. 4, such as e.g. various cleaning operations as known in the art. For example, in some embodiments, the substrate may be cleaned prior to or/and after any of the processes of the bilayer stack method 400 described herein, e.g. to remove surface-bound organic and metallic

contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).

[0071] The method 400 may begin with providing a bilayer stack of conductive, e.g.

superconductive (SC) materials over a substrate (process 402 shown in FIG. 4, a result of which is illustrated with an assembly 502 shown in FIG. 5A for the first embodiment and with an assembly 602 shown in FIG. 6A for the second embodiment, with the assemblies 502 and 602 being the substantially the same for both embodiments). The assembly 502 illustrates a substrate 512, which could be any of the substrates described above, with a first conductive layer 522 provided over the substrate 522 and a second conductive layer 524, made of a material different from that of the first conductive layer 522 (in particular, a material having sufficiently different etch properties), provided over the first conductive layer 522. Together, the first and second conductive layers 522, 524 form a bilayer stack 520 indicated in FIG. 5A.

[0072] In various embodiments, any suitable deposition techniques may be used for providing the bilayer stack 520 in the process 402, such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating, and each of the first and second conductive layers 522, 524 may include any conducting or superconducting material suitable for providing electrical connectivity in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting/conducting materials. For example, in some embodiments, providing the first conductive layer 522 over the substrate 512 may include depositing a conductive material, e.g. Al, of the first conductive layer using thermal evaporation, e- beam evaporation, or sputtering, while providing the second conductive layer 524 over the first conductive layer 522 may include depositing a conductive material, e.g. a material other than Al, of the second conductive layer using sputtering (e.g. using direct current (DC) or radio frequency (RF) sputtering for depositing Nb, or reactively sputtering NbN or NbTiN), PVD (e.g. to deposit Nb, NbN, NbTiN, or TiN), CVD, or ALD (e.g. to deposit TiN).

[0073] In various embodiments, a thickness of the first conductive layer 522 (i.e. a dimension measured along the z-axis of the coordinate system as shown in FIGS. 5A-5C and FIGS. 6A-6C) provided in the process 402 may be between about 5 and 200 nanometers, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 5 and 35 nm. In various embodiments, a thickness of the second conductive layer 524 (also a dimension measured along the z-axis of the coordinate system as shown in FIGS. 5A-5C and FIGS. 6A-6C) provided in the process 402 may be between about 50 and 500 nanometers, including all values and ranges therein, e.g. between about 100 and 250 nm.

[0074] The method may then proceed with etching either both layers of the bilayer stack 520 (the first embodiment as shown in FIGS. 5A-5C) or etching substantially only the upper SC layer, i.e. the second conductive layer 524 (the second embodiment as shown in FIGS. 6A-6C), to define one or more conductive circuit elements of supporting circuitry for a quantum circuit (process 404 shown in FIG. 4, a result of which is illustrated with an assembly 504 shown in FIG. 5B for the first embodiment and with an assembly 604 shown in FIG. 6B for the second embodiment).

[0075] FIG. 5B illustrates supporting circuitry in a form of a conductive circuit element 544 defined by patterning both layers of the bilayer stack 520. FIG. 6B illustrates supporting circuitry in a form of a conductive circuit element 644 defined by patterning substantially only the upper layer (i.e. the second conductive layer 524) of the bilayer stack 520.

[0076] In various embodiments, any suitable patterning techniques may be used for defining the supporting circuitry 544/644 in the process 404, such as e.g. photolithographic or electron-beam (e- beam) patterning, possibly in conjunction with a dry etch, such as e.g. RF or inductively coupled plasma (ICP) reactive ion etch (RIE), to etch either both layers of the bilayer stack 520, as shown in FIG. 5B, or only the second conductive layer 524, as shown in FIG. 6B, into the specified geometries for a given implementation.

[0077] For the first embodiment, the etch of the process 404 is carried out down to the substrate 522. For example, this may be accomplished with a single etch chemistry with high enough etch rate for each material so as to enable etching down to the substrate 512 in a reasonable amount of processing time. In the case, where the two conductive materials exhibit substantially different etch characteristics, then a first etch chemistry can be used to etch through the top material 524 and then a second etch chemistry can be used to etch through the lower material 522 down to the substrate or slightly into the substrate. For example, this may be accomplished with a single etch chemistry with high enough etch rate for each material so as to enable etching down to the substrate 512 in a reasonable amount of processing time. In the case where the two conductive materials exhibit substantially different etch characteristics, then a first etch chemistry can be used to etch through the top material 524 and then a second etch chemistry can be used to etch through the lower material 522 down to the substrate or slightly into the substrate.

[0078] For the second embodiment, the etch of the process 404 is either carried out down to first conductive layer 522 of the bilayer stack 520 (i.e. the first conductive layer 522 is not etched at all) or the etch of the process 404 is such that the first conductive layer 522 is etched together with the second conductive layer 524, but to a much lower degree than the second conductive layer 524. For example, since first and second conductive layers 522, 524 are made of different materials (i.e. are etch-selective with respect to one another), in the second embodiment, the etch of the process 404 may be a dry etch that provides a higher etch rate for the material of the second conductive layer 524 than for the material of the first conductive layer 522. In some embodiments, when the first conductive layer 522 is Al, a tetrafluoromethane (CF4) based etch for Nb and NbN and NbTiN metals of the second conductive layer 524 may be chosen so that the dry etch stops on the first conductive layer 522 due to the difference in etch rates.

[0079] The method may then proceed with etching the lower SC layer, i.e. the first conductive layer 522, under the upper SC layer, i.e. the second conductive layer 524, of the conductive circuit element 544/644 formed in the process 404 in order to recess the first conductive layer 522 on one or both sides of the conductive circuit element 544/644, thus creating an undercut (process 406 shown in FIG. 4, a result of which is illustrated with an assembly 506 shown in FIG. 5C for the first embodiment and with an assembly 606 shown in FIG. 6C for the second embodiment).

[0080] FIG. 5C illustrates undercut supporting circuitry in a form of a conductive circuit element 546 with one or more undercuts 530. FIG. 6C illustrates undercut supporting circuitry in a form of a conductive circuit element 646 with one or more undercuts 630, the undercut conductive circuit element 646 being substantially the same as the undercut conductive circuit element 546 (i.e. the first and second embodiments of the bilayer stack method 400 described herein only differ in the process 404 as shown in FIGS. 5B and 6B).

[0081] The undercut conductive circuit element 546/646 could be an undercut conductive line as described above with reference to the undercut signal line 316, or an undercut ground plane as described above with reference to the undercut ground planes 314, 318, where the undercuts 530 and 630 shown in FIGS. 5C and 6C are analogous to the undercuts 330 shown in FIG. 3. Detailed descriptions of the undercuts are, therefore, in the interests of brevity, not repeated here.

[0082] In some embodiments, the undercut conductive circuit element 546/646 could be an element of supporting circuitry such as e.g. a conductive circuit element of the circuit elements 106 of the quantum circuit 100 described above. In such embodiments, the conductive circuit element 546/646 could be e.g. a portion of a conductive loop of a SQUID of a superconducting qubit (i.e. a conductive, e.g. superconductive, loop containing two parallel Josephson Junctions used to tune the qubit frequency with a magnetic field that is applied using a flux bias line), a larger electrode for setting an overall capacitance of a qubit, or/and a port for capacitively coupling a Josephson Junction to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line.

[0083] In other embodiments, the undercut conductive circuit element 546/646 could be could be an element of supporting circuitry such as e.g. a portion of (e.g. a signal line) one of the non- resonant transmission lines 108 of the quantum circuit 100 described above. In such embodiments, the conductive circuit element 546/646 could be e.g. a portion of a flux bias line or a microwave feed line.

[0084] In still other embodiments, the undercut conductive circuit element 546/646 could be could be an element of supporting circuitry such as e.g. a portion of (e.g. a signal line) one of the resonators 110 of the quantum circuit 100 described above. In such embodiments, the conductive circuit element 546/646 could be e.g. a portion of a coupling resonator or a read out resonator.

[0085] As is seen in FIG. 5B, in the first embodiment, etching of the process 404 results in the sidewalls of the first conductive layer 522 being substantially aligned with the sidewalls of the second conductive layer 524. In such an embodiment, the etch of the process 406 includes applying etchants to further etch the first conductive layer 522 to recess the first conductive layer 522 to create an undercut 530.

[0086] On the other hand, as is seen in FIG. 6B, in the second embodiment, patterning the upper SC layer 524 results in exposing portions of the lower SC layer, i.e. the first conductive layer 522 (i.e. the etch of the second conductive layer 524 in the process 404 is performed until the first conductive layer 522). In such an embodiment, the etch of the process 406 includes etching at least a portion of the lower SC layer, i.e. the first conductive layer 522, exposed by the etching of the process 404, and then continuing the etch further down to the substrate 512 and so as to recess the first conductive layer 522 to create an undercut 630.

[0087] In both the first and the second embodiments, etching the first conductive layer 522 of a conductive line 544/644 under (or further than) the second conductive layer 524 to suspend a portion of the conductive line 544/644 over the substrate 512 may include performing a wet or an isotropic dry etch to remove a portion of the first conductive layer 522 under the second conductive layer 524 of the conductive line 544/644, thus creating an undercut of depth d_u under a portion of the conductive line. For example, the etch of the process 406 may include performing an etch that has a higher etch rate for the first conductive layer 522 than for the second conductive layer 524. For example, in some embodiments, an etchant used in the process 406 may include approximately 2% tetramethylammonium hydroxide (T AH), in case the first conductive layer 522 includes Al, in order to selectively etch Al to create an undercut.

[0088] As a result of creating the undercut because of uneven removal of the material of the first conductive layer 522 compared to the material of the second conductive layer 524, portions of the supporting circuitry such as e.g. portions of the conductive circuit elements 544/644 may be suspended at a distance to the substrate 512 that is equal to the thickness of the first conductive layer 522, i.e. between about 5 and 200 nm.

[0089] To summarize, various embodiments of employing the bilayer fabrication method described above result in quantum circuit assemblies where some lower portions of conductive lines of one or more conductive circuit elements are recessed compared to the upper portions, resulting in some upper portions of the conductive lines being suspended over a substrate so that the superconductive material of those lines is not interfacing the dielectric of the substrate.

[0090] The different views of the quantum circuit assemblies with undercut conductive circuit elements as described herein are shown in the FIGS, with precise right angles and straight lines, which does not reflect example real world process limitations which may cause the features to not look so ideal when any of the structures described above are examined using e.g. scanning electron microscopy (SEM) images or transmission electron miscroscope (TEM) images. In such images of real structures, possible processing defects could also be visible, such as e.g. tapered vias, occasional screw, edge, or combination dislocations within the crystalline region, occasional dislocation defects of single atoms or clusters of atoms.

Exemplary pubit devices

[0091] Quantum circuit assemblies/structures as described above may be included in any kind of qubit devices or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 7A-7B, 8, and 9.

[0092] FIGS. 7A-7B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure. The dies 1102 may include any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, and may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assemblies which include undercut conductive circuit elements as shown in FIGS. 5C and 6C, or any further embodiments of these assemblies as described herein. The wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product. A die 1102 may include one or more quantum circuits 100, including any supporting conductive circuitry to route electrical signals within the quantum circuits 100 (e.g., the undercut conductive circuit elements as described herein), as well as any other IC components. In some embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 9) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0093] FIG. 8 is a cross-sectional side view of a device assembly 1200 that may include any of the embodiments of the quantum circuit assemblies disclosed herein. The device assembly 1200 includes a number of components disposed on a circuit board 1202. The device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.

[0094] In some embodiments, the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. In other embodiments, the circuit board 1202 may be a package substrate or flexible board.

[0095] The IC device assembly 1200 illustrated in FIG. 8 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216. The coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. [0096] The package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218. The coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 8, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204. The interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220. The package 1220 may be a quantum circuit device package as described herein, e.g. a package including the quantum circuit 100 with any of the quantum circuit assemblies as described herein, or a combination thereof, or may be a conventional IC package, for example. Generally, the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202. In the embodiment illustrated in FIG. 8, the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204. In some embodiments, three or more components may be interconnected by way of the interposer 1204.

[0097] The interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1206. The interposer 1204 may further include embedded devices 1214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.

[0098] The device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222. The coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216, and the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220. The package 1224 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional IC package, for example. In some embodiments, the package 1224 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein.

[0099] The device assembly 1200 illustrated in FIG. 8 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228. The package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232. The coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above. Each of the packages 1226 and 1232 may be a qubit device package as described herein or may be a conventional IC package, for example. In some embodiments, one or both of the packages 1226 and 1232 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein, or a combination thereof.

[0100] FIG. 9 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuits with any of the quantum circuit assemblies disclosed herein. A number of components are illustrated in FIG. 9 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 9, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.

[0101] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum circuits 100 with any of the quantum circuit assemblies disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.

[0102] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0103] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0104] The quantum computing device 2000 may include a cooling apparatus 2024. The cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0105] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0106] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0107] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0108] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0109] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0110] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0111] The quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above). The audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MI DI) output).

[0112] The quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above). The GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0113] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0114] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0115] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

Select Examples

[0116] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0117] Example 1 provides a quantum circuit assembly that includes quantum circuit assembly including a substrate; a plurality of qubits provided over or in the substrate; and a conductive circuit element for one or more of the plurality of qubits, the conductive circuit element provided over the substrate and including a conductive line, where a portion of the conductive line is suspended over the substrate.

[0118] Example 2 provides the quantum circuit assembly according to Example 1, where a width of the conductive line portion suspended over the substrate (or, correspondingly, a depth of an undercut in the lower portion of the conductive line which resulted in the portion of the conductive line being suspended over the substrate) is between about 1 and 5000 nanometers, including all values and ranges therein, e.g. between about 10 and 200 nm, or between about 20 and 100 nm.

[0119] Example 3 provides the quantum circuit assembly according to Example 1, where a width of the conductive line portion suspended over the substrate (or, correspondingly, a depth of an undercut in the lower portion of the conductive line which resulted in the portion of the conductive line being suspended over the substrate) is between about 1% and 40% of a total width of the conductive line, including all values and ranges therein, e.g. between about 5% and 25%, or between about 10% and 20%.

[0120] Example 4 provides the quantum circuit assembly according to any one of the preceding Examples, where a distance between the substrate and the conductive line portion suspended over the substrate is between about 5 and 200 nanometers, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 5 and 35 nm.

[0121] Example 5 provides the quantum circuit assembly according to any one of the preceding Examples, where the conductive line portion is a first portion and the conductive circuit element further includes a second portion of the conductive line suspended over the substrate, where the first portion is provided on a first side of the conductive line along the length of the conductive line and the second portion is provided on a second side of the conductive line, the second side being opposite to the first side (i.e. a conductive line may be undercut on both sides, as e.g. shown with the undercuts 310 on each side of the signal line 326 shown in FIG. 3).

[0122] Example 6 provides the quantum circuit assembly according to any one of the preceding

Examples, where the conductive line has a lower portion and an upper portion, where the lower portion is provided over the substrate, the upper portion is provided over the lower portion, and the conductive line portion suspended over the substrate is a part of the upper portion.

[0123] Example 7 provides the quantum circuit assembly according to Example 6, where the upper portion and the lower portion are made of different electrically conductive, e.g. superconductive, materials. In such an Example, the manufacturing process could rely on different etch selectivity of the different conductive materials for the lower and the upper portions of the resonator.

[0124] Example 8 provides the quantum circuit assembly according to Example 7, where the lower portion includes Al, and the upper portion includes Nb, NbN, ΤΪΝ, or NbTiN, or some other electrically conductive, e.g. superconductive, material, different from Al.

[0125] Example 9 provides the quantum circuit assembly according to any one of Examples 6-8, where a width of the upper portion is greater than a width of the lower portion. [0126] Example 10 provides the quantum circuit assembly according to any one of Examples 6-9, where a thickness of the lower portion is between about 5 and 200 nanometers, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 5 and 35 nm.

[0127] Example 11 provides the quantum circuit assembly according to any one of Examples 6-10, where a thickness of the upper portion is between about 50 and 500 nanometers, including all values and ranges therein, e.g. between 100 and 250 nm.

[0128] Example 12 provides the quantum circuit assembly according to any one of the preceding Examples, where the conductive circuit element is a coplanar waveguide (CPW) and the conductive line is a signal line of the CPW, the conductive circuit element further including a ground plane on each side of the conductive line, where a portion of the ground plane on each side of the signal line is suspended over the substrate. In such embodiments, various considerations provided above with respect to one or more portions of the signal line being suspended over the substrate are applicable to one or more portions of the ground line being suspended in a similar manner.

[0129] Example 13 provides the quantum circuit assembly according to any one of Examples 1-12, where the conductive circuit element is a quantum circuit resonator coupled to the one or more of the plurality of qubits. For example, in some embodiments, the conductive circuit element may be a coupling resonator for coupling two or more of the plurality of qubits. In other embodiments, the conductive circuit element may be a readout resonator for reading out a state of one of the plurality of qubits.

[0130] Example 14 provides the quantum circuit assembly according to any one of Examples 1-12, where the conductive circuit element is a non-resonant transmission line.

[0131] Example 15 provides the quantum circuit assembly according to Example 14, where the non- resonant transmission line is a flux bias line or a microwave feed line.

[0132] Example 16 provides a method of fabricating a quantum circuit assembly, the method including providing a bilayer stack of conductive materials over a substrate, the bilayer stack including a first conductive layer over the substrate and a second conductive layer over the first conductive layer; etching the bilayer stack to form a conductive line of a conductive circuit element over the substrate; and etching the first conductive layer of the conductive line under (i.e. further than) the second conductive layer of the conductive line to suspend a portion of the conductive line over the substrate (i.e. to undercut a portion of the conductive line).

[0133] Example 17 provides the method according to Example 16, where etching the bilayer stack to form the conductive line includes performing a dry etch, possibly in combination with standard photo-lithography or e-beam-lithography patterning processes. [0134] Example 18 provides the method according to Examples 16 or 17, where etching the first conductive layer of the conductive line under (or further than) the second conductive layer of the conductive line to suspend the portion of the conductive line over the substrate includes performing a wet or an isotropic dry etch to remove a portion of the first conductive layer under the second conductive layer of the conductive line, thus creating an undercut of depth d_u under a portion of the conductive line.

[0135] Example 19 provides the method according to any one of Examples 16-18, where etching the first conductive layer of the conductive line further than the second conductive layer of the conductive line to suspend the portion of the conductive line over the substrate includes performing an etch that has a higher etch rate for the first conductive layer than for the second conductive layer, e.g. in the case of Al under a Nb based material using 2% TMAH to selectively etch Al to create an undercut.

[0136] Example 20 provides the method according to any one of Examples 16-19, where providing the first conductive layer over the substrate includes depositing a conductive material (e.g. Al) of the first conductive layer using thermal evaporation, e-beam evaporation, or sputtering.

[0137] Example 21 provides the method according to any one of Examples 16-20, where providing the second conductive layer over the first conductive layer includes depositing a conductive material (e.g. a material other than Al) of the second conductive layer using sputtering (e.g. using DC or RF sputtering for depositing Nb, or reactively sputtering NbN or NbTiN), physical vapor deposition (e.g. to deposit Nb, NbN, NbTiN, or TiN), chemical vapor deposition, or atomic layer deposition (e.g. to deposit TiN).

[0138] Example 22 provides a quantum computing device that includes a quantum processing device and a memory device. The quantum processing device includes a die comprising a plurality of qubits over or in a substrate, and at least one conductive circuit element for one or more of the plurality of qubits, where the conductive circuit element includes a conductive line comprising an undercut so that at least a portion of the conductive line is suspended over the substrate. The memory device is configured to store data generated by the plurality of qubits during operation of the quantum processing device

[0139] Example 23 provides the quantum computing device according to Example 22, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

[0140] Example 24 provides the quantum computing device according to Examples 22 or 23, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device. [0141] Example 25 provides the quantum computing device according to any one of Examples 22- 24, further including a non-quantum processing device coupled to the quantum processing device.

[0142] In further Examples, the quantum processing device of the quantum computing device according to any one of Examples 22-25 may include a quantum circuit assembly according to any one of Examples 1-15, and/or at least portions of the quantum processing device of the quantum computing device may be fabricated using the method according to any one of Examples 16-21.

[0143] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0144] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims:

1. A quantum circuit assembly comprising:

a substrate;

a plurality of qubits over or in the substrate; and

a conductive circuit element for one or more of the plurality of qubits, the conductive circuit element over the substrate and comprising a conductive line, wherein a portion of the conductive line is suspended over the substrate.

2. The quantum circuit assembly according to claim 1, wherein a width of the portion suspended over the substrate is between about 1 and 5000 nanometers.

3. The quantum circuit assembly according to claim 1, wherein a width of the portion suspended over the substrate is between 1% and 40% of a width of the conductive line.

4. The quantum circuit assembly according to any one of claims 1-3, wherein a distance between the substrate and the portion suspended over the substrate is between 5 and 200 nanometers.

5. The quantum circuit assembly according to any one of claims 1-3, wherein the portion is a first portion and the conductive circuit element further includes a second portion of the conductive line suspended over the substrate, wherein the first portion is on a first side of the conductive line and the second portion is on a second side of the conductive line.

6. The quantum circuit assembly according to any one of claims 1-3, wherein the conductive line has a lower portion and an upper portion, wherein:

the lower portion is over the substrate,

the upper portion is over the lower portion, and

the portion suspended over the substrate is a part of the upper portion.

7. The quantum circuit assembly according to claim 6, wherein the upper portion and the lower portion are made of different conductive materials.

8. The quantum circuit assembly according to claim 7, wherein the lower portion comprises aluminum (Al), and the upper portion comprises niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), or niobium titanium nitride (NbTiN).

9. The quantum circuit assembly according to claim 6, wherein a width of the upper portion is greater than a width of the lower portion.

10. The quantum circuit assembly according to claim 6, wherein a thickness of the lower portion is between 5 and 200 nanometers.

11. The quantum circuit assembly according to claim 6, wherein a thickness of the upper portion is between 50 and 500 nanometers.

12. The quantum circuit assembly according to any one of claims 1-3, wherein the conductive circuit element is a coplanar waveguide (CPW) and the conductive line is a signal line of the CPW, the conductive circuit element further comprising a ground plane on each side of the conductive line, wherein a portion of the ground plane on each side of the signal line is suspended over the substrate.

13. The quantum circuit assembly according to any one of claims 1-3, wherein the conductive circuit element is a quantum circuit resonator coupled to the one or more of the plurality of qubits.

14. The quantum circuit assembly according to any one of claims 1-3, wherein the conductive circuit element is a non-resonant transmission line.

15. The quantum circuit assembly according to claim 14, wherein the non-resonant transmission line is a flux bias line or a microwave feed line.

16. A method of fabricating a quantum circuit assembly, the method comprising:

providing a bilayer stack of conductive materials over a substrate, the bilayer stack comprising a first conductive layer over the substrate and a second conductive layer over the first conductive layer;

etching the bilayer stack to form a conductive line of a conductive circuit element; and etching the first conductive layer of the conductive line under the second conductive layer of the conductive line to suspend a portion of the conductive line over the substrate.

17. The method according to claim 16, wherein etching the bilayer stack to form the conductive line comprises performing a dry etch.

18. The method according to claim 16, wherein etching the first conductive layer of the conductive line under the second conductive layer of the conductive line to suspend the portion of the conductive line over the substrate comprises performing a wet or an isotropic dry etch.

19. The method according to any one of claims 16-18, wherein etching the first conductive layer of the conductive line further than the second conductive layer of the conductive line to suspend the portion of the conductive line over the substrate comprises performing an etch that has a higher etch rate for the first conductive layer than for the second conductive layer.

20. The method according to any one of claims 16-18, wherein providing the first conductive layer over the substrate comprises depositing a conductive material of the first conductive layer using thermal evaporation, e-beam evaporation, or sputtering.

21. The method according to any one of claims 16-18, wherein providing the second conductive layer over the first conductive layer comprises depositing a conductive material of the second conductive layer using sputtering, physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

22. A quantum computing device, comprising:

a quantum processing device that includes a die comprising a plurality of qubits over or in a substrate and at least one conductive circuit element for one or more of the plurality of qubits, where the conductive circuit element includes a conductive line comprising an undercut so that at least a portion of the conductive line is suspended over the substrate; and

a memory device configured to store data generated by the plurality of qubits during operation of the quantum processing device.

23. The quantum computing device according to claim 22, further comprising a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

24. The quantum computing device according to claims 22 or 23, wherein the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

25. The quantum computing device according to claims 22 or 23, further comprising a non- quantum processing device coupled to the quantum processing device.