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WO2019022825A3 - Génération d'histogrammes de tension - Google Patents

Génération d'histogrammes de tension Download PDF

Info

Publication number
WO2019022825A3
WO2019022825A3 PCT/US2018/033975 US2018033975W WO2019022825A3 WO 2019022825 A3 WO2019022825 A3 WO 2019022825A3 US 2018033975 W US2018033975 W US 2018033975W WO 2019022825 A3 WO2019022825 A3 WO 2019022825A3
Authority
WO
WIPO (PCT)
Prior art keywords
propagation speed
delay stages
stage
voltage
histogram generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2018/033975
Other languages
English (en)
Other versions
WO2019022825A2 (fr
Inventor
Ryan Michael Coutts
Shahin Solki
Paul Ivan Penzes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to CN201880049595.6A priority Critical patent/CN110945788A/zh
Publication of WO2019022825A2 publication Critical patent/WO2019022825A2/fr
Publication of WO2019022825A3 publication Critical patent/WO2019022825A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

L'invention concerne un circuit intégré pour la génération d'histogrammes de tension. Dans un aspect donné à titre d'exemple, le circuit intégré comprend de multiples étages de retard couplés en série et de multiples compteurs. Les multiples étages de retard comprennent un premier trajet de signalisation pour propager un premier signal à une première vitesse de propagation et un second trajet de signalisation pour propager un second signal à une seconde vitesse de propagation. La première vitesse de propagation est inférieure à la seconde vitesse de propagation, et les deux vitesses dépendent de la tension. Les multiples étages de retard comprennent également un circuit de détection de temps d'arrivée (TOA) respectif pour chaque étage de retard respectif. Le circuit de détection de TOA respectif génère un signal de synchronisation d'étage respectif indiquant un temps d'arrivée relatif entre les premier et second signaux à l'étage de retard respectif. Les multiples compteurs sont respectivement couplés aux multiples étages de retard et ont des valeurs de compteur respectives. Les valeurs de compteur respectives sont incrémentées en réponse au signal de synchronisation d'étage respectif.
PCT/US2018/033975 2017-07-28 2018-05-22 Génération d'histogrammes de tension Ceased WO2019022825A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201880049595.6A CN110945788A (zh) 2017-07-28 2018-05-22 电压直方图生成

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201715663389A 2017-07-28 2017-07-28
US15/663,389 2017-07-28

Publications (2)

Publication Number Publication Date
WO2019022825A2 WO2019022825A2 (fr) 2019-01-31
WO2019022825A3 true WO2019022825A3 (fr) 2019-05-16

Family

ID=63643037

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2018/033975 Ceased WO2019022825A2 (fr) 2017-07-28 2018-05-22 Génération d'histogrammes de tension

Country Status (2)

Country Link
CN (1) CN110945788A (fr)
WO (1) WO2019022825A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114727051B (zh) * 2022-06-06 2022-09-02 宏晶微电子科技股份有限公司 一种媒体资源传输装置、系统及方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0547349A2 (fr) * 1991-12-16 1993-06-23 Hewlett-Packard Company Circuit intégré à sortie programmable
GB2285373A (en) * 1993-12-21 1995-07-05 Fujitsu Ltd Code error counting circuit
US20070033448A1 (en) * 2003-12-10 2007-02-08 Waschura Thomas E Method and apparatus for using dual bit decisions to measure bit errors and event occurences
US7750305B2 (en) * 2006-06-15 2010-07-06 Koninklijke Philips Electronics N.V. Integrated multi-channel time-to-digital converter for time-of-flight pet
US20110060975A1 (en) * 2009-08-07 2011-03-10 Stmicroelectronics S.R.L. System for detecting operating errors in integrated circuits
WO2013039624A1 (fr) * 2011-09-12 2013-03-21 Rambus Inc. Étalonnage d'égalisation de rétroaction de décision et de décalage
US20130293281A1 (en) * 2012-05-03 2013-11-07 Intel Mobile Communications GmbH Circuit arrangement and method for operating a circuit arrangement
US20160217872A1 (en) * 2015-01-26 2016-07-28 9011579 Canada Incorporee Adaptive analog-to-digital conversion based on signal prediction
US9459314B1 (en) * 2014-10-08 2016-10-04 Microsemi Storage Solutions (U.S.), Inc. Circuit and method for real-time monitoring of process, temperature, and voltage variations

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100531469B1 (ko) * 2003-01-09 2005-11-28 주식회사 하이닉스반도체 지연고정 정보저장부를 구비한 아날로그 지연고정루프
US6958592B2 (en) * 2003-11-26 2005-10-25 Power-One, Inc. Adaptive delay control circuit for switched mode power supply
CN106970519A (zh) * 2017-05-17 2017-07-21 宁波大学 时间测试电路及时间测试方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0547349A2 (fr) * 1991-12-16 1993-06-23 Hewlett-Packard Company Circuit intégré à sortie programmable
GB2285373A (en) * 1993-12-21 1995-07-05 Fujitsu Ltd Code error counting circuit
US20070033448A1 (en) * 2003-12-10 2007-02-08 Waschura Thomas E Method and apparatus for using dual bit decisions to measure bit errors and event occurences
US7750305B2 (en) * 2006-06-15 2010-07-06 Koninklijke Philips Electronics N.V. Integrated multi-channel time-to-digital converter for time-of-flight pet
US20110060975A1 (en) * 2009-08-07 2011-03-10 Stmicroelectronics S.R.L. System for detecting operating errors in integrated circuits
WO2013039624A1 (fr) * 2011-09-12 2013-03-21 Rambus Inc. Étalonnage d'égalisation de rétroaction de décision et de décalage
US20130293281A1 (en) * 2012-05-03 2013-11-07 Intel Mobile Communications GmbH Circuit arrangement and method for operating a circuit arrangement
US9459314B1 (en) * 2014-10-08 2016-10-04 Microsemi Storage Solutions (U.S.), Inc. Circuit and method for real-time monitoring of process, temperature, and voltage variations
US20160217872A1 (en) * 2015-01-26 2016-07-28 9011579 Canada Incorporee Adaptive analog-to-digital conversion based on signal prediction

Also Published As

Publication number Publication date
CN110945788A (zh) 2020-03-31
WO2019022825A2 (fr) 2019-01-31

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