WO2019020028A1 - Method and apparatus for allocating shared resource - Google Patents

Abstract

Provided are a method and apparatus for allocating a shared resource. The method comprises: detecting an operating state of a shared resource and counting in the operating state when a plurality of threads simultaneously access the shared resource; reading a count value to acquire the number of basic clock periods, the number of waiting clock periods and the number of interference clock periods, wherein the number of basic clock periods is the count value of the shared resource in a first state, the number of waiting clock periods is the count value of the shared resource in a second state, and the number of interference clock periods is the count value of the shared resource in a third state; and according to the number of basic clock periods, the number of waiting clock periods and the number of interference clock periods, adjusting the amount of the shared resource to be allocated to a target thread, so as to ensure the quality of service of the target thread.

Description

Shared resource allocation method and device Technical field

The present application relates to the field of information technology, and in particular, to a shared resource allocation method and apparatus.

Background technique

With the development of the Internet and cloud computing, more and more threads are being migrated from the local to the data center server in the cloud. In order to reduce the hardware overhead of the data center server and improve the resource utilization of the data center server, multiple Thread-mixed deployment strategy, that is, multiple threads are mixed and deployed in the same data center server. Because multiple threads of the hybrid deployment need to share the hardware and software resources (that is, shared resources) in the data center server, resource competition occurs, resulting in mixing. Unpredictable thread performance of the deployment can seriously affect the quality of service of the target thread (such as high priority threads).

Summary of the invention

To solve the problem of the prior art, the embodiment of the present application provides a shared resource allocation method and apparatus, which detects a working state of a target thread when multiple threads access a shared resource at the same time, and adjusts a target thread according to the detected working state. The allocation of shared resources to ensure the quality of service of the target thread.

In a first aspect, an embodiment of the present application provides a method for allocating a shared resource, including: detecting a working state of a shared resource when multiple threads access a shared resource at the same time and counting in a working state, where the working state includes using the shared resource by the target thread without blocking. a first state, a second state in which the target thread blocks the shared resource, and a third state in which the non-target thread causes the shared resource to block, and the count value is read to obtain the basic clock cycle number, the waiting clock cycle number, and the number of interference clock cycles, wherein The basic clock cycle number is a count value of the shared resource in the first state, the waiting clock cycle number is a count value of the shared resource in the second state, and the number of the interference clock cycles is a count value of the shared resource in the third state, according to The number of basic clock cycles, the number of waiting clock cycles, and the number of interfering clock cycles are adjusted to adjust the allocation amount of the shared resources of the target thread.

In the embodiment of the present application, since the usage of the shared resource by the target thread is detected, the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles of the target thread are respectively counted, and the clock is waited according to the basic clock cycle number. The number of cycles and the number of interference clock cycles are used to adjust the allocation quota of the shared resources of the target thread, so that the allocation quota of the shared resources of the target thread can be dynamically adjusted according to the working state of the shared resources, thereby ensuring the quality of service of the target thread.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the shared resource includes multiple sub-shared resources, and the target thread and the non-target thread access multiple sub-shared resources in a serial manner, and the target thread is used without blocking. When any of the plurality of sub-shared resources is in the first state, when the target thread causes any of the plurality of sub-shared resources to block, the shared resource is in the second state, and the non-target thread causes the plurality of sub-shared resources When one is blocked, the shared resource is in the third state.

When multiple sub-shared resources are accessed by multiple threads in a pipeline manner, the working state of each sub-shared resource is detected, and the working state of each sub-shared resource is integrated, and the global working state of the shared resource is summarized, and the target thread pair is integrated as a whole. Judging the occupancy rate of shared resources can effectively improve the accuracy of the adjustment of shared resources.

With reference to the first aspect or the first possible implementation manner of the first aspect, in the second possible implementation manner of the first aspect, the basic clock cycle number, the number of waiting clock cycles, and the number of interference clock cycles are determined according to the target thread. Adjusting the allocation quota of the shared resource of the target thread includes: determining the exclusive running time of the target thread and the actual running time of the target thread according to the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles, in the exclusive running time and the actual time When the ratio between the running times is less than the quality of service Qos indicator, the allocation amount of the shared resources of the target thread is increased.

Since the exclusive running time and the actual running time are obtained according to the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles, directly reflecting the use of the shared resources by the target thread, obtaining the Qos indicator set by the user, and monopolizing the running time. Compared with the actual running time, the ratio between the actual running time and the Qos index can be used to know whether the target thread's usage of the shared resource satisfies the user's expectation, and maintains the allocation of the shared resource to the target thread when the user expects, or increases the shared resource to the non-target. The allocation of threads can improve the utilization of shared resources while ensuring the performance of the target thread. When the user expects not to be satisfied, the service quality of the target thread can be guaranteed by increasing the allocation quota of the shared resources of the target thread.

With the second possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the target thread is maintained when the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator The allocation of shared resources.

With reference to the second possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, when the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator, the non-target is added. The allocation amount of the shared resource of the thread.

In a possible implementation manner, determining the exclusive running time of the target thread and the actual running time of the target thread according to the basic clock cycle number, the number of waiting clock cycles, and the number of the interference clock cycles, including: waiting for the basic clock cycle, waiting The number of clock cycles and the number of interfering clock cycles are summed to obtain the actual running time, and the number of basic clock cycles and the number of waiting clock cycles are summed to obtain exclusive running time.

The exclusive running time of the target thread indicates that the target thread exclusively uses the shared resource without being interfered by the non-target thread. Therefore, the exclusive running time can be the sum of the basic clock period and the waiting clock period, for example, in practical applications, In a multi-threaded mixed-running scenario, when the target thread is not prioritized and the target thread can monopolize the shared resource, the target thread is inevitably affected by the non-target thread, so the actual running time of the target thread should be the basic clock period. The sum of the number, the number of waiting clock cycles, and the number of interfering clock cycles.

In a possible implementation manner, the shared resource includes a front-end shared resource and a back-end shared resource, and the allocation quota of the shared resource of the target thread is increased, which includes: increasing the allocation quota of the front-end shared resource of the target thread, and increasing the target thread. After the front-end shared resource allocation quota, when the ratio between the exclusive running time and the actual running time is still less than the quality of service QoS indicator, the allocation quota of the target thread's back-end shared resource is increased.

Since both the instruction of the target thread and the instruction of the non-target thread use the front-end shared resource and then use the back-end shared resource, the number of interference clock cycles can be reduced relatively quickly by preferentially increasing the allocation amount of the front-end shared resource of the target thread. The ratio between the exclusive running time and the actual running time is rapidly increased to be greater than or equal to the Qos indicator.

In a possible implementation manner, the front-end shared resource includes an fetch unit and a first-level instruction cache, and the back-end shared resource includes a fetch queue, a first-level data cache, an instruction queue, an instruction reorder cache, and a physical rename register.

In a second aspect, the embodiment of the present application provides a thread resource allocation apparatus, including: a counting module, configured to detect a working state of a shared resource when multiple threads access a shared resource at the same time, and the working state includes a target thread that uses a shared resource without blocking. a state, a second state in which the target thread blocks the shared resource, and a third state in which the non-target thread causes the shared resource to be blocked, the counting module is configured to count in the working state, and the clock cycle number reading module is used to read the count The value is used to obtain the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles. The number of basic clock cycles is the count value of the shared resource in the first state, and the number of waiting clock cycles is the count of the shared resource in the second state. The value of the interference clock cycle is a count value of the shared resource in the third state; the resource allocation quota adjustment module is configured to adjust the allocation of the shared resource of the target thread according to the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles. Amount.

The implementation of the second aspect or the second aspect is the device implementation corresponding to the first aspect or the implementation manner of any one of the first aspect, and the description in any one of the first aspect or the first aspect is applicable to the second aspect. Or any implementation of the second aspect, and details are not described herein again.

In a third aspect, an embodiment of the present application provides a thread resource allocation apparatus, including a processor and a memory, where the memory stores program instructions, and the processor runs the program instructions to perform the steps of the first aspect and various possible implementation manners of the first aspect. .

A fourth aspect of the present application provides a multi-threaded control device comprising at least one processing element (or chip) for performing the method of the above first aspect.

A fifth aspect of the present application provides a program for executing the method of the first aspect and various possible implementations of the first aspect, when executed by a processor.

A sixth aspect of the present application provides a program product, such as a computer readable storage medium, comprising the program of the fifth aspect.

A seventh aspect of the present application provides a computer readable storage medium having stored therein instructions that, when run on a computer, cause the computer to perform the method of the first aspect described above.

DRAWINGS

1 is a schematic structural diagram of a shared resource allocation system according to an embodiment of the present application;

2 is a flowchart of a shared resource allocation method according to an embodiment of the present application;

FIG. 3 is another schematic structural diagram of a shared resource allocation system according to an embodiment of the present application; FIG.

4 is a schematic diagram of connection between a primary instruction cache and a primary instruction cache state detection module according to an embodiment of the present application;

FIG. 5 is a schematic diagram of connection between an indexing unit and a value unit status detecting module according to an embodiment of the present application; FIG.

6 is a schematic diagram of a connection between a physical rename register and a physical rename register state detection module according to an embodiment of the present application;

7 is a schematic diagram of a connection of an instruction reordering cache and an instruction reordering buffer state detecting module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a connection between an instruction queue and an instruction queue state detection module according to an embodiment of the present application; FIG.

9 is a schematic diagram of connection between a memory access queue and a memory access queue state detecting module according to an embodiment of the present application;

10 is a schematic diagram of connection between a primary data cache and a primary data cache state detection module according to an embodiment of the present application;

11 is a schematic diagram of a connection relationship between a first state detecting module and a basic clock counter according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a connection relationship between a second state detecting module and a waiting clock counter according to an embodiment of the present application; FIG.

FIG. 13 is a connection diagram of a third state detecting module and an interference clock counter according to an embodiment of the present application; FIG.

FIG. 14 is a schematic diagram of a hardware structure of a shared resource allocation apparatus according to an embodiment of the present application.

Detailed ways

First, please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a shared resource allocation system according to an embodiment of the present application. As shown in FIG. 1, the shared resource allocation system 100 includes a target thread 102, a non-target thread 103, a shared resource 300, and a shared resource. Distribution device 200.

In the embodiment of the present application, the target thread 102 refers to a thread that needs to guarantee the quality of service, which requires less delay, and needs to ensure that the shared resources occupied by it are sufficient, and the non-target thread 103 refers to a thread that does not need to guarantee the quality of service. The delay requirement may be larger than the target thread, and the shared resources occupied by the non-target thread 103 may be sacrificed under the premise of guaranteeing the quality of service of the target thread 102.

Specifically, the target thread 102 and the non-target thread 103 respectively include at least one instruction, and each instruction carries an instruction content and a thread number, and the thread number is used to identify the thread to which the instruction belongs. In the embodiment of the present application, the target thread 102 The instruction carries the target thread number, the instruction of the non-target thread 103 carries the non-target thread number, and the target thread 102 and the non-target thread 103 simultaneously access the shared resource 300, and share the resource according to the target thread 102 and/or the non-target thread 103. With the use of 300, the shared resource 300 can be in different working states.

The working state of the shared resource 300 includes a first state in which the target thread 102 is non-blocking using the shared resource 300, a second state in which the target thread 102 causes the shared resource 300 to be blocked, and a third state in which the non-target thread 103 causes the shared resource 300 to block. .

Specifically, the first state is specifically that when the shared resource 300 is sufficient, the instruction of the target thread 102 can directly use the state of the shared resource 300 without waiting; the second state is specifically, when the shared resource 300 is insufficient, part of the instruction of the target thread 102 Using the shared resource 300, while other instructions of the target thread 102 are waiting for the state of the shared resource 300, it is worth noting that in the second state, the other instruction causing the target thread 102 to wait for the shared resource is that the shared resource 300 has been targeted Part of the instructions of the thread 102 are used to cause blocking; the third state is specifically when the shared resource 300 is insufficient, the instruction of the non-target thread 103 uses the shared resource 300, and the instruction of the target thread 102 waits for the state of the shared resource 300, in the third state The reason for causing the instruction of the target thread 102 to wait for the shared resource is that the shared resource 300 has been used by the instruction of the non-target thread 103, causing blocking.

In the embodiment of the present application, the shared resource allocation apparatus 200 is connected to the shared resource 300 for detecting the working state of the shared resource 300, and adjusting the allocation quota of the shared resource 300 that the target thread 102 can use according to the detected working state, so that The shared resource quota that the target thread 102 can use corresponds to the operational state of the target thread 102.

Referring further to FIG. 1, the shared resource includes a plurality of sub-shared resources 1, 2, 3, 4, and the target thread 102 and the non-target thread 103 access the plurality of sub-shared resources 1, 2, 3, 4 in a serial manner, at the target thread 102. When any of the plurality of sub-shared resources 1, 2, 3, 4 is used without blocking, the shared resource 300 is in the first state, causing any of the plurality of sub-shared resources 1, 2, 3, 4 to be blocked at the target thread 102. At the same time, the shared resource 300 is in the second state, and when the non-target thread 103 causes any of the plurality of child shared resources 1, 2, 3, 4 to block, the shared resource 300 is in the third state.

It should be noted that, in the embodiment of the present application, the number of sub-shared resources is not limited to the number shown in FIG. 1. In an alternative embodiment, the number of sub-shared resources may be set according to actual needs.

The shared resource allocation apparatus 200 includes a state detecting module 210, a counting module 240, a clock cycle reading module 220, and a resource allocation amount adjustment module 230. The counting module 240 includes a basic clock counter 282, a waiting clock counter 284, and an interference clock counter 286. The state detecting module 210 includes a first sub-shared resource state detecting module 2101, a second sub-shared resource state detecting module 2102, and a third sub-share. The resource status detection module 2103 and the fourth sub-shared resource status detection module 2104, in the embodiment of the present application, each sub-shared resource sets a sub-shared resource status detection module, and the sub-shared resource status detection module can detect the corresponding sub-shared resource. The working state, wherein the working state includes a first state, a second state, and a third state.

The state detecting module 210 further includes a first state detecting module 281, a second state detecting module 283, and a third state detecting module 285. The first state detecting module 281 respectively uses the first child shared resource state detecting module 2101 and the second child shared resource. The state detecting module 2102, the third sub-shared resource state detecting module 2103, and the fourth sub-shared resource state detecting module 2104 know whether the sub-shared resources 1 to 4 operate in the first state, and operate at the first in the shared resources 1 to 4 In the state, it is confirmed that the target thread 102 uses any of the plurality of sub-shared resources 1, 2, 3, and 4 without blocking. At this time, the shared resource 300 as a whole is in the first state, and the first state detecting module 281 notifies the basic clock counter. 282 is counted.

Further, the second state detecting module 283 is known from the first sub-shared resource state detecting module 2101, the second sub-shared resource state detecting module 2102, the third sub-shared resource state detecting module 2103, and the fourth sub-shared resource state detecting module 2104, respectively. Whether the child shared resources 1 to 4 operate in the second state, and when any of the shared resources 1 to 4 operates in the second state, it is confirmed that the target thread 102 causes any of the plurality of child shared resources 1, 2, 3, and 4 One is blocked. At this time, the shared resource 300 is in the second state as a whole, and the second state detecting module 283 notifies the waiting clock counter 284 to count.

Similarly, the third state detecting module 285 is respectively configured from the first sub-shared resource state detecting module 2101, the second sub-shared resource state detecting module 2102, the third sub-shared resource state detecting module 2103, and the fourth sub-shared resource state detecting module 2104. Whether the sub-shared resources 1 to 4 are operating in the third state, and when any of the shared resources 1 to 4 is operating in the third state, it is confirmed that the non-target threads 103 cause a plurality of sub-shared resources 1, 2, 3, 4 Either one of them is blocked, and at this time, the shared resource 300 is in the third state as a whole, and the third state detecting module 285 notifies the interference clock counter 286 to count.

It is to be noted that, because the sub-shared resources are serially connected, in the embodiment of the present application, when each sub-shared resource is not blocked, it can be confirmed that the shared resource 300 works in the first state, and when any sub-shared resource When the device is blocked, it is confirmed that the shared resource 300 operates in the second state or the third state, wherein the source of the shared resource 300 is determined by determining whether the source of the child shared resource blocking is the target thread 102 or the non-target thread 103. The method of judgment is described in detail below.

The clock cycle reading module 220 is configured to read the count value of the counting module 240 to obtain the basic clock cycle number, the number of waiting clock cycles, and the number of interference clock cycles. The basic clock cycle number is output by the basic clock counter 282, which is the shared resource 300. The count value in the first state, the number of waiting clock cycles is output by the wait clock counter 284, is the count value of the shared resource 300 in the second state, and the number of interference clock cycles is output by the interference clock counter 286, which is the shared resource 300. The count value in the three states.

The resource allocation quota adjustment module 230 is configured to adjust the allocation quota of the shared resource 300 of the target thread according to the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles.

For further clarification, reference is made to FIG. 2 below. FIG. 2 is a flowchart of a shared resource allocation method according to an embodiment of the present application. As shown in FIG. 2, the shared resource allocation method includes the following steps:

Step 401: The shared resource allocation device 200 obtains a quality of service (QoS) indicator.

Specifically, the resource allocation quota adjustment module 230 in the shared resource allocation apparatus 200 stores in advance a Qos indicator, which can be input by the user or set according to a default value.

The Qos indicator is a quality of service indicator for the target thread 102, and the value ranges from 0 to 100%, and is used to indicate the priority requirement of the user for the target thread 102. For example, when the Qos indicator is 100%, Indicates that the user wants the target thread 102 to monopolize the shared resource 300. When the target thread 102 uses the shared resource 300, the shared resource 300 can be released to the non-target thread 103. When the Qos indicator is 50%, the user wants the target thread 102. The non-target threads 103 each occupy half of the shared resource 300; and when the Qos indicator is 0, it indicates that the user wants the target thread 102 not to occupy the shared resource 300.

Step 402: The shared resource allocation device 200 detects the working state of the shared resource 300 and counts when the multi-thread simultaneously accesses the shared resource 300.

Specifically, as shown in FIG. 1 and its corresponding content, the state detecting module 210 of the shared resource allocation apparatus 200 simultaneously accesses the plurality of sub-shared resources 1 to 4 in the shared resource 300 in a serial manner at the target thread 102 and the non-target thread 103. When the working state of the shared resource 300 is detected, the counting module 240 cumulatively counts the duration of the working state, wherein the basic clock counter 282 outputs the count value of the shared resource 300 in the first state, and waits for the clock counter 284 to output the shared resource 300. The count value in the second state, the interference clock counter 286 outputs the count value of the shared resource 300 in the third state.

It should be noted that in the embodiment of the present application, the number of target threads 102 may be one or more, and the number of non-target threads 103 may also be one or more.

Step 403: The clock cycle reading module 220 of the shared resource allocation device 200 reads the count value from the counting module 240 to obtain the basic clock cycle number, the waiting clock cycle number, and the number of interference clock cycles.

The number of basic clock cycles is the count value output by the basic clock counter 282, the number of waiting clock cycles is the count value output by the wait clock counter 284, and the number of interference clock cycles is the count value output by the interference clock counter 286.

Specifically, the clock cycle read module 220 acquires the number of basic clock cycles from the basic clock counter 282, the number of wait clock cycles from the wait clock counter 284, and the number of interference clock cycles from the interference clock counter 286.

In the embodiment of the present application, since the shared resource 300 is simultaneously used by the target thread 102 and the non-target thread 103, the shared resource 300 dynamically switches the working state between the first state, the second state, and the third state, because it is a dynamic switch. Therefore, the duration of the first state, the second state, or the third state is not a continuous period of time, but a plurality of discrete periods of time, and thus the accumulation of the first state, the second state, and the third state separately is required. The time is counted to obtain the proportion of time occupied by the first state, the second state, and the third state within a predetermined time period.

The predetermined time period described in this example may be a statistical period. In the embodiment of the present application, after the basic clock cycle number, the number of waiting clock cycles, and the number of interference clock cycles are obtained in one statistical cycle, according to the basic clock cycle. The number, the number of waiting clock cycles, and the number of interference clock cycles are adjusted, and the allocation quota of the shared resource 300 of the target thread 102 is adjusted, and the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles are continuously acquired in the next statistical cycle, and further determined. After adjusting the allocation quota of the shared resource 300 of the target thread 102 in the previous statistical period, whether the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles in the current statistical period satisfy the Qos indicator.

The statistical period can be set to be between 1 ms and 1 s, for example, depending on the actual application scenario.

Step 404: The resource allocation quota adjustment module 230 of the shared resource allocation apparatus 200 determines the exclusive running time of the target thread 102 and the actual running time of the target thread 102 according to the basic clock cycle number, the number of waiting clock cycles, and the number of interference clock cycles.

The exclusive runtime of the target thread 102 indicates that the target thread 102 exclusively uses the shared resource 300 without interference from the non-target thread 103, so the exclusive runtime may be, for example, the sum of the number of basic clock cycles and the number of waiting clock cycles.

In a practical application, in the multi-threaded running scenario, when the target thread 102 is not prioritized and the target thread 102 can monopolize the shared resource 300, the target thread 102 is inevitably affected by the non-target thread 103. The actual running time of the target thread 102 should be the sum of the number of basic clock cycles, the number of waiting clock cycles, and the number of interfering clock cycles.

Step 405: The resource allocation quota adjustment module 230 of the shared resource allocation device 200 determines that the ratio between the exclusive running time and the actual running time is smaller than the quality of service Qos indicator. If yes, step 406 is performed, and if no, step 407 is performed.

Step 406: The resource allocation quota adjustment module 230 of the shared resource allocation device 200 increases the allocation quota of the shared resource 300 of the target thread 102 when the ratio between the exclusive running time and the actual running time is less than the quality of service QoS indicator.

When the ratio between the exclusive running time and the actual running time is less than the quality of service QoS indicator, it indicates that the quota occupied by the target thread 102 to the shared resource 300 belongs to a level that the user can be unacceptable, and the shared resource allocating device 200 needs to increase the shared resource of the target thread 102. 300 allocation quota.

In some examples, the shared resource 300 includes a front-end shared resource and a back-end shared resource. As shown in FIG. 1 , the child shared resources 1 and 2 in FIG. 1 may be front-end shared resources, and the child shared resources 3 and 4 may be Share resources for the back end. In this step, increasing the allocation quota of the shared resource 300 of the target thread 102 may include: increasing the allocation quota of the front-end shared resource of the target thread 102, and increasing the allocation quota of the shared resource of the front-end thread of the target thread 102, and operating exclusively. When the ratio between the time and the actual running time is still less than the quality of service Qos indicator, the allocation amount of the shared resources of the back end of the target thread 102 is increased.

Since both the instruction of the target thread 102 and the instruction of the non-target thread 103 use the front-end shared resource and then use the back-end shared resource, the interference clock period can be quickly reduced by preferentially increasing the allocation amount of the front-end shared resource of the target thread 102. The number is such that the ratio between the exclusive running time and the actual running time is rapidly increased to be greater than or equal to the Qos indicator.

After the allocation quota of the shared resources of the front end of the target thread 102 is increased, if the ratio is greater than or equal to the Qos indicator, the allocation quota of the shared resources of the backend of the target thread 102 may be further considered, thereby reducing the number of interference clock cycles. Increase the ratio between the exclusive running time and the actual running time to be greater than or equal to the Qos indicator.

For example, in a processor architecture of a Reduced Instruction Set Computer (RISC), the front-end shared resource includes an instruction fetch unit and a first-level instruction cache, and the back-end shared resources include a fetch queue, a first-level data cache, Instruction queues, instruction reorder buffers, and physical rename registers.

Since the instruction of the target thread 102 first accesses the front-end shared resource and then accesses the back-end shared resource, first increasing the allocation amount of the front-end shared resource of the target thread 102 can immediately reduce the number of interference clock cycles, thereby making the exclusive running time and the actual running time. The ratio between them increases relatively quickly to a value not less than the Qos indicator.

Step 407: The resource allocation quota adjustment module 230 of the shared resource allocation device 200 maintains the allocation quota of the shared resource 300 of the target thread 102 when the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator, and/ Or increase the allocation amount of the shared resource 300 of the non-target thread 103.

In this step, when the ratio between the exclusive running time and the actual running time is not less than the quality of service Qos indicator, it indicates that the quota occupied by the target thread 102 occupying the shared resource 300 belongs to a level acceptable to the user, and at this time, as an optional The resource allocation quota adjustment module 230 does not need to adjust the allocation quota of the shared resource 300 of the target thread 102, but in another alternative, the resource allocation quota adjustment module 230 may appropriately increase the shared resource 300 of the non-target thread 103. The allocation quota, thereby effectively utilizing the spare shared resource 300, or, in another alternative, the resource allocation quota adjustment module 230 can maintain the allocation quota for the shared resource 300 of the target thread 102, and at the same time appropriately increase the non-target The allocation amount of the shared resource 300 of the thread 103.

In summary, the embodiment of the present application detects the working state of the shared resource 300 when the multi-thread accesses the shared resource 300 at the same time, and adjusts the allocation quota of the shared resource 300 of the target thread 102 according to the detected working state, thereby ensuring the target thread. 102 quality of service.

For further clarification, reference is made to FIG. 3 for reference. FIG. 3 is another schematic structural diagram of a shared resource allocation system according to an embodiment of the present application. The shared resource allocation system shown in FIG. 3 includes a target thread 102 and a non-target thread 103. The shared resource 300, the shared resource allocation device 200, and the functional module, wherein the functional module includes a decoding unit 501, a rename/allocation unit 502, and a functional unit 503. The shared resource 300 includes an instruction fetch unit 301, a first-level instruction cache 302, and an access. Memory queue 306, primary data cache 307, instruction queue 304, instruction reorder buffer 305, and physical rename register 303. The fetch unit 301 and the first-level instruction cache 302 are front-end shared resources, and the fetch queue 306, the first-level data cache 307, the instruction queue 304, the instruction re-order cache 305, and the physical rename register 303 are back-end shared resources. The shared resource allocation apparatus 200 of the embodiment of the present application is applicable to a RISC processor architecture. Specifically, the RISC processor architecture includes the shared resource 300 and functional modules (including the decoding unit 501, the rename/allocation unit 502) shown in FIG. And functional unit 503), the resource allocation device 200 is exemplified below for application to the RISC processor architecture.

It should be noted that in an alternative embodiment, the shared resource allocation apparatus 200 of the embodiment of the present application is also applicable to a processor architecture of a Complex Instruction Set Computer (CISC) or other processor architecture.

Moreover, FIG. 3 specifically illustrates the example shown in FIG. 1 in a RISC processor architecture. In FIG. 3, the fetch unit 301, the first-level instruction cache 302, the fetch queue 306, the primary data cache 307, and the instruction queue 304 are shown. The instruction reorder buffer 305 and the physical rename register 303 are specific implementations of the sub-shared resources shown in FIG. 1.

In the RISC processor architecture shown in FIG. 3, the instructions of the target thread 102 and the non-target thread 103 are placed in the level one instruction cache 302, and when the level one instruction cache 302 detects the hit instruction, the hit instruction is sent to the fetch. Referring to the unit 301, the fetching unit 301 sends the fetched instruction to the decoding unit 501 for decoding. The decoded instruction is reordered in the renaming/allocating unit 502 and the corresponding physical renaming register 303 is assigned, and renamed. The /allocation unit 502 places the instructions that are reordered and assigned the corresponding physical rename register 303 into the instruction reorder buffer 305, and fetches the instruction from the instruction reorder buffer 305 and sends it to the instruction queue 304 when the functional unit 503 is idle. The function unit 503 executes the instruction. Moreover, when it is determined that the instruction is a memory access instruction, the rename/allocation unit 502 sends the memory access instruction to the memory access queue 306 via the instruction queue 304, and the memory access instruction caches the primary data cache 307 through the memory access queue 306. Make an access.

Further, the state detecting module 210 is configured to detect the working states of the fetching unit 301, the first-level instruction cache 302, the fetch queue 306, the primary data cache 307, the instruction queue 304, the instruction reorder buffer 305, and the physical rename register 303, respectively. The accumulation time of the working states of the fetch unit 301, the first-level instruction cache 302, the fetch queue 306, the primary data cache 307, the instruction queue 304, the instruction reorder buffer 305, and the physical rename register 303, respectively. Counting is performed to obtain the basic clock cycle number of the target thread 102, the number of waiting clock cycles, and the number of interference clock cycles.

Specifically, as shown in FIG. 4 to FIG. 13 , in the embodiment, the state detecting module 210 includes an fetching unit state detecting module 2108 , a first-level instruction cache state detecting module 2109 , and a physical renaming register state detecting module 2110 . The instruction reordering buffer state detecting module 2111, the instruction queue state detecting module 2105, the memory access queue state detecting module 2106, and the first level data buffer state detecting module 2107, wherein each of the foregoing functional modules is the sub-shared resource state detecting module shown in FIG. Implementation.

Referring to FIG. 4, FIG. 4 is a schematic diagram of a connection between a first-level instruction cache and a first-level instruction cache state detection module according to an embodiment of the present application. As shown in FIG. 4, the first-level instruction cache 302 stores a cache address and a thread number 2 The cache space pointed to by the cache address has a cached instruction.

The first level instruction cache 302 is configured to receive the instruction 1000 from the target thread 102 or the non-target thread 103, and determine whether the received address carried by the received instruction 1000 is consistent with the cache address stored by itself, and if so, the memory access hit, indicating a The level instruction cache 302 does not have a memory conflict, and the level one instruction cache 302 buffers the received instruction and generates a hit enable signal of a high level (hereinafter indicated by a high level), and if not, one level The instruction cache 302 has a memory collision conflict, and the level one instruction cache 302 generates a hit enable signal of a low level (hereinafter, 0 indicates a low level).

In some examples, the memory access address is calculated by the first level instruction cache 302 according to the check digit of the instruction 1000. In other examples, the thread number and the instruction content carried by the instruction 1000 may also be calculated, and the specific calculation manner is The embodiments of the present application are not related to the present disclosure.

Further, when the memory access hits, the first-level instruction cache 302 caches the instruction 1000. At this time, the first-level instruction cache state detecting module 2109 needs to determine that the instruction 1000 for the cache processing in the first-level instruction cache 302 belongs to the target thread. 102 is also a non-target thread 103, i.e., whether the target thread 102 uses the level one instruction cache 302. In this embodiment, the first determining unit 224 determines whether the thread number carried by the instruction 1000 received by the first level instruction cache 302 is consistent with the target thread number. If yes, the instruction 1000 belongs to the target thread 102, that is, the target thread 102. The instruction may use the first level instruction cache 302 without blocking. At this time, the first determining unit 224 outputs 1 . If not, it indicates that the instruction belongs to the non-target thread 103 , and the instruction of the non-target thread 103 can use the first level instruction cache 302 without blocking. The first determining unit 224 outputs 0.

Therefore, when the memory access hits, and the thread number carried by the instruction 1000 received by the first-level instruction cache 302 is consistent with the target thread number, the first-level instruction cache 302 is not blocked, and the target thread 102 can use the first-level instruction without blocking. The buffer 302, at this time, the first state output interface 223 outputs 1, the third state output interface 222 outputs 0, and the second state output interface 221 outputs 0.

When the access conflict occurs, the first-level instruction cache 302 is blocked, and the first-level instruction cache 302 generates a hit enable signal 0 and inputs it to the input of the AND gate 229, so that the output of the AND gate 229 outputs 0, thereby causing the first state. The output interface 223 outputs 0. The first level instruction cache state detecting module 2109 further determines whether the source causing the blocking of the level one instruction cache 302 is the instruction of the target thread 102 or the instruction of the non-target thread 103. Specifically, the first determining unit 224 receives the level one instruction cache 302. The thread number carried by the instruction 1000 is compared with the target thread number. If the two are consistent, the thread waiting for the level one instruction cache 302 is the target thread 102, and the output is 1. If the two are inconsistent, the thread waiting for the level one instruction cache 302 is indicated. For non-target thread 103, 0 is output.

Therefore, when the hit enable signal is 0, and the first determining unit 224 outputs 1, the third state output interface 222 outputs 0, the second state output interface 221 outputs 1; the hit enable signal is 0, and the first judgment When unit 224 outputs 0, third state output interface 222 outputs 1 and second state output interface 221 outputs 0.

Referring to FIG. 5, FIG. 5 is a schematic diagram of connection between an instruction fetching unit and an fetching unit state detecting module according to an embodiment of the present application. As shown in FIG. 5, the fetching unit 301 is configured to obtain an instruction 1000 from the first-level instruction cache 302. The fetching unit state detecting module 2108 is configured to compare the thread number carried by the instruction 1000 acquired by the fetching unit 301 with the target thread number.

Specifically, the second determining unit 213 compares whether the thread number 1 carried by the instruction 1000 acquired by the fetching unit 301 is consistent with the target thread number, and if so, the second determining unit 213 outputs 1, and the second status output interface 211 Output 1, the third state output interface 212 outputs 0; if not, the first determining unit outputs 0, the second state output interface 211 outputs 0, and the third state output interface 212 outputs 1.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a connection between a physical rename register and a physical rename register state detection module according to an embodiment of the present application. As shown in FIG. 6, when the physical rename register 303 is not blocked, the instruction 1000 may not be needed. The physical rename register 303 is used awaitingly. At this time, the physical rename register output of the physical rename register 303 blocks the set signal to 0, and the first state output interface 233 outputs 1.

When the physical rename register 303 is blocked, the physical rename register output of the physical rename register 303 blocks the set signal to 1, and the first state output interface 233 outputs 0.

In the embodiment of the present application, the third determining unit 234 is configured to be enabled by the physical renaming register blocking setting signal. Specifically, when the physical renaming register blocking setting signal is 1, the third determining unit 234 operates, and the physical When the rename register blocking set signal is 0, the third judging unit 234 does not operate.

Therefore, when the physical rename register blocking set signal is 1, the physical rename register state detecting module 2110 needs to further determine whether the instruction 1000 causing the physical rename register 303 to block is an instruction of the target thread 102 or an instruction of the non-target thread 103. At this time, the third determining unit 234 determines whether the thread number carried by the instruction 1000 is consistent with the target thread number. If yes, it indicates that the instruction of the target thread 102 causes the physical rename register 303 to block, and the third determining unit 234 outputs 1, If not, it indicates that the instruction of the non-target thread 103 causes the physical rename register 303 to block, and the third determination unit 234 outputs 0.

When the third determining unit 234 outputs 1, the second state output interface 231 outputs 1, the third state output interface 232 outputs 0; when the third determining unit 234 outputs 0, the third state output interface 232 outputs 0, the second state Output interface 231 outputs 1.

It should be noted that FIG. 7 to FIG. 9 respectively introduce a physical rename register state detecting module 2110 having a similar structure and function to the physical rename register state detecting module 2110, an instruction reordering buffer state detecting module 2111, and an instruction queue state detecting. The module 2105 and the memory access queue state detecting module 2106 differ only in the reason that the blocking set signal is generated, wherein the instruction reordering buffer blocking set signal shown in FIG. 7 is 1 when the instruction reordering buffer 305 is blocked. Otherwise it is 0. The instruction queue blocking set signal shown in Figure 8 is 1 when the instruction queue 304 is blocked, and is 0 otherwise. The fetch queue blocking set signal shown in FIG. 10 is 1 when the fetch queue 306 is blocked, and 0 otherwise. The above modules are similar to the physical rename register state detecting module 2110, and are not described herein.

Further, FIG. 10 introduces a primary data cache state detecting module 2107. The primary data cache state detecting module 2107 is similar to the primary command cache state detecting module 2109 shown in FIG. 4, and details are not described herein.

Referring to FIG. 11 , FIG. 11 is a schematic diagram of a connection relationship between a first state detecting module and a basic clock counter according to an embodiment of the present application. In FIG. 11 , the first state detecting module 281 of FIG. 1 is specifically implemented as an AND gate 281 . The input terminal of the AND gate 281 is connected to the first state output interfaces 223, 233, 243, 253, 263, and 273 shown in FIG. 4, FIG. 6 to FIG. 10, respectively, and the output signal of the output terminal of the AND gate 281 is paired with the basic clock counter. 282 is enabled. When any of the first state output interfaces is 0, the output signal of the output of the AND gate 281 is 0, the basic clock counter 282 is not counted, and when all the first state output interface outputs are 1, the AND gate 281 The output signal at the output is 1, and the basic clock counter 282 counts.

In the present embodiment, the output level of the AND gate 281 indicates the first state. When the output level of the gate 281 is 1, it indicates that the shared resource 300 is in the first state, and when the output level of the gate 281 is 0, it indicates The shared resource 300 is not in the first state.

Referring to FIG. 12, FIG. 12 is a schematic diagram of a connection relationship between a second state detecting module and a waiting clock counter according to an embodiment of the present application. In FIG. 12, the second state detecting module 283 shown in FIG. 1 is specifically implemented as an OR gate. 283, the input terminals of the OR gate 283 are respectively connected to the second state output interfaces 211, 221, 231, 241, 251, 261, and 271 shown in FIG. 4 to FIG. 10, and the output signals of the output terminals of the OR gates 283 are waiting for the clock. Counter 284 is enabled, waiting for clock counter 284 to count when any of the wait clock counter interface outputs is 1, and waits for clock counter 284 not to count when all wait clock counter interface outputs are zero.

In the present embodiment, the output level of the AND gate 283 indicates the second state. When the output level of the gate 283 is 1, it indicates that the shared resource 300 is in the second state, and when the output level of the gate 283 is 0, it indicates The shared resource 300 is not in the second state.

Referring to FIG. 13, FIG. 13 is a connection diagram of a third state detecting module and an interference clock counter according to an embodiment of the present application. In FIG. 13, the third state detecting module 285 shown in FIG. 1 is specifically implemented as an OR gate. 285, the input of the OR gate 285 is connected to the third state output interfaces 212, 222, 232, 242, 252, 262, and 272 shown in FIG. 4 to FIG. 10, respectively, and the output signal of the output of the OR gate 285 interferes with the clock. Counter 286 is enabled. When any of the interfering clock counter interface outputs are 1, the interfering clock counter counts. When all interfering clock counter interface outputs are zero, the interfering clock counter 286 does not count.

In the present embodiment, the output level of the AND gate 285 indicates the third state. When the output level of the gate 285 is 1, it indicates that the shared resource 300 is in the third state, and when the output level of the gate 285 is 0, it indicates The shared resource 300 is not in the third state.

Thus, based on the architecture illustrated in Figures 4-11, the base clock counter 282 can count the accumulated time of the first state of the shared resource 300 to obtain the number of basic clock cycles, the waiting clock counter can be the second state of the shared resource 300 The accumulated time is counted to obtain the number of waiting clock cycles, and the interference clock counter can count the accumulated time of the third state of the shared resource 300 to obtain the number of clock cycles, and the clock cycle reading module 220 shown in FIG. The counter 282 acquires the number of basic clock cycles, acquires the number of waiting clock cycles from the waiting clock counter 284, and acquires the number of waiting clock cycles from the interference clock counter 286.

The resource allocation quota adjustment module 230 adjusts the allocation quota of the shared resources of the target thread according to the number of basic clock cycles, the number of waiting clock cycles, and the number of waiting clock cycles. For example, the resource allocation quota adjustment module 230 can implement the target thread by the following manner. Adjustment of the allocation quota of the shared resource: adjusting the allocation quota of the instruction of the target thread in the primary instruction cache 302, the primary data cache 307, and the instruction reordering cache 305, or adjusting the instruction of the target thread in the physical rename register 303, fetching fingers The number of allocations in unit 301, instruction queue 304, and fetch queue 306. For details, refer to step 404 to step 407 shown in FIG. 2 .

In summary, a shared resource allocation method and apparatus provided by an embodiment of the present invention can detect a working state of a target thread when multiple threads access a shared resource at the same time, and adjust a shared resource of the target thread according to the detected working state. The quota is divided to ensure the quality of service of the target thread.

In the embodiment of the present application, the shared resource allocation device may be implemented by an integrated circuit including a logic gate. In an alternative embodiment of the present application, the shared resource allocation device may also pass a Field Programmable Gate Array (FPGA). Implementation, specifically by the program instructions written to the FPGA chip to achieve the corresponding function. Referring to FIG. 14 , FIG. 14 is a schematic diagram of a hardware structure of a shared resource allocation apparatus according to an embodiment of the present application. As shown in FIG. 14 , the shared resource allocation apparatus 200 includes a memory 501 , a bus 503 , and a processor 502 , and a processor 502 . The memory 501 is connected to a bus 503, which stores program instructions, and the processor 502 runs program instructions to implement the functions of the shared resource allocation device 200 described above.

It should be noted that any of the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as the cells may or may not be Physical units can be located in one place or distributed to multiple network elements. Some or all of the processes may be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, in the drawings of the apparatus embodiments provided by the present application, the connection relationship between processes indicates that there is a communication connection between them, and specifically may be implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement without any creative effort.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, dedicated hardware, dedicated CPU, dedicated memory, dedicated memory, Special components and so on. In general, functions performed by computer programs can be easily implemented with the corresponding hardware, and the specific hardware structure used to implement the same function can be various, such as analog circuits, digital circuits, or dedicated circuits. Circuits, etc. However, software program implementation is a better implementation for more applications in this application. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer. , U disk, mobile hard disk, Read-Only Memory (ROM), Random Access Memory (RAM), disk or optical disk, etc., including a number of instructions to make a computer device (may be A personal computer, server, or network device, etc.) performs the methods described in various embodiments of the present application.

A person skilled in the art can clearly understand that the specific working process of the system, the device or the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims (17)

A shared resource allocation method, comprising: Detecting a working state of the shared resource when the multi-threaded accesses the shared resource at the same time, and counting in the working state, the working state includes a first state in which the target thread is non-blocking to use the shared resource, and the target thread causes the sharing a second state in which the resource is blocked, and a third state in which the non-target thread causes the shared resource to be blocked; Reading the count value to obtain the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles, wherein the number of basic clock cycles is a count value of the shared resource in the first state, the waiting clock cycle The number is a count value of the shared resource in the second state, and the number of the interference clock cycles is a count value of the shared resource in the third state; And adjusting, according to the basic clock cycle number, the number of the waiting clock cycles, and the number of the interference clock cycles, an allocation quota of the shared resources of the target thread. The method according to claim 1, wherein the shared resource comprises a plurality of sub-shared resources, and the target thread and the non-target thread access the plurality of sub-shared resources in a serial manner, in the target thread When any one of the plurality of sub-shared resources is used without blocking, the shared resource is in the first state, and when the target thread causes any one of the plurality of sub-shared resources to block, the shared resource In the second state, when the non-target thread causes any one of the plurality of sub-shared resources to block, the shared resource is in the third state. The method according to claim 1 or 2, wherein the adjusting the shared resources of the target thread according to the number of basic clock cycles of the target thread, the number of waiting clock cycles, and the number of the interference clock cycles The amount of distribution, including: Determining, according to the number of the basic clock cycles, the number of the waiting clock cycles, and the number of the interference clock cycles, an exclusive running time of the target thread and an actual running time of the target thread; When the ratio between the exclusive running time and the actual running time is less than the quality of service QoS indicator, the allocation quota of the shared resources of the target thread is increased. The method according to claim 3, wherein the adjusting the allocation of the shared resources of the target thread according to the number of basic clock cycles of the target thread, the number of waiting clock cycles, and the number of the interference clock cycles The amount also includes: When the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator, the allocation quota of the shared resources of the target thread is maintained. The method according to claim 3, wherein the adjusting the allocation of the shared resources of the target thread according to the number of basic clock cycles of the target thread, the number of waiting clock cycles, and the number of the interference clock cycles The amount also includes: When the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator, the allocation quota of the shared resources of the non-target thread is increased. The method according to any one of claims 3 to 5, wherein the determining the exclusive operation of the target thread according to the number of basic clock cycles, the number of waiting clock cycles, and the number of the interference clock cycles The time and the actual running time of the target thread specifically include: And performing a summation operation on the basic clock cycle number, the number of the waiting clock cycles, and the number of the interference clock cycles to obtain the actual running time; And summing the number of basic clock cycles and the number of waiting clock cycles to obtain the exclusive running time. The method according to any one of claims 3 to 6, wherein the shared resource includes a front-end shared resource and a back-end shared resource, and the adding the quota of the shared resource of the target thread includes: Increasing an allocation quota of the front-end shared resource of the target thread; After increasing the allocation quota of the front-end shared resource of the target thread, when the ratio between the exclusive running time and the actual running time is still less than the quality of service QoS indicator, increasing the back-end sharing of the target thread The amount of resources allocated. The method according to any one of claims 1 to 7, wherein the front-end shared resource comprises an fetching unit and a first-level instruction cache, and the back-end shared resource comprises a fetch queue, a first-level data cache, and an instruction. Queue, instruction reorder buffer, and physical rename registers. A shared resource allocation device, comprising: a state detecting module, configured to detect a working state of the shared resource when the multi-thread simultaneously accesses the shared resource, where the working state includes a first state in which the target thread uses the shared resource without blocking, and the target thread causes the shared resource to be blocked a second state, and a third state in which the non-target thread causes the shared resource to be blocked; a counting module, configured to count in the working state; a clock cycle number reading module, configured to read a count value to obtain a basic clock cycle number, a waiting clock cycle number, and an interference clock cycle number, wherein the basic clock cycle number is the shared resource in the first state a count value, the number of waiting clock cycles is a count value of the shared resource in the second state, and the number of the interference clock cycles is a count value of the shared resource in the third state; The resource allocation quota adjustment module is configured to adjust an allocation quota of the shared resources of the target thread according to the basic clock cycle number, the number of the waiting clock cycles, and the number of the interference clock cycles. The apparatus according to claim 9, wherein the shared resource comprises a plurality of sub-shared resources, and the target thread and the non-target thread access the plurality of sub-shared resources in a serial manner, in the target thread When any one of the plurality of sub-shared resources is used without blocking, the shared resource is in the first state, and when the target thread causes any one of the plurality of sub-shared resources to block, the shared resource In the second state, when the non-target thread causes any one of the plurality of sub-shared resources to block, the shared resource is in the third state. The device according to claim 9 or 10, wherein the resource allocation quota adjustment module is specifically configured to: Determining, according to the number of the basic clock cycles, the number of the waiting clock cycles, and the number of the interference clock cycles, an exclusive running time of the target thread and an actual running time of the target thread; When the ratio between the exclusive running time and the actual running time is less than the quality of service QoS indicator, the allocation quota of the shared resources of the target thread is increased. The device according to claim 11, wherein the resource allocation quota adjustment module is specifically configured to: When the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator, the allocation quota of the shared resources of the target thread is maintained. The device according to claim 11, wherein the resource allocation quota adjustment module is specifically configured to: When the ratio between the exclusive running time and the actual running time is not less than the quality of service QoS indicator, the allocation quota of the shared resources of the non-target thread is increased. The device according to any one of claims 11 to 13, wherein the resource allocation quota adjustment module is specifically configured to: And performing a summation operation on the basic clock cycle number, the number of the waiting clock cycles, and the number of the interference clock cycles to obtain the actual running time; And summing the number of basic clock cycles and the number of waiting clock cycles to obtain the exclusive running time. The device according to any one of claims 11 to 14, wherein the shared resource includes a front-end shared resource and a back-end shared resource, and the resource allocation quota adjustment module is specifically configured to: When the ratio between the exclusive running time and the actual running time is less than the quality of service QoS indicator, increasing the allocation quota of the front-end shared resource of the target thread; After increasing the allocation quota of the front-end shared resource of the target thread, when the ratio between the exclusive running time and the actual running time is still less than the quality of service QoS indicator, increasing the back-end sharing of the target thread The amount of resources allocated. The apparatus according to any one of claims 9 to 15, wherein the front-end shared resource comprises an instruction fetching unit and a first-level instruction cache, and the back-end shared resource comprises a memory access queue, a primary data cache, and an instruction. Queue, instruction reorder buffer, and physical rename registers. A shared resource allocation apparatus, comprising: a processor and a memory, wherein the memory stores program instructions, and the processor runs the program instructions to perform the following steps: Detecting a working state of the shared resource when the multi-threaded accesses the shared resource at the same time, and counting in the working state, the working state includes a first state in which the target thread is non-blocking to use the shared resource, and the target thread causes the sharing a second state in which the resource is blocked, and a third state in which the non-target thread causes the shared resource to be blocked; Reading the count value to obtain the number of basic clock cycles, the number of waiting clock cycles, and the number of interference clock cycles, wherein the number of basic clock cycles is a count value of the shared resource in the first state, the waiting clock cycle The number is a count value of the shared resource in the second state, and the number of the interference clock cycles is a count value of the shared resource in the third state; And adjusting, according to the basic clock cycle number, the number of the waiting clock cycles, and the number of the interference clock cycles, an allocation quota of the shared resources of the target thread.

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