WO2019005094A1

WO2019005094A1 - Low contact resistance thin film transistor

Info

Publication number: WO2019005094A1
Application number: PCT/US2017/040202
Authority: WO
Inventors: Gilbert Dewey; Van H. Le; Abhishek A. Sharma; Shriram SHIVARAMAN; Ravi Pillarisetty; Christopher J. Jezewski; Justin R. WEBER; Tahir Ghani; Jack T. Kavalieros
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03
Anticipated expiration: 2019-12-30

Abstract

Techniques are disclosed for forming thin film transistor integrated circuit structures that include a low band gap semiconductor material layer disposed between an oxide semiconductor layer and an electrode structure. Disposing a low band gap semiconductor material between the oxide semiconductor layer and the electrode structure reduces access resistance of the device. The low Eg semiconductor material layers provide higher charge carrier concentrations and mobilities in source and drain regions of the TFT than would otherwise be present in oxide semiconductor devices.

Description

LOW CONTACT RESISTANCE THIN FILM TRANSISTOR

BACKGROUND

Thin film transistors ("TFTs") can be used in a number of applications and are often used in conjunction with light emitting diodes (LEDs) and organic light emitting diodes (OLEDs). This is due, in part, because thin film transistors can be formed on a substrate that is not necessarily a semiconductor. For example, TFTs can be formed as a component of an LED or OLED display on an electrically insulating, optically transparent display screen (whether glass or polymer). TFTs can then be used to control the light emitting diodes that are used to form an image on the display screen. TFTs can also be fabricated, in part, from optically transparent semiconductor materials such as indium tantalum oxide ("ITO"). The use of these optically transparent materials can also facilitate their use in display technology because some or all of a transparent TFT can be coextensive with a display and not obscure the image that is displayed. Thin film transistors typically use an oxide semiconductor channel having wider band gaps compared to silicon transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FTG. 1 is a schematic cross-section of a traditional thin film transistor ("TFT") taken along a direction perpendicular to a gate of the TFT.

FIG. 2A is a method flow diagram depicting an example method for fabricating a thin film transistor that includes a low band gap semiconductor layer between an oxide semiconductor layer and an electrode, in accordance with an embodiment of the present disclosure.

FTG. 2B is a method flow diagram depicting another example method for fabricating a thin film transistor that includes a low band gap semiconductor layer between an oxide semiconductor layer and an electrode, in accordance with an embodiment of the present disclosure.

FIG. 2C is a method flow diagram depicting another example method for fabricating a thin film transistor that includes a low band gap semiconductor layer between an oxide semiconductor layer and an electrode, in accordance with an embodiment of the present disclosure.

FIGS. 3 A-3D are schematic cross-sections of a TFT progressively fabricated according to the method flow of FIG. 2 A taken along a direction parallel to a gate of the TFT, in accordance with an embodiment of the present disclosure.

FTGS. 3E-3H are schematic cross-sections of a TFT progressively fabricated according to the method flow of FIG. 2B taken along a direction parallel to a gate of the TFT, in accordance with an embodiment of the present disclosure.

FIGS. 3I-3L are schematic cross-sections of a TFT progressively fabricated according to the method flow of FIG. 2C taken along a direction parallel to a gate of the TFT, in accordance with an embodiment of the present disclosure. FIG. 4A is a method flow diagram depicting another example method for fabricating a thin film transistor that includes a low band gap semiconductor layer between an oxide semiconductor layer and an electrode, in accordance with an embodiment of the present disclosure.

FIG. 4B is a schematic cross-section of a TFT fabricated according to the method flow of FIG. 4A taken along a direction parallel to a gate of the TFT, in accordance with an embodiment of the present disclosure.

FIG. 5 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

The figures depict various embodiments of the present disclosure for purposes of illustration only. Numerous variations, configurations, and other embodiments will be apparent from the following detailed discussion. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real -world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for forming thin film transistor ("TFT") integrated circuit structures that include a low band gap ("low E_g ') semiconductor material layer disposed between an oxide semiconductor layer and an electrode. Disposing a low E_g semiconductor material between the oxide semiconductor layer and the electrode reduces the access resistance (R^) of the device as a whole, thus improving device performance. The intervening low E_g semiconductor material also provides a lower electrical contact resistance between the electrode and the oxide semiconductor layer. These improved electrical characteristics are accomplished because a low E_g semiconductor material layer provides higher charge carrier concentrations and mobilities in source and drain regions of the TFT than would otherwise be present in direct contact between an electrode and an oxide semiconductor layer.

Examples of oxide semiconductors that can be used in TFT devices of the present disclosure include, but are not limited to, indium gallium zinc oxide ("IGZO"), indium oxide, tin oxide (SnO), gallium oxide, zinc oxide (ZnO), titanium oxide (TiO), antimony oxide , and zinc oxide nitride ("ZON"). Examples of low E_g semiconductors of the present disclosure include, but are not limited to, indium arsenide (InAs), indium antimonide (InSb), indium arsenide antimonide (InAsSb), indium gallium arsenide (InGaAs), indium tin oxide ("ITO"), indium oxide ("10"), antimony oxide, indium antimonide (InSbOi), antimony oxide, among others. The low E_g semiconductors of the present disclosure can be single crystalline, polycrystalline, or amorphous.

The disclosed techniques may provide various advantages over traditionally fabricated and configured TFTs. For example, because of the improved device performance due to the lower ¾_Λ, TFTs of the present disclosure can be used within integrated circuits to perform more and different functions. This can allow transistors to be placed within interconnect layers of an integrated circuit rather than on a semiconducting substrate. This in turn increases transistor density and computing power per unit area of semiconducting substrate.

General Overview

As indicated above, a traditionally configured TFT, such as the one shown in FIG. 1, includes a substrate 104, an oxide semiconductor layer 108, a gate dielectric layer 112, source and drain electrodes 1 16A, 115B, a gate electrode 120 and spacers 124. The substrate 104 need not be a semiconductor material, unlike many other types of semiconductor devices. Rather, the substrate 104 can be any material, whether insulating (e.g., silicon dioxide), conductive (e.g., copper, aluminum), semiconducting (silicon, ΙΠ-V material), and combinations thereof (SOX). The oxide semiconductor 108 supplies the semiconducting component of the TFT, rather than the substrate 104, as would be the case in more common types of semiconducting devices. Gate spacers 124 are formed on sides of the gate electrode 120 and gate dielectric 112. Source and drain electrodes 1 16A, 116B are formed over a first portion and a second portion, respectively, of the oxide semiconductor 108. While exhibiting many benefits, the TFT 100 (and similarly configured TFTs) does have some disadvantages. For example, the oxide semiconductor 108 is typically an intrinsic semiconductor material with a high band gap (E_g ~ 2 electron Volts (eV) or higher). While the high band gap of the oxide semiconductor layer 1 08 material does make for an effective gate in the TFT 100 (a low off-state leakage device), this requires higher input currents and input voltages to cause current to flow through the device 100. Also, generally materials used for the oxide semiconductor 108 do not lend themselves to doping. Thus, it is difficult to produce local decreases in resistance within the oxide semiconductor layer 108 to form conductive source and drain regions. This inhibits the performance of the device because the access resistivity (R_ext) of an oxide semiconductor device is high (partly from lacking doped source and drain regions). For the same reason, the contact resistance between the oxide semiconductor 108 and the source electrode 1 16A and the drain electrode 116B is also high, again inhibiting device performance. This latter effect is sometimes referred to as having a high "spreading resistance."

Thus, techniques are disclosed herein that dispose a low band gap ("E_g") material (having an E_g of 2 eV, 1.5 eV or lower) between an oxide semiconductor layer and source and drain electrodes of an oxide semiconductor TFT. Disposing a low E_g material at this location lowers contact resistance between the source and drain regions of an oxide semiconductor TFT and its corresponding electrodes. Using a low E_g material as described herein can also lower R_ext, reduces spreading resistance, and otherwise improves oxide semiconductor TFT device performance. This improvement in performance increases a variety of applications in which oxide semiconductor TFTs can be applied. In some embodiments, the relatively low band gap material may be provisioned by grading a component of the oxide semiconductor layer to a higher concentration, thereby transitioning from a first relatively high band gap compound (attributable to the oxide semiconductor layer) to a second relatively lower band gap compound (attributable to a resistance reducing low band gap layer). In other embodiments, the oxide semiconductor layer and the low band gap layer are distinct and non-continuous layers. In such embodiments, grading is not necessarily needed, although it may be used for other reasons (e.g., lattice matching).

Methodology and Architecture FIG. 2A is a flow diagram of an example method 200 for fabricating a TFT device, in accordance with an embodiment of the present disclosure. The description of the method 200 is accompanied by concurrent descriptions of schematic cross-sections of corresponding example TFT structures. These cross-sections are depicted in FTGS. 3A to 3D and are taken in a direction parallel to the gate.

The method 200 begins by providing 204 a substrate 304, as shown in FIG. 3A. The substrate 304 can be, but need not be, a semiconductor material (e.g., silicon). Instead, because the substrate 304 functions primarily as a physical support for an oxide semiconductor layer 308, the substrate 304 can be fabricated from any material that can withstand the temperatures used to form the oxide semiconductor layer, as will be described below in more detail. In examples, the substrate 304 can be fabricated from any of a number of insulator materials or semi-insulator materials used for electrical insulation in an interconnect layer of an integrated circuit. These insulator materials include, for instance, nitrides (e.g., Si₃N₄), oxides (e.g., Si0₂, A1₂0_¾ AlSiO_x), oxynitrides (e.g., SiO_xN_y), carbides (e.g., SiC), oxycarbides, polymers, silanes, siloxanes, or other suitable insulator materials. In some embodiments, the substrate 304 is implemented with ultra-low-k insulator materials, low-k dielectric materials, or high-k dielectric materials depending on the application. Example low-k and ultra-low-k dielectric materials include porous silicon dioxide, carbon doped oxide (CDO), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, because the oxide semiconductor layer 308 can be formed using relatively low temperature processes (e.g., ALD), the oxide semiconductor 308 can be formed on any number of substrates 304, including substrates (a given layer's surface) provisioned in the back end interconnect structure.

In some examples, these substrate materials can be generically referred to as inter layer dielectric (ILD) because they may be used as an electrically insulating material within an interconnect layer of an integrated circuit. The ILD thus prevents or reduces the occurrence of electrical shorting and or electomigration of interconnect materials between metal features that connect successively larger numbers of transistors together.

Techniques for forming 204 the substrate 304 can be any of a wide range of suitable deposition techniques, including but not necessarily limited to: physical vapor deposition (PVD), chemical vapor deposition (CVD); spin coating/spin-on deposition (SOD); and/or a combination of any of the aforementioned. Other suitable configurations, materials, deposition techniques, and/or thicknesses for the substrate 304 will depend on a given application and will be apparent in light of this disclosure. The substrate 304 can be planarized in some examples so that subsequent deposition and/or patterning (e.g., photolithography and etch) processes can operate on a surface that is more uniform and flatter than the as-deposited surface. Planarization and/or polishing techniques include chemical-mechanical planarization (CMP) processes or other appropriate polishing/planarization processes as desired. As also shown in FIG. 3 A, an oxide semiconductor layer 308 is formed 208 on the substrate 304. As will be explained in more detail below, a center portion of the oxide semiconductor layer 308 (indicated in FIGS. 3 A-3D) corresponds to a channel region of an oxide semiconductor transistor (equivalently referred to as a thin film transistor of "TFT"). First and second portions of the oxide semiconductor layer 308 (also indicated in FIGS. 3A-3D) correspond to a source region and a drain region, respectively.

As will be appreciated in light of the present disclosure, oxide semiconductor-based transistors can be fabricated within interconnect layers, thus increasing transistor density within an integrated circuit. As mentioned above, this benefit is due to the processing temperatures of oxide semiconductor materials that are compatible with the processing temperatures used for an interconnect layer (in a "back end") of an integrated circuit, all of which are generally lower than the temperatures used for device layer (or "front end") processing. Examples of materials used for the oxide semiconductor 308 include indium gallium zinc oxide (IGZO) (whether low indium content or high indium content), indium oxide, indium tin oxide, titanium oxide, tin oxide, gallium oxide, zinc oxide, zinc oxide nitride, antimony oxide, among others.

The oxide semiconductor layer 308, which can be amorphous, single crystalline (or monocrystalline), or polycrystalline, is formed 208 by, for example, sputtering (also known as physical vapor deposition or PVD), plasma enhanced chemical vapor deposition (PECVD), epitaxial growth (for single crystal embodiments epitaxially matched to the substrate 304), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), among other deposition techniques. In the example of the method 200, the formation 208 of the oxide semiconductor layer 308 is that of a uniform layer over ( a blanket deposition process). In some example embodiments, a thickness of the oxide semiconductor layer 308 (shown as dimension a in FIGS. 3 A to 3F) can be within any of the following range: from 5 nm to 50 nm; from 5 nm to 25 nm; from 5 nm to 10 nm, from 25 nm to 50 nm; from 45 nm to 50 nm, from 10 nm to 25 nm. It will be noted that blanket deposition is not the only method for forming the oxide semiconductor layer 308. Alternative methods 228 and 256 are illustrated in FIG. 2B and FIG. 2C, and are accompanied by FIGS. 3E to 3H, and FIGS. 31 to 3L, respectively, all of which are described below.

As described above, the use of an oxide semiconductor layer 308 for a channel region within a transistor, particularly a transistor disposed within an interconnect layer of an integrated circuit, has a number of advantages. For example, because the oxide semiconductor 308 can be formed using relatively low temperature processes (e.g., ALD), the oxide semiconductor 308 can be formed on any number of substrates 204. Examples of substrates include, but are not limited to, interlayer dielectric materials within an interconnect layer of an integrated circuit. Conventional semiconductor device material layers (such as silicon) are not generally disposed within interconnect layers because the temperatures used to process (whether for deposition, dopant implantation, dopant anneal, etc.) semiconducting materials are much higher than those temperatures compatible with the materials (e.g., conductive metals) used in interconnect layers. This ease of deposition of oxide semiconductor 308 materials provides many of the benefits for oxide semiconductor TFTs described above. Another example advantage is that because many oxide semiconductors have a relatively large band gap E_g that is greater than silicon (i.e., a band gap of greater than 2 eV), devices that have an oxide semiconductor channel region have very low off- state leakage. For example, a silicon-based transistor may have an off state leakage current that is on the order of 1 x 10^"" amps. A similarly configured transistor using an oxide semiconductor layer 308 in place of silicon for a channel region may have an off state leakage current that is on the order of 1 x 10^'14 amps, 1 x 10^'20 amps, or lower. This low off state leakage is also enabled because materials used for the oxide semiconductor layer 308 (e.g., IGZO) have predominantly a single type of charge carrier (often electrons). For this reason, junction leakage is dramatically reduced or eliminated because the oxide semiconductor transistor can transmit a single type of charge carrier overwhelmingly in one current direction (corresponding to an "on" state). Current flow in the reverse direction in an off state, which would rely on the opposite charge carrier, is extremely low because of the extremely low concentration of oppositely charged carriers.

Another advantage of using an oxide semiconductor layer as a component in a transistor is that ranges of temperatures for formation 208 of the oxide semiconductor layer 308 are compatible with other back end processes (e.g., metal deposition for metal interconnects) and materials. For example, formation 208 of the oxide semiconductor layer 308 can, in some examples, take place from 20°C to a range of from 350°C to 450°C, or from 20°C to a range of from 400°C to 500°C. These temperatures are, in particular, achievable when forming the oxide semiconductor layer 308 as an amorphous layer. Formation of the oxide semiconductor layer 308 in a crystalline form will generally use processing temperatures at an upper end of the ranges indicated above compared to formation in an amorphous form, which will generally use processing temperatures at a lower end of the ranges indicated above.

Regardless, these formation 208 temperatures are sufficiently low that metal diffusion from metal interconnects is not activated during formation 208 of the oxide semiconductor layer 308. This in turn reduces the likelihood of electrical shorts (or other diffusion-induced or

electromigration defects) forming between metal interconnects. Furthermore, because transistors that use an oxide semiconductor layer 308 are generally not doped, high temperature diffusion anneals are not used to form source and drain regions within the oxide semiconductor layer 308. Because high temperature processing is avoided, so too is thermal damage to interconnects and other structures. As a result, oxide semiconductor devices can be formed in an interconnect layer of an integrated circuit, thus increasing transistor density per unit of substrate area of the integrated circuit as a whole.

Despite these many advantages, challenges remain for integrating oxide semiconductor materials within integrated circuits. For example, because oxide semiconductor materials generally have a high E_g (e.g., greater than 2 eV), they have a large Schottky barrier height with a corresponding electrically connected electrode. In other words, the difference in energy level between a Fermi level of the oxide semiconductor material and a Fermi level of the metallic material used for the contact is large enough to cause high contact resistance between them. This high contact resistance also causes high access resistance to the transistor as a whole. This is unlike the situation common for a metallic contact on an undoped semiconductor substrate material, like silicon or III-V materials, where the Schottky barrier height is about half of the E_g of the semiconductor material. To overcome the high Schottky barrier height described above, and thus broaden the applications in which oxide semiconductor devices can be used, embodiments of the present disclosure include a low E_E (e.g., a band gap of 2.0 eV or less, or 1.5 eV or less, or 1.0 eV or less) semiconductor layer 328 formed 212 on the oxide semiconductor layer 308. Tn this method 200, the low E_g semiconductor layer 328 is formed 212 as a blanket layer on the oxide semiconductor layer 308. Example techniques for forming 212 the blanket layer of the low E_g semiconductor layer 328 can include metalorganic vapor phase epitaxy (MOVPE), MOCVD, PVD, CVD, ALD, and molecular beam epitaxy (MBE). FIG. 3B illustrates a structure produced by this formation 212 process. Different methods of forming the low E_g semiconductor layer 328 are described in the contexts of method 228 (FIG. 2B), method 256 (FIG. 2C) and method 400 (FIG. 4A). As will be appreciated in light of this disclosure, while many figures depict layers 308 and 328 as two distinct non-continuous layers, note that layers 308 and 328 may effectively be portions of a single continuous graded layer having one or more components that are graded in concentration to tune the band gap of the continuous layer from a relatively high band gap to a relatively low band gap. For instance, the amount of indium can be graded. In general, the higher the concentration of indium in a given III-V compound, the lower the band gap of that compound. Other examples of graded layers will be apparent.

Example materials that can be used for the low E_g semiconductor layer 328 include indium arsenide, indium antimonide, indium arsenic antimonide, indium gallium arsenide, indium oxide, antimony oxide, indium titanium oxide, among others. Some materials (e.g., InSb, InAs) used for the low E_g semiconductor layer 328 may also pin a Fermi level near the conduction band of a metal contact on the E_g semiconductor layer 328. Regardless, the materials used for the low E_g semiconductor layer 328 generally have higher charge carrier mobilities and high charge carrier concentrations compared to the material used for the oxide semiconductor layer 308. Disposing the low E_g semiconductor layer 328 between the oxide semiconductor layer 308 and electrodes corresponding to source and drain electrodes reduces the contact resistance, spreading resistance, and R_cxt of the oxide semiconductor device.

Continuing with the method 200, the source electrode 312A and the drain electrode 312B are formed 216 on the low E_g semiconductor layer 328 as shown in FIG. 3C. The electrodes 312A and 312B can be formed 216 using any number of techniques, including patterning and formation techniques described above. These techniques can include photolithography of "soft" masks (such as photoactive polymers) that enable selective deposition of an electrode material. These techniques also include forming a hard mask of a dielectric material such as silicon dioxide or other dielectric material, etching channels or cavities within the dielectric material to expose a first portion and a second portion of the low E_g semiconductor layer 328, and forming an electrode material, thus placing the electrodes 312A, 312B in electrical contact with the low E_g semiconductor layer 328 Example materials used for the source electrode 3 12A and the drain electrode 312B include copper, aluminum, TiN, and TaN, among others. These materials can be formed 216 using CVD, PE CVD, sputtering, among other techniques. Note that the source electrode 312 A and the drain electrode 312B structures may include multiple layers or features, and need not be a single material or compound. Tn some embodiments, for instance, the source electrode 312A and the drain electrode 312B structures include liners and/or work function tuning layers. Continuing the description of the method 200, FIG. 3D illustrates removal 220 of a portion of the low Eg semiconductor layer 328 corresponding to a center portion of the oxide semiconductor layer 308 and formation 224 of a "gate stack" on the center portion of the oxide semiconductor layer 308. The center portion of the oxide semiconductor layer 308 that is exposed upon removal 220 of the low E_g semiconductor layer 328 corresponds to a channel region of the transistor. By removing 220 this portion of the low E_g semiconductor layer 328, a gate stack is able to control current flow from a source to a drain.

Removal 220 of a portion of the low E_g semiconductor layer 328 can be accomplished by etching using any patterning techniques including photolithography, "wet" etches (e.g., chemical etches), dry etches such as reactive ion etches (RTE), and combinations thereof. As shown in FIG. 3D, this has the effect of dividing the low E_g semiconductor layer 328 into a first low E_g semiconductor layer 328A between the first portion of the oxide semiconductor layer 308 and the source electrode 312A and a second low E_E semiconductor layer 328B between second portion of the oxide semiconductor layer 308 and the drain electrode 312B.

The method 200 continues with formation 224 of spacers 324, a gate dielectric layer 316, and a gate electrode 320 (collectively "the gate stack") on the center portion of the oxide semiconductor 308 exposed from the removal 220 of a corresponding portion of the low E_g semiconductor layer 328.

In the method 200, material used for the spacers 324 is formed 224 within the trench between the source electrode 312A and the drain electrode 12B as shown in FIG. 3C. When deposited, the material can either fill the trench or be conformally deposited in a layer on the exposed sidewalk of the source and drain electrodes 3 12A, 3 I2B and on the exposed center portion of the low E_g semiconductor layer 328. The material used for the spacers (also referred to as a barrier layer) can be formed of Si₃N₄, any of silicon oxide nitrides (SiQxNy), and Si0₂, among other materials. Deposition techniques include using any of the techniques described above in the context of formation of ELD. The as-formed barrier layer can be etched using a directional etch to form 224 spacers 324. Examples of directional etches that preferentially etch surfaces perpendicular to the direction of the etch, include, but are not limited to, dry etches such as reactive ion etches (RTE) using ozone, ionized argon, among others. The result of applying a directional etch to the barrier layer is removal of portions of the barrier layer except those in contact on side surfaces of the dummy gate, which are indicated as spacers 324 in FIG. 3D. In some examples, the spacers 324 can define a space within which a gate material can be formed without resorting to traditional patterning (e.g., photolithography) and can aid electrical insulation between source/drain electrodes and the gate electrode.

The gate dielectric layer 316 is formed 224 on the oxide semiconductor layer 308 to provide an electrically insulating layer between the gate and the oxide semiconductor layer 308. The gate dielectric layer 316 can be formed 224 using any of the materials and any of the processes and materials already described above in the context of providing 204 a substrate 304 using dielectric material. Example materials that can be used to form 224 the gate dielectric layer 316 include, but are not limited to, silicon oxide, lanthanum oxide, titanium oxide, tantalum silicon oxide, aluminum silicon oxide, aluminum oxide, in examples. Formation 224 of a gate electrode 320 can be accomplished by forming a conductor within the trench defined by the spacers 324 and the gate dielectric layer 316. The gate electrode 320 can be formed using any of the previously described deposition techniques include PVD, CVD, among others. Examples of materials used for the gate electrode 320 may include a wide range of materials, such as polysilicon, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), platinum, palladium, for example. These materials can be deposited by sputtering, chemical vapor deposition, pressure enhanced chemical vapor deposition, ALD, among other techniques.

FIG. 2B is a flow diagram of another example method 228 for fabricating a TFT device, in accordance with an embodiment of the present disclosure. The description of the method 228 is accompanied by concurrent descriptions of schematic cross-sections of corresponding example TFT structures. These cross-sections are depicted in FIGS. 3E to 3H and are taken in a direction parallel to the gate.

A benefit of the example method 228 is that it can produce a structure (shown in FIG. 3H) in which tip regions 330A and 330B are formed during formation of the low E_g semiconductor layers 328A and 328B. These tip regions 330A, 330B extend the low E_g semiconductor layers 328A and 328B below the spacers 324 so that the low E_g semiconductor material forming the layers 328A, 328B is closer to the channel region below the gate electrode 320. This configuration lowers the "spreading resistance" of a TFT of the present disclosure, thus improving transistor performance.

As shown in Fig. 3E, the method 228 begins by providing 204 a substrate 304, and forming 208 an oxide semiconductor layer 308 on the substrate 304, as described above in the context of the method 200. A layer of interlayer dielectric 310 is then formed 232 and planarized 232 using any of the previously described methods and materials. A portion of the ILD 310 corresponding to the center portion of the oxide semiconductor 308 is removed 236 (not shown), thus forming a gate stack trench. Removal 236 of this portion of the ILD can include using, for example, a directional (or "isotropic") etch (e.g., a reactive ion etch) so as to expose the center portion of the oxide semiconductor 308. In an alternative embodiment, other patterning techniques, such as using a photoactive polymer (e.g., a photoresist) can be used in place of the ILD 310.

Referring to FIG. 3F, a gate stack can be formed 244 in the gate stack trench. A material corresponding to the spacers 324 can be formed in the gate stack trench using any of the materials or processes described above. Then, using a direction etch, spacer material corresponding to a bottom of the gate stack trench is removed, thus exposing a center portion of the oxide semiconductor layer 308 and thus leaving the spacers 324. Examples of directional etches that preferentially etch surfaces perpendicular to the direction of the etch, include, but are not limited to, dry etches such as reactive ion etches (RIE) using ozone, ionized argon, among others. A gate dielectric layer 3 16 can then be formed which, in this method 228, includes conformal deposition (e.g., via ALD) on the exposed oxide semiconductor layer 308 and on the exposed surfaces of the spacers 324.

A gate electrode 320 can then be formed 240 on and within the conformally formed gate dielectric 316, thus completing the gate stack. Examples of materials used for the gate electrode 320 may include a wide range of materials, such as polysilicon, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), platinum, and palladium, for example. These materials can be deposited by sputtering, chemical vapor deposition, pressure enhanced chemical vapor deposition, ALD, among other techniques.

As shown in FIG. 3G, portions of the ILD 310 on either side of the gate stack can then be removed, thus exposing 248 the first and the second portions of the oxide semiconductor 308. In one embodiment, an anisotropic etch (such as a wet chemical etch using hydrofluoric acid or hydrochloric acid, or a high energy reactive ion etch) can be used to remove the portions of the ILD 310. An anisotropic etch can be used to remove some of the oxide semiconductor 308 so as to undercut the spacers 324. The low E_g semiconductor material layers 328A and 328B can then be formed, as described above, over the exposed first and second portions of the oxide semiconductor layer 308 and below at least a portion of the spacers 324, thus forming tip regions 330A and 330B. A benefit of these tip regions 330A and 330B is a reduction in resistance between the low E_g semiconductor layers 328A and 328B and the gate electrode 320 due to less intervening oxide semiconductor 308 material. A source electrode 3 12A and a drain electrode 312B can then be formed on low E_g semiconductor layers 328A and 328B, respectively.

As shown in FIGS. 3G and 3H, one embodiment includes a reduction in the thickness of the oxide semiconductor layer 308 from the dimension a (below the gate stack and protected from the anisotropic etch described above) to a dimension β less than the dimension a in the first and second portions of the oxide semiconductor layer. It will be appreciated that this need not be the case, and that some embodiments fabricated according to the method 228 include an oxide semiconductor layer 308 with a uniform thickness a and no tip regions 330A and 330B.

FIG. 2C is a flow diagram of another example method 256 for fabricating a TFT device, in accordance with an embodiment of the present disclosure. The description of the method 256 is accompanied by concurrent descriptions of schematic cross-sections of corresponding example TFT structures. These cross-sections are depicted in FIGS. 31 to 3L and are taken in a direction parallel to the gate.

The method 256 begins by providing 204 a substrate and forming 208 an oxide semiconductor layer on the substrate. Both of these elements, depicted in FIG. 31, have been described above in the context of the method 200 and need no further explanation. A dummy gate stack is formed 260 on a center portion of the oxide semiconductor layer 308. As shown in FIG. 3 J, the dummy gate stack includes a dummy gate electrode 334, a gate dielectric layer 316 and spacers 324. In an example, the gate dielectric layer 316 is formed, then the dummy gate electrode 336 is formed on the gate dielectric layer 316. A conformal layer of barrier material is then formed over both the dummy gate electrode 336 and gate dielectric layer 316. This conformal layer of barrier material layer is then etched with a directional etch. The resulting structure, shown in FIG. 3 J, includes the spacers 324.

As also shown in FIG. 3 J, low band gap layers 328A and 328B are then formed 264 on the first portion and the second portion of the oxide semiconductor layer 308. In an embodiment, an ILD layer 338 is formed on both of the low band gap layers 328A and 328B. As shown in FIG. 3K, the dummy gate electrode 334 is removed 268 using patterning techniques and chemistries described above, thus forming a gate electrode trench defined by the spacers 324 and the gate dielectric layer 3 16. As shown in FIG. 3L, the gate electrode 342 is then formed 272 in the gate electrode trench using any of the materials and processes described above, including the ability to "self-align" the gate electrode 342 formation between the spacers 324. The source electrode 312A and the drain electrode 312B are then formed 276 on the low band gap semiconductor layers over the first and second portions of the oxide semiconductor layer 308, as described above.

A method 400, which is a variation of the method 228, is shown in FIG. 4A. A corresponding cross section parallel to the direction of the gate is shown in FIG. 4B. The method 400 includes elements 204, 208, 232, 240, and 244 already described previously in the context of the method 228. However, unlike the method 228, only a portion of the ILD 310 corresponding to a via is removed, thus exposing less of the first portion and the second portion of the oxide semiconductor layer 308 than that illustrated in FIG. 3G of the method 228. This forms 404 source/drain electrode vias within these portions of the ILD 310. Low E_g semiconductor layers 416A and 416B are conformally formed 408 within these vias using any of the processes and materials described above for formation of the low E_g semiconductor material, such as ALD. Source and drain electrodes 420A, 420B are formed 412 within the confOrmally formed low E_g semiconductor material 416A, 416B, respectively.

It will be appreciated that the cross-sections shown in FIGS. 3 A to 3L and FIG. 4B include features depicted in a way that is convenient for explanation. The various structures are not necessarily drawn to scale, but rather the sizes of the features are selected for clarity of explanation and ease of depiction. For instance, the gate dielectric layer is relatively thin (e.g., 1.5 nm to 4 nm) compared to other layers, but is depicted thicker so that it can be labeled. Furthermore, the orientation of the various devices is depicted such that electrodes are disposed on one side of the oxide semiconductor layer. However, it will be appreciated that embodiments of the present disclosure can be configured such that one or more of the electrodes can be disposed between an oxide semiconductor layer and a substrate. For example, in addition to the configurations shown, the gate electrode alone can be disposed between the oxide semiconductor layer and the substrate with source and drain electrodes (and corresponding low E_g semiconductor layers) on an opposite side of the oxide semiconductor layer from the gate electrode. Tn another example, the source, drain, and gate electrodes (and source and drain low E_g semiconductor layers) are all between the oxide semiconductor layer and the substrate. In still another example, source and drain electrodes (and corresponding low E_g semiconductor layers) are disposed between the substrate and the oxide semiconductor layer and the gate electrode is on an opposite side of the oxide semiconductor layer from the source and drain electrodes. In a more general sense, in embodiments where a transistor structure is in an interconnect layer, the gate and source/drain contacts can be either side of the device (i.e., on the "bottom" or the "top"). In the figures provided, the structure is oriented so that connections are on the top. However, for some embodiments such as TFT configurations, there are advantages to having the gate contact on one side of the device (e.g., the bottom) and the S/D contacts on the opposite side of the device (e.g., the top). Numerous configurations and variations will be apparent in light of this disclosure, such as top gate and top source drain contacts, or bottom gate and top S D contacts, or top gate and bottom S/D contacts, or bottom gate and bottom S/D contacts. Analytical Techniques

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning transmission electron microscopy (SEM TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS), x-ray photoelectron spectroscopy (XPS); secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate the presence of a low Ε₈ material between one or more of a source and drain electrode and an oxide semiconductor layer (example compositions of which are indicated above) as an element of a transistor.

Example System

FIG. 5 is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 500 houses a motherboard 502. The motherboard 502 may include a number of components, including, but not limited to, a processor 504 and at least one communication chip 506, each of which can be physically and electrically coupled to the motherboard 502, or otherwise integrated therein. As will be appreciated, the motherboard 502 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 500, etc.

Depending on its applications, computing system 500 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 502. These other components may include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 500 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., to include a low E_g semiconductor layer, example compositions of which are indicated above, between a conductive electrode and an oxide semiconductor layer within a transistor or integrated circuit device). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 506 can be part of or otherwise integrated into the processor 504).

The communication chip 506 enables wireless communications for the transfer of data to and from the computing system 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. In some embodiments, communication chip 506 may include one or more transistor structures having a gate stack an access region polarization layer as variously described herein.

The processor 504 of the computing system 500 includes an integrated circuit die packaged within the processor 504. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 506 also may include an integrated circuit die packaged within the communication chip 506. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices as variously described herein. As will be appreciated in light of this disclosure, note that multi- standard wireless capability may be integrated directly into the processor 504 (e.g., where functionality of any chips 506 is integrated into processor 504, rather than having separate communication chips). Further note that processor 504 may be a chip set having such wireless capability. In short, any number of processor 504 and/or communication chips 506 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 500 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 includes a thin film transistor integrated circuit device comprising a first layer comprising an oxide semiconductor and having a first band gap of greater than 2 electron volts (eV), the first layer having a first portion, a second portion, and a center portion between the first portion and the second portion; a second layer comprising a semiconductor, the second layer on the first portion of the first layer, the second layer having a second band gap that is lower than the first band gap; a third layer comprising the semiconductor, the third layer on the second portion of the first layer, the third layer having the second band gap; and a gate stack on the center portion of the first layer, the gate stack comprising a gate dielectric layer, a gate electrode, and spacers. EKample 2 includes the subject matter of Example 1, and further includes a source electrode on at least some of the second layer and a drain electrode on at least some of the third layer.

Example 3 includes the subject matter of Example 1 or 2, wherein the oxide semiconductor of the first layer comprises an amorphous oxide semiconductor.

Example 4 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises indium, gallium, zinc, and oxygen.

Example 5 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises indium and oxygen.

Example 6 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises tin and oxygen.

Example 7 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises gallium and oxygen.

Example 8 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises zinc and oxygen.

Example 9 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises zinc, oxygen, and nitrogen.

Example 10 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises titanium and oxygen.

Example 11 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises indium, tin, and oxygen.

Example 12 includes the subject matter of any of Examples 1 to 3, wherein the oxide semiconductor of the first layer comprises antimony and oxygen.

Example 13 includes the subject matter of any of the preceding examples, wherein the band gap of the first layer is greater than 3 eV.

Example 14 includes the subject matter of any of the preceding examples, wherein the band gap of the first layer is greater than 4 eV.

Example 1 5 includes the subject matter of any of the preceding examples, wherein the band gap of the second and third layers is less than 1 ,5 eV.

Example 16 includes the subject matter of any of the preceding examples, wherein the band gap of the second and third layers is less than 1.0 eV.

Example 17 includes the subject matter of any of Examples 1 to 16, wherein the semiconductor of the second layer and the third layer comprises indium and arsenic.

Example 18 includes the subject matter of any of Examples 1 to 16, wherein the semiconductor of the second layer and the third layer comprises indium and antimony.

Example 19 includes the subject matter of any of Examples 1 to 16, wherein the semiconductor of the second layer and the third layer comprises indium, arsenic, and antimony.

Example 20 includes the subject matter of any of Examples 1 to 1 6, wherein the semiconductor of the second layer and the third layer comprises indium, gallium, and arsenic.

Example 21 includes the subject matter of any of Examples 1 to 16, wherein the semiconductor of the second layer and the third layer comprises indium, tin, and oxygen.

Example 22 includes the subject matter of any of Examples 1 to 1 6, wherein the semiconductor of the second layer and the third layer comprises indium and oxygen. Example 23 includes the subject matter of any of Examples 1 to 16, wherein the semiconductor of the second layer and the third layer comprises antimony and oxygen.

Example 24 includes the subject matter of any of Examples 1 to 16, wherein the semiconductor of the second layer and the third layer comprises indium, titanium and oxygen.

Example 25 includes the subject matter of any of Examples 4, 5, 11, 17 to 22, and 24, wherein each of the first layer, second layer, and third layer comprises indium, but the second and third layers have a greater concentration of indium than the first layer.

Example 26 includes the subject matter of Example 25, wherein the concentration of indium is graded such that the grading causes transition from the first band gap to the second band gap.

Example 27 includes the subject matter of any of the preceding examples, wherein the second layer and the third layer comprise a second tip region and a third tip region, respectively, and the second and third tip regions are disposed below spacers of the gate stack.

Example 28 includes the subject matter of any of the preceding examples, further comprising a substrate.

Example 29 includes the subject matter of Example 28, wherein the substrate comprises at least one of an insulator material or a semi-insulator material.

Example 30 includes the subject matter of Examples 28 or 29, wherein the substrate is an interlayer dielectric material in an interconnect layer of an integrated circuit device.

Example 31 includes a computing device comprising the thin film transistor integrated circuit device of any of Examples 1-30.

Example 32 includes a method for forming a thin film transistor device comprising forming a first layer comprising an oxide semiconductor on a substrate, the first layer having a first portion, a second portion, and a center portion between the first portion and the second portion, each of the first, second, and center portions having a first band gap of greater than 2 electron volts (eV); forming a second layer on at least a portion of the first layer, the second layer comprising a semiconductor, the second layer having a second band gap that is lower than the first band gap; forming a source electrode on the second layer corresponding to the first portion of the first layer; forming a drain electrode on the second layer corresponding to the second portion of the first layer; and forming a gate stack on the center portion of the first layer.

Example 33 includes the subject matter of Example 32, wherein the band gap of the first layer is greater than 3 eV.

Example 34 includes the subject matter of Example 32 or Example 33, wherein the band gap of the first layer is greater than 4.1 eV.

Example 35 includes the subject matter of any of Examples 32 to 34, wherein the band gap of the second layer is less than 1.5 eV.

Example 36 includes the subject matter of any of Examples 32 to 35, wherein the band gap of the second layer is less than 1.0 eV.

Example 37 includes the subject matter of any of Examples 32 to 36, wherein the second layer is conformally formed within a source electrode trench and a drain electrode trench, the trenches formed in an interlayer dielectric; the source electrode is formed within a first space defined by the conformally formed second layer within the source electrode trench; and the drain electrode is formed within a second space defined by the conformally formed second layer within the drain electrode trench.

Example 38 includes the subject matter of any of Examples 32 to 37, further comprising removing a portion of the second layer to expose the center portion of the first layer prior to forming the gate stack on the center portion.

Example 39 includes the subject matter of any of Examples 32 to 38, forming a dummy gate stack on the center portion of the first layer prior to forming the second layer, the dummy gate stack comprising a gate dielectric layer, spacers, and a dummy gate electrode; and wherein forming the gate stack comprises replacing the dummy gate electrode with a gate electrode.

Claims

What is claimed is:

1. An thin film transistor integrated circuit device comprising:

a first layer comprising an oxide semiconductor and having a first band gap of greater than 2 electron volts (eV), the first layer having a first portion, a second portion, and a center portion between the first portion and the second portion;

a second layer comprising a semiconductor, the second layer on the first portion of the first layer, the second layer having a second band gap that is lower than the first band gap;

a third layer comprising the semiconductor, the third layer on the second portion of the first layer, the third layer having the second band gap; and

a gate stack on the center portion of the first layer, the gate stack comprising a gate dielectric layer, a gate electrode, and spacers.

2. The thin film transistor integrated circuit device of claim 1, further comprising a source electrode on at least some of the second layer and a drain electrode on at least some of the third layer.

3. The thin film transistor integrated circuit device of claim 1 , wherein the oxide semiconductor of the first layer comprises an amorphous oxide semiconductor.

4. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises indium, gallium, zinc, and oxygen.

5. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises indium and oxygen.

6. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises tin and oxygen.

7. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises gallium and oxygen.

8. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises zinc and oxygen,

9. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises zinc, oxygen, and nitrogen.

10. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises titanium and oxygen.

1 1. The thin film transistor integrated circuit device of claim 1 , wherein the oxide semiconductor of the first layer comprises indium, tin, and oxygen.

12. The thin film transistor integrated circuit device of claim 1, wherein the oxide semiconductor of the first layer comprises antimony and oxygen.

13. The thin film transistor integrated circuit device of claim 1, wherein the band gap of the first l yer is greater than 3 eV.

14. The thin film transistor integrated circuit device of claim 1, wherein the band gap of the second and third layers is less than 1.5 eV.

15. The thin film transistor integrated circuit device of claim 1 , wherein the semiconductor of the second layer and the third layer comprises indium and arsenic.

16. The thin film transistor integrated circuit device of claim 1, wherein the semiconductor of the second layer and the third layer comprises indium and antimony.

17. The thin film transistor integrated circuit device of claim 1, wherein the semiconductor of the second layer and the third layer comprises indium, arsenic, and antimony.

18. The thin film transistor integrated circuit device of claim 1, wherein the semiconductor of the second layer and the third layer comprises indium, gallium, and arsenic.

19. The thin film transistor integrated circuit device of claim 1, wherein the semiconductor of the second layer and the third layer comprises indium, tin, and oxygen.

20. The thin film transistor integrated circuit device of claim 1 , wherein the semiconductor of the second layer and the third layer comprises indium and oxygen.

21. The thin film transistor integrated circuit device of claim 1 , wherein the semiconductor of the second layer and the third layer comprises antimony and oxygen,

22. The thin film transistor integrated circuit device of claim 1, wherein the semiconductor of the second layer and the third layer comprises indium, titanium and oxygen.

23. The thin film transistor integrated circuit device of claim 28, further comprising a substrate comprising at least one of an insulator material or a semi-insulator material.

24. The thin film transistor integrated circuit device of claim 23, wherein the substrate is an interlayer dielectric material in an interconnect layer of an integrated circuit device.

25. A computing device comprising the thin film transistor integrated circuit device of any of claims 1-24.