WO2018235360A1 - Imaging device - Google Patents

Abstract

The imaging device (1) includes a read signal generation circuit (20) and a reset signal generation circuit (30), while the read signal generation circuit (20) reads out the charge accumulated in the photodiode (PD). The reset signal generation circuit (30) is a photodiode (a row of pixels (PX1_ij) that is different from the row of the pixels (PX1_ij) whose charge is being read out by the readout signal generation circuit (20). Remove the charge remaining on PD.

Description

Imaging device

The present invention relates to an imaging device.

A CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device is roughly classified into an APS (Active Pixel Sensor) method and a PPS (Passive Pixel Sensor) method. In the medical or nondestructive inspection X-ray imaging apparatus, the PPS imaging system is often adopted because the circuit structure is simple.

The imaging device has an imaging unit in which a plurality of pixels are arranged two-dimensionally. In the PPS method, one pixel is provided with a photoelectric conversion unit and a switch for controlling conduction / non-conduction between the photoelectric conversion unit and a readout line. Moreover, in the PPS method, one pixel is connected to each readout line provided for each column of pixels.

The charge stored in the photodiode (photoelectric conversion element) of each pixel is read row by row, and when the read switch of the selected row is turned on, the charge stored in the photodiode of the pixel of the selected row Are supplied to the readout unit of the imaging device via the readout line. The charge stored in the photodiode of the pixel is removed by supplying the charge to the readout unit of the imaging device.

However, when the readout time is short, charge may remain in the photodiode of the pixel. If the charge remains in the photodiode, the imaging device can not display an accurate image because the remaining charge is read out at the next reading.

Further, depending on the type of photodiode included in the imaging device, generation of charge may continue for a while after the irradiation of light to the imaging unit is finished. In this case, even if the charge is supplied to the reading unit of the imaging device, there is a problem that erroneous detection is performed when the light is irradiated to the pixel that should be detected as dark.

In order to solve this problem, for example, the photoelectric conversion device disclosed in Patent Document 1 includes a read control unit that reads out the charge stored in the charge storage unit that stores light as a charge. Further, the photoelectric conversion device disclosed in Patent Document 1 includes a reset unit which is connected to the read signal line and discharges the charge remaining in the charge storage unit in units of the read signal line.

Further, in the solid-state imaging device disclosed in Patent Document 2, after the charge remaining in the photodiode is removed by the pixel reset switch, the photoelectrically converted charge is accumulated in the photodiode, and the charge accumulated in the photodiode is read out.

Japanese Patent Publication "Japanese Unexamined Patent Publication No. 2010-011033 (published on January 14, 2010)" Japanese Patent Publication "Japanese Patent Application Publication No. 2003-298942 (October 17, 2003)"

In the photoelectric conversion device disclosed in Patent Document 1 and the solid-state imaging device disclosed in Patent Document 2, a process for removing the charge remaining in the photodiode is required before the charge readout process, There is a problem that the charge readout process can not be performed at high speed.

An object of one embodiment of the present invention is to realize high-speed charge reading processing.

In order to solve the above-mentioned subject, an imaging device concerning one mode of the present invention is the imaging device by which a plurality of pixels including a photoelectric conversion element which stores electric charge according to the quantity of light were arranged two-dimensionally. A readout circuit for reading out the charge accumulated in the photoelectric conversion element by outputting a readout signal for each row of the pixels to a readout control line connected to the pixel, and a reset control line connected to the pixel And a reset circuit for removing charges remaining in the photoelectric conversion element by outputting a reset signal for each row, and the reset circuit while the readout circuit reads out the charge accumulated in the photoelectric conversion element. The row of the pixels different from the row of the pixels for which readout of the charge accumulated in the photoelectric conversion element is performed by the readout circuit; Removing the charges remaining in the serial photoelectric conversion element.

According to one embodiment of the present invention, the effect of being able to perform charge readout processing at high speed is achieved.

(A) is a block diagram which shows a structure of the imaging device based on Embodiment 1 of this invention, (b) is a circuit diagram which shows the internal structure of the pixel shown to (a). (A) is a block diagram which shows an example of a structure of the imaging device shown in FIG. 1, (b) is a circuit diagram which shows the internal structure of the pixel shown to (a). It is a figure which shows an example of a switch operation of the imaging device shown in FIG. It is a figure which shows another example of switch operation of the imaging device shown in FIG. It is a timing chart which shows the signal waveform of the reset control line of an imaging device shown in FIG. 1, and a read-out control line. 5 is a timing chart showing other signal waveforms of a reset control line and a read control line of the imaging device shown in FIG. (A) is a figure which shows the electric potential of PD in case the residual electric charge is not removed, an integrator output, and the signal waveform of a read-out signal, (b) is an electric potential of PD when the residual electric charge is removed, It is a figure which shows an integrator output and the signal waveform of a read-out signal and a reset signal. It is a timing chart which shows the signal waveform of the reset control line of an imaging device concerning Embodiment 2 of the present invention, and a reading control line. It is a timing chart which shows the signal waveform of the reset control line of an imaging device concerning Embodiment 3 of the present invention, and a reading control line. (A) is an example of the block diagram which shows the structure of the imaging device which concerns on Embodiment 4 of this invention, (b) is a circuit diagram which shows the internal structure of the pixel shown to (a). It is an example of a block diagram showing composition of an imaging device concerning Embodiment 6 of the present invention. It is an example of the block diagram which shows the other structure of the imaging device which concerns on Embodiment 6 of this invention.

Embodiment 1
The embodiment of the present invention is described below with reference to FIGS. 1 to 7. FIG. 1A is a block diagram showing the configuration of the imaging device 1 according to Embodiment 1 of the present invention, and FIG. 1B is a circuit showing the internal structure of the pixel PX1_ij shown in FIG. FIG.

(Configuration of imaging device 1)
As shown in FIG. 1A, the imaging device 1 has a structure in which a plurality of pixels PX1_ij (i and j are integers of 1 or more and 5 or less) are two-dimensionally arranged, and includes integrators I_1 to I_5. ing. The imaging device 1 further includes a control circuit 10, a read signal generation circuit 20 (read out circuit), a reset signal generation circuit 30 (reset circuit), a bias power supply 40, a read power supply 50, and a reset power supply 60. The imaging device 1 captures an image according to the amount of light that has been irradiated to a subject. In addition, the imaging device 1 may be a radiation detector that detects a dose of incident radiation, a photoelectric conversion panel that converts incident light into electric power, or an X-ray detector that detects a dose of incident X-rays. .

Here, in a region where a plurality of pixels PX1_ij shown in (a) of FIG. 1 are arranged, the first column from the left, the second column, the third column, the fourth column, and the fifth column are used. The second line, the third line, the fourth line, and the fifth line. The first to fifth lines indicate that i is 1 to 5, and the first to fifth columns indicate that j is 1 to 5, respectively. For example, the pixel PX1_ij corresponding to the first row and the fourth column is described as a pixel PX1_14, and the pixel PX1_ij corresponding to the third row and the fifth column is described as a pixel PX1_35.

The internal structure of the pixel PX1_ij will be described based on FIG. 1 (b). Here, the pixel PX1_11 is selected from the plurality of pixels PX1_ij and described. That is, (b) of FIG. 1 is a circuit diagram showing an internal structure of the pixel PX1_11. The other pixels PX1_ij also have the same structure as the pixels PX1_11. As shown in FIG. 1B, the pixel PX1_11 is provided with a photodiode PD (photoelectric conversion element), a reset switch SW10, and a read switch SW20. Further, the reset control line CL10_1, the read control line CL20_1, the PD bias line PDBL_1, the bias line BL_1, and the read line RL_1 pass through the pixel PX1_11.

Here, it is assumed that the reset switch SW10 and the readout switch SW20 have a first terminal, a second terminal, and a third terminal. The first terminal of the reset switch SW10 is connected to the bias line BL_1, and the second terminal of the reset switch SW10 is connected to the cathode electrode of the photodiode PD and the first terminal of the readout switch SW20. The second terminal of the read switch SW20 is connected to the read line RL_1. The anode electrode of the photodiode PD is connected to the PD bias line PDBL_1. The third terminal of the reset switch SW10 is connected to the reset control line CL10_1, and the reset switch SW10 is controlled to be ON / OFF by a reset signal supplied from the reset control line CL10_1. The third terminal of the read switch SW20 is connected to the read control line CL20_1, and the read switch SW20 is controlled to be ON / OFF by a read signal supplied from the read control line CL20_1. The photodiode PD is not limited to the use of a photodiode, and any other photoelectric conversion element may be used. The photodiode PD includes a capacitance, and accumulates a charge according to the amount of incident light.

Reset control lines CL10_1 to CL10_5, read control lines CL20_1 to CL20_5, and PD bias lines PDBL_1 to PDBL_5 are provided in each row of the pixels PX1_ij. Bias lines BL_1 to BL_5 and readout lines RL_1 to RL_5 are provided in each column of the pixels PX1_ij.

The control circuit 10 instructs the read signal generation circuit 20 to supply the read signal, and instructs the reset signal generation circuit 30 to supply the reset signal.

The read signal generation circuit 20 supplies a read signal for each row of the pixels PX1_ij via the read control lines CL20_1 to CL20_5. Therefore, the readout switch SW20 provided in the pixels PX1_11 to PX1_15, which are the five pixels PX1_ij belonging to the same row, is controlled by the readout signal supplied via the readout control line CL20_1.

The readout switches SW20 provided in the pixels PX1_21 to PX1_25 are controlled by a readout signal supplied via the readout control line CL20_2. The readout switches SW20 provided in the pixels PX1_3 1 to PX1_35 are controlled by the readout signal supplied via the readout control line CL20_3. The readout switch SW20 provided in the pixel PX1_41 to the pixel PX1_45 is controlled by the readout signal supplied via the readout control line CL20_4. The readout switches SW20 provided in the pixels PX1_51 to PX1_55 are controlled by the readout signal supplied via the readout control line CL20_5. The read switch SW20 is a switching element.

The reset signal generation circuit 30 supplies a reset signal for each row of the pixels PX1_ij through the reset control lines CL10_1 to CL10_5. Therefore, the reset switches SW10 provided in the pixels PX1_11 to PX1_15, which are five pixels PX1_ij belonging to the same row, are controlled by the reset signal supplied via the reset control line CL10_1. The reset switch SW10 is a switching element.

The reset switches SW10 provided in the pixels PX1_21 to PX1_25 are controlled by a reset signal supplied via the reset control line CL10_2. The reset switches SW10 provided in the pixels PX1_3 1 to PX1_35 are controlled by a reset signal supplied via the reset control line CL10_3. The reset switches SW10 provided to the pixels PX1_41 to PX1_45 are controlled by a reset signal supplied via the reset control line CL10_4. The reset switch SW10 provided in the pixel PX1_51 to the pixel PX1_55 is controlled by a reset signal supplied via the reset control line CL10_5.

The bias power supply 40 applies a predetermined bias potential to the anode electrode of the photodiode PD via the PD bias lines PDBL_1 to PDBL_5.

The read power supply 50 applies a predetermined potential to the second terminal of the read switch SW20 and the negative terminals of the operational amplifiers O_1 to O_5 via the read lines RL_1 to RL_5.

The reset power supply 60 applies a reset potential to the first terminal of the reset switch SW10 and the positive terminals of the operational amplifiers O_1 to O_5 via the bias lines BL_1 to BL_5.

The integrators I_1 to I_5 are connected to the read lines RL_1 to RL_5, respectively. The integrators I_1 to I_5 respectively include operational amplifiers O_1 to O_5 and capacitors C_1 to C_5. For example, the integrator I_1 includes an operational amplifier O_1 and a capacitor C_1, and the integrator I_2 includes an operational amplifier O_2 and a capacitor C_2. Other integrators also have op amps and capacitances as well. The integrators I_1 to I_5 have a configuration in which the potential to be output is determined by virtual short at the time of charge readout.

As shown in (a) and (b) of FIG. 2, the reset transistor TFT10 may be used as the reset switch SW10, and the readout transistor TFT20 may be used as the readout switch SW20. FIG. 2A is a block diagram showing an example of the configuration of the imaging device 1, and FIG. 2B is a circuit diagram showing the internal structure of the pixel PX1_ij shown in FIG.

(Operation of imaging device 1)
Next, the operation of the imaging device 1 will be described based on FIG. FIG. 3 is a diagram showing an example of the switch operation of the imaging device 1. For example, it is assumed that the read signal generation circuit 20 reads out the charge accumulated in the photodiode PD of the fourth row (pixel PX1_41 to pixel PX1_45) of the pixel PX1_ij. In this case, as shown in FIG. 3, the read signal generation circuit 20 supplies a read signal to the read switch SW20 in the fourth row of the pixel PX1_ij via the read control line CL20_4. The readout switch SW20 in the fourth row of the pixel PX1_ij is turned ON when the readout signal is supplied from the readout signal generation circuit 20. When the readout switch SW20 in the fourth row of the pixel PX1_ij is turned on, the charge accumulated in the photodiode PD is read out through the readout switch SW20, readout lines RL_1 to RL_5, and integrators I_1 to I_5. For example, the charge accumulated in the photodiode PD provided in the pixel PX1_41 is read out via the read switch SW20, the read line RL_1, and the integrator I_1. Therefore, the read signal generation circuit 20 reads the charge accumulated in the photodiode PD in the fourth row of the pixel PX1_ij by supplying a read signal to the read control line CL20_4.

While the read out signal generation circuit 20 reads out the charge accumulated in the photodiode PD in the fourth row of the pixel PX1_ij, the reset switch SW10 in the fourth row of the pixel PX1_ij is in the OFF state. The readout switch SW20 in the first, second, third, and fifth rows of the pixel PX1_ij is in the OFF state.

While the read out signal generation circuit 20 reads out the charge accumulated in the photodiode PD in the fourth row of the pixel PX1_ij, the reset signal generation circuit 30 remains in the photodiode PD in the second and third rows of the pixel PX1_ij. Remove the charge. Specifically, as shown in FIG. 3, the reset signal generation circuit 30 supplies a reset signal to the reset switch SW10 in the second and third rows of the pixel PX1_ij via the reset control lines CL10_2 and CL10_3. The reset switch SW10 in the second and third rows of the pixel PX1_ij is turned on when a reset signal is supplied from the reset signal generation circuit 30. When the reset switch SW10 in the second and third rows of the pixel PX1_ij is turned on, the charge remaining in the photodiode PD is removed via the reset switch SW10 and the bias lines BL_1 to BL_5. For example, the charge remaining in the photodiode PD provided in the pixel PX1_21 is removed via the reset switch SW10 and the bias line BL_1. Therefore, the reset signal generation circuit 30 removes the charges remaining in the photodiodes PD in the second and third rows of the pixel PX1_ij by supplying a reset signal to the reset control lines CL10_2 and CL10_3.

While the reset signal generation circuit 30 removes the charge remaining in the photodiode PD in the second and third rows of the pixel PX1_ij, the readout switch SW20 in the second and third rows of the pixel PX1_ij is in the OFF state. It is. The reset switch SW10 in the first, fourth, and fifth rows of the pixel PX1_ij is in the OFF state.

Also, while the read signal generation circuit 20 reads the charge stored in the photodiode PD in the fourth row of the pixel PX1_ij, the reset switch SW10 and the read switch SW20 in the first and fifth rows of the pixel PX1_ij are in the OFF state. It is. As a result, charges are accumulated in the photodiodes PD in the first and fifth rows of the pixel PX1_ij in accordance with the amount of incident light. That is, the first and fifth rows of the pixel PX1_ij are in a state in which charge is accumulated in the photodiode PD according to the amount of incident light.

Further, when the processing for reading out the charge accumulated in the photodiode PD in the fourth row of the pixel PX1_ij and the processing for removing the charge remaining in the photodiode PD in the second and third rows of the pixel PX1_ij are completed, The following processing is performed. Specifically, the read signal generation circuit 20 reads the charge stored in the photodiode PD of the fifth row (the pixel PX1_51 to the pixel PX1_55) of the pixel PX1_ij. As shown in FIG. 4, the read signal generation circuit 20 supplies a read signal to the read switch SW20 in the fifth row of the pixel PX1_ij via the read control line CL20_5. FIG. 4 is a view showing another example of the switch operation of the imaging device 1. The readout switch SW20 in the fifth row of the pixel PX1_ij is turned ON when a readout signal is supplied from the readout signal generation circuit 20. When the readout switch SW20 in the fifth row of the pixel PX1_ij is turned on, the charges accumulated in the photodiode PD are read out through the readout switch SW20, readout lines RL_1 to RL_5, and integrators I_1 to I_5. For example, the charge accumulated in the photodiode PD provided in the pixel PX1_51 is read out via the read switch SW20, the read line RL_1, and the integrator I_1. Therefore, the read signal generation circuit 20 reads the charge accumulated in the photodiode PD in the fifth row of the pixel PX1_ij by supplying a read signal to the read control line CL20_5.

The reset switch SW10 in the fifth row of the pixel PX1_ij is in the OFF state while the read signal generation circuit 20 reads the charge accumulated in the photodiode PD in the fifth row of the pixel PX1_ij. Further, the readout switch SW20 in the first to fourth rows of the pixel PX1_ij is in the OFF state.

While the read signal generation circuit 20 reads the charge accumulated in the photodiode PD in the fifth row of the pixel PX1_ij, the reset signal generation circuit 30 remains in the photodiode PD in the third and fourth rows of the pixel PX1_ij. Remove the charge. Specifically, as shown in FIG. 4, the reset signal generation circuit 30 supplies a reset signal to the reset switch SW10 in the third and fourth rows of the pixel PX1_ij via the reset control lines CL10_3 and CL10_4. When the reset signal is supplied from the reset signal generation circuit 30, the reset switch SW10 in the third and fourth rows of the pixel PX1_ij is turned ON. When the reset switch SW10 in the third and fourth rows of the pixel PX1_ij is turned on, the charge remaining in the photodiode PD is removed via the reset switch SW10 and the bias lines BL_1 to BL_5. For example, the charge remaining in the photodiode PD provided in the pixel PX1_31 is removed via the reset switch SW10 and the bias line BL_3. Therefore, the reset signal generation circuit 30 removes the charges remaining in the photodiodes PD in the third and fourth rows of the pixel PX1_ij by supplying a reset signal to the reset control lines CL10_3 and CL10_4.

While the reset signal generation circuit 30 removes the charge remaining on the photodiode PD in the third and fourth rows of the pixel PX1_ij, the readout switch SW20 in the third and fourth rows of the pixel PX1_ij is in the OFF state. It is. The reset switch SW10 in the first, second, and fifth rows of the pixel PX1_ij is in the OFF state.

Also, while the read signal generation circuit 20 reads the charge stored in the photodiode PD in the fifth row of the pixel PX1_ij, the reset switch SW10 and the read switch SW20 in the first and second rows of the pixel PX1_ij are in the OFF state. It is. As a result, charges are accumulated in the photodiodes PD in the first row and the second row of the pixel PX1_ij in accordance with the amount of incident light. That is, the first and second rows of the pixel PX1_ij are in a state where charge is accumulated in the photodiode PD in accordance with the amount of incident light.

In addition, in the imaging device 1, the time for which the reset signal generation circuit 30 removes the charge remaining in the photodiode PD is twice the time for the read signal generation circuit 20 to read out the charge accumulated in the photodiode PD. This is because charge readout is performed on two rows of pixels PX1_ij, while removal of remaining charge is performed on one row of pixels PX1_ij. Therefore, the time taken for the reset signal generation circuit 30 to remove the charge remaining in the photodiode PD is longer than the time taken for the read signal generation circuit 20 to read the charge accumulated in the photodiode PD.

The timing at which the read signal and the reset signal are output in the imaging device 1 is represented by a timing chart as shown in FIG. FIG. 5 is a timing chart showing signal waveforms of the reset control line and the read control line of the imaging device 1. Specifically, for example, a read signal is supplied to the read control line CL20_1, and the charge accumulated in the photodiode PD in the first row of the pixel PX1_ij is read. After that, a reset signal is supplied to the reset control line CL10_1, and the charge remaining in the photodiode PD in the first row of the pixel PX1_ij is removed. At the same time as a reset signal is supplied to the reset control line CL10_1, a read signal is supplied to the read control line CL20_2, and the charge accumulated in the photodiode PD in the second row of the pixel PX1_ij is read out. After that, a reset signal is supplied to the reset control line CL10_2, and the charge remaining on the photodiode PD in the second row of the pixel PX1_ij is removed. At the same time as a reset signal is supplied to the reset control line CL10_2, a read signal is supplied to the read control line CL20_3, and the charge accumulated in the photodiode PD in the third row of the pixel PX1_ij is read out. The timing at which the supply of the reset signal to the reset control line CL10_1 ends is the same as the timing at which the supply of the read signal to the read control line CL20_3 ends. The subsequent processing is performed in the same manner. The process in the case of FIG. 3 described above corresponds to the process performed at time t1 and time t3, and the process in the case of FIG. 4 corresponds to the process performed at time t2 and time t4.

In the case of FIG. 5, the removal time of the charge remaining in the photodiode PD was twice as long as the charge readout time. However, as shown in FIG. 6, the time for removing the charge remaining in the photodiode PD does not necessarily have to be twice the time for reading out the charge, and may be set to a predetermined time. FIG. 6 is a timing chart showing other signal waveforms of the reset control line and the readout control line of the imaging device 1.

In the imaging device 1, while charge readout is performed on one row of the pixels PX1 _ij, charge removal is performed on the other rows of the pixels PX1 _ij. Therefore, the imaging time in the imaging device 1 is not significantly increased. The charge readout process can be performed at high speed. Further, in the imaging device 1, since the charge remaining in the photodiode PD is removed, it is possible to prevent an afterimage from appearing in a captured image.

Further, in this case, the row of the pixels PX1 _ij from which the charge is read out is adjacent to the row of the pixels PX1 _ij from which the charge removal is performed. However, the row of the pixels PX1_ij from which the charge is read and the row of the pixels PX1_ij from which the charge is removed need not necessarily be adjacent to each other.

(About the output result of the imaging device 1)
Next, the output result of the imaging device 1 will be described based on FIG. (A) of FIG. 7 is a figure which shows the electric potential of PD in case the residual electric charge is not removed, an integrator output, and the signal waveform of a read-out signal. (B) of FIG. 7 is a diagram showing the electric potential of the PD, the integrator output, and the signal waveforms of the read signal and the reset signal when the remaining charge is removed. The rightward direction in (a) and (b) of FIG. 7 is time.

Even if the same amount of light is incident on the photodiode PD of the pixel PX1_ij at different times, the same charge should be read out from the pixel PX1_ij. However, if the charge remaining in the photodiode PD is not removed, the same charge may not be read out. If the charge remaining in the photodiode PD is not removed, the charge remains in the photodiode PD after the charge readout process is completed. When charge remains in the photodiode PD, as shown in FIG. 7A, the potential of the photodiode PD and the output of the integrator change with time. Specifically, for example, even if the same amount of light is incident on the photodiode PD of the pixel PX1_11, the output of the integrator I_1 in the pixel PX1_11 increases with time (a large amount of charge is read) Become). In addition, as time passes, the potential of the photodiode PD increases. Since the charge remaining in the photodiode PD is read out at the time of the next reading, the influence of the charge remaining in the photodiode PD appears as an afterimage in the captured image captured by the imaging device 1.

Therefore, in each pixel PX1 _ij of the imaging device 1, processing is performed in the order of charge accumulation, charge readout, and removal of the charge remaining in the photodiode PD, and then the process is performed again from charge accumulation.

As shown in (b) of FIG. 7, even if the reset signal generation circuit 30 supplies a reset signal after the read signal generation circuit 20 supplies a read signal, even if charge remains in the photodiode PD. The charge remaining on the photodiode PD is removed. Therefore, for example, when the same amount of light is incident on the photodiode PD of the pixel PX1_11, the output of the integrator I_1 does not change even if time passes in the pixel PX1_11 (the amount of charge read does not change) ). Therefore, it is possible to prevent the influence of the charge remaining in the photodiode PD from appearing as an afterimage in the captured image captured by the imaging device 1.

Second Embodiment
Another embodiment of the present invention will be described below with reference to FIG. In addition, about the member which has the same function as the member demonstrated in the said embodiment for convenience of explanation, the same code | symbol is appended and the description is abbreviate | omitted. FIG. 8 is a timing chart showing signal waveforms of the reset control line and the read control line of the imaging device according to the second embodiment of the present invention.

As shown in FIG. 8, for example, after a read signal is supplied to the read control line CL20_1 and charges accumulated in the photodiode PD in the first row of the pixels PX1 _ij are read, a pulse is applied to the reset control line CL10_1. A reset signal may be provided. That is, a plurality of pulsed reset signals (eight pulsed reset signals in FIG. 8) may be supplied to the reset control line CL10_1. Supplying a pulse-like reset signal as shown in FIG. 8 to reset control line CL10_1 is easier to realize than supplying a reset signal as shown in FIG. 6 to reset control line CL10_1. It is possible. Therefore, by setting the signal supplied to the reset control line CL10_1 to be a pulse-like reset signal, it is possible to more easily realize an imaging device that performs charge readout processing at high speed.

Third Embodiment
Another embodiment of the present invention is described below with reference to FIG. In addition, about the member which has the same function as the member demonstrated in the said embodiment for convenience of explanation, the same code | symbol is appended and the description is abbreviate | omitted. FIG. 9 is a timing chart showing signal waveforms of the reset control line and the read control line of the imaging device according to the third embodiment of the present invention.

When the processing speed for reading out the charge accumulated in the photodiode PD is increased, the charge may be read out simultaneously for a plurality of rows of the pixel PX1_ij. For example, in the case where charge is read out simultaneously for two rows of pixels PX1_ij, the process shown in FIG. 9 is performed. Specifically, the read signal is simultaneously supplied to the read control line CL20_1 and the read control line CL20_2. Thus, the charges accumulated in the photodiodes PD in the first and second rows of the pixels PX1_ij are simultaneously read out.

After that, the reset signal is simultaneously supplied to the reset control line CL10_1 and the reset control line CL10_2. As a result, the charges remaining on the photodiodes PD in the first and second rows of the pixels PX1_ij are removed. At the same time as the reset signal is supplied to the reset control line CL10_1 and the reset control line CL10_2, the read signal is simultaneously supplied to the read control line CL20_3 and the read control line CL20_4. Thereby, the charges accumulated in the photodiodes PD in the third and fourth rows of the pixel PX1_ij are simultaneously read out. The subsequent processing is performed in the same manner.

Note that when charge reading is simultaneously performed on a plurality of rows of the pixel PX1_ij, it is not possible to know which row the read charge is the charge read from the photodiode PD. For example, it is assumed that charges are simultaneously read out for the first and second rows of the pixel PX1_ij. In this case, assuming that the charge read from the first row of the pixel PX1_ij is Q1 and the charge read from the second row of the pixel PX1_ij is Q2, the read charge is Q1 + Q2. Therefore, it is not known which of the first and second rows of the pixel PX1_ij is the charge read from the photodiode PD of the read row. However, if charges are read out for two rows of pixels PX1_ij, the time required to read out data for imaging a single captured image is 1⁄2.

That is, if the charge readout is simultaneously performed on the m (m is a natural number) row of the pixel PX1_ij, the resolution is 1 / m times that of the case where the charge is read out on one row. The time required is 1 / m times, and the processing speed of charge readout can be increased. Therefore, it is effective when priority is given to the processing speed of charge readout over the resolution of the captured image.

Embodiment 4
Another embodiment of the present invention will be described below with reference to FIG. In addition, about the member which has the same function as the member demonstrated in the said embodiment for convenience of explanation, the same code | symbol is appended and the description is abbreviate | omitted. (A) of FIG. 10 is an example of a block diagram showing the configuration of the imaging device 2 according to Embodiment 4 of the present invention, and (b) of FIG. 10 shows the internal structure of the pixel PX2_ij shown in (a) of FIG. It is a circuit diagram shown.

(Configuration of imaging device 2)
As shown in (a) of FIG. 10, a plurality of pixels PX2_ij (i and j are integers of 1 or more and 5 or less) are two-dimensionally arranged in place of the pixels PX1_ij as shown in FIG. It differs in that it has a different structure. Further, the imaging device 2 is different from the imaging device 1 in that the reset signal generation circuit 30 is changed to the reset signal generation circuit 31, and instead of the reset power supply 60, a first reset power supply 61 (power supply) and a second The difference is that a reset power supply 62 (power supply) is provided.

Here, in a region where a plurality of pixels PX2_ij shown in (a) of FIG. 10 are arranged, the first column from the left, the second column, the third column, the fourth column, and the fifth column are used. The second line, the third line, the fourth line, and the fifth line. The first to fifth lines indicate that i is 1 to 5, and the first to fifth columns indicate that j is 1 to 5, respectively. For example, the pixel PX2_ij corresponding to the first row and the fourth column is described as a pixel PX2_14, and the pixel PX2_ij corresponding to the third row and the fifth column is described as a pixel PX2_35.

The internal structure of the pixel PX2_ij will be described based on FIG. 10 (b). Here, the pixel PX2_11 is selected from the plurality of pixels PX2_ij and described. That is, (b) of FIG. 10 is a circuit diagram showing an internal structure of the pixel PX2_11. The other pixels PX2_ij also have the same structure as the pixels PX2_11. As shown in (b) of FIG. 10, the pixel PX2_11 is provided with a first reset transistor TFT11 (switching element) and a second reset transistor TFT12 (switching element) instead of the reset transistor TFT10 as compared to the pixel PX1_11. The difference is that Further, the pixel PX2_11 is different from the pixel PX1_11 in that the first reset control line CL11_1 and the second reset control line CL12_1 pass in place of the reset control line CL10_1. Further, the pixel PX2_11 differs from the pixel PX1_11 in that the first bias line BL1_1 and the second bias line BL2_1 pass in place of the bias line BL_1.

Here, it is assumed that the first reset transistor TFT11, the second reset transistor TFT12, and the read transistor TFT20 have a source electrode, a gate electrode, and a drain electrode. The source electrodes of the first reset transistor TFT11 and the second reset transistor TFT12 are connected to the bias line BL_1. The drain electrodes of the first reset transistor TFT11 and the second reset transistor TFT12 are connected to the cathode electrode of the photodiode PD and the drain electrode of the readout transistor TFT20. The source electrode of the read out transistor TFT20 is connected to the read out line RL_1. The anode electrode of the photodiode PD is connected to the PD bias line PDBL_1. The gate electrode of the first reset transistor TFT11 is connected to a first reset control line CL11_1, and the first reset transistor TFT11 is controlled to be ON / OFF by a first reset signal supplied from the first reset control line CL11_1. The gate electrode of the second reset transistor TFT12 is connected to a second reset control line CL12_1, and the second reset transistor TFT12 is controlled to be ON / OFF by a second reset signal supplied from the second reset control line CL12_1. The gate electrode of the read transistor TFT20 is connected to the read control line CL20_1, and the read transistor TFT20 is controlled to be ON / OFF by the read signal supplied from the read control line CL20_1.

First reset control lines CL11_1 to CL11_5, second reset control lines CL12_1 to CL12_5, read control lines CL20_1 to CL20_5, and PD bias lines PDBL_1 to PDBL_5 are provided in each row of the pixels PX2_ij. In each column of the pixels PX2_ij, first bias lines BL1_1 to BL1_5, second bias lines BL2_1 to BL2_5, and read lines RL_1 to RL_5 are provided.

Here, although two reset transistors (first reset transistor TFT11 and second reset transistor TFT12) are provided in the pixel PX2_ij, the number of reset transistors is not limited to two, and is three or more. It is also good. Further, the number of reset control lines and bias lines may be changed in accordance with the number of reset transistors of the pixel PX2_ij. This reset control line has the same role as the first reset control lines CL11_1 to CL11_5 and the second reset control lines CL12_1 to CL12_5. Also, this bias line has the same role as the first bias lines BL1_1 to BL1_5 and the second bias lines BL2_1 to BL2_5.

The reset signal generation circuit 31 supplies a first reset signal for each row of the pixels PX2_ij via the first reset control lines CL11_1 to CL11_5. Further, the reset signal generation circuit 31 supplies a second reset signal for each row of the pixels PX2_ij through the second reset control lines CL12_1 to CL12_5. The first reset transistor TFT11 provided in the pixels PX2_11 to PX2_15, which are five pixels PX2_ij belonging to the same row, is controlled by a first reset signal supplied via the first reset control line CL11_1. Further, the second reset transistor TFT12 provided in the pixel PX2_11 to the pixel PX2_15 is controlled by a second reset signal supplied via the second reset control line CL12_1.

The first reset transistor TFT11 provided in the pixel PX2_21 to the pixel PX2_25 is controlled by a first reset signal supplied via the first reset control line CL11_2. The first reset transistor TFT11 provided in the pixels PX1_3 1 to PX1_35 is controlled by a first reset signal supplied via the first reset control line CL11_3. The first reset transistor TFT11 provided in the pixels PX1_41 to PX1_45 is controlled by a first reset signal supplied via the first reset control line CL11_4. The first reset transistor TFT11 provided in the pixels PX1_51 to PX1_55 is controlled by a first reset signal supplied via the first reset control line CL11_5.

Further, the second reset transistor TFT12 provided in the pixel PX2_21 to the pixel PX2_25 is controlled by a second reset signal supplied via the second reset control line CL12_2. The second reset transistor TFT12 provided in the pixels PX2_3 1 to PX2_35 is controlled by a second reset signal supplied via the second reset control line CL12_3. The second reset transistor TFT12 provided in the pixel PX2_41 to the pixel PX2_45 is controlled by the second reset signal supplied via the second reset control line CL12_4. The second reset transistor TFT12 provided in the pixel PX2_51 to the pixel PX2_55 is controlled by a second reset signal supplied via the second reset control line CL12_5.

The first reset power source 61 applies a first reset potential to the source electrode of the first reset transistor TFT11 and the positive terminals of the operational amplifiers O_1 to O_5 via the first bias lines BL1_1 to BL1_5. The second reset power supply 62 applies a second reset potential to the source electrode of the second reset transistor TFT12 via the second bias lines BL2_1 to BL2_5.

(Operation of the imaging device 2)
Next, the operation of the imaging device 2 will be described. The operation of the imaging device 2 is different from the operation of the imaging device 1 in the process of removing the charge remaining in the photodiode PD. For example, it is assumed that the reset signal generation circuit 31 removes the charge remaining in the photodiode PD in the second and third rows of the pixel PX1_ij. Specifically, the reset signal generation circuit 31 supplies the first reset signal to the first reset transistor TFT11 in the second and third rows of the pixel PX2_ij through the first reset control lines CL11_2 and CL11_3. The first reset transistor TFT11 in the second and third rows of the pixel PX2_ij is turned on when the first reset signal is supplied from the reset signal generation circuit 31. When the first reset transistor TFT11 in the second and third rows of the pixel PX2_ij is turned on, the charge remaining in the photodiode PD is removed via the first reset transistor TFT11 and the first bias lines BL1_1 to BL1_5. Therefore, the reset signal generation circuit 31 removes the charge remaining in the photodiode PD by supplying the first reset signal to the first reset control lines CL11_2 and CL11_3.

After the charge remaining in the photodiode PD is removed, the reset signal generation circuit 31 stops the supply of the first reset signal to the first reset transistor TFT11 in the second and third rows of the pixel PX2_ij. Thereafter, the reset signal generation circuit 31 supplies a second reset signal to the second reset transistor TFT12 in the second and third rows of the pixel PX2_ij. When the second reset signal is supplied from the reset signal generation circuit 31, the second reset transistor TFT12 in the second and third rows of the pixel PX2_ij is turned ON. When the second reset transistor TFT12 in the second and third rows of the pixel PX2_ij is turned on, the second reset potential is applied to the photodiode PD from the second reset power supply 62 via the second bias lines BL2_1 to BL2_5.

If the first reset potential is set to a voltage low enough to apply a forward bias to the photodiode PD, charges remaining in the photodiode PD can be removed quickly. After the charge remaining in the photodiode PD is quickly removed, the second reset potential is applied to the photodiode PD, so that the photodiode PD can store the charge according to the amount of light. The second reset potential is a potential applied to the photodiode PD when the photodiode PD performs a process of accumulating a charge according to the amount of light. Thus, in the processing in which the photodiode PD stores charge, the potential state of the photodiode PD expected in the processing in which the photodiode PD stores charge can be realized.

Therefore, reset potentials (first reset potential and second reset potential) can be applied to the photodiode PD in two steps. For example, one reset potential is set to a potential at which the charge remaining in the photodiode PD is easily removed, and the other reset potential is applied to the photodiode PD when the photodiode PD is charged. It can be set to an applied potential. Thereby, the photodiode PD can accumulate charge while efficiently removing the charge remaining in the photodiode PD.

Fifth Embodiment
It will be as follows if other embodiment of this invention is described. In addition, about the member which has the same function as the member demonstrated in the said embodiment for convenience of explanation, the same code | symbol is appended and the description is abbreviate | omitted.

In the case of removing the charge remaining in the photodiode PD in the imaging device 2, it is considered to apply a forward bias to the photodiode PD. Here, it is assumed that the first reset transistor TFT11 and the readout transistor TFT20 have a source electrode, a gate electrode, and a drain electrode. At this time, the first reset transistor TFT11 is not controlled by supplying a reset signal to the gate electrode of the first reset transistor TFT11, but is controlled by the following process. Specifically, the reset transistor TFT 10 may be controlled by changing the first reset potential applied from the first reset power supply 61 to the source electrode of the first reset transistor TFT 11.

When changing the first reset potential, a constant potential is applied to the gate electrode of the first reset transistor TFT11 by the reset signal generation circuit 31, and a bias line is provided for each row of the pixels PX2_ij. The bias line is a line connected to the first reset power supply 61 and the source electrode of the first reset transistor TFT11.

Here, the first reset potential is Vr, the potential applied to the drain electrode of the first reset transistor TFT11 is Vd, and the potential applied to the gate electrode of the first reset transistor TFT11 is Vg. Further, the threshold potential of the first reset transistor TFT11 is set to Vth.

The first reset power supply 61 changes the first reset potential applied to the source electrode of the first reset transistor TFT11 via the bias line for each row of the pixels PX2_ij. When the first reset transistor TFT11 is turned on, the first reset power supply 61 lowers the first reset potential Vr. Specifically, the first reset power supply 61 applies the first reset potential Vr to the source electrode of the first reset transistor TFT11 so that Vg >> Vr + Vth. When the first reset transistor TFT11 is turned on, a forward bias is applied to the photodiode PD. When a forward bias is applied to the photodiode PD, charges remaining in the photodiode PD are removed via the bias line.

When the first reset transistor TFT11 is turned off, the first reset power supply 61 raises the first reset potential Vr. Specifically, the first reset power supply 61 applies the first reset potential Vr to the source electrode of the first reset transistor TFT11 so that Vr ≧ Vd. When the first reset transistor TFT11 is turned off, Vg << Vd + Vth.

On the other hand, as described in the fourth embodiment, it is assumed that the charge remaining in the photodiode PD is removed by applying a negative potential while applying the first reset signal to the gate electrode of the first reset transistor TFT11. In this case, a constant negative potential is applied to the source electrode of the first reset transistor TFT 11 by the first reset power supply 61.

When the first reset transistor TFT11 is turned on, the reset signal generation circuit 31 raises the potential Vg (the potential of the first reset signal). Specifically, the reset signal generation circuit 31 applies the potential Vg to the gate electrode of the first reset transistor TFT11 such that Vg >> Vr + Vth.

When the first reset transistor TFT11 is turned off, the reset signal generation circuit 31 lowers the potential Vg. Specifically, the reset signal generation circuit 31 applies the potential Vg to the gate electrode of the first reset transistor TFT11 so that Vg << Vr + Vth. That is, to turn off the first reset transistor TFT11, the potential (Vg) of the first reset signal is sufficiently lower than the constant negative potential (Vr) applied to the source electrode of the first reset transistor TFT11. You need to For this reason, the potential (Vg) of the first reset signal is set to a potential sufficiently lower than the constant negative potential (Vr) applied to the source electrode of the first reset transistor TFT11, so that the power consumption increases. is there.

Therefore, when removing the charge remaining in the photodiode PD by applying a negative potential, it is desirable to control the first reset transistor TFT 11 by changing the first reset potential Vr. Thus, even in the case where a negative potential is applied to the imaging device 2, the first reset transistor TFT11 can be controlled by changing the first reset potential Vr. In addition, in the case of changing the first reset potential Vr, the potential applied to the first reset transistor TFT11 is smaller than in the case of changing the potential (Vg) of the first reset signal, so power consumption can be reduced. it can.

Furthermore, in the case of changing the first reset potential Vr, the potential applied to the first reset transistor TFT 11 and the potential applied to the read transistor TFT 20 may be able to be shared. The reason for this will be described below. In the case of changing the first reset potential Vr, the potential applied to the first reset transistor TFT11 is smaller than in the case of changing the potential (Vg) of the first reset signal. Since the potential applied to the readout transistor TFT 20 is small, the potential applied to the first reset transistor TFT 11 and the potential applied to the readout transistor TFT 20 can be easily equalized.

Sixth Embodiment
It will be as follows if other embodiment of this invention is described based on FIG.11 and FIG.12. In addition, about the member which has the same function as the member demonstrated in the said embodiment for convenience of explanation, the same code | symbol is appended and the description is abbreviate | omitted.

(Configuration of imaging device 3)
The imaging device 3 differs from the imaging device 1 in that the reset signal generation circuit 30 is changed to the common signal generation circuit 70 and that the readout signal generation circuit 20 is not provided, as shown in FIG. . Further, in the imaging device 3, the read control lines CL20_1 to CL20_5 are connected to the common signal generation circuit 70. FIG. 11 is an example of a block diagram showing a configuration of an imaging device 3 according to Embodiment 6 of the present invention.

The reset control line CL10_1 is connected to the readout control line CL20_2 of the next row of the pixels PX1_ij to form one line, and the one line is connected to the common signal generation circuit 70. The reset control line CL10_2 is connected to the readout control line CL20_3 of the next row of the pixels PX1_ij to be one line, and the one line is connected to the common signal generation circuit 70. Similarly, the reset control line CL10_3 is connected to the read control line CL20_4 to be one line, and the one line is connected to the common signal generation circuit 70. Further, the reset control line CL10_4 is connected to the read control line CL20_5 to be one line, and the one line is connected to the common signal generation circuit 70. The reset control line CL10_5 is connected to the common signal generation circuit 70.

The common signal generation circuit 70 supplies common signals to the reset control lines CL10_1 to CL10_5 and the read control lines CL20_1 to CL20_5, and controls the reset transistor TFT10 and the read transistor TFT20. Specifically, the common signal generation circuit 70 supplies a common signal to, for example, the reset control line CL10_1 and the read control line CL20_2. Thus, the common signal generation circuit 70 turns on the reset transistor TFT10 in the first row of the pixels PX1_ij, and turns on the read transistor TFT20 in the second row of the pixels PX1_ij. When the reset transistor TFT10 in the first row of the pixel PX1_ij is turned on, the charge remaining in the photodiode PD in the first row of the pixel PX1_ij is removed. When the readout transistor TFT20 in the second row of the pixel PX1_ij is turned on, the charge accumulated in the photodiode PD in the second row of the pixel PX1_ij is read out. The same process is performed on the other lines of the pixel PX1_ij.

Thereby, in the imaging device 3, the charge of the photodiode PD can be read out and removed only by the common signal generation circuit 70. Therefore, since the number of circuits of the imaging device 3 is reduced as compared with the imaging device 1, the manufacturing cost of the imaging device 3 can be reduced.

In the imaging device 3, the time for removing the charge remaining in the photodiode PD is the same as the time for reading out the charge. This is because both readout of the charge and removal of the charge are performed for each row of the pixel PX1_ij.

(Modification)
The imaging device 4 differs from the imaging device 2 in that the reset signal generation circuit 31 is changed to the common signal generation circuit 71 and that the readout signal generation circuit 20 is not provided, as shown in FIG. 12. . Further, in the imaging device 4, the read control lines CL20_1 to CL20_5 are connected to the common signal generation circuit 71. FIG. 12 is an example of a block diagram showing another configuration of the imaging device 4 according to Embodiment 6 of the present invention.

The first reset control line CL11_1 is connected to the readout control line CL20_2 of the next row of the pixel PX2_ij to be a single line, and the one line is connected to the common signal generation circuit 71. The second reset control line CL12_1 is connected to the first reset control line CL11_2 in the next row of the pixel PX1_ij and the read control line CL20_3 in the next row of the pixel PX1_ij to form one line. The one line is connected to the common signal generation circuit 71. Similarly, the second reset control line CL12_2 is connected to the first reset control line CL11_3 and the read control line CL20_4 to form one line, and the one line is connected to the common signal generation circuit 71. Further, the second reset control line CL12_3 is connected to the first reset control line CL11_4 and the read control line CL20_5 to form one line, and the one line is connected to the common signal generation circuit 71. The second reset control line CL12_4 is connected to the first reset control line CL11_5 to be a single line, and the single line is connected to the common signal generation circuit 71. The second reset control line CL12_5 is connected to the common signal generation circuit 71.

The common signal generation circuit 71 supplies a common signal to the first reset control lines CL11_1 to CL11_5, the second reset control lines CL12_1 to CL12_5, and the read control lines CL20_1 to CL20_5. The common signal generation circuit 71 controls the first reset transistor TFT11, the second reset transistor TFT12, and the read transistor TFT20 by supplying a common signal. Specifically, the common signal generation circuit 71 supplies a common signal to, for example, the second reset control line CL12_1, the first reset control line CL11_2, and the read control line CL20_3. Thus, the common signal generation circuit 71 turns on the second reset transistor TFT12 in the first row of the pixel PX2_ij, and turns on the first reset transistor TFT11 in the second row of the pixel PX2_ij. At the same time with these processes, the readout transistor TFT 20 in the third row of the pixel PX2_ij is turned on.

When the second reset transistor TFT12 in the first row of the pixel PX2_ij is turned on, the second reset potential is applied to the photodiode PD from the second reset power supply 62 via the second bias lines BL2_1 to BL2_5. When the first reset transistor TFT11 in the second row of the pixel PX2_ij is turned on, the charge remaining in the photodiode PD in the second row of the pixel PX2_ij is removed. When the readout transistor TFT20 in the third row of the pixel PX2_ij is turned on, the charge accumulated in the photodiode PD in the third row of the pixel PX2_ij is read out. The same process is performed on the other lines of the pixel PX2_ij.

Thus, in the imaging device 4, the charge of the photodiode PD can be read out and removed only by the common signal generation circuit 71. Further, in the imaging device 4, the reset potential (first reset potential and second reset potential) can be applied to the photodiode PD only by the common signal generation circuit 71. Therefore, since the number of circuits of the imaging device 4 is reduced as compared with the imaging device 2, the manufacturing cost of the imaging device 4 can be reduced.

In the imaging device 4, the time for removing the charge remaining in the photodiode PD is the same as the time for reading out the charge. This is because both readout of the charge and removal of the charge are performed for each row of the pixel PX2_ij.

Further, in this case, the row of the pixels PX2 _ij from which the charge is read out is adjacent to the row of the pixels PX2 _ij from which the charge removal is performed. However, the row of the pixels PX2_ij from which the charge is read out and the row of the pixels PX2_ij from which the charge removal is performed do not necessarily have to be adjacent to each other.

[Summary]
In the imaging devices 1, 2, 3, and 4 according to aspect 1 of the present invention, a plurality of pixels PX1_ij and PX2_ij including a photoelectric conversion element (photodiode PD) that accumulates electric charge according to the amount of light are two-dimensionally arranged. Readout circuit (readout signal generation circuit 20) for reading out the charge accumulated in the photoelectric conversion element by outputting a readout signal for each row of the pixels to readout control lines CL20_1 to CL20_5 connected to the pixels. And reset circuits (reset signal generation circuits 30, 31) for removing charges remaining in the photoelectric conversion elements by outputting reset signals to the reset control lines CL10_1 to CL10_5 connected to the pixels for each row of the pixels. While the readout circuit reads out the charge accumulated in the photoelectric conversion element, The reset circuit is configured to use the charge remaining in the photoelectric conversion element for the row of the pixels different from the row of the pixels on which the charge accumulated in the photoelectric conversion element is read by the reading circuit. Remove.

According to the above configuration, while the read out circuit reads out the charge accumulated in the photoelectric conversion element, the reset circuit reads the charge accumulated in the photoelectric conversion element by the read out circuit, and the row of pixels and Target the rows of other pixels to remove the charge remaining in the photoelectric conversion element. Thus, the charge readout process and the charge removal process are performed in parallel, so that the charge readout process can be performed at high speed.

In the imaging device according to aspect 2 of the present invention, in the aspect 1, the time during which the reset circuit (reset signal generation circuits 30 and 31) removes the charge remaining in the photoelectric conversion element (photodiode PD) is the readout It may be longer than the time for the circuit (readout signal generation circuit 20) to read out the charge accumulated in the photoelectric conversion element.

According to the above configuration, the time taken for the reset circuit to remove the charge remaining in the photoelectric conversion element is longer than the time taken for the reading circuit to read the charge accumulated in the photoelectric conversion element. Accordingly, since the reset circuit takes a long time to remove the charge remaining in the photoelectric conversion element, the charge remaining in the photoelectric conversion element can be accurately removed.

In the imaging device according to aspect 3 of the present invention, in the aspect 1 or 2, the pixel PX2_ij includes a plurality of switching elements (the first reset transistor TFT11, the second reset transistor TFT12), and the plurality of switching elements The reset circuit (reset signal generation circuit 31) is connected to a plurality of power supplies (first reset power supply 61, second reset power supply 62) for applying different potentials, and the photoelectric conversion element (photodiode PD). Outputs the reset signal to each of the plurality of reset control lines (first reset control lines CL11_1 to CL11_5 and second reset control lines CL12_1 to CL12_5) provided for each row of the pixels PX2_ij, By controlling the switching element, Different potentials to the photoelectric conversion elements may be applied.

According to the above configuration, different potentials can be applied to the photoelectric conversion element. For example, consider the case of applying a two-step potential to the photoelectric conversion element. In this case, for example, one of the potentials is set to a potential at which the charge remaining in the photoelectric conversion element is easily removed, and the other potential is a photoelectric conversion element when the photoelectric conversion element is charged Can be set to the potential applied to the Thus, the photoelectric conversion element can accumulate the charge while efficiently removing the charge remaining in the photoelectric conversion element.

In the imaging device according to aspect 4 of the present invention, in the above aspect 1 or 2, the pixel PX2_ij includes two switching elements (first reset transistor TFT11, second reset transistor TFT12), and the two switching elements are respectively The reset circuit (reset signal generation circuit 31) is connected to two power supplies (a first reset power supply 61 and a second reset power supply 62) applying different potentials, and the photoelectric conversion element (photodiode PD). Outputs the reset signal to each of the two reset control lines (first reset control lines CL11_1 to CL11_5, second reset control lines CL12_1 to CL12_5) provided for each row of the pixels, and The photoelectric conversion element is controlled by controlling a switching element It may be applied to different potentials.

According to the above configuration, different potentials can be applied to the photoelectric conversion element. For example, consider the case of applying a two-step potential to the photoelectric conversion element. In this case, for example, one of the potentials is set to a potential at which the charge remaining in the photoelectric conversion element is easily removed, and the other potential is a photoelectric conversion element when the photoelectric conversion element is charged Can be set to the potential applied to the Thus, the photoelectric conversion element can accumulate the charge while efficiently removing the charge remaining in the photoelectric conversion element.

In the imaging device according to aspect 5 of the present invention, in the aspect 4, the switching element (the first reset transistor TFT11, the second reset transistor TFT12) is a transistor having a source electrode and a gate electrode, and the reset circuit (reset The signal generation circuit 31) outputs the reset signal having a constant potential to the gate electrode, and one of the two power supplies (the first reset power supply 61 and the second reset power supply 62) is the source electrode. The switching element may be controlled by changing the negative potential applied to the

According to the above configuration, the reset circuit outputs a reset signal having a constant potential to the gate electrode, and one of the two power supplies changes the switching element by changing the negative potential applied to the source electrode. Control. Thereby, even in the case where a negative potential is applied to the imaging device 2, the switching element can be controlled by changing the negative potential.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

1, 2, 3 and 4 imaging device 10 control circuit 20 readout signal generation circuit (readout circuit)
30, 31 Reset signal generation circuit (reset circuit)
40 bias power supply 50 read power supply 60 reset power supply 61 first reset power supply (power supply)
62 2nd reset power supply (power supply)
70, 71 Common signal generation circuit CL10_1 to CL10_5 reset control line CL11_1 to CL11_5 first reset control line CL12_1 to CL12_5 second reset control line CL20_1 to CL20_5 read control line SW10 reset switch SW20 read switch TFT10 reset transistor TFT11 first reset transistor ( Switching element)
TFT12 Second reset transistor (switching element)
TFT20 Readout transistor PDBL_1 to PDBL_5 PD bias line PD photodiode (photoelectric conversion element)
BL_1 to BL_5 bias line BL1_1 to BL1_5 first bias line BL2_1 to BL2_5 second bias line RL_1 to RL_5 readout line PX1_ij, PX2_ij pixel I_1 to I_5 integrator O_1 to O_5 operational amplifier C_1 to C_5 capacitance

Claims (5)

In an imaging device in which a plurality of pixels including a photoelectric conversion element that accumulates a charge according to the amount of light are two-dimensionally arranged,
A readout circuit for reading out the charge accumulated in the photoelectric conversion element by outputting a readout signal for each row of the pixel to a readout control line connected to the pixel;
The reset control line connected to the pixel includes a reset circuit that removes a charge remaining in the photoelectric conversion element by outputting a reset signal for each row of the pixel.
While the readout circuit reads out the charge accumulated in the photoelectric conversion element, the reset circuit is configured to read the charge accumulated in the photoelectric conversion element by the readout circuit. An imaging device for removing charges remaining in the photoelectric conversion element with respect to another row of the pixels; The imaging device according to claim 1, wherein the time for which the reset circuit removes the charge remaining in the photoelectric conversion element is longer than the time for the readout circuit to read out the charge accumulated in the photoelectric conversion element. . The pixel includes a plurality of switching elements,
The plurality of switching elements are respectively connected to a plurality of power sources applying different potentials, and the photoelectric conversion element.
The reset circuit applies different potentials to the photoelectric conversion elements by outputting the reset signal to each of the plurality of reset control lines provided for each row of the pixels to control the plurality of switching elements. The imaging device according to claim 1 or 2, wherein The pixel includes two switching elements,
The two switching elements are respectively connected to two power supplies applying different potentials and the photoelectric conversion element,
The reset circuit applies different potentials to the photoelectric conversion element by outputting the reset signal to each of the two reset control lines provided for each row of the pixels and controlling the two switching elements. The imaging device according to claim 1 or 2, wherein The switching element is a transistor having a source electrode and a gate electrode,
The reset circuit outputs the reset signal having a constant potential to the gate electrode,
The imaging device according to claim 4, wherein one of the two power supplies controls the switching element by changing a negative potential applied to the source electrode.

Images