WO2018211368A1 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device capable of achieving good electric properties and high integration. This semiconductor device has an oxide in a channel formation region, and is provided with a transistor and a wiring, wherein the transistor has: an oxide on a first insulator; a second insulator on the oxide; a first conductor on the second insulator; a third insulator on the first conductor; a fourth insulator in contact with the second insulator, the first conductor, and the third insulator; and a fifth insulator in contact with the fourth insulator. The oxide has: a first region overlapping the second insulator; a second region overlapping the fourth insulator; and a third region in contact with the second region, wherein the third region has an oxygen concentration which is lower than those of the first region and second region, and the second region has an oxygen concentration which is lower than that of the first region. The wiring is in contact with the fifth insulator, and electrically connected to the third region.

Description

Semiconductor device and manufacturing method of semiconductor device

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and formed with electrodes serving as connection terminals.

A semiconductor circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and is used as one of various electronic device components.

Also, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

Further, it is known that a transistor using an oxide semiconductor has extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).

In addition, as a transistor using an oxide semiconductor, a self-aligned transistor has been proposed. As the self-aligned transistor, a metal film is formed over the source region and the drain region, and heat treatment is performed on the metal film, thereby increasing the resistance of the metal film and reducing the resistance of the source region and the drain region. Is disclosed (see Patent Document 2).

As a method for manufacturing a transistor including an oxide semiconductor, a metal film is formed over the source region and the drain region, heat treatment is performed, and then a dopant is introduced through the metal film, so that the source region and the drain region are introduced. A method for reducing the resistance of the drain region is disclosed (see Patent Document 3).

In recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which transistors and the like are integrated at high density. There is also a need for improved productivity of semiconductor devices including integrated circuits.

JP 2012-257187 A JP 2011-228622 A JP2013-016782A

In Patent Document 2, when the resistance of the source region and the drain region is lowered, a metal film is formed on the source region and the drain region, and the metal film is heat-treated in an oxygen atmosphere. By performing the heat treatment, the constituent element of the metal film enters the source region and the drain region of the oxide semiconductor film as a dopant to reduce the resistance. In addition, heat treatment is performed in an oxygen atmosphere to oxidize the conductive film and increase the resistance of the conductive film. However, since heat treatment is performed in an oxygen atmosphere, the metal film has a low effect of extracting oxygen from the oxide semiconductor film.

In Patent Document 2, the oxygen concentration in the channel formation region is described, but the concentration of impurities such as water and hydrogen is not mentioned. That is, the channel formation region has not been highly purified (reduction of impurities such as water and hydrogen, typically dehydration / dehydrogenation), and thus there is a problem that normally-on transistor characteristics are likely to occur. . Note that normally-on transistor characteristics refer to a state in which a channel exists even when a potential is not applied to the gate and current flows through the transistor. On the other hand, normally-off transistor characteristics are states in which no current flows through the transistor when no potential is applied to the gate.

In view of the above problems, one embodiment of the present invention provides a semiconductor device having favorable electrical characteristics by stably reducing resistance of a source region and a drain region of a transistor and highly purifying a channel formation region. One of the issues is to do.

Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these issues does not disturb the existence of other issues. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention is a semiconductor device including a transistor, the transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, and a first insulator. And a second insulator disposed on the side surface of the conductor, and an oxide, a second insulator, and a layer having a metal atom disposed on the conductor. 1 region, a second region, and a third region located between the first region and the second region, wherein the first region overlaps with the first insulator, The second region overlaps with the layer having a metal atom and has a metal compound, the third region has a region overlapping with the second insulator, and the second region is the first region. The region where the oxygen concentration is lower than those of the first region and the third region, and the third region has an oxygen concentration between the oxygen concentration of the first region and the oxygen concentration of the second region. A semiconductor device having a.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, A side surface of the insulator, and a second insulator disposed on the side surface of the conductor, and the oxide is formed of the first region, the second region, the first region, and the second region. A first region overlapping with the first insulator, a second region having a metal compound, and a third region having a second region The second region has a lower oxygen concentration than the first region and the third region, the third region has an oxygen concentration in the first region, and the second region has a region overlapping with the insulator. The semiconductor device includes a portion having an oxygen concentration between the region and the oxygen concentration.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, On the side surface of the insulator, the second insulator disposed on the side surface of the conductor, the oxide, the second insulator, the layer having metal atoms disposed on the conductor, and the layer having metal atoms A third insulator disposed on the third insulator and a fourth insulator disposed on the third insulator, wherein the fourth insulator has less carbon than the second insulator, and the third insulator The insulator has an excess oxygen region, and the oxide has a first region, a second region, and a third region located between the first region and the second region. The first region overlaps with the first insulator, the second region overlaps with the layer having a metal atom, and has a metal compound, and the third region is The second region has a region overlapping with the second insulator, the second region has a lower resistance than the first region and the third region, and the first region has a higher resistance than the third region. is there.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, On the side surface of the insulator, the second insulator disposed on the side surface of the conductor, the oxide, the second insulator, the third insulator disposed on the conductor, and the third insulator A fourth insulator, wherein the fourth insulator has less carbon than the second insulator, the third insulator has an excess oxygen region, and the oxide is: A first region; a second region; and a third region located between the first region and the second region, wherein the first region overlaps with the first insulator. The second region includes a metal compound, the third region includes a region overlapping with the second insulator, and the second region is lower than the first region and the third region. resistance There, the first region is a high-resistance than the third region.

In the above, the oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Further, in the above, the value of In in the oxide is larger in In value than in the element M in the atomic ratio.

In the above, the metal compound has at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above, the second region has nitrogen.

In the above, the first region has a lower hydrogen concentration than the second region.

In the above, the first region has a lower hydrogen concentration than the second region and the third region.

In the above, the transistor is a normally-off type.

Further, in the above, the metal compound has a portion mixed with the second region.

In the above, the metal compound has at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above, the metal compound has aluminum and titanium.

In the above, the metal compound has nitrogen.

In the above, the metal compound has one or both of nitrogen and oxygen.

In the above, the metal compound is 0.5 nm or more and less than 5 nm.

In the above, the carbon included in the second insulator and the carbon included in the fourth insulator are measured by X-ray photoelectron spectroscopy.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first insulator, an oxide over the first insulator, a second insulator over the oxide, and a first insulator. 3 insulator, a conductor on the second insulator, a fourth insulator on the third insulator, a second insulator, a conductor, a third insulator, and a fourth insulator A fifth insulator provided on the oxide and a sixth insulator provided on the fifth insulator with the insulator interposed between the first region and the fifth insulator; A second region and a third region located between the first region and the second region, the first region having a region overlapping with the second insulator, The third region has a region overlapping with the third insulator and the fourth insulator, and the second region has a lower oxygen concentration than the first region and the third region, and the third region Area A region having an oxygen concentration between the oxygen concentration of the second region and the oxygen concentration of the second region, and the third insulator has a region in contact with the second insulator and the side surface of the conductor. The fourth insulator is a semiconductor device having a region facing the side surface of the second insulator and the conductor via the third insulator.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first insulator, an oxide over the first insulator, and a second insulator over the oxide. , First film and third insulator, conductor on the second insulator, fourth insulator on the third insulator, second insulator, conductor, third And a fifth insulator provided on the oxide via a fourth insulator, and a sixth insulator provided on the fifth insulator, and oxidized. The object has a first region, a second region, and a third region located between the first region and the second region, wherein the first region is a second insulator. And the third region has a region overlapping with the third insulator and the fourth insulator, and the second region is more than the first region and the third region. Low oxygen concentration The third region has a portion having an oxygen concentration between the oxygen concentration of the first region and the oxygen concentration of the second region, and the first film is provided in contact with the second region. The third insulator has a region in contact with the second insulator and a side surface of the conductor, and the fourth insulator is connected to the second insulator and the conductor through the third insulator. A semiconductor device having a region facing a side surface of a body.

In the above, the third insulator may have a region in contact with the upper surface of the first insulator.

In the above, the oxide may include In, an element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the value of In in the oxide may be larger than the value of the element M in the atomic ratio.

In the above, the second region may include at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above, the second region may further contain nitrogen.

In the above description, the first region may have a lower hydrogen concentration than the second region.

In the above, the first region may have a lower hydrogen concentration than the second region and the third region.

In the above, the transistor may be a normally-off transistor.

Further, in the above, the first film may have a portion mixed with the second region.

In the above, the first film may have at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above, the first film may have aluminum and titanium.

In the above, the first film may further include one or both of nitrogen and oxygen.

In the above, the first film may be 0.5 nm or more and less than 5 nm.

Another embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, in which the transistor is located between the first region, the second region, and the first region and the second region. An oxide including a third region, a first insulator and a second insulator over the oxide, a conductor over the first insulator, and a second region overlapping with the second region A third insulator provided on the insulator and in contact with side surfaces of the first insulator and the conductor; an oxide; a first insulator; a conductor; a second insulator; and a third insulator A fourth insulator on the insulator and a fifth insulator on the fourth insulator; an oxide, a first insulator, a conductor, a second insulator, and a third insulator; A first film containing a metal is formed so as to cover the insulator and to be in contact with the second region, and at least nitrogen is applied to the oxide and the first film. By performing the first heat treatment in the absence of an atmosphere, oxygen contained in the second region is pulled out to the first film, a method for manufacturing a semiconductor device.

In the above, the first film may be formed by a sputtering method using any one or a plurality of gases selected from argon, nitrogen, and nitrogen.

In the above, the first film may be removed after the first heat treatment.

Further, in the above, a second heat treatment may be further performed after the first heat treatment.

In the above description, the fourth insulator and the fifth insulator may be formed after the removal of the first film.

Another embodiment of the present invention is a semiconductor device including an oxide in a channel formation region, the semiconductor device including a transistor and a wiring, and the transistor includes an oxide over a first insulator and an oxide. The second insulator above, the first conductor on the second insulator, the third insulator on the first conductor, the second insulator, the first conductor, and A fourth insulator that is in contact with the third insulator, and a fifth insulator that is in contact with the fourth insulator; and the oxide overlaps with the second insulator; The second region overlaps with the fourth insulator, and the third region is in contact with the second region, and the third region has an oxygen concentration higher than that of the first region and the second region. A semiconductor device in which the second region has a lower oxygen concentration than the first region, and the wiring is in contact with the fifth insulator and is electrically connected to the third region A.

Another embodiment of the present invention is a semiconductor device including an oxide in a channel formation region, the semiconductor device including a transistor and a wiring, the transistor including an oxide over the first insulator, A second insulator and a first film on the oxide; a first conductor on the second insulator; a third insulator on the first conductor; a second insulator; A first insulator and a fourth insulator in contact with the third insulator; and a fifth insulator in contact with the fourth insulator; and the oxide is the second insulator. A first region overlapping with the fourth insulator, a second region overlapping with the fourth insulator, and a third region in contact with the second region, the first film being in contact with the third region The third region has a lower oxygen concentration than the first region and the second region, the second region has a lower oxygen concentration than the first region, and the wiring has a fifth Edge member and the contact is and connected to the third region and electrically, is a semiconductor device according to claim.

In the above, the oxide is a semiconductor device containing In, an element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the oxide is a semiconductor device in which the value of In is larger than the value of the element M in the atomic ratio.

In the above, the third region is a semiconductor device in which the carrier density is higher than that of the second region, and the second region is higher in carrier density than the first region.

In the above, the third region is a semiconductor device including at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above, the third region is a semiconductor device further containing nitrogen.

In the above, the first region is a semiconductor device having a lower hydrogen concentration than the second region.

In the above, the first region is a semiconductor device having a lower hydrogen concentration than the second region and the third region.

In the above, the fifth insulator is a semiconductor device including a metal oxide.

In the above, the transistor is preferably a normally-off transistor.

In the above, it is preferable that the first film has a portion mixed with the third region.

In the above, it is preferable that the first film has at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above, the first film may include aluminum and titanium.

In the above, it is preferable that the first film further includes one or both of nitrogen and oxygen.

In the above, the first film is preferably 0.5 nm or more and less than 5 nm.

According to another embodiment of the present invention, a first insulator is formed over a substrate, an oxide layer is formed over the first insulator, and the first insulating layer is formed over the oxide layer. The film, the first conductive film, and the second insulating film are sequentially formed, and the first insulating film, the first conductive film, and the second insulating film are processed to form the second insulator, the first insulating film, Forming a conductor, a third insulator, covering the first insulator, the oxide layer, the second insulator, the first conductor, and the third insulator; The fourth insulating film is sequentially formed, and the third insulating film and the fourth insulating film are processed, so that the fourth insulating film is in contact with the second insulator, the first conductor, and the third insulator. Forming an insulator and a fifth insulator in contact with the fourth insulator, and forming a first film containing a metal in contact with the first insulator, the oxide layer, and the fifth insulator; Heat treatment in an atmosphere containing nitrogen The first film is removed, a sixth insulator is formed over the first insulator, the oxide layer, and the fifth insulator, an opening is formed in the sixth insulator, and the opening is filled. In this manner, the second conductor is formed as described above.

Further, in the above, the first film is preferably formed by a sputtering method using any one or a plurality of gases selected from argon, nitrogen, and oxygen.

Further, in the above, it is preferable that oxygen contained in the region is extracted by the first film in the region where the oxide layer of the oxide layer and the first film are in contact with each other by performing heat treatment.

In the above, after the heat treatment, a second film covering at least the oxide, the first insulator, the third insulator, the fourth insulator, and the fifth insulator may be formed.

Further, in the above, the opening is preferably formed so that at least a part of the fifth insulator, the upper surface of the oxide layer, and the side surface of the oxide layer are exposed.

In the above, the third insulating film and the fourth insulating film are preferably processed by anisotropic etching using a dry etching method.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly productive semiconductor device can be provided.

Alternatively, a semiconductor device capable of retaining data for a long time can be provided. Alternatively, a semiconductor device with high information writing speed can be provided. Alternatively, a semiconductor device with a high degree of design freedom can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A and 6B illustrate an energy band structure of an oxide semiconductor. Schematic diagram illustrating an area division of InGaZnO ₄ in the crystal. InO ₂ surface and (Ga, Zn) and the moving path of hydrogen atoms in the region between the O surface diagram illustrating the activation barrier on the path. The figure explaining the movement path | route of the hydrogen atom in a (Ga, Zn) O area | region, and the activation barrier on the path | route. A moving path of hydrogen atoms in the InO ₂ regions, diagram illustrating the activation barrier on the path. The figure explaining the movement path | route of the hydrogen atom along c-axis direction, and the activation barrier on the path | route. The figure explaining a calculation model. The figure explaining the relative value of the total energy of an oxygen deficiency model. The figure explaining the model of an initial state, and the model of a final state. The figure explaining an activation barrier. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. The circuit diagram which shows the structural example of an inverter circuit, and the timing chart which shows the operation example. FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. 4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device. FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. 1 is a block diagram illustrating a configuration example of an AI system according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. FIG. 10 is a schematic perspective view illustrating a configuration example of an IC incorporating an AI system according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. The figure explaining the sheet resistance of the sample of a present Example. The figure explaining the SIMS analysis result of the sample of a present Example. The figure which shows the Id-Vg characteristic of the sample which concerns on a present Example. The figure which shows the Id-Vg characteristic of the sample which concerns on a present Example.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may be omitted in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

In this specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

In addition, in this specification and the like, terms indicating arrangements such as “above” and “below” are used for convenience in order to explain the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

For example, in this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected, and X and Y are functional. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And it has a region where a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and through the region where the channel is formed, A current can flow between the source and the drain. Note that in this specification and the like, a region where a channel is formed refers to a region where current mainly flows.

Also, the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, in a top view of a transistor in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or in a region where a channel is formed. This is the length of a region where a vertical channel is formed with reference to the channel length direction. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter, “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

In addition, the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. When the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by mixing impurities. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Note that in this specification and the like, a silicon oxynitride film has a higher oxygen content than nitrogen as its composition. For example, preferably oxygen is 55 atomic% to 65 atomic%, nitrogen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range. The silicon nitride oxide film has a nitrogen content higher than that of oxygen. For example, preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.

In addition, in this specification and the like, the terms “film” and “layer” can be interchanged. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

Further, in this specification and the like, the term “insulator” can be referred to as an insulating film or an insulating layer. In addition, the term “conductor” can be restated as a conductive film or a conductive layer. In addition, the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.

Further, the transistors described in this specification and the like are field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

In addition, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal system.

Note that in this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.

In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, in the case where a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET or an OS transistor, it can be said to be a transistor including an oxide or an oxide semiconductor.

In this specification and the like, normally-off means that when a voltage is not applied to the gate or a ground potential is applied to the gate, a current per channel width of 1 μm flowing through the transistor is 1 × 10 ⁻²⁰ at room temperature. A or lower, 1 × 10 ⁻¹⁸ A or lower at 85 ° C., or 1 × 10 ⁻¹⁶ A or lower at 125 ° C.

(Embodiment 1)
An example of a semiconductor device including the transistor 200A according to one embodiment of the present invention is described below.

<Configuration example of semiconductor device>
1A, 1B, 1C, and 1D are a top view and a cross-sectional view of the transistor 200A according to one embodiment of the present invention and the periphery of the transistor 200A.

FIG. 1A is a top view of a semiconductor device having a transistor 200A. 1B, 1C, and 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view in the channel length direction of the transistor 200A. FIG. 1C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 1A and is a cross-sectional view in the channel width direction of the transistor 200A. FIG. 1D is a cross-sectional view taken along the dashed-dotted line A5-A6 in FIG. 1A and is a cross-sectional view of the source region or the drain region of the transistor 200A. Note that in the top view of FIG. 1A, some elements are omitted for clarity.

The semiconductor device of one embodiment of the present invention includes the transistor 200A, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 280, the insulator 282, and the insulator 284. In addition, a conductor 203 that is electrically connected to the transistor 200A and functions as a wiring, and a conductor 240 (a conductor 240a and a conductor 240b) that function as a plug are included.

Note that the conductor 203 is in contact with the inner wall of the opening of the insulator 212, the first conductor of the conductor 203 is formed, and the second conductor of the conductor 203 is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be approximately the same. Note that although a structure in which the first conductor of the conductor 203 and the second conductor of the conductor 203 are stacked is described in this embodiment, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a stacked structure including three or more layers. Moreover, when a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

The conductor 240 is formed in contact with the inner walls of the openings of the insulator 273, the insulator 274, the insulator 280, the insulator 282, and the insulator 284. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 284 can be approximately the same. Note that although a structure in which the conductor 240 has a two-layer structure is shown in this embodiment mode, the present invention is not limited to this. For example, the conductor 240 may be a single layer or a stacked structure of three or more layers.

[Transistor 200A]
As illustrated in FIG. 1, the transistor 200 </ b> A includes an insulator 214 and an insulator 216 disposed over a substrate (not shown), and a conductor disposed to be embedded in the insulator 214 and the insulator 216. 205, insulator 216, insulator 220 disposed over conductor 205, insulator 222 disposed over insulator 220, insulator 224 disposed over insulator 222, insulation Oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on body 224, insulator 250 disposed on oxide 230, and metal disposed on insulator 250 The oxide 252, the conductor 260 (the conductor 260 a and the conductor 260 b) disposed over the metal oxide 252, the insulator 270 disposed over the conductor 260, and the insulator 270 An insulator 271 disposed on the side surface of at least the oxide 230c, the insulator 250, the metal oxide 252, and the conductor 260, the oxide 230, and the insulator 275. And the insulator 273 disposed on the layer 242 and the insulator 274 disposed on the insulator 273.

Note that although the transistor 200A shows a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked, the present invention is not limited to this. For example, a structure in which a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be employed. In the transistor 200A, the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this.

The transistor 200A includes a metal functioning as an oxide semiconductor in the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a region where a channel is formed (hereinafter also referred to as a channel formation region). It is preferable to use an oxide (hereinafter also referred to as an oxide semiconductor).

Since the transistor 200A using an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200A included in a highly integrated semiconductor device.

For example, the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) It is preferable to use a metal oxide such as one or a plurality selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

Here, an oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements included in the oxide semiconductor, and has low resistance. Turn into. Note that aluminum, titanium, tantalum, tungsten, or the like is preferably used.

In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film, and oxygen vacancies are formed. The vicinity of the interface may be reduced in resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, a metal element which is a component of the film is converted into an oxide semiconductor or a component of an oxide semiconductor from a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. A certain metal element diffuses into the film, and the oxide semiconductor and the film form a metal compound, so that resistance can be reduced. The metal element added to the oxide semiconductor is in a relatively stable state by forming a metal compound with the oxide semiconductor, the metal element, and thus a highly reliable semiconductor device can be provided.

Further, a compound layer (hereinafter also referred to as a different layer) may be formed at the interface between the metal film, the nitride film containing a metal element, or the oxide film containing a metal element and the oxide semiconductor. Note that a compound layer (different layer) is a layer having a metal compound including a metal film, a nitride film containing a metal element, or a component of an oxide film containing a metal element and a component of an oxide semiconductor. For example, a layer in which a metal element of an oxide semiconductor and an added metal element are alloyed may be formed as the compound layer. The alloyed layer is in a relatively stable state, and a highly reliable semiconductor device can be provided.

In addition, hydrogen existing in the oxide semiconductor diffuses into a region where the resistance of the oxide semiconductor is reduced, and becomes relatively stable when it enters oxygen vacancies existing in the region where the resistance is reduced. In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. Has been found to be relatively stable. Accordingly, a region where the resistance of the oxide semiconductor is reduced by heat treatment or a region where the metal compound is formed is further reduced, and an oxide semiconductor which is not reduced in resistance is highly purified (impurities such as water and hydrogen). There is a tendency to increase resistance.

In addition, in an oxide semiconductor, the carrier density increases when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancy, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen or nitrogen to an oxide semiconductor, a high resistance region and a low resistance region can be provided in the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

Here, FIG. 2 shows an enlarged view of a region 239 including the oxide 230b which is selectively reduced in resistance and is surrounded by a broken line in FIG.

As illustrated in FIG. 2, the oxide 230 includes a region 234 that functions as a channel formation region of a transistor, a region 231 (a region 231 a and a region 231 b) that functions as a source region or a drain region, a region 234, and a region 231. And a region 232 (region 232a and region 232b) provided between the two.

The region 231 functioning as a source region or a drain region is a region having a low oxygen concentration and a low resistance. The region 234 functioning as a channel formation region is a high-resistance region having a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region. The region 232 has a higher oxygen concentration and a lower carrier density than the region 231 that functions as a source region or a drain region, and a lower oxygen concentration and a carrier density than the region 234 that functions as a channel formation region. It is a high area.

Note that the region 231 preferably has a higher concentration of at least one of the metal element and the impurity element such as hydrogen and nitrogen than the region 232 and the region 234.

For example, the region 231 preferably includes one or more metal elements selected from metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium in addition to the oxide 230.

In order to form the region 231, for example, the layer 242 may be provided as a film containing a metal element in contact with the region 231 of the oxide 230. Note that as the layer 242, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element can be used. At that time, a compound layer may be formed at the interface between the layer 242 and the oxide 230. Note that the compound layer is a layer having a metal compound including the component of the layer 242 and the component of the oxide 230. For example, a layer in which the metal element in the oxide 230 and the added metal element are alloyed may be formed as the compound layer.

By adding a metal element to the oxide 230, a metal compound is formed in the oxide 230, and the resistance of the region 231 can be reduced. Note that the metal compound is not necessarily formed in the oxide 230. For example, a metal compound may be formed in the layer 242. Further, for example, the oxide layer may be provided on the surface of the oxide 230, the surface of the layer 242, or the compound layer formed at the interface between the layer 242 and the oxide 230.

Therefore, the region 231 may include a low-resistance region of the layer 242 or a low-resistance region of a compound layer formed between the layer 242 and the oxide 230. That is, in this specification, a region functioning as a source region or a drain region is a region 231.

The region 232 has a region overlapping with the insulator 275. The region 232 preferably has a higher concentration of at least one of a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium and an impurity element such as hydrogen or nitrogen than the region 234. For example, the layer 242 that is a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided in contact with the region 231 of the oxide 230, whereby the components in the layer 242 and the oxide semiconductor component May form a metal compound. The metal compound may attract hydrogen contained in the oxide 230 in some cases. Therefore, the concentration of hydrogen in the region 232 in the vicinity of the region 231 may increase.

Note that one or both of the region 232 a and the region 232 b may have a region overlapping with the conductor 260. With this structure, the conductor 260 can overlap the region 232a and the region 232b.

In FIG. 2, the region 234, the region 231, and the region 232 are formed in the oxide 230 b, but are not limited thereto. For example, these regions may be formed in the layer 242, the compound layer formed between the layer 242 and the oxide 230, the oxide 230a, and the oxide 230c. In FIG. 2, the boundaries of the regions are displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this. For example, the region 232 may protrude to the conductor 260 side in the vicinity of the surface of the oxide 230b and recede to the conductor 240a side or the conductor 240b side in the vicinity of the lower surface of the oxide 230a.

In addition, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes between the regions, but also continuously change (also referred to as gradation) within each region. Also good. That is, the closer to the channel formation region, the lower the concentration of the metal element and impurity elements such as hydrogen and nitrogen.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity, such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and an impurity is added to a desired region. That's fine. Note that as the impurity, an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used. Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

The region 231 can have high carrier density and low resistance by increasing the content of the above-described metal element that increases conductivity, an element that forms oxygen vacancies, or an element that is trapped by oxygen vacancies. it can.

In order to reduce the resistance of the region 231, for example, the layer 242 may be formed in contact with the region 231 of the oxide 230. As the layer 242, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like can be used. The layer 242 is preferably provided over the oxide 230 with at least the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, the insulator 271, and the insulator 275 interposed therebetween.

When the oxide 230 and the layer 242 are in contact with each other, the component of the layer 242 and the component of the oxide 230 form a metal compound, which becomes a region 231 and has a low resistance. In addition, part of oxygen in the oxide 230 located in the vicinity of the interface between the oxide 230 and the layer 242 or in the vicinity of the interface is absorbed by the layer 242, and oxygen vacancies are formed in the oxide 230. 231 may be formed.

Further, heat treatment may be performed in an atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. Through the heat treatment, the metal element which is a component of the layer 242 is diffused from the layer 242 to the oxide 230 or the metal element which is a component of the oxide 230 is diffused to the layer 242, so that the oxide 230 and the layer 242 are formed. A metal compound is formed to reduce resistance. At that time, the metal element of the oxide 230 and the metal element of the layer 242 may be alloyed. When the metal element of the oxide 230 and the metal element of the layer 242 are alloyed, the metal element is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen), and has a higher resistance.

On the other hand, in the region where the conductor 260 and the insulator 275 of the oxide 230 overlap with each other (the region 234 and the region 232), addition of a metal element is suppressed by the conductor 260 and the insulator 275. In addition, in the region 234 and the region 232 of the oxide 230, oxygen atoms in the oxide 230 are suppressed from being absorbed into the layer 242 described above.

Further, when the layer 242 absorbs oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231, oxygen vacancies may be generated in the region 231 and the region 232. As hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the resistance of the region 231 and the region 232 of the oxide 230 is reduced.

Here, in the case where the layer 242 has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Further, the layer 242 may be removed together with hydrogen absorbed from the oxide 230 in a later step.

Note that the layer 242 is not necessarily removed. For example, if the layer 242 is insulated and has a high resistance, it may remain. For example, the layer 242 may be oxidized by oxygen absorbed from the oxide 230 to be an insulator and have high resistance. In that case, the layer 242 may function as an interlayer film.

Further, for example, in the case where a conductive region remains in the layer 242, it is oxidized by heat treatment to become an insulator, and the resistance is increased. The heat treatment is preferably performed in an oxidizing atmosphere, for example. In the case where there is a structure including oxygen in the vicinity of the layer 242, the layer 242 may react with oxygen included in the structure and be oxidized by heat treatment.

By leaving the layer 242 as an insulator, it can function as an interlayer film. In the case of the structure, the layer 242 is provided with a thickness that can be insulated in a later step. For example, the layer 242 may be provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. Note that in the case where the heat treatment is performed in the above oxidizing atmosphere, it is preferable that the heat treatment is performed once in the atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. By performing heat treatment once in an atmosphere containing nitrogen, oxygen in the oxide 230 can easily diffuse into the layer 242.

Here, in a transistor including an oxide semiconductor, if an impurity and an oxygen vacancy exist in a region where a channel is formed in the oxide semiconductor, electric characteristics may be easily changed and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

Therefore, as illustrated in FIG. 2, the insulating layer 250, the region 232 of the oxide 230b, and the oxide 230c are in contact with each other and contain more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. An insulator 275 is preferably provided. That is, excess oxygen in the insulator 275 is diffused into the region 234 of the oxide 230, whereby oxygen vacancies in the region 234 of the oxide 230 can be reduced.

In order to provide an excess oxygen region in the insulator 275, an oxide film may be formed as the insulator 273 adjacent to the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide, an insulator with few impurities such as water or hydrogen can be formed. In the case of using a sputtering method, for example, it is preferable to form a film using a facing target type sputtering apparatus. Since the facing target type sputtering apparatus can form a film without exposing the film formation surface to a high electric field region between the facing targets, the film formation surface can be formed without being easily damaged by plasma. This is preferable because film-forming damage to the oxide 230 can be reduced when the insulator 273 is formed. A film forming method using a facing target type sputtering apparatus can be referred to as VDSP (Vapor Deposition SP) (registered trademark).

During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

The ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, so that the sputtered particles are ejected from the target. The sputtered particles adhere to and deposit on the film formation surface to form a film. Some ions recoil by the target, pass through a film formed as recoil ions, and may be taken into the insulator 275 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 275. When the ions are taken into the insulator 275, a region into which the ions are taken is formed in the insulator 275. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 275.

By introducing excess oxygen into the insulator 275, an excess oxygen region can be formed in the insulator 275. Excess oxygen in the insulator 275 can be supplied to the region 234 of the oxide 230 to compensate for oxygen vacancies in the oxide 230.

Note that the insulator 275 is preferably formed using silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes. Materials such as silicon oxynitride tend to form excess oxygen regions. On the other hand, compared to the above-described materials such as silicon oxynitride, the oxide 230 tends to hardly form an excess oxygen region even if an oxide film formed by a sputtering method is formed over the oxide 230. Therefore, by providing the insulator 275 having an excess oxygen region around the region 234 of the oxide 230, the excess oxygen of the insulator 275 can be effectively supplied to the region 234 of the oxide 230.

The insulator 273 is preferably made of aluminum oxide. Aluminum oxide may extract hydrogen in the oxide 230 by performing heat treatment in the state of being close to the oxide 230. Note that in the case where the layer 242 is provided between the oxide 230 and aluminum oxide, the hydrogen in the layer 242 is absorbed by the aluminum oxide, and the layer 242 in which hydrogen is reduced reduces the hydrogen in the oxide 230. May absorb. Therefore, the hydrogen concentration in the oxide 230 can be reduced. In addition, oxygen may be supplied from the insulator 273 to the oxide 230, the insulator 224, or the insulator 222 by performing heat treatment in a state where the insulator 273 and the oxide 230 are in proximity to each other.

The oxide 230 can be selectively reduced in resistance by combining the above structure or the above steps.

That is, when a low resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260 functioning as a gate electrode and the insulator 275 as a mask. Therefore, when the plurality of transistors 200A are formed at the same time, variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200A is determined by the width of the conductor 260 and the film thickness of the insulator 275, and the transistor 200A can be miniaturized by setting the width of the conductor 260 to the minimum processing dimension. Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, a detailed structure of a semiconductor device including the transistor 200A according to one embodiment of the present invention will be described.

As shown in FIGS. 1A and 1C, the conductor 203 is extended in the channel width direction and functions as a wiring for applying a potential to the conductor 205. Note that the conductor 203 is preferably provided so as to be embedded in the insulator 212.

The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided in contact with the conductor 203. The conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 200A can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200A can be higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when a negative potential is not applied.

Further, by providing the conductor 205 over the conductor 203, the distance between the conductor 203 having the function of the first gate electrode and the wiring and the conductor 203 can be appropriately designed. That is, by providing the insulator 214, the insulator 216, and the like between the conductor 203 and the conductor 260, parasitic capacitance between the conductor 203 and the conductor 260 can be reduced, and the conductor 203 and the conductor 260 can be reduced. The insulation breakdown voltage can be increased.

Further, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor 200A can be improved and a transistor having high frequency characteristics can be obtained. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200A can be improved. Therefore, it is preferable to increase the thickness of the insulator 214 and the insulator 216. Note that the extending direction of the conductor 203 is not limited thereto, and may be extended in the channel length direction of the transistor 200A, for example.

Note that the conductor 205 is provided so as to overlap with the oxide 230 and the conductor 260 as illustrated in FIG. The conductor 205 is preferably provided larger than the region 234 in the oxide 230. In particular, as illustrated in FIG. 1C, the conductor 205 is preferably extended also in a region outside the end portion that intersects the channel width direction of the region 234 of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. The area can be covered.

That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. . In this specification, a transistor structure that electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

Further, the conductor 205 is formed with a first conductor in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and further a second conductor is formed inside. Here, the height of the upper surface of the first conductor of the conductor 205 and the second conductor of the conductor 205 and the height of the upper surface of the insulator 216 can be approximately the same. Note that although the transistor 200A illustrates a structure in which the first conductor of the conductor 205 and the second conductor of the conductor 205 are stacked, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a stacked structure including three or more layers.

Here, the first conductor of the conductor 205 or the conductor 203 includes a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), copper It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as atoms (the impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen hardly transmits). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

Since the conductor 205 or the first conductor of the conductor 203 has a function of suppressing diffusion of oxygen, the conductor 205 or the second conductor of the conductor 203 is oxidized to reduce conductivity. This can be suppressed. As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Therefore, the conductive material may be a single layer or a stacked layer as the first conductor of the conductor 205 or the conductor 203. Thus, impurities such as hydrogen and water can be prevented from diffusing from the substrate side (below the insulator 210) to the transistor 200A side through the conductor 203 and the conductor 205.

In addition, the second conductor of the conductor 205 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the second conductor of the conductor 205 is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium or titanium nitride and the above conductive material.

Further, since the second conductor of the conductor 203 functions as a wiring, a conductor having higher conductivity than the second conductor of the conductor 205 is preferably used. For example, a conductive material mainly containing copper or aluminum can be used. The second conductor of the conductor 203 may have a stacked structure, for example, a stack of titanium or titanium nitride and the above conductive material.

In particular, it is preferable to use copper for the conductor 203. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, the electrical characteristics of the transistor 200 </ b> A may be deteriorated by diffusing into the oxide 230. Therefore, for example, by using a material such as aluminum oxide or hafnium oxide having low copper permeability for the insulator 214, copper diffusion can be suppressed.

Note that the conductor 205, the insulator 214, and the insulator 216 are not necessarily provided. In that case, part of the conductor 203 can function as the second gate electrode.

The insulator 210, the insulator 214, and the insulator 282 preferably function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor 200A from the substrate side or the insulator 284 side. Therefore, the insulator 210, the insulator 214, and the insulator 282 include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N ₂ O, NO, NO _{2, and the} like), a copper atom, and the like. It is preferable to use an insulating material having a function of suppressing diffusion of impurities (the above impurities are difficult to transmit). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen hardly transmits).

For example, aluminum oxide or the like is preferably used as the insulator 210 and the insulator 282, and silicon nitride or the like is preferably used as the insulator 214. Thus, impurities such as hydrogen and water can be prevented from diffusing from the substrate side to the transistor 200A side with respect to the insulator 210 and the insulator 214. Alternatively, diffusion of oxygen contained in the insulator 224 and the like to the substrate side with respect to the insulator 210 and the insulator 214 can be suppressed. Alternatively, diffusion of impurities such as hydrogen and water from the insulator 284 side to the transistor 200A side rather than the insulator 282 can be suppressed.

In addition, by providing a structure in which the conductor 205 is provided over the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even when a metal that easily diffuses, such as copper, is used for the second conductor of the conductor 203, by providing silicon nitride or the like as the insulator 214, the metal diffuses into a layer above the insulator 214. Can be suppressed.

In addition, the insulator 212, the insulator 216, the insulator 280, and the insulator 284 that function as interlayer films preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

For example, as the insulator 212, the insulator 216, the insulator 280, and the insulator 284, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT) ), An insulator such as strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used in a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 220, the insulator 222, and the insulator 224 have a function as a gate insulator.

Here, the insulator 224 in contact with the oxide 230 is preferably an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200A can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 × 10 ¹⁸ atoms in a thermal desorption gas spectroscopy (TDS) analysis. / Cm ³ or more, preferably 1.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ or more It is. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

In the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen is difficult to transmit). It is preferable.

Since the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region included in the insulator 224 can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. . In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.

Examples of the insulator 222 include so-called aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). An insulator including a high-k material is preferably used as a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

In particular, an insulator including one or both of oxides of aluminum and hafnium, which is an insulating material having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to permeate) may be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200A. Acts as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

In addition, the insulator 220 or the insulator 224 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a gate insulator is formed to have a stacked structure that is thermally stable and has a high relative dielectric constant when combined with an insulator of a high-k material. Can do.

Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.

The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By including the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Further, by including the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

Note that the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Further, it is preferable that the energy level at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy level at the lower end of the conduction band of the oxide 230b. In other words, the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.

Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined. In order to achieve this, the defect state density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is preferably low.

Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed. can do. For example, in the case where the oxide 230b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 230a and the oxide 230c.

At this time, the main path of the carrier is the oxide 230b. When the oxide 230a and the oxide 230c have the above structure, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence on the carrier conduction due to the interface scattering is reduced, and the transistor 200A can obtain a high on-state current.

In addition, the oxide 230 includes a region 231, a region 232, and a region 234. Note that at least part of the region 231 has a region in proximity to the insulator 273. The region 232 has at least a region overlapping with the insulator 275.

Note that when the transistor 200A is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least part of the region 234 functions as a region where a channel is formed. By having the region 232 between the region 231 and the region 234, in the transistor 200A, the on-state current can be increased and the leakage current (off-state current) during non-conduction can be reduced.

In the transistor 200A, when the region 232 is provided, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; thus, on-state current and mobility of the transistor Can be increased. In addition, since the region 232 includes the source region, the drain region, and the first gate electrode (conductor 260) in the channel length direction, unnecessary capacitance is formed between the two. Can be suppressed. In addition, by including the region 232, leakage current at the time of non-conduction can be reduced.

That is, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide used for the region 234, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.

Since a transistor including an oxide semiconductor has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in TDS analysis, the amount of released oxygen in terms of oxygen molecules is 1.0 × 10 ¹⁸ molecules / cm ³ or more, preferably 1.0 × 10 ¹⁹ molecules / cm ³ or more, more preferably 2 The oxide film is 0.0 × 10 ¹⁹ molecules / cm ³ or 3.0 × 10 ²⁰ molecules / cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

An insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the top surface of the oxide 230c, whereby oxygen can be effectively supplied from the insulator 250 to the region 234 of the oxide 230b. . Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Further, a metal oxide 252 may be provided in order to efficiently supply excess oxygen included in the insulator 250 to the oxide 230. Therefore, the metal oxide 252 preferably suppresses oxygen diffusion from the insulator 250. By providing the metal oxide 252 that suppresses oxygen diffusion, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Note that the metal oxide 252 may have a function as a part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide 252. In that case, by forming the conductor 260 by a sputtering method, the electric resistance value of the metal oxide 252 can be reduced, whereby the conductor can be obtained. This can be called an OC (Oxide Conductor) electrode.

Further, the metal oxide 252 may function as a part of the gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide 252 is preferably a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat | fever, and a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.

In the transistor 200A, the metal oxide 252 is shown as a single layer; however, a stacked structure including two or more layers may be used. For example, a metal oxide that functions as part of the first gate electrode and a metal oxide that functions as part of the gate insulator may be stacked.

In the case where the metal oxide 252 serves as the first gate electrode, the on-state current of the transistor 200A can be improved without weakening the influence of the electric field from the conductor 260. Alternatively, in the case of functioning as a gate insulator, the distance between the conductor 260 and the oxide 230 is maintained by the physical thickness of the insulator 250 and the metal oxide 252, so that the conductor 260 Leakage current between the oxide 230 can be suppressed. Therefore, by providing a stacked structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 are It can be easily adjusted as appropriate.

Specifically, by reducing the resistance of an oxide semiconductor that can be used for the oxide 230 as the metal oxide 252, the metal oxide 252 can be used as the metal oxide 252. Alternatively, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process. Note that the metal oxide 252 is not an essential component. What is necessary is just to design suitably according to the transistor characteristic to request | require.

The conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. Like the first conductor of the conductor 205, the conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), a copper atom It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

When the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the conductivity from being lowered due to oxidation of the conductor 260b due to excess oxygen included in the insulator 250 and the metal oxide 252. . As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

Further, since the conductor 260 functions as a wiring, it is preferable to use a conductor having high conductivity. For example, the conductor 260b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

In addition, as illustrated in FIG. 1C, when the conductor 205 extends in a region outside the end portion that intersects the channel width direction of the oxide 230, the conductor 260 It is preferable to overlap with the insulator 250. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a stacked structure outside the side surface of the oxide 230.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. The area can be covered.

That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. .

Further, an insulator 270 that functions as a barrier film may be provided over the conductor 260b. As the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Accordingly, it is possible to suppress the conductor 260 from being oxidized by oxygen from above the insulator 270. Further, impurities such as water or hydrogen from above the insulator 270 can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.

Further, it is preferable to dispose an insulator 271 functioning as a hard mask over the insulator 270. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle formed between the side surface of the conductor 260 and the substrate surface is 75 ° to 100 °, Preferably, it can be 80 ° or more and 95 ° or less. By processing the conductor 260 into such a shape, the insulator 275 to be formed next can be formed into a desired shape.

Note that the insulator 271 may also function as a barrier film by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 270 is not necessarily provided.

The insulator 275 functioning as a buffer layer is provided in contact with the side surface of the oxide 230 c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270.

For example, as the insulator 275, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 275 preferably has an excess oxygen region. By providing an insulator from which oxygen is released by heating as the insulator 275 in contact with the oxide 230c and the insulator 250, oxygen is effectively supplied from the insulator 250 to the region 234 of the oxide 230b. be able to. In addition, the concentration of impurities such as water or hydrogen in the insulator 275 is preferably reduced.

The insulator 273 is provided over at least the region 231 of the oxide 230 and the insulator 275. By depositing the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275. Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region. In addition, by providing the insulator 273 over the region 231 of the oxide 230, hydrogen in the oxide 230 can be extracted to the insulator 273.

For example, as the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm.

In addition, an insulator 274 is provided over the insulator 273. The insulator 274 is preferably formed using a film having barrier properties and a reduced hydrogen concentration. For example, as the insulator 274, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, or the like may be used. By providing the insulator 273 having a barrier property and the insulator 274 having a barrier property, diffusion of impurities from other structures such as an interlayer film to the transistor 200A can be suppressed.

Further, an insulator 280 that functions as an interlayer film is preferably provided over the insulator 274. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that an insulator 282 similar to the insulator 210 may be provided over the insulator 280. By forming the insulator 282 by a sputtering method, impurities in the insulator 280 can be reduced. Further, the insulator 284 similar to the insulator 280 may be provided over the insulator 282.

In addition, the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the insulator 273. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 284.

The conductor 240a is in contact with the region 231a that functions as one of the source region and the drain region of the transistor 200A, and the conductor 240b is in contact with the region 231b that functions as the other of the source region and the drain region of the transistor 200. Therefore, the conductor 240a can function as one of the source electrode and the drain electrode, and the conductor 240b can function as the other of the source electrode and the drain electrode.

Note that a conductor 240a is formed in contact with the inner walls of the openings of the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the insulator 273. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, a conductor 240b is formed in contact with the inner walls of the openings of the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the insulator 273. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

Here, as shown in FIG. 1D, the conductor 240a and the conductor 240b preferably overlap with the side surface of the oxide 230. In particular, the conductor 240a and the conductor 240b preferably overlap with both or one of the side surface on the A5 side and the side surface on the A6 side on the side surface intersecting the channel width direction of the oxide 230. Alternatively, the conductor 240a and the conductor 240b may overlap with the side surface on the A1 side (A2 side) on the side surface intersecting the channel length direction of the oxide 230. In this manner, the conductor 240a and the conductor 240b overlap with the side surface of the oxide 230 (particularly, the region 231 serving as a source region or a drain region), whereby the conductor 240a and the conductor 240b Without increasing the projected area of the contact portion of the transistor 200A, the contact area of the contact portion can be increased, and the contact resistance between the conductor 240a and the conductor 240b and the transistor 200A can be reduced. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.

The conductive material 240a and the conductive material 240b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

Here, for example, when an opening is formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the insulator 273, the region where the resistance of the region 231 is reduced in the oxide 230 is removed, The oxide 230 that has not been reduced in resistance may be exposed. In that case, a metal film, a nitride film containing a metal element, or a metal element is used as a conductor used for a conductor in contact with the oxide 230 of the conductor 240 (hereinafter also referred to as a first conductor of the conductor 240). It is preferable to use an oxide film having the same. That is, when the oxide 230 whose resistance is not reduced and the first conductor of the conductor 240 are in contact with each other, oxygen vacancies are formed in the metal compound or the oxide 230, and the first conductor of the conductor 240 The resistance of the oxide 230 in contact with the oxide is reduced. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. Therefore, the first conductor of the conductor 240 preferably includes a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten.

In the case where the conductor 240 has a stacked structure, the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the conductor in contact with the insulator 273 include the first conductor of the conductor 205, and the like. Similarly, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from the upper layer than the insulator 280 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.

Although not shown, a conductor functioning as a wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. As the conductor functioning as the wiring, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. The conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material. Note that like the conductor 203 and the like, the conductor may be formed so as to be embedded in an opening provided in the insulator.

<Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used for the semiconductor device will be described.

<< Board >>
For example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used as the substrate over which the transistor according to one embodiment of the present invention is formed. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

Further, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled and transferred to a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used. A substrate that is a flexible substrate is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed. As the substrate that is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.

<< Insulator >>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

For example, when the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the voltage during transistor operation can be reduced while maintaining the physical film thickness. On the other hand, a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film. Therefore, the material may be selected according to the function of the insulator.

Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium. There are oxynitrides having silicon and nitrides having silicon and hafnium.

Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.

In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.

In addition, a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.

Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

For example, as the insulator 273 and the insulator 282, a metal containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like An oxide can be used.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be increased by increasing the film thickness. Therefore, by adjusting the film thickness of hafnium oxide, appropriate addition amounts of hydrogen and nitrogen can be adjusted.

For example, the insulator 224 and the insulator 250 that function as part of the gate insulator are preferably insulators having an excess oxygen region. For example, by using a structure in which silicon oxide or silicon oxynitride having an excess oxygen region is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

For example, in the insulator 222 that functions as part of the gate insulator, an insulator including one or more oxides of aluminum, hafnium, and gallium can be used. In particular, as the insulator including one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

For example, for the insulator 220, it is preferable to use silicon oxide or silicon oxynitride which is stable against heat. The gate insulator has a laminated structure of a heat stable film and a film having a high relative dielectric constant, so that a thin film having an equivalent oxide thickness (EOT) of the gate insulator is maintained while maintaining a physical film thickness. Can be realized.

With the above laminated structure, the on-current can be improved without weakening the influence of the electric field from the gate electrode. In addition, the leakage current between the gate electrode and the channel formation region can be suppressed by maintaining the distance between the gate electrode and the region where the channel is formed depending on the physical thickness of the gate insulator. .

The insulator 212, the insulator 216, the insulator 271, the insulator 275, the insulator 280, and the insulator 284 preferably have an insulator with a low relative dielectric constant. For example, the insulator 212, the insulator 216, the insulator 271, the insulator 275, the insulator 280, and the insulator 284 are formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, or carbon. It is preferable to include added silicon oxide, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or a resin. Alternatively, the insulator 212, the insulator 216, the insulator 271, the insulator 275, the insulator 280, and the insulator 284 are formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, or carbon. It is preferable to have a stacked structure of added silicon oxide, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

As the insulator 210, the insulator 214, the insulator 270, the insulator 273, the insulator 284, and the insulator 282, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Examples of the insulator 210, the insulator 214, the insulator 270, the insulator 273, the insulator 284, and the insulator 282 include aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, A metal oxide such as lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like may be used.

<< Conductor >>
As the conductor, a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

Note that in the case where an oxide is used for a channel formation region of the transistor, the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate electrode. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

As the conductor 260, the conductor 203, the conductor 205, and the conductor 240, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium A material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

<< Metal oxide >>
As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. Below, the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.

The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, a case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

In addition, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor. Note that in the case where CAC-OS or CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function prevents electrons from flowing. A function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.

Also, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).

[Structure of metal oxide]
An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, it is difficult to check a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.

The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear crystal grain boundary in the CAAC-OS, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of the metal oxide may be reduced due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.

Nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

A-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors (metal oxides) have various structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with metal oxide]
Next, the case where the metal oxide is used for a channel formation region of a transistor will be described.

Note that a transistor with high field-effect mobility can be realized by using the metal oxide for a channel formation region of the transistor. In addition, a highly reliable transistor can be realized.

For the transistor, a metal oxide with low carrier density is preferably used. In the case where the carrier density of the metal oxide film is lowered, the impurity concentration in the metal oxide film may be lowered and the defect level density may be lowered. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

Further, since the metal oxide film having high purity intrinsic or substantially high purity intrinsic has a low defect level density, the trap level density may also be low.

Further, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor including a metal oxide with a high trap state density in a channel formation region may have unstable electrical characteristics.

Therefore, to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

In the metal oxide, when silicon or carbon, which is one of Group 14 elements, is included, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Therefore, in the metal oxide, nitrogen in the channel formation region is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS, Preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

Stable electrical characteristics can be imparted by using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor.

<Method for Manufacturing Semiconductor Device>
Next, a manufacturing method of a semiconductor device including the transistor 200A according to the present invention will be described with reference to FIGS. 3 to 13, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A1-A2 in (A). Moreover, (C) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A3-A4 in (A). Moreover, (D) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A5-A6 in (A).

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The insulator 210 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an atom. It can be performed using a layer deposition (ALD: Atomic Layer Deposition) method or the like.

In addition, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

The plasma CVD method can obtain a high-quality film at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

The ALD method is also a film forming method that can reduce plasma damage to the object to be processed. In addition, since ALD does not cause plasma damage during film formation, a film with few defects can be obtained. Note that some precursors used in the ALD method include impurities such as carbon. Therefore, a film provided by the ALD method may contain a larger amount of impurities such as carbon than a film provided by another film formation method. The quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, compared to film formation using multiple film formation chambers, the time required for film formation is shortened by the time required for transport and pressure adjustment. can do. Therefore, the productivity of the semiconductor device may be increased.

In this embodiment, an aluminum oxide film is formed as the insulator 210 by a sputtering method. The insulator 210 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, an aluminum oxide film may be formed by an ALD method, and an aluminum oxide film may be formed on the aluminum oxide by a sputtering method.

Next, an insulator 212 is formed on the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 212 by a CVD method.

Next, an opening reaching the insulator 210 is formed in the insulator 212. The opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing. The insulator 210 is preferably selected from an insulator that functions as an etching stopper film when the opening is formed by etching the insulator 212. For example, in the case where a silicon oxide film is used for the insulator 212 that forms the opening, the insulator 210 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film as an insulating film that functions as an etching stopper film.

After the opening is formed, a conductive film to be a first conductor of the conductor 203 is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the first conductor of the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as the conductive film to be the first conductor of the conductor 203, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the first conductor of the conductor 203, even if a metal that is easily diffused, such as copper, is used in the second conductor of the conductor 203, which will be described later, the metal is the conductor 203. It is possible to suppress the diffusion from the first conductor.

Next, a conductive film to be the second conductor of the conductor 203 is formed over the conductive film to be the first conductor of the conductor 203. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film to be the second conductor of the conductor 203.

Next, by performing a CMP (Chemical Mechanical Polishing) process, the conductive film to be the first conductor of the conductor 203 and a part of the conductive film to be the second conductor of the conductor 203 are removed. The insulator 212 is exposed. As a result, the conductive film that becomes the first conductor of the conductor 203 and the conductive film that becomes the second conductor of the conductor 203 remain only in the opening. Thus, the conductor 203 including the first conductor of the conductor 203 and the second conductor of the conductor 203 having a flat upper surface can be formed (see FIG. 3). Note that part of the insulator 212 may be removed by the CMP treatment.

Next, an insulator 214 is formed over the insulator 212 and the conductor 203. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is formed as the insulator 214 by a CVD method. In this manner, by using an insulator that hardly transmits copper, such as silicon nitride, as the insulator 214, even if a metal that easily diffuses such as copper is used for the second conductor of the conductor 203, the metal is insulated. Diffusion to a layer above the body 214 can be suppressed.

Next, an insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 216 by a CVD method.

Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing.

After the opening is formed, a conductive film to be a first conductor of the conductor 205 is formed. The conductive film to be the first conductor of the conductor 205 preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the first conductor of the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, tantalum nitride is formed by a sputtering method as the conductive film to be the first conductor of the conductor 205.

Next, a conductive film to be the second conductor of the conductor 205 is formed over the conductive film to be the first conductor of the conductor 205. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as a conductive film to be the second conductor of the conductor 205, titanium nitride is formed by a CVD method, and tungsten is formed over the titanium nitride by a CVD method.

Next, by performing CMP treatment, the conductive film to be the first conductor of the conductor 205 and a part of the conductive film to be the second conductor of the conductor 205 are removed, and the insulator 216 is exposed. To do. As a result, the conductive film to be the first conductor of the conductor 205 and the conductive film to be the second conductor of the conductor 205 remain only in the opening. Thus, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 having a flat upper surface can be formed (see FIG. 3). Note that part of the insulator 216 may be removed by the CMP treatment.

Next, the insulator 220 is formed over the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 220 by a CVD method.

Next, an insulator 222 is formed on the insulator 220. As the insulator 222, an insulator including one or both of aluminum and hafnium may be formed. Note that as the insulator including one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water included in the structure provided around the transistor 200A to the inside of the transistor 200A through the insulator 222 is suppressed. In addition, generation of oxygen vacancies in the oxide 230 can be suppressed.

The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 3). In this embodiment, silicon oxide is formed as the insulator 224 by a CVD method.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or inert gas. May be.

In this embodiment, as the heat treatment, treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere after the insulator 224 is formed. By the heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed.

The heat treatment can also be performed at the timing after the insulator 220 is formed and after the insulator 222 is formed. Although the heat treatment conditions described above can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.

Here, in order to form an excess oxygen region in the insulator 224, plasma treatment including oxygen may be performed in a reduced pressure state. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. it can. Alternatively, plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.

Next, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 4). Note that the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.

The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the oxide film is formed by a sputtering method, the In-M-Zn oxide target can be used.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, more preferably 100%.

In the case where the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have a relatively high field-effect mobility.

In this embodiment, the oxide film 230A is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. The oxide film 230B is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Note that each oxide film is preferably formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In this embodiment mode, after processing for one hour at a temperature of 400 ° C. in a nitrogen atmosphere, the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.

Next, the oxide film 230A and the oxide film 230B are processed into island shapes to form the oxide 230a and the oxide 230b (see FIG. 5).

Here, the oxide 230 a and the oxide 230 b are formed so that at least a part thereof overlaps with the conductor 205. The side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200A are provided, the area can be reduced and the density can be increased. Note that the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.

Further, a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the oxide 230b. By not having a corner at the end, the coverage of the film in the subsequent film forming process is improved.

Note that the oxide film may be processed using a lithography method. For the processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.

In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, writing is performed directly on the resist, so that the resist exposure mask described above becomes unnecessary. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process. .

Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do. The etching of the oxide film 230A and the oxide film 230B may be performed after the resist mask is removed, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the oxide film is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

Further, by performing the above-described treatment such as dry etching, impurities due to an etching gas or the like may adhere to or diffuse on the surface or inside of the oxide 230a and the oxide 230b. Examples of impurities include fluorine and chlorine.

¡Clean to remove the above impurities. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.

As the wet cleaning, cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.

Next, an oxide film 230C to be the oxide 230c is formed over the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 6).

The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c. In this embodiment, the oxide film 230C is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].

Subsequently, an insulating film 250A, a metal oxide film 252A, a conductive film 260A, a conductive film 260B, an insulating film 270A, and an insulating film 271A are sequentially formed over the oxide film 230C (see FIG. 6).

First, an insulating film 250A is formed. The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, silicon oxynitride is preferably formed by a CVD method. Note that the deposition temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly preferably around 400 ° C. By forming the insulating film 250A at 400 ° C., an insulator with few impurities can be formed.

Note that oxygen can be introduced into the insulating film 250A by exciting oxygen with a microwave to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.

Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.

Subsequently, a metal oxide film 252A, a conductive film 260A, and a conductive film 260B are formed. As the metal oxide film 252A, an In—Ga—Zn oxide is formed by a sputtering method. As a formation method of the metal oxide film 252A, a sputtering method is preferably used in an atmosphere containing oxygen gas. By forming the metal oxide film 252A in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. The excess oxygen added to the insulating film 250 </ b> A can compensate oxygen vacancies in the oxide 230 by supplying oxygen to the oxide 230.

Here, as a means for forming the metal oxide film 252A, the insulating film 250A and the insulator 224 are formed while forming the metal oxide film 252A by forming the film in an oxygen gas atmosphere using a sputtering apparatus. Oxygen can be introduced into the. Further, by using one or both of aluminum and hafnium having barrier properties for the metal oxide film 252A, excess oxygen introduced into the insulating film 250A can be effectively contained.

The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, titanium nitride may be formed as the conductive film 260A, and tungsten may be formed as the conductive film 260B.

For example, a metal nitride may be formed as the conductive film 260A by a sputtering method. For example, in the case where an oxide semiconductor typified by an In—Ga—Zn oxide is used as the metal oxide film 252A, the carrier density of the metal oxide film 252A is increased when nitrogen or hydrogen is supplied. That is, it functions as an oxide conductor (OC: Oxide Conductor). Therefore, by forming a metal nitride as the conductive film 260A by a sputtering method, a constituent element (particularly nitrogen) in the metal nitride diffuses into the metal oxide film 252A, and the resistance of the metal oxide film 252A is reduced. Further, the resistance of the metal oxide film 252A is reduced due to damage (for example, sputtering damage) when the conductive film 260A is formed. Accordingly, the carrier density of the metal oxide film 252A is increased, and the conductivity of the metal oxide film 252A is increased.

Further, by stacking a low-resistance metal film as the conductive film 260B, a transistor with a low driving voltage can be provided.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed. Through this heat treatment, excess oxygen is added from the metal oxide film 252A to the insulating film 250A, and an excess oxygen region can be easily formed in the insulating film 250A.

The insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, the oxidation of the conductor 260 can be suppressed. Further, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed. In this embodiment, aluminum oxide is formed as the insulating film 270A by an ALD method.

The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 275A to be formed in a later step. Thus, the insulator 271 can be easily left on the conductor 260 when the insulator 275 is formed in a later step. In this embodiment, silicon oxide is formed by a CVD method as the insulating film 271A.

Next, the insulating film 271A is etched to form an insulator 271. Here, the insulator 271 functions as a hard mask. By providing the insulator 271, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 are substantially perpendicular to the top surface of the substrate. Can be formed.

Next, using the insulator 271 as a mask, the oxide film 230C, the insulating film 250A, the metal oxide film 252A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form the oxide 230c, the insulator 250, and the metal oxide The object 252, the conductor 260 (the conductor 260 a and the conductor 260 b), and the insulator 270 are formed (see FIG. 7).

In addition, the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.

Further, the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270 are preferably in the same plane.

The same surface shared by the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270 is substantially perpendicular to the upper surface of the substrate. It is preferable. That is, in the cross-sectional shape, the angle between the side surface of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 is preferably as large as possible. Note that a cross-sectional shape of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270, and the top surface of the oxide 230 may be formed at an acute angle. In that case, the angle formed by the side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 is preferably as large as possible.

Even after the above-described processing, a post-process may be performed without removing the hard mask (insulator 271).

Next, an insulating film 275A is formed to cover the oxide 230, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 8).

The insulating film 275A preferably includes an insulator having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with holes, or resin It is preferable to have. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes for the insulating film 275A because an excess oxygen region can be easily formed in the insulator 275 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Next, anisotropic etching is performed on the insulating film 275A to form the insulator 275 on side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 (FIG. 9). reference.). Note that in this step, the insulator 224 may be processed into an island shape. In that case, the insulator 222 can be used as an etching stopper film.

Note that although not illustrated, the insulator 275 may also remain on the side surface of the insulator 224. In that case, the film property of an interlayer film formed in a later process can be improved. In addition, since the structure in which the insulator 275 remains is formed in contact with the side surface of the insulator 224, the insulator 224 can be provided with an excess oxygen region.

Subsequently, a film 242A is formed over the insulator 224 and the oxide 230 through the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 275 (FIG. 10). Note that the film 242A has a thickness of 0.5 nm to 5 nm, preferably, 1 nm to 3 nm. As the film 242A, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used. The film 242A is a film containing a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. Note that the film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment is performed (see FIG. 11). By the heat treatment in an atmosphere containing nitrogen, the metal element which is a component of the film 242A is diffused from the film 242A to the oxide 230, or the metal element which is a component of the oxide 230 is diffused to the film 242A. Then, the film 242A can form a metal compound, and the resistance can be reduced. Since the oxide 230 and the film 242A form a metal compound to be in a relatively stable state, a highly reliable semiconductor device can be provided.

Here, a metal compound is formed using the metal element of the film 242A and the metal element of the oxide 230, whereby the layer 242 is obtained. In addition, a compound layer may be formed at the interface between the film 242A and the oxide 230. Note that the compound layer is a layer having a metal compound including the component of the film 242A and the component of the oxide 230. Note that in this specification, the layer 242 may include a compound layer. For example, as the compound layer, a layer in which the metal element of the oxide 230 and the metal element of the film 242A are alloyed may be formed. By alloying, the metal element is in a relatively stable state, and a highly reliable semiconductor device can be provided.

The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state.

Further, oxygen near the interface between the oxide 230 and the layer 242 may be absorbed by the layer 242. As a result, the resistance in the vicinity of the interface between the oxide 230 and the layer 242 is reduced (see FIG. 11). On the other hand, the layer 242 may be oxidized by oxygen absorbed from the oxide 230 to be an insulator, which may increase resistance.

At that time, a part of the oxide 230 and the metal element described above may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 is in a relatively stable state; thus, a highly reliable semiconductor device can be provided. Further, the layer 242 with increased resistance may be used as an interlayer film.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen), and has a higher resistance.

Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.

Further, in the case where a conductive region remains in the layer 242, it is oxidized by performing heat treatment in an oxidizing atmosphere to be an insulator and have high resistance. By leaving the layer 242 as an insulator, the layer 242 can function as an interlayer film.

In the formation process of the layer 242 or heat treatment, oxygen in the region 231 of the oxide 230 and the region 232 in the vicinity of the region 231 is absorbed by the layer 242, so that oxygen vacancies are generated in the region 231 and the region 232. May occur. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the region 231 and the region 232 of the oxide 230 are n-type and have low resistance.

Note that the layer 242 may be removed. For example, a dry etching method or a wet etching method can be used as a removal method. By removing the layer 242, hydrogen in the oxide 230 absorbed by the layer 242 can be removed at the same time. Accordingly, hydrogen which is an impurity in the transistor 200A can be reduced.

Subsequently, an insulator 273 is formed over the insulator 275 and the oxide 230 (see FIG. 12).

Further, the insulator 273 is preferably formed by a sputtering method. By using a sputtering method, an insulator with few impurities such as water or hydrogen can be formed. For example, aluminum oxide may be used as the insulator 273.

Further, by forming a film in an oxygen gas atmosphere using a sputtering apparatus, oxygen can be introduced into the insulator 275 while the insulator 273 is formed. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is used as the insulator 275, an excess oxygen region tends to be easily formed in the insulator 275. On the other hand, compared with the above-described silicon oxide, the oxide 230 tends to hardly form an excess oxygen region. In addition, an oxide film formed by a sputtering method may extract hydrogen from a deposition target structure. Therefore, for example, when an oxide film using a sputtering method is formed as the insulator 273, an excess oxygen region can be selectively formed in the insulator 275. At this time, since an excess oxygen region is hardly formed in the oxide 230, the resistance reduction region in the oxide 230 can be prevented from increasing in resistance. In addition, by absorbing hydrogen and water from the oxide 230 and the insulator 275, the hydrogen concentration in the oxide 230 and the insulator 275 can be reduced.

The insulator 275 in which the excess oxygen region is formed as described above can effectively supply oxygen from the excess oxygen region to the region 234 of the oxide 230.

With the above structure, each region of the oxide 230 can be formed in a self-aligning manner. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273, so that hydrogen in the oxide 230 can be reduced.

Next, the insulator 274 is formed over the insulator 273 (see FIG. 12). The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator 274 preferably does not use hydrogen gas as a deposition gas. By not using hydrogen gas, an insulating film with reduced hydrogen concentration can be formed. For example, as the insulator 274, silicon nitride may be formed by a CVD method using silane (SiH ₄ ) and nitrogen (N ₂ ) gas.

Next, an insulator 280 is formed over the insulator 274 (see FIG. 12). The insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used. . For example, silicon oxynitride may be used as the insulator 280.

Next, a part of the insulator 280 is removed. The insulator 280 is preferably formed so that the upper surface has flatness. For example, the insulator 280 may have a flat upper surface immediately after film formation. Alternatively, for example, the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.

Subsequently, an insulator 282 is formed on the insulator 280. The insulator 282 is preferably formed with a sputtering apparatus. With such a structure, hydrogen can be prevented from entering the structure below the insulator 282. Further, since hydrogen or water in the insulator 280 is absorbed by the insulator 282, the impurity concentration in the insulator 280 can be reduced.

Subsequently, an insulator 284 is formed over the insulator 282 (see FIG. 12). For example, as the insulator 284, an insulator containing oxygen such as a silicon oxide film or a silicon oxynitride film is formed by a CVD method. The insulator 284 preferably has a lower dielectric constant than the insulator 282. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

Next, an opening reaching the oxide 230 is formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the insulator 273. The opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 240a and the conductor 240b are provided in contact with the side surface of the oxide 230.

Next, a conductive film to be a first conductor of the conductor 240 and a conductive film to be a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when the openings are formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, and the insulator 273, the region having reduced resistance in the region 231 may be removed. In that case, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used as the first conductor of the conductor 240. That is, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen deficiency is formed in the contact region, and the resistance of the contact region between the oxide 230 and the conductor 240 is reduced. be able to. By reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured. Therefore, the first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium.

Next, by performing a CMP process, a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 284 is exposed. As a result, the conductor 240a and the conductor 240b having a flat upper surface can be formed by leaving the conductive film only in the opening (see FIG. 13).

Through the above steps, a semiconductor device including the transistor 200A can be manufactured. As illustrated in FIGS. 3 to 13, the transistor 200A can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

<Modification of semiconductor device>
Hereinafter, an example of a semiconductor device including the transistor 200A according to one embodiment of the present invention will be described with reference to FIGS.

Here, (A) in each figure shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A1-A2 in (A). Moreover, (C) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A3-A4 in (A). Moreover, (D) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A5-A6 in (A). In the top view of each drawing (A), some elements are omitted for clarity.

Note that in the semiconductor device illustrated in FIGS. 14 to 17, the structure having the same function as the structure of the semiconductor device illustrated in <Structure Example of Semiconductor Device> is denoted by the same reference numeral.

Hereinafter, the configuration of the semiconductor device will be described with reference to FIGS. In this item as well, the material described in detail in <Structural example of semiconductor device> can be used as the constituent material of the semiconductor device.

[Modification Example 1 of Semiconductor Device]
In the semiconductor device illustrated in FIG. 14, the side surface of the oxide 230 and a surface parallel to the substrate have a taper angle. Specifically, as illustrated in FIG. 14B, the taper angle (θ) may be 45 ° or more and 80 ° or less, and preferably 50 ° or more and 70 ° or less. When the oxide 230 has a tapered structure, the side surface of the oxide 230 can be exposed when anisotropic etching is performed on the insulator 275.

Therefore, the side surface of the oxide 230 is also in contact with the film 242A, a metal compound is formed, and the resistance can be reduced. That is, the region 231 can also be formed on the side surface of the oxide 230. In addition, since the oxide 230 has a tapered structure, the film property of a structure formed in an upper layer than the oxide 230 can be improved.

[Second Modification of Semiconductor Device]
The semiconductor device illustrated in FIG. 15 is different from the semiconductor device illustrated in <Structure example of semiconductor device> in that the insulated region of the layer 242 is removed. Specifically, as shown in FIG. 15, the layer 242 may remain only on the oxide 230. Alternatively, in the case where a metal compound is formed in the oxide 230, the layer 242 may be removed. Therefore, the region 231 may be formed only in the oxide 230.

Note that in the case where the layer 242 has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the layer 242. Thus, by removing the layer 242, hydrogen absorbed from the oxide 230 can also be removed. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced.

[Modification 3 of Semiconductor Device]
The semiconductor device illustrated in FIG. 16 is different from the semiconductor device illustrated in <Structure example of semiconductor device> in the shape of the conductor 240. That is, the semiconductor device described in <Structure Example of Semiconductor Device> has a structure in which the conductor 240 is provided in contact with the insulator 280, the insulator 282, and the insulator 284 which function as interlayer films. On the other hand, in the semiconductor device illustrated in FIG. 16, openings are formed in the insulator 273 and the insulator 274 to form the conductor 240. That is, the conductor 240 has a structure that does not contact the interlayer film. Accordingly, the impurity of the insulator functioning as an interlayer film can be prevented from diffusing into the transistor 200A through the conductor 240. Therefore, an insulator having a barrier property is preferably provided over the conductor 240.

[Modification 4 of Semiconductor Device]
The semiconductor device illustrated in FIG. 17 is different from the semiconductor device illustrated in <Structure Example of Semiconductor Device> between the conductor 240 and the insulator 280, the insulator 282, and the insulator 284 that function as an interlayer film. The difference is that an insulator 276 (insulator 276a and insulator 276b) which functions as a layer is provided. Note that in the case of this structure, the insulator 276 and the insulator 282 preferably have barrier properties against oxygen, hydrogen, and water.

Specifically, as illustrated in FIG. 17, an insulator 276 may be provided between the conductor 240, the insulator 280, and the insulator 282 having a barrier property. In particular, the insulator 276 is preferably provided in contact with the insulator 282 having a barrier property. When the insulator 276 and the insulator 282 are provided in contact with each other, the insulator 276 extends to the insulator 284, so that diffusion of oxygen and impurities can be further suppressed.

That is, by providing the insulator 276, impurities included in the insulator 280 can be prevented from diffusing into the transistor 200A through the conductor 240, thereby reducing the reliability of the semiconductor device. In addition, the provision of the insulator 276 can increase the range of materials for conductors used for plugs and wirings.

For the insulator 276, for example, a metal oxide can be used. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 2)
An example of a semiconductor device including the transistor 200B according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 200A described in Embodiment 1, will be described below.

Note that in the semiconductor device described in this embodiment, the structure having the same function as the structure of the semiconductor device described in the above embodiment is denoted by the same reference numeral. Therefore, a description is mainly given of differences from the semiconductor device described in the above embodiment, and a repetitive description is omitted. Furthermore, in the case where there is no particular description of a material, a function, a manufacturing method, or the like of a structure denoted by the same reference numeral, the contents described in the above embodiments are referred to for the material, function, a manufacturing method, and the like of the structure. be able to.

<Configuration example of semiconductor device>
18A, 18B, 18C, and 18D are a top view and a cross-sectional view of the transistor 200B according to one embodiment of the present invention and the periphery of the transistor 200B.

FIG. 18A is a top view of a semiconductor device including a transistor 200B. 18B, 18C, and 18D are cross-sectional views of the semiconductor device. Here, FIG. 18B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 18A and also a cross-sectional view in the channel length direction of the transistor 200B. FIG. 18C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 18A and also a cross-sectional view in the channel width direction of the transistor 200B. FIG. 18D is a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 18A and is a cross-sectional view of the source region or the drain region of the transistor 200B. Note that in the top view of FIG. 18A, some elements are omitted for clarity.

The semiconductor device of one embodiment of the present invention includes the transistor 200B, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 280, the insulator 282, and the insulator 284. In addition, a conductor 203 which is electrically connected to the transistor 200B and functions as a wiring and a conductor 240 (a conductor 240a and a conductor 240b) which function as a plug are included.

The conductor 240 is formed in contact with the inner wall of the opening of the insulator 275, the insulator 273, the insulator 274, the insulator 280, the insulator 282, and the insulator 284. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 284 can be approximately the same. Note that although a structure in which the conductor 240 has a two-layer structure is shown in this embodiment mode, the present invention is not limited to this. For example, the conductor 240 may be a single layer or a stacked structure of three or more layers.

[Transistor 200B]
A transistor 200B illustrated in FIG. 18 includes at least an oxide 230c, an insulator 250, a metal oxide 252, and an insulator 272 disposed in contact with a side surface of the conductor 260, the oxide 230, and the insulator 272. A layer 242 disposed; an insulator 275 disposed on the layer 242; an insulator 273 disposed on the insulator 275; and an insulator 274 disposed on the insulator 273. This is different from the transistor 200A described in Embodiment 1.

In the transistor 200B, an oxide semiconductor is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

Since the transistor 200B using an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200B included in a highly integrated semiconductor device.

Here, an oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements included in the oxide semiconductor, and has low resistance. Turn into. Note that aluminum, titanium, tantalum, tungsten, or the like is preferably used.

In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film, and oxygen vacancies are formed. The vicinity of the interface may be reduced in resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, a metal element which is a component of the film is converted into an oxide semiconductor or a component of an oxide semiconductor from a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. A certain metal element diffuses into the film, and the oxide semiconductor and the film form a metal compound, so that resistance can be reduced. The metal element added to the oxide semiconductor is in a relatively stable state by forming a metal compound with the oxide semiconductor, the metal element, and thus a highly reliable semiconductor device can be provided.

Further, a compound layer (different layer) may be formed at the interface between the metal film, the nitride film containing the metal element, or the oxide film containing the metal element and the oxide semiconductor. Note that a compound layer (different layer) is a layer having a metal compound including a metal film, a nitride film containing a metal element, or a component of an oxide film containing a metal element and a component of an oxide semiconductor. For example, a layer in which a metal element of an oxide semiconductor and an added metal element are alloyed may be formed as the compound layer. The alloyed layer is in a relatively stable state, and a highly reliable semiconductor device can be provided.

In addition, hydrogen existing in the oxide semiconductor diffuses into a region where the resistance of the oxide semiconductor is reduced, and becomes relatively stable when it enters oxygen vacancies existing in the region where the resistance is reduced. In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. Has been found to be relatively stable. Accordingly, a region where the resistance of the oxide semiconductor is reduced by heat treatment or a region where the metal compound is formed is further reduced, and an oxide semiconductor which is not reduced in resistance is highly purified (impurities such as water and hydrogen). There is a tendency to increase resistance.

In addition, in an oxide semiconductor, the carrier density increases when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancy, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

Here, FIG. 19 shows an enlarged view of a region 239 including the oxide 230b selectively reduced in resistance, which is surrounded by a broken line in FIG. 18B.

As illustrated in FIG. 19, the oxide 230 includes a region 234 that functions as a channel formation region of a transistor, a region 231 (a region 231 a and a region 231 b) that functions as a source region or a drain region, a region 234, and a region 231. And a region 232 (region 232a and region 232b) provided between the two.

The region 232 has a region overlapping with the insulator 272.

In order to reduce the resistance of the region 231, for example, the layer 242 may be formed in contact with the region 231 of the oxide 230. As the layer 242, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like can be used. The layer 242 is preferably provided over the oxide 230 with at least the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, the insulator 271, and the insulator 272 interposed therebetween.

When the oxide 230 and the layer 242 are in contact with each other, the component of the layer 242 and the component of the oxide 230 form a metal compound, which becomes a region 231 and has a low resistance. In addition, part of oxygen in the oxide 230 located in the vicinity of the interface between the oxide 230 and the layer 242 or in the vicinity of the interface is absorbed by the layer 242, and oxygen vacancies are formed in the oxide 230. 231 may be formed.

Further, heat treatment may be performed in an atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. Through the heat treatment, the metal element which is a component of the layer 242 is diffused from the layer 242 to the oxide 230 or the metal element which is a component of the oxide 230 is diffused to the layer 242, so that the oxide 230 and the layer 242 are formed. A metal compound is formed to reduce resistance. At that time, the metal element of the oxide 230 and the metal element of the layer 242 may be alloyed. When the metal element of the oxide 230 and the metal element of the layer 242 are alloyed, the metal element is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen), and has a higher resistance.

On the other hand, in the regions (region 234 and region 232) overlapping with the conductor 260 and the insulator 272 of the oxide 230, addition of a metal element is suppressed by the conductor 260 and the insulator 272. In addition, in the region 234 and the region 232 of the oxide 230, oxygen atoms in the oxide 230 are suppressed from being absorbed into the layer 242 described above.

Further, when the layer 242 absorbs oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231, oxygen vacancies may be generated in the region 231 and the region 232. As hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the resistance of the region 231 and the region 232 of the oxide 230 is reduced.

Here, in the case where the layer 242 has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Further, the layer 242 may be removed together with hydrogen absorbed from the oxide 230 in a later step.

Note that the layer 242 is not necessarily removed. For example, if the layer 242 is insulated and has a high resistance, it may remain. For example, the layer 242 may be oxidized by oxygen absorbed from the oxide 230 to be an insulator and have high resistance. In that case, the layer 242 may function as an interlayer film.

Further, for example, in the case where a conductive region remains in the layer 242, it is oxidized by heat treatment to become an insulator, and the resistance is increased. The heat treatment is preferably performed in an oxidizing atmosphere, for example. In the case where there is a structure including oxygen in the vicinity of the layer 242, the layer 242 may react with oxygen included in the structure and be oxidized by heat treatment.

By leaving the layer 242 as an insulator, it can function as an interlayer film. In the case of the structure, the layer 242 is provided with a thickness that can be insulated in a later step. For example, the layer 242 may be provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. Note that in the case where the heat treatment is performed in the above oxidizing atmosphere, it is preferable that the heat treatment is performed once in the atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. By performing heat treatment once in an atmosphere containing nitrogen, oxygen in the oxide 230 can easily diffuse into the layer 242.

Here, in a transistor including an oxide semiconductor, if an impurity and an oxygen vacancy exist in a region where a channel is formed in the oxide semiconductor, electric characteristics may be easily changed and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

Therefore, as illustrated in FIG. 19, it is preferable to provide an insulator 275 that contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition in the vicinity of the oxide 230. The excess oxygen included in the insulator 275 passes through the layer 242 and diffuses into the oxide 230, so that oxygen vacancies in the oxide 230 can be reduced.

That is, excess oxygen contained in the insulator 275 diffuses into the region 234 of the oxide 230, whereby oxygen vacancies in the region 234 of the oxide 230 can be reduced. On the other hand, oxygen vacancies formed in the region 231 of the oxide 230 are also compensated by oxygen supplied from the insulator 275. However, the low resistance region formed in the oxide 230 and the layer 242 is stable because the metal compound is formed. Therefore, lower resistance can be maintained than in the region 234 where the metal compound is not formed.

In order to provide an excess oxygen region in the insulator 275, an oxide film may be formed as the insulator 273 in contact with the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide, an insulator with few impurities such as water or hydrogen can be formed.

By introducing excess oxygen into the insulator 275, an excess oxygen region can be formed in the insulator 275. Excess oxygen in the insulator 275 is supplied to the oxide 230 so that oxygen vacancies in the oxide 230 can be compensated.

The insulator 273 is preferably made of aluminum oxide. Aluminum oxide may extract hydrogen in the oxide 230 by performing heat treatment in the state of being close to the oxide 230. Note that in the case where the layer 242 and the insulator 275 are provided between the oxide 230 and aluminum oxide, the hydrogen in the layer 242 and the insulator 275 is absorbed by the aluminum oxide, and the hydrogen is reduced. 242 may absorb hydrogen in the oxide 230. Therefore, the hydrogen concentration in the oxide 230 can be reduced. In addition, oxygen may be supplied from the insulator 273 to the oxide 230, the insulator 224, or the insulator 222 by performing heat treatment in a state where the insulator 273 and the oxide 230 are in proximity to each other.

The oxide 230 can be selectively reduced in resistance by combining the above structure or the above steps.

That is, when forming a low resistance region in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260 functioning as a gate electrode and the insulator 272 as a mask. Therefore, when the plurality of transistors 200B are formed at the same time, variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200B is determined by the width of the conductor 260 and the film thickness of the insulator 272. By setting the width of the conductor 260 to the minimum processing dimension, the transistor 200B can be miniaturized.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, differences in the structure of the semiconductor device including the transistor 200B according to one embodiment of the present invention from the semiconductor device including the transistor 200A described in Embodiment 1 will be described.

The region 232 has at least a region overlapping with the insulator 272.

Further, it is preferable to dispose an insulator 271 functioning as a hard mask over the insulator 270. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle formed between the side surface of the conductor 260 and the substrate surface is 75 ° to 100 °, Preferably, it can be 80 ° or more and 95 ° or less. By processing the conductor 260 into such a shape, the insulator 272 to be formed next can be formed into a desired shape.

The insulator 272 functioning as a buffer layer is provided in contact with the side surface of the oxide 230 c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270. Note that the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 272 also has a function as a barrier layer.

For example, the insulator 272 is preferably formed using an ALD method. By using the ALD method, a dense thin film can be formed. For the insulator 272, for example, aluminum oxide, hafnium oxide, or the like is preferably used. In the case where aluminum oxide is provided using the ALD method as the insulator 272, the thickness of the insulator 272 is preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm.

By providing the insulator 272, side surfaces of the insulator 250, the metal oxide 252, and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Therefore, entry of impurities such as hydrogen and water into the oxide 230 from the insulator 250, the end portions of the metal oxide 252, and the like can be suppressed. Therefore, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200B can be improved. That is, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulator.

An insulator 275 is provided over the oxide 230, the insulator 272, and the insulator 271. The insulator 275 having an excess oxygen region is provided in the vicinity of the oxide 230.

For example, as the insulator 275, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 275 preferably has an excess oxygen region. By providing an insulator from which oxygen is released by heating as the insulator 275 in contact with the oxide 230c and the insulator 250, oxygen is effectively supplied from the insulator 250 to the region 234 of the oxide 230b. be able to. In addition, the concentration of impurities such as water or hydrogen in the insulator 275 is preferably reduced.

By providing the insulator 272 and the insulator 275, excess oxygen included in the insulator 275 can be supplied to the oxide 230 while suppressing oxidation of the conductor 260. In other words, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230, so that oxygen vacancies in the region 234 of the oxide 230 are reduced, so that the region 234 of the oxide 230 has higher resistance. To do. On the other hand, oxygen vacancies formed in the region 231 of the oxide 230 are similarly compensated by oxygen supplied from the insulator 275.

However, the low resistance region formed in the oxide 230 and the layer 242 is stable because a metal compound is formed. Therefore, lower resistance can be maintained than in the region 234 where the metal compound is not formed.

The insulator 273 is provided over at least the region 231 of the oxide 230 and the insulator 275. By depositing the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275. Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region. In addition, by providing the insulator 273 over the region 231 of the oxide 230, hydrogen in the oxide 230 can be extracted to the insulator 273.

For example, as the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm.

In addition, the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the insulator 275.

Note that a conductor 240a is formed in contact with the inner wall of the opening of the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the insulator 275. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, the insulator 240, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the conductor 240b are formed in contact with the inner walls of the openings of the insulator 275. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

Here, for example, when an opening is formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the insulator 275, the region in which the resistance of the region 231 is reduced in the oxide 230 May be removed, and the oxide 230 that is not reduced in resistance may be exposed. In that case, a metal film, a nitride film containing a metal element, or a metal element is used as a conductor used for a conductor in contact with the oxide 230 of the conductor 240 (hereinafter also referred to as a first conductor of the conductor 240). It is preferable to use an oxide film having the same. That is, when the oxide 230 whose resistance is not reduced and the first conductor of the conductor 240 are in contact with each other, oxygen vacancies are formed in the metal compound or the oxide 230, and the first conductor of the conductor 240 The resistance of the oxide 230 in contact with the oxide is reduced. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. Therefore, the first conductor of the conductor 240 preferably includes a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten.

In the case where the conductor 240 has a stacked structure, the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the conductor in contact with the insulator 275 include the first of the conductor 205. Like a conductor, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from the upper layer than the insulator 280 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including the transistor 200B according to the present invention will be described with reference to FIGS. 20 to 25, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A1-A2 in (A). Moreover, (C) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A3-A4 in (A). Moreover, (D) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A5-A6 in (A).

The manufacturing method of the semiconductor device illustrated in FIG. 18 is similar to the manufacturing method of the semiconductor device illustrated in FIG. 1 until the insulator 271 is formed. Therefore, the method for manufacturing the semiconductor device according to FIGS. 3 to 7 can be referred to.

Note that the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260. In this embodiment, silicon oxide is formed by a CVD method as the insulating film 271A.

After the insulator 271 is formed, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 20). .

The insulating film 272A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by an ALD method having excellent coverage. By using the ALD method, even in a step portion formed by the conductor 260 or the like, an insulation having a uniform thickness with respect to the side surfaces of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270. A film 272A can be formed. In addition, a dense thin film can be formed by using the ALD method.

On the other hand, aluminum oxide having a barrier property or the like may be provided as the insulating film 272A. For example, in the case where the conductor 260 is a metal film that is easily oxidized, an insulator having a barrier property can be used to suppress the conductor 260 from being oxidized by oxygen from above the insulating film 272A. Thereby, it can suppress that the resistance value of the conductor 260 goes up.

In the case where aluminum oxide is provided using the ALD method as the insulating film 272A, the thickness of the insulating film 272A is preferably 0.5 nm to 3.0 nm. With this structure, excess oxygen included in the insulator 275 can be supplied to the oxide 230 and the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, anisotropic etching is performed on the insulating film 272A to form the insulator 272 on side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 (FIG. 21). reference).

As the anisotropic etching process, it is preferable to perform a dry etching process. Thus, the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.

Note that in this step, the insulator 224 may be processed into an island shape. In that case, the insulator 222 can be used as an etching stopper film.

Subsequently, a film 242A is formed over the insulator 224 and the oxide 230 through the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 272 (FIG. 22). For the material, the deposition method, and the like of the film 242A, the film 242A in Embodiment 1 can be referred to.

Subsequently, heat treatment is performed (see FIG. 23). By the heat treatment in an atmosphere containing nitrogen, the metal element which is a component of the film 242A is diffused from the film 242A to the oxide 230, or the metal element which is a component of the oxide 230 is diffused to the film 242A. Then, the film 242A can form a metal compound, and the resistance can be reduced. Since the oxide 230 and the film 242A form a metal compound to be in a relatively stable state, a highly reliable semiconductor device can be provided.

Here, a metal compound is formed using the metal element of the film 242A and the metal element of the oxide 230, whereby the layer 242 is obtained. In addition, a compound layer may be formed at the interface between the film 242A and the oxide 230. Note that the compound layer is a layer having a metal compound including the component of the film 242A and the component of the oxide 230. Note that in this specification, the layer 242 may include a compound layer. For example, as the compound layer, a layer in which the metal element of the oxide 230 and the metal element of the film 242A are alloyed may be formed. By alloying, the metal element is in a relatively stable state, and a highly reliable semiconductor device can be provided.

The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state.

Further, oxygen near the interface between the oxide 230 and the layer 242 may be absorbed by the layer 242. As a result, the resistance in the vicinity of the interface between the oxide 230 and the layer 242 is reduced (see FIG. 23). On the other hand, the layer 242 may be oxidized by oxygen absorbed from the oxide 230 to be an insulator, which may increase resistance.

At that time, a part of the oxide 230 and the metal element described above may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 is in a relatively stable state; thus, a highly reliable semiconductor device can be provided. Further, the layer 242 with increased resistance may be used as an interlayer film.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen), and has a higher resistance.

Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.

Further, in the case where a conductive region remains in the layer 242, it is oxidized by performing heat treatment in an oxidizing atmosphere to be an insulator and have high resistance. By leaving the layer 242 as an insulator, the layer 242 can function as an interlayer film.

In the formation process of the layer 242 or heat treatment, oxygen in the region 231 of the oxide 230 and the region 232 in the vicinity of the region 231 is absorbed by the layer 242, so that oxygen vacancies are generated in the region 231 and the region 232. May occur. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the region 231 and the region 232 of the oxide 230 are n-type and have low resistance.

Note that the layer 242 may be removed. For example, a dry etching method or a wet etching method can be used as a removal method. By removing the layer 242, hydrogen in the oxide 230 absorbed by the layer 242 can be removed at the same time. Accordingly, hydrogen which is an impurity in the transistor 200B can be reduced.

Subsequently, an insulator 275 is formed over the layer 242 (see FIG. 24). For the material of the insulator 275, the insulating film 275A in Embodiment 1 can be referred to.

Note that although not illustrated, the insulator 275 may also remain on the side surface of the insulator 224. In that case, the film property of an interlayer film formed in a later process can be improved. In addition, since the structure in which the insulator 275 remains is formed in contact with the side surface of the insulator 224, the insulator 224 can be provided with an excess oxygen region.

Subsequently, an insulator 273 is formed over the insulator 275 (see FIG. 24). The insulator 273 in Embodiment 1 can be referred to for the material of the insulator 273, the deposition method, and the like.

Further, by forming a film in an oxygen gas atmosphere using a sputtering apparatus, oxygen can be introduced into the insulator 275 while the insulator 273 is formed. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is used as the insulator 275, an excess oxygen region tends to be easily formed in the insulator 275. In addition, an oxide film formed by a sputtering method may extract hydrogen from a deposition target structure. Therefore, for example, when an oxide film using a sputtering method is formed as the insulator 273, an excess oxygen region can be selectively formed in the insulator 275. In addition, by absorbing hydrogen and water from the insulator 275, the hydrogen concentration of the insulator 275 can be reduced.

The insulator 275 in which the excess oxygen region is formed as described above can effectively supply oxygen from the excess oxygen region to the oxide 230. In other words, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230, so that oxygen vacancies in the region 234 of the oxide 230 are reduced, so that the region 234 of the oxide 230 has higher resistance. To do. On the other hand, oxygen vacancies formed in the region 231 of the oxide 230 are similarly compensated by oxygen supplied from the insulator 275.

However, the low resistance region formed in the oxide 230 and the layer 242 is stable because a metal compound is formed. Therefore, lower resistance can be maintained than in the region 234 where the metal compound is not formed.

With the above structure, each region of the oxide 230 can be formed in a self-aligning manner. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273, so that hydrogen in the oxide 230 can be reduced.

Next, the insulator 274, the insulator 280, the insulator 282, and the insulator 284 are sequentially formed over the insulator 273 (see FIG. 24). Note that the materials and formation methods of the insulator 274, the insulator 280, the insulator 282, and the insulator 284 are the same as those of the insulator 274, the insulator 280, the insulator 282, and the insulator 284 of Embodiment 1, respectively. You can visit.

Next, an opening reaching the oxide 230 is formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the insulator 275. The opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 240a and the conductor 240b are provided in contact with the side surface of the oxide 230.

Next, a conductive film to be a first conductor of the conductor 240 and a conductive film to be a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when the opening is formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the insulator 275, the region where the resistance is reduced in the region 231 may be removed. is there. In that case, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used as the first conductor of the conductor 240. That is, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen deficiency is formed in the contact region, and the resistance of the contact region between the oxide 230 and the conductor 240 is reduced. be able to. By reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured. Therefore, the first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium.

Next, by performing a CMP process, a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 284 is exposed. As a result, the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIG. 25).

Through the above steps, a semiconductor device including the transistor 200B can be manufactured. As illustrated in FIGS. 20 to 25, the transistor 200B can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

<Modification of semiconductor device>
Hereinafter, an example of a semiconductor device including the transistor 200B according to one embodiment of the present invention will be described with reference to FIGS.

Here, (A) in each figure shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A1-A2 in (A). Moreover, (C) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A3-A4 in (A). Moreover, (D) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A5-A6 in (A). In the top view of each drawing (A), some elements are omitted for clarity.

Note that, in the semiconductor device illustrated in FIGS. 26 to 29, the structure having the same function as the structure of the semiconductor device illustrated in <Structure Example of Semiconductor Device> is denoted by the same reference numeral.

Hereinafter, the configuration of the semiconductor device will be described with reference to FIGS. Note that in this item as well, the material described in detail in the above embodiment and <Example of Configuration of Semiconductor Device> can be used as the constituent material of the semiconductor device.

[Modification Example 1 of Semiconductor Device]
In the semiconductor device illustrated in FIG. 26, the side surface of the oxide 230 and a surface parallel to the substrate have a taper angle. Specifically, as illustrated in FIG. 26B, the taper angle (θ) may be 45 ° to 80 °, preferably 50 ° to 70 °. When the oxide 230 has a tapered structure, the side surface of the oxide 230 can be exposed when anisotropic etching is performed on the insulator 272.

Therefore, the side surface of the oxide 230 is also in contact with the film 242A, a metal compound is formed, and the resistance can be reduced. That is, the region 231 can also be formed on the side surface of the oxide 230. In addition, since the oxide 230 has a tapered structure, the film property of a structure formed in an upper layer than the oxide 230 can be improved.

[Second Modification of Semiconductor Device]
The semiconductor device illustrated in FIG. 27 is different from the semiconductor device illustrated in <Structure example of semiconductor device> in that the insulated region of the layer 242 is removed. Specifically, as shown in FIG. 27, the layer 242 may remain only on the oxide 230. Alternatively, in the case where a metal compound is formed in the oxide 230, the layer 242 may be removed. Therefore, the region 231 may be formed only in the oxide 230.

Note that in the case where the layer 242 has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the layer 242. Thus, by removing the layer 242, hydrogen absorbed from the oxide 230 can also be removed. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced.

[Modification 3 of Semiconductor Device]
The semiconductor device illustrated in FIG. 28 is different from the semiconductor device illustrated in <Structure example of semiconductor device> in the shape of the conductor 240. That is, the semiconductor device described in <Structure Example of Semiconductor Device> has a structure in which the conductor 240 is provided in contact with the insulator 280, the insulator 282, and the insulator 284 which function as interlayer films. On the other hand, in the semiconductor device illustrated in FIG. 28, openings are formed in the insulator 275, the insulator 273, and the insulator 274 to form the conductor 240. That is, the conductor 240 has a structure that does not contact the interlayer film. Therefore, the impurity of the insulator functioning as an interlayer film can be prevented from diffusing into the transistor 200B through the conductor 240. Therefore, an insulator having a barrier property is preferably provided over the conductor 240.

[Modification 4 of Semiconductor Device]
The semiconductor device illustrated in FIG. 29 is different from the semiconductor device illustrated in <Structure Example of Semiconductor Device> between the conductor 240 and the insulator 280, the insulator 282, and the insulator 284 functioning as an interlayer film. The difference is that an insulator 276 (insulator 276a and insulator 276b) which functions as a layer is provided. Note that in the case of this structure, the insulator 276 and the insulator 282 preferably have barrier properties against oxygen, hydrogen, and water.

Specifically, as illustrated in FIG. 29, an insulator 276 may be provided between the conductor 240, the insulator 280, and the insulator 282 having a barrier property. In particular, the insulator 276 is preferably provided in contact with the insulator 282 having a barrier property. When the insulator 276 and the insulator 282 are provided in contact with each other, the insulator 276 extends to the insulator 284, so that diffusion of oxygen and impurities can be further suppressed.

That is, by providing the insulator 276, impurities included in the insulator 280 can be prevented from diffusing into the transistor 200B through the conductor 240, thereby reducing the reliability of the semiconductor device. In addition, the provision of the insulator 276 can increase the range of materials for conductors used for plugs and wirings.

For the insulator 276, for example, a metal oxide can be used. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 3)
An example of a semiconductor device including the transistor 200C according to one embodiment of the present invention is described below.

Note that in the semiconductor device described in this embodiment, the structure having the same function as the structure of the semiconductor device described in the above embodiment is denoted by the same reference numeral. Therefore, a description is mainly given of differences from the semiconductor device described in the above embodiment, and a repetitive description is omitted. Further, in the case where there is no particular description of a material, a manufacturing method, or the like having a structure with the same symbol, the contents described in the above embodiment modes can be referred to for the material, the manufacturing method, and the like of the structure.

<Configuration example of semiconductor device>
30A to 30D are a top view and a cross-sectional view of the transistor 200C according to one embodiment of the present invention and the periphery of the transistor 200C.

FIG. 30A is a top view of a semiconductor device having a transistor 200C. FIGS. 30B, 30C, and 30D are cross-sectional views of the semiconductor device. Here, FIG. 30B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 30A and also a cross-sectional view in the channel length direction of the transistor 200C. FIG. 30C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 30A and also a cross-sectional view in the channel width direction of the transistor 200C. FIG. 30D is a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 30A and also a cross-sectional view of the source region or the drain region of the transistor 200C. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The semiconductor device of one embodiment of the present invention includes the transistor 200C, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 280, and the insulator 282. In addition, a conductor 203 which is electrically connected to the transistor 200C and functions as a wiring, and a conductor 240 which functions as a plug are included.

Note that, in the conductor 203, the first conductor 203a of the conductor 203 is formed in contact with the inner wall of the opening of the insulator 212, and the second conductor 203b of the conductor 203 is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be approximately the same. Note that although the transistor 200C illustrates a structure in which the first conductor 203a of the conductor 203 and the second conductor 203b of the conductor 203 are stacked, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a stacked structure including three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

In addition, the conductor 240 is in contact with the inner walls of the openings of the insulator 280 and the insulator 282 to form the first conductor of the conductor 240, and further, the second conductor of the conductor 240 is formed inside. ing. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be approximately the same. Note that although the transistor 200C illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

[Transistor 200C]
As illustrated in FIG. 30, the transistor 200C includes an insulator 214 and an insulator 216 which are disposed over a substrate (not illustrated), and a conductor 205 which is disposed so as to be embedded in the insulator 214 and the insulator 216. An insulator 220 disposed on the insulator 216 and the conductor 205, an insulator 222 disposed on the insulator 220, an insulator 224 disposed on the insulator 222, and an insulator Oxide 230 disposed on 224 (oxide 230a, oxide 230b, and oxide 230c), insulator 250 disposed on oxide 230, and conductor disposed on insulator 250 260 (conductor 260a and conductor 260b), insulator 271 disposed on conductor 260, at least oxide 230c, insulator 250, and conductor 260 Surface in contact, and have an oxide insulator 272 disposed part the contact of the upper surface of the 230b, and the insulator 273 disposed on a side face of the conductor 260 through an insulator 272, a.

In the transistor 200C, an oxide semiconductor is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

Since the transistor 200C using an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a low power consumption semiconductor device can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200C included in a highly integrated semiconductor device.

Here, an oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements included in the oxide semiconductor, and has low resistance. Turn into. Note that aluminum, titanium, tantalum, tungsten, or the like is preferably used. In order to add the metal element to the oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film and the like, thereby forming oxygen vacancies and oxidation. The vicinity of the interface of the physical semiconductor may have a low resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element diffuses from the metal film into the oxide semiconductor, and the metal element can be added to the oxide semiconductor. At that time, the oxide semiconductor and the metal element may be alloyed. When the oxide semiconductor and the metal element are alloyed, the metal element added to the oxide semiconductor is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

In addition, hydrogen existing in the oxide semiconductor diffuses into a region where the resistance of the oxide semiconductor is reduced, and becomes relatively stable when it enters oxygen vacancies existing in the region where the resistance is reduced. In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. Has been found to be relatively stable. Therefore, the resistance of the oxide semiconductor or the region where the metal compound is formed by heat treatment is further reduced, and the oxide semiconductor that is not reduced in resistance is highly purified (impurities such as water and hydrogen). There is a tendency to increase resistance.

In addition, in an oxide semiconductor, the carrier density increases when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen deficiency, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, a high resistance region and a low resistance region can be provided in the oxide semiconductor by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

Here, FIG. 31 shows an enlarged view of a region 239 including the oxide 230b which is selectively reduced in resistance and is surrounded by a broken line in FIG.

As illustrated in FIG. 31, the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200C, a region 231 (region 231a and region 231b) functioning as a source region or a drain region, a region 234, and a region 231. And a region 232 (region 232a and region 232b) provided between the first and second regions.

For example, the region 231 preferably includes one or more metal elements selected from metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium in addition to the oxide 230. By adding a metal element to the oxide 230, the resistance of the region 231 can be reduced. Note that the region 231 may include a region in which the metal element in the oxide 230 and the added metal element are alloyed.

The region 232 has a region overlapping with the insulator 272. The region 232 preferably has a higher concentration of at least one of a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium and an impurity element such as hydrogen and nitrogen than the region 234. In order to form the region 232, for example, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be provided in contact with the region 231 of the oxide 230. Accordingly, the metal element in the film is added to the oxide semiconductor, and a metal compound may be formed in the oxide semiconductor. The metal compound may attract hydrogen contained in the oxide 230 in some cases. Thereby, the hydrogen concentration in the region 232 in the vicinity of the region 231 may increase.

Note that one or both of the region 232 a and the region 232 b may have a region overlapping with the conductor 260. With this structure, the conductor 260 can overlap the region 232a and the region 232b.

In FIGS. 30 and 31, the region 234, the region 231 and the region 232 are formed in the oxide 230b, but the present invention is not limited to this. For example, these regions may be formed in the oxide 230a or the oxide 230c. In FIGS. 30 and 31, the boundary between the regions is displayed substantially perpendicular to the top surface of the oxide 230, but this embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 near the surface of the oxide 230b and recede toward the conductor 240a or the conductor 240b near the lower surface of the oxide 230b.

In addition, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to stepwise changes between the regions, but also continuously change (also referred to as gradation) within each region. May be. That is, the closer to the channel formation region, the lower the concentration of the metal element and impurity elements such as hydrogen and nitrogen.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity, such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and an impurity may be added to a desired region. Good. Note that as the impurity, an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used. Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

Therefore, the region 231 has a high carrier density and a low resistance by increasing the content of the above-described metal element that increases conductivity, an element that forms oxygen vacancies, or an element that is trapped by oxygen vacancies. be able to.

In order to reduce the resistance of the region 231, for example, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like may be formed in contact with the region 231 of the oxide 230. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized through at least the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 273. It is preferable to provide on the object 230b.

By providing a metal film, a nitride film containing a metal element, or an oxide film containing a metal element in contact with the region 231 of the oxide 230, the metal element diffuses from the film into the region 231 of the oxide 230. A metal compound is formed at 231 to reduce resistance. In addition, part of oxygen in the oxide 230 located in the vicinity of the interface between the region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element or in the vicinity of the interface is absorbed by the film, In some cases, oxygen vacancies are formed in the region 231 to reduce resistance. Note that in FIG. 31, a region where the resistance of the oxide 230 is reduced is represented by oblique lines as an example. Note that in this specification and the like, the range represented by the oblique lines is not limited to the range shown in FIG. For example, the low resistance region (or range) is formed in a region near the interface between the oxide 230 and the conductor 240 or a region in the region 231 from the upper surface of the oxide 230 to the lower surface of the oxide 230. There is a case. The same applies to other drawings.

Further, heat treatment may be performed in an atmosphere containing nitrogen in a state where the region 231 is in contact with a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. By the heat treatment, the metal element is diffused from the metal film to the region 231 of the oxide 230, and the metal element can be added to the region 231. At that time, the region 231 of the oxide 230 and the metal element may be alloyed. When the region 231 of the oxide 230 and the metal element are alloyed, the metal element added to the oxide semiconductor is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and has a higher resistance.

On the other hand, in the regions (region 234 and region 232) overlapping with the conductor 260 and the insulator 272 of the oxide 230, addition of a metal element is suppressed by the conductor 260 and the insulator 272. Further, in the region 234 and the region 232 of the oxide 230, oxygen atoms in the oxide 230 are suppressed from being absorbed into the metal film, the nitride film containing a metal element, or the oxide film containing a metal element. The

Further, the region 231 of the oxide 230 and the region 232 adjacent to the region 231 are absorbed by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element, whereby the region 231 and the region Oxygen deficiency may occur in 232. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the resistance of the region 231 and the region 232 of the oxide 230 is reduced.

Here, in the case where a metal film, a nitride film containing a metal element, or an oxide film containing a metal element has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Further, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element may be removed together with hydrogen absorbed from the oxide 230 in a later step.

Note that the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is not necessarily removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230 to become an insulator and have a high resistance, it may be left. . In that case, it may function as an interlayer film.

Further, for example, when a conductive region remains in a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, the metal film can be oxidized by performing heat treatment in an oxidizing atmosphere. It becomes an insulator and increases resistance. By leaving the metal film, the nitride film containing a metal element, or the oxide film containing a metal element as an insulator, it can function as an interlayer film.

Therefore, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is preferably provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. For example, when aluminum of 0.5 nm to 5 nm is oxidized by heat treatment, aluminum oxide of 0.7 nm to 8 nm may be formed.

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to fluctuate and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

Therefore, as illustrated in FIGS. 30 and 31, an insulator 273 containing more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition is provided over the region 231 of the oxide 230. Is preferred. That is, excess oxygen included in the insulator 273 diffuses through the insulator 272, the insulator 280, and the regions 231 and 232 of the oxide 230 into the region 234 of the oxide 230, whereby the region of the oxide 230 Oxygen deficiency at 234 can be reduced.

Note that the insulator 272 provided under the insulator 273 is preferably formed using silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes. Materials such as silicon oxynitride tend to form excess oxygen regions. Therefore, for example, oxygen supplied from the insulator 273 may form an excess oxygen region in the insulator 272. As shown in FIGS. 30 and 31, the insulator 272 having the excess oxygen region is provided around the region 234 of the oxide 230, so that the excess oxygen of the insulator 272 has an effect on the region 234 of the oxide 230. Can be supplied automatically.

The insulator 273 serving as an oxygen supply source is preferably an oxide formed by a sputtering method. An oxide film formed by a sputtering method can contain an oxygen-rich insulator with little impurity such as water or hydrogen. As the oxide, it is particularly preferable to use aluminum oxide.

In the case of using a sputtering method for forming an oxide, it is preferable to form the film using, for example, a facing target type sputtering apparatus. The facing target type sputtering apparatus can form a film without exposing the film forming surface to a high electric field region between the facing targets, so that the film forming surface is not easily damaged by plasma. Therefore, film formation damage to the insulator 272 and the oxide 230 can be reduced during the formation of the insulator to be the insulator 273, which is preferable.

During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

The ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, so that the sputtered particles are ejected from the target. The sputtered particles adhere to and deposit on the film formation surface to form a film. Further, some ions recoil by the target, pass through a film formed as recoil ions, and may be taken into the insulator 272 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 272. When the ions are taken into the insulator 272, a region into which the ions are taken is formed in the insulator 272. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 272.

An excess oxygen region can be formed in the insulator 272 by introducing excess oxygen into the insulator 272. Excess oxygen in the insulator 272 is supplied to the oxide 230 in contact with the insulator 272. By supplying the oxygen to the region 234 of the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

The oxide 230 can be selectively reduced in resistance by combining the above structure or the above steps.

That is, when the low resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260, the insulator 272, or the insulator 273 functioning as a gate electrode as a mask. To do. Therefore, when the plurality of transistors 200C are formed at the same time, variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200C is determined by the width of the conductor 260 and the film thickness of the insulator 272. By setting the width of the conductor 260 to the minimum processing dimension, the transistor 200C can be miniaturized. Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, differences in the structure of the semiconductor device including the transistor 200C according to one embodiment of the present invention from the semiconductor device including the transistor 200A described in Embodiment 1 will be described.

In the conductor 205, a first conductor 205a is formed in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and a second conductor 205b is formed further inside. Here, the heights of the upper surfaces of the first conductor 205a and the second conductor 205b and the height of the upper surface of the insulator 216 can be approximately the same. Note that in the transistor 200C, a structure in which the first conductor 205a and the second conductor 205b are stacked is described; however, the present invention is not limited thereto. For example, the conductor 205 may be provided as a single layer or a stacked structure including three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

Here, the first conductor of the conductor 205 or the conductor 203 (the conductor 205a or the conductor 203a) is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ₂ O, It is preferable to use a conductive material that has a function of suppressing diffusion of impurities such as NO and NO ₂ and copper atoms (the impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen hardly transmits). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

The conductor 205 or the first conductor of the conductor 203 (the conductor 205a or the conductor 203a) has a function of suppressing diffusion of oxygen, whereby the conductor 205 or the second conductor of the conductor 203 (conductivity). It is possible to prevent the conductivity from decreasing due to oxidation of the body 205b or the conductor 203b). As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductive material may be a single layer or a stacked layer as the first conductor of the conductor 205 or the conductor 203 (the conductor 205a or the conductor 203a). Accordingly, impurities such as hydrogen and water can be prevented from diffusing from the substrate side (below the insulator 210) to the transistor 200C side through the conductor 203 and the conductor 205.

In addition, the second conductor 205b of the conductor 205 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that the second conductor 205b of the conductor 205 is illustrated as a single layer, but may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

Further, since the second conductor 203b of the conductor 203 functions as a wiring, a conductor having higher conductivity than the second conductor 205b of the conductor 205 is preferably used. For example, a conductive material mainly containing copper or aluminum can be used. The second conductor 203b of the conductor 203 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

In particular, it is preferable to use copper for the conductor 203. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, the electrical characteristics of the transistor 200C may be deteriorated by diffusing into the oxide 230. Thus, for example, the insulator 214 can be made of copper diffusion by using a material such as aluminum oxide or hafnium oxide having low copper permeability.

Note that the conductor 205, the insulator 214, and the insulator 216 are not necessarily provided. In that case, part of the conductor 203 can function as the second gate electrode.

The insulator 220, the insulator 222, and the insulator 224 have a function as a gate insulator.

Here, the insulator 224 in contact with the oxide 230 is preferably an oxide insulator containing oxygen in excess of the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200C can be improved.

In addition, the oxide 230 includes a region 231, a region 232, and a region 234. Note that the region 232 includes at least a region overlapping with the insulator 272.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in TDS analysis, the amount of released oxygen in terms of oxygen molecules is 1.0 × 10 ¹⁸ molecules / cm ³ or more, preferably 1.0 × 10 ¹⁹ molecules / cm ³ or more, more preferably 2 The oxide film is 0.0 × 10 ¹⁹ molecules / cm ³ or 3.0 × 10 ²⁰ molecules / cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

An insulator from which oxygen is released by heating is provided as the insulator 250 so as to be in contact with the upper surface of the oxide 230c, whereby oxygen can be effectively supplied from the insulator 250 to the region 234 of the oxide 230b through the oxide 230c. Can be supplied. Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260 in order to supply the excess oxygen of the insulator 250 to the oxide 230 efficiently. The metal oxide preferably suppresses oxygen diffusion from the insulator 250. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Note that the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat | fever, and a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.

In addition, the metal oxide may have a function as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming a film of the conductor 260 by a sputtering method, the electric resistance value of the metal oxide can be reduced to obtain a conductor (OC electrode).

By including the metal oxide, the on-current of the transistor 200C can be improved without weakening the influence of the electric field from the conductor 260. Further, the leakage current between the conductor 260 and the oxide 230 is maintained by maintaining the distance between the conductor 260 and the oxide 230 depending on the physical thickness of the insulator 250 and the metal oxide. Can be suppressed. In addition, by providing a stacked structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be reduced. It can be easily adjusted as appropriate.

Specifically, as the metal oxide, a metal containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium An oxide can be used. Further, by reducing the resistance of an oxide semiconductor that can be used for the oxide 230, the metal oxide can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process.

The conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. Like the first conductor of the conductor 205, the conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), a copper atom It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

Since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductivity from being lowered due to oxidation of the conductor 260b due to excess oxygen of the insulator 250. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion.

Further, an insulator that functions as a barrier film may be disposed over the conductor 260b. As the insulator, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, it is possible to suppress the conductor 260 from being oxidized by oxygen from above the insulator. In addition, impurities such as water or hydrogen from above the insulator can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.

Further, it is preferable to dispose an insulator 271 that functions as a hard mask over the insulator. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle formed between the side surface of the conductor 260 and the substrate surface is 75 ° to 100 °, Preferably, it can be 80 ° or more and 95 ° or less. By processing the conductor 260 into such a shape, the insulator 272 to be formed next can be formed into a desired shape.

Note that the insulator 271 may also function as a barrier film by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, an insulator having a function as the above-described barrier film is not necessarily provided over the conductor 260b.

As shown in FIG. 30B, the insulator 272 functioning as a barrier film and a buffer layer includes a portion of the top surface of the oxide 230b (a portion overlapping with the region 232) in the channel length direction of the transistor 200C. It is provided in contact with the side surface of the object 230 c, the side surface of the insulator 250, and the side surface of the conductor 260. In addition, as illustrated in FIG. 30C, the transistor 200C is provided in contact with part of the top surface of the insulator 222 in the channel width direction of the transistor 200C.

For example, the insulator 272 is preferably formed using an ALD method. By using the ALD method, a dense thin film can be formed.

As the insulator 272, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having holes Etc. are preferable. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

Alternatively, the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxygen in the insulator 250 can be prevented from diffusing to the outside. Further, entry of impurities such as hydrogen and water into the oxide 230 from an end portion of the insulator 250 or the like can be suppressed. Therefore, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200C can be improved.

Further, by providing the insulator 272, side surfaces of the oxide 230c, the insulator 250, and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. . Thus, impurities such as water or hydrogen from above the transistor 200C can be prevented from entering the region 234 of the oxide 230 through the oxide 230c, the insulator 250, and the conductor 260. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulator.

Alternatively, the insulator 272 preferably includes an insulator having a low relative dielectric constant. For example, the insulator 272 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or a resin or the like. Alternatively, the insulator 272 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

Note that in the case where aluminum oxide is provided as the insulator 272 by using an ALD method, the thickness of the insulator 272 is preferably 0.5 nm to 3.0 nm.

An insulator 273 is provided on part of the top surface of the oxide 230b (a portion overlapping with the region 232), the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 with the insulator 272 interposed therebetween. . With this structure, the insulator 273 serving as an oxygen supply source to the oxide 230 is not in direct contact with the conductor 260. Therefore, oxidation of the conductor 260 functioning as the gate electrode due to oxygen from the insulator 273 can be suppressed.

The insulator 273 is provided over the insulator 272 so as to have a region overlapping with the region 232 of the oxide 230. By depositing the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 272. Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region.

For example, as the insulator 273, a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. Can do.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by a sputtering method can serve as an oxygen supply source and function as a barrier film for impurities such as hydrogen. For example, by using aluminum oxide formed by a sputtering method for the insulator 273, the insulator 273 supplies oxygen to the insulator 272, and impurities such as hydrogen from above the insulator 273 are exposed to the insulator 272. It can suppress mixing in the side.

Further, an insulator 280 that functions as an interlayer film is preferably provided over the insulator 273. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

Further, it is preferable to provide an insulator 282 made of the same material as the insulator 273 on the insulator 280. With this structure, impurities such as hydrogen from above the insulator 282 can be prevented from entering the transistor 200C side. In some cases, hydrogen contained in the insulator 280 can be extracted to the insulator 282. Note that an insulator similar to the insulator 210 may be provided over the insulator 282.

Further, the conductor 240a and the conductor 240b are disposed in the openings formed in the insulator 282 and the insulator 280. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 282.

Note that the first conductor of the conductor 240a is formed in contact with the inner walls of the openings of the insulator 282 and the insulator 280. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, the first conductor of the conductor 240b is formed in contact with the inner walls of the openings of the insulator 282 and the insulator 280. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

Here, for example, when the openings are formed in the insulator 282 and the insulator 280, the region of the oxide 230 in which the resistance is reduced may be removed. In that case, as the conductor used for the first conductor of the conductor 240, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used. In other words, when the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or an oxygen vacancy is formed, and the resistance of the region 231 of the oxide 230 is reduced. Therefore, the contact resistance between the oxide 230 and the conductor 240 can be reduced by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240. The first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten.

In the case where the conductor 240 has a stacked structure, the conductor in contact with the insulator 280 and the insulator 282 transmits impurities such as water or hydrogen, like the first conductor 205a of the conductor 205. It is preferable to use a conductive material having a suppressing function. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 282 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.

Although not shown, a conductor functioning as a wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. As the conductor functioning as the wiring, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. The conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material. Note that like the conductor 203 and the like, the conductor may be formed so as to be embedded in an opening provided in the insulator.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including the transistor 200C according to the present invention will be described with reference to FIGS. Further, in FIGS. 32 to 41, (A) in each figure shows a top view. Further, (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line in A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200C. Further, (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200C. Further, (D) in each drawing is a cross-sectional view of a portion indicated by a dashed line A5-A6 in (A) of each drawing, and is also a cross-sectional view of a source region or a drain region of the transistor 200C. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.

First, a substrate (not shown) is prepared, and the insulator 210, the insulator 212, the conductor 203, the insulator 214, the insulator 216, the conductor 205, the insulator 220, and the insulator 222 are sequentially formed over the substrate. (See FIG. 32). Note that the materials, formation methods, and the like of the insulator 210, the insulator 212, the conductor 203, the insulator 214, the insulator 216, the conductor 205, the insulator 220, and the insulator 222 are the same as those in Embodiment 1. The body 210, the insulator 212, the conductor 203, the insulator 214, the insulator 216, the conductor 205, the insulator 220, and the insulator 222 can be referred to.

Next, an insulating film 224A is formed over the insulator 222. The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 32). In this embodiment, silicon oxide is formed by a CVD method as the insulating film 224A.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or inert gas. May be.

In this embodiment, as the heat treatment, treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere after the insulating film 224A is formed. By the heat treatment, impurities such as hydrogen and water contained in the insulating film 224A can be removed.

The heat treatment can also be performed at the timing after the insulator 220 is formed and after the insulator 222 is formed. Although the heat treatment conditions described above can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.

Here, in order to form an excess oxygen region in the insulating film 224A, plasma treatment including oxygen may be performed in a reduced pressure state. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently guided into the insulating film 224A. it can. Alternatively, after performing plasma treatment containing an inert gas using this apparatus, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions for the plasma treatment, impurities such as hydrogen and water contained in the insulating film 224A can be removed. In that case, heat treatment may not be performed.

Next, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulating film 224A (see FIG. 32). Note that the oxide film 230A and the oxide film 230B in Embodiment 1 can be referred to for materials, formation methods, and the like of the oxide film 230A and the oxide film 230B, respectively.

Next, the insulating film 224A, the oxide film 230A, and the oxide film 230B are processed into island shapes to form the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 33).

Here, the insulator 224, the oxide 230a, and the oxide 230b are formed so that at least a part thereof overlaps with the conductor 205. The side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200C are provided, the area can be reduced and the density can be increased. Become. Note that an angle formed by the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and the upper surface of the insulator 222 may be an acute angle. In that case, the angle formed between the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and the upper surface of the insulator 222 is preferably as large as possible.

Further, a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the oxide 230b. By not having a corner at the end, the coverage of the film in the subsequent film forming process is improved.

Note that the oxide film may be processed using a lithography method. For the processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.

Note that a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do. The etching of the insulating film 224A, the oxide film 230A, and the oxide film 230B may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the oxide film is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

In addition, by performing the dry etching or the like, impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the insulator 224, the oxide 230a, the oxide 230b, and the like. Examples of impurities include fluorine and chlorine.

¡Clean to remove the above impurities. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.

As the wet cleaning, cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.

Next, an oxide film to be the oxide film 230C is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b.

The oxide film to be the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An oxide film to be the oxide film 230C may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c. In this embodiment, the oxide film to be the oxide film 230C is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].

Next, the oxide film to be the oxide film 230C is etched to form the oxide film 230C (see FIG. 34).

Subsequently, an insulating film 250A, a conductive film 260A, a conductive film 260B, and an insulating film 271A are sequentially formed over the oxide film 230C (see FIG. 34). Note that materials, formation methods, and the like of the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 271A are the same as the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 271A of Embodiment 1, respectively. You can visit.

Note that a metal oxide film may be separately formed before the conductive film 260A is formed. As the metal oxide film, an In—Ga—Zn oxide is formed by a sputtering method, for example. As a method for forming the metal oxide film, a sputtering method is preferably used in an atmosphere containing oxygen gas. By forming the metal oxide film in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. The excess oxygen added to the insulating film 250 </ b> A can compensate oxygen vacancies in the oxide 230 by supplying oxygen to the oxide 230.

Here, as a means for forming the metal oxide film, the insulating film 250A and the insulating film 224A are formed while forming the metal oxide film by forming a film in an oxygen gas atmosphere using a sputtering apparatus. Oxygen can be introduced into the. In addition, by using one or both of aluminum and hafnium having barrier properties for the metal oxide film, excess oxygen introduced into the insulating film 250A can be effectively contained.

For example, a metal nitride may be formed as the conductive film 260A by a sputtering method. For example, in the case where an oxide semiconductor typified by an In—Ga—Zn oxide is formed as the above-described metal oxide film over the insulating film 250A, nitrogen or hydrogen is supplied to the metal oxide film. , Carrier density increases. That is, the metal oxide film functions as an oxide conductor (OC). Therefore, by forming a metal nitride as the conductive film 260A by a sputtering method, a constituent element (particularly nitrogen) in the metal nitride is diffused into the metal oxide film, and the resistance of the metal oxide film is reduced. Further, the resistance of the metal oxide film is reduced due to damage (for example, sputtering damage) when the conductive film 260A is formed. Therefore, the carrier density of the metal oxide film is increased, and the conductivity of the metal oxide film is increased.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed. Through this heat treatment, excess oxygen is added to the insulating film 250A from the above-described metal oxide film, and an excess oxygen region can be easily formed in the insulating film 250A.

The film thickness of the insulating film 271A is preferably larger than the film thickness of the insulating film 272A to be formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260.

Note that an insulating film having a function as a barrier film may be separately formed before the insulating film 271A is formed. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, the oxidation of the conductor 260 can be suppressed. Further, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed.

Next, the insulating film 271A is etched to form an insulator 271. Here, the insulator 271 functions as a hard mask. By providing the insulator 271, the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the conductor 260a, and the side surface of the conductor 260b can be formed substantially perpendicular to the top surface of the substrate.

Next, using the insulator 271 as a mask, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are etched, and the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260) are etched. 260b) (see FIG. 35).

Note that part of the insulator 222 may be removed in a region where the insulator 222 and the insulator 250 do not overlap with each other by the etching. In this case, the thickness of the region of the insulator 222 that overlaps with the insulator 250 may be greater than the thickness of the region that does not overlap with the insulator 250.

In addition, the oxide 230c, the insulator 250, the conductor 260, and the insulator 271 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.

Further, the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 are preferably in the same plane.

Further, the same surface shared by the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 is preferably substantially perpendicular to the upper surface of the substrate. That is, in the cross-sectional shape, it is preferable that the angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 be an acute angle and large. Note that in the cross-sectional shape, an angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the upper surface of the oxide 230 may be an acute angle. In that case, the angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 is preferably as large as possible.

Even after the above-described processing, a post-process may be performed without removing the hard mask (insulator 271).

Next, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 271 (see FIG. 36). The insulating film 272A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by an ALD method having excellent coverage. By using the ALD method, the insulating film 272A having a uniform thickness is formed on the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 even in the step portion formed by the conductor 260 and the like. be able to. In addition, a dense thin film can be formed by using the ALD method.

As the insulating film 272A, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or It is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

On the other hand, aluminum oxide having a barrier property or the like may be provided as the insulating film 272A. For example, in the case where the conductor 260 is a metal film that is easily oxidized, an insulator having a barrier property can be used to suppress the conductor 260 from being oxidized by oxygen from above the insulating film 272A. Thereby, it can suppress that the resistance value of the conductor 260 goes up.

In the case where aluminum oxide is provided using the ALD method as the insulating film 272A, the thickness of the insulating film 272A is preferably 0.5 nm to 3.0 nm. With this structure, excess oxygen included in the insulator 273 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an insulating film 273A is provided over the insulating film 272A (see FIG. 36). As the insulating film 273A, aluminum oxide formed by a sputtering method is preferably used. By using a sputtering method, an aluminum oxide film containing a large amount of oxygen and containing a small amount of impurities such as water or hydrogen can be formed.

Further, by forming a film in an oxygen gas atmosphere using a sputtering apparatus, oxygen can be introduced into the insulating film 272A while forming the insulating film 273A. Accordingly, oxygen in the insulating film 273A is supplied to the insulating film 272A using the insulating film 273A as an oxygen supply source, and an excess oxygen region can be formed in the insulating film 272A. Oxygen in the excess oxygen region is supplied to the oxide 230 by a subsequent heat treatment or the like, so that oxygen vacancies in the region 234 of the oxide 230 can be compensated.

Next, anisotropic etching is performed on the insulating film 272A and the insulating film 273A to form the insulator 272 and the insulator 273 on the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 (see FIG. 37). .)

As the anisotropic etching process, it is preferable to perform a dry etching process. Thus, the insulator 272 and the insulator 273 can be formed in a self-aligning manner by removing the insulating film formed on the surface substantially parallel to the substrate surface. Note that the insulator 222 can be used as an etching stopper film in the treatment.

Subsequently, a film is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b through the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 273. A film 242A is formed (see FIG. 38). Note that the film 242A has a thickness of 0.5 nm to 5 nm, preferably, 1 nm to 3 nm. As the film 242A, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used. The film 242A is a film containing a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. Note that the film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, it is preferable to perform heat treatment. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state. For example, as the heat treatment, treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the film 242A is formed.

By the heat treatment in an atmosphere containing nitrogen, the above-described metal element diffuses from the film 242A to the oxide 230, and the metal element can be added to the oxide 230. In addition, oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed by the film 242A. As a result, the vicinity of the interface of the oxide 230 with the film 242A becomes a metal compound, and the resistance is reduced. At that time, part of the oxide 230 and the metal element described above may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and has a higher resistance.

Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.

Further, in the case where a conductive region remains in the film 242A, the film 242A is oxidized by performing heat treatment in an oxidizing atmosphere, so that it becomes an insulator and has high resistance. By leaving the film 242A as an insulator, the film 242A can function as an interlayer film.

In the film formation step of the film 242A or heat treatment, oxygen in the region 231 and the region 232 is absorbed by the film 242A because oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 are absorbed. May occur. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Therefore, the region 231 and the region 232 of the oxide 230 are n-type and have low resistance.

Subsequently, the film 242A is removed (see FIG. 39). In the figure, the region where the resistance of the oxide 230 is reduced by the above-described treatment is indicated by hatching. Note that the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is not necessarily removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230 to become an insulator and have a high resistance, it may be left. . In that case, it may function as an interlayer film. In this step, a dry etching method or a wet etching method can be used. By removing the film 242A, hydrogen in the oxide 230 absorbed by the film 242A can be removed at the same time. Accordingly, hydrogen which is an impurity in the transistor 200C can be reduced.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed into the insulator 273 through the insulator 272 or the insulator 280, so that hydrogen in the oxide 230 is reduced. be able to.

Next, an insulator 280 is formed on the insulator 273. Note that the insulator 280 of Embodiment 1 can be referred to for a material, a formation method, and the like of the insulator 280.

Next, an insulator 282 is formed over the insulator 280 (see FIG. 40). The insulator 282 is preferably provided with an insulator 282 made of the same material as the insulator 273. With this structure, impurities such as hydrogen and water from above the insulator 282 can be prevented from entering the transistor 200C side. In some cases, hydrogen contained in the insulator 280 can be extracted to the insulator 282.

Next, an opening reaching the oxide 230 is formed in the insulator 282 and the insulator 280 (see FIG. 41). The opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 240a and the conductor 240b are provided in contact with the side surface of the oxide 230.

Next, a conductive film to be a first conductor of the conductor 240 and a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when the openings are formed in the insulator 282 and the insulator 280, the region of the oxide 230 in which the resistance is reduced may be removed. Alternatively, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used as the first conductor of the conductor 240. Accordingly, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or an oxygen vacancy is formed in the region, and the contact region between the oxide 230 and the conductor 240 is reduced in resistance. Can be By reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured. Therefore, the first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium.

Next, by performing a CMP process, a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 282 is exposed. As a result, the conductor 240a and the conductor 240b having a flat upper surface can be formed by leaving the conductive film only in the openings (see FIG. 30).

Through the above steps, a semiconductor device including the transistor 200C can be manufactured. As illustrated in FIGS. 32 to 41, the transistor 200C can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

<Modification of semiconductor device>
An example of a semiconductor device including the transistor 200C according to one embodiment of the present invention is described below with reference to FIGS.

FIG. 42A is a top view of a semiconductor device having a transistor 200C. FIG. 42B, FIG. 42C, and FIG. 42D are cross-sectional views of the semiconductor device. Here, FIG. 42B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 42A and also a cross-sectional view in the channel length direction of the transistor 200C. FIG. 42C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 42A and is a cross-sectional view in the channel width direction of the transistor 200C. FIG. 42D is a cross-sectional view taken along the dashed-dotted line A5-A6 in FIG. 42A and is a cross-sectional view of the source region or the drain region of the transistor 200C. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

42, the structure having the same function as the structure of the semiconductor device (see FIG. 30) illustrated in <Structure example of semiconductor device> is denoted by the same reference numeral.

Hereinafter, the structure of the transistor 200C will be described with reference to FIG. Note that also in this item, the material described in detail in the above embodiment and <Structure Example of Semiconductor Device> can be used as a material of the transistor 200C.

42, the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and a surface parallel to the substrate surface have a taper angle. Specifically, as illustrated in FIG. 42B, the taper angle may be 45 ° to 80 °, preferably 50 ° to 70 °. When the insulator 224, the oxide 230a, and the oxide 230b have a tapered structure, anisotropic etching is performed on the insulating film 272A and the insulating film 273A (see FIGS. 36 and 37). Further, the side surfaces of the oxide 230a and the oxide 230b can be completely exposed.

Therefore, as compared with the semiconductor device having a structure having no tapered structure (see FIG. 30), the side surface of the oxide 230a and the oxide 230b is also in contact with the film 242A (see FIG. 38). Become. Accordingly, the metal compound is reliably formed on the side surfaces of the oxide 230a and the oxide 230b, and the resistance can be reduced. That is, the region 231 can be reliably formed also on the side surface of the oxide 230. In addition, since the oxide 230a and the oxide 230b have a tapered structure, the coatability of the structure formed in an upper layer than the oxide 230a and the oxide 230b can be improved.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 4)
An example of a semiconductor device including the transistor 200D according to one embodiment of the present invention, which is different from the semiconductor device including the transistor described in Embodiment 3 will be described below.

Note that in the semiconductor device described in this embodiment, the structure having the same function as the structure of the semiconductor device described in the above embodiment is denoted by the same reference numeral. Therefore, a description is mainly given of differences from the semiconductor device described in the above embodiment, and a repetitive description is omitted. Further, in the case where there is no particular description of a material, a manufacturing method, or the like having a structure with the same symbol, the contents described in the above embodiment modes can be referred to for the material, the manufacturing method, and the like of the structure.

<Configuration example of semiconductor device>
43A to 43D are a top view and a cross-sectional view of the transistor 200D according to one embodiment of the present invention and the periphery of the transistor 200D.

FIG. 43A is a top view of a semiconductor device having a transistor 200D. FIGS. 43B, 43C, and 43D are cross-sectional views of the semiconductor device. Here, FIG. 43B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 43A and also a cross-sectional view in the channel length direction of the transistor 200D. FIG. 43C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 43A and is a cross-sectional view in the channel width direction of the transistor 200D. FIG. 43D is a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 43A and is a cross-sectional view of the source region or the drain region of the transistor 200D. Note that in the top view of FIG. 1A, some elements are omitted for clarity.

The semiconductor device of one embodiment of the present invention includes the transistor 200D, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 280, and the insulator 282. In addition, a conductor 203 which is electrically connected to the transistor 200D and functions as a wiring, and a conductor 240 which functions as a plug are included.

The conductor 240 is in contact with the inner walls of the openings of the insulator 275, the insulator 273, the insulator 280, and the insulator 282, and the first conductor of the conductor 240 is formed. A second conductor is formed. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be approximately the same. Note that although the transistor 200D illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

[Transistor 200D]
A transistor 200D illustrated in FIG. 43 includes an insulator 277 disposed on a side surface of the conductor 260 with the insulator 272 interposed therebetween, an insulator 275 disposed on the side surface of the insulator 277 and the oxide 230, and an insulator And the transistor 273 which is provided over the H.275, is different from the transistor 200C described in Embodiment 3.

In the transistor 200, an oxide semiconductor is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

Since the transistor 200D using an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200D included in a highly integrated semiconductor device.

Here, an oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements included in the oxide semiconductor, and has low resistance. Turn into. Note that aluminum, titanium, tantalum, tungsten, or the like is preferably used. In order to add the metal element to the oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film and the like, thereby forming oxygen vacancies and oxidation. The vicinity of the interface of the physical semiconductor may have a low resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element diffuses from the metal film into the oxide semiconductor, and the metal element can be added to the oxide semiconductor. At that time, the oxide semiconductor and the metal element may be alloyed. When the oxide semiconductor and the metal element are alloyed, the metal element added to the oxide semiconductor is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

In addition, hydrogen existing in the oxide semiconductor diffuses into a region where the resistance of the oxide semiconductor is reduced, and becomes relatively stable when it enters oxygen vacancies existing in the region where the resistance is reduced. In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. Has been found to be relatively stable. Therefore, the resistance of the oxide semiconductor or the region where the metal compound is formed by heat treatment is further reduced, and the oxide semiconductor that is not reduced in resistance is highly purified (impurities such as water and hydrogen). There is a tendency to increase resistance.

In addition, in an oxide semiconductor, the carrier density increases when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen deficiency, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, a high resistance region and a low resistance region can be provided in the oxide semiconductor by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

Here, FIG. 44 shows an enlarged view of the region 239 including the oxide 230b which is selectively reduced in resistance and is surrounded by a broken line in FIG.

As shown in FIG. 44, the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200D, a region 231 (region 231a and region 231b) functioning as a source region or a drain region, a region 234, and a region 231. And a region 232 (region 232a and region 232b) provided between the first and second regions.

In order to reduce the resistance of the region 231, for example, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like may be formed in contact with the region 231 of the oxide 230. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized through at least the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 277. It is preferable to provide on the object 230b.

By providing a metal film, a nitride film containing a metal element, or an oxide film containing a metal element in contact with the region 231 of the oxide 230, the metal element diffuses from the film into the region 231 of the oxide 230. A metal compound is formed at 231 to reduce resistance. In addition, part of oxygen in the oxide 230 located in the vicinity of the interface between the region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element or in the vicinity of the interface is absorbed by the film, In some cases, oxygen vacancies are formed in the region 231 to reduce resistance. Note that in FIG. 2, a region where the resistance of the oxide 230 is reduced is represented by hatching as an example. Note that in this specification and the like, the range represented by the oblique lines is not limited to the range of FIG. For example, the low resistance region (or range) is formed in a region near the interface between the oxide 230 and the conductor 240 or a region in the region 231 from the upper surface of the oxide 230 to the lower surface of the oxide 230. There is a case. The same applies to other drawings.

Further, heat treatment may be performed in an atmosphere containing nitrogen in a state where the region 231 is in contact with a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. By the heat treatment, the metal element is diffused from the metal film to the region 231 of the oxide 230, and the metal element can be added to the region 231. At that time, the region 231 of the oxide 230 and the metal element may be alloyed. When the region 231 of the oxide 230 and the metal element are alloyed, the metal element added to the oxide semiconductor is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and has a higher resistance.

On the other hand, in the regions (region 234 and region 232) overlapping with the conductor 260 and the insulator 272 of the oxide 230, addition of a metal element is suppressed by the conductor 260 and the insulator 272. Further, in the region 234 and the region 232 of the oxide 230, oxygen atoms in the oxide 230 are suppressed from being absorbed into the metal film, the nitride film containing a metal element, or the oxide film containing a metal element. The

Further, the region 231 of the oxide 230 and the region 232 adjacent to the region 231 are absorbed by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element, whereby the region 231 and the region Oxygen deficiency may occur in 232. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the resistance of the region 231 and the region 232 of the oxide 230 is reduced.

Here, in the case where a metal film, a nitride film containing a metal element, or an oxide film containing a metal element has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Further, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element may be removed together with hydrogen absorbed from the oxide 230 in a later step.

Note that the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is not necessarily removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230 to become an insulator and have a high resistance, it may be left. . In that case, it may function as an interlayer film.

Further, for example, when a conductive region remains in a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, the metal film can be oxidized by performing heat treatment in an oxidizing atmosphere. It becomes an insulator and increases resistance. By leaving the metal film, the nitride film containing a metal element, or the oxide film containing a metal element as an insulator, it can function as an interlayer film.

Therefore, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is preferably provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. For example, when aluminum of 0.5 nm to 5 nm is oxidized by heat treatment, aluminum oxide of 0.7 nm to 8 nm may be formed.

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to fluctuate and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

Therefore, as illustrated in FIGS. 43 and 44, an insulator 275 including more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition is preferably provided in contact with the oxide 230b. That is, excess oxygen in the insulator 275 is diffused into the region 234 of the oxide 230, whereby oxygen vacancies in the region 234 of the oxide 230 can be reduced.

Note that the insulator 275 is preferably formed using silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes. Materials such as silicon oxynitride tend to form excess oxygen regions. On the other hand, compared to the above-described materials such as silicon oxynitride, the oxide 230 tends to hardly form an excess oxygen region. Therefore, by providing the insulator 275 having an excess oxygen region around the region 234 of the oxide 230, the excess oxygen of the insulator 275 can be effectively supplied to the region 234 of the oxide 230.

In order to provide an excess oxygen region in the insulator 275, an oxide film may be formed as the insulator 273 in contact with the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide, an insulator containing a large amount of oxygen and containing few impurities such as water or hydrogen can be formed. In the case of using a sputtering method, for example, it is preferable to form a film using a facing target type sputtering apparatus. The facing target type sputtering apparatus can form a film without exposing the film forming surface to a high electric field region between the facing targets, so that the film forming surface is not easily damaged by plasma. Therefore, film formation damage to the insulator 275 and the oxide 230 can be reduced during the formation of the insulator to be the insulator 273, which is preferable.

During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

The ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, so that the sputtered particles are ejected from the target. The sputtered particles adhere to and deposit on the film formation surface to form a film. Some ions recoil by the target, pass through a film formed as recoil ions, and may be taken into the insulator 275 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 275. When the ions are taken into the insulator 275, a region into which the ions are taken is formed in the insulator 275. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 275.

By introducing excess oxygen into the insulator 275, an excess oxygen region can be formed in the insulator 275. Excess oxygen in the insulator 275 is supplied to the oxide 230 in contact with the insulator 275. By supplying the oxygen to the region 234 of the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

The insulator 273 is preferably made of aluminum oxide. In particular, it is preferable to use aluminum oxide formed by sputtering. By using aluminum oxide formed by a sputtering method, the insulator 273 containing a large amount of oxygen can be formed. Thus, the insulator 273 serves as an oxygen supply source, and oxygen can be supplied to the insulator 275 and the region 230 of the oxide 230 as described above.

43 and 44, the insulator 275 and the conductor 260 are physically separated by the insulator 271, the insulator 272, and the insulator 277. With the transistor 200D having such a structure, the conductor 260 functioning as a gate electrode can be prevented from being oxidized by oxygen from the insulator 275.

The oxide 230 can be selectively reduced in resistance by combining the above structure or the above steps.

That is, when the low resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260, the insulator 272, or the insulator 277 functioning as a gate electrode as a mask. To do. Therefore, when a plurality of transistors 200D are formed at the same time, variation in electrical characteristics between transistors can be reduced. Further, the channel length of the transistor 200D is determined by the width of the conductor 260 and the film thickness of the insulator 272. By setting the width of the conductor 260 to the minimum processing dimension, the transistor 200D can be miniaturized. Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, a structure of a semiconductor device including the transistor 200D according to one embodiment of the present invention is different from the semiconductor device including the transistor 200A described in Embodiment 1 and the semiconductor device including the transistor 200C described in Embodiment 3. The point will be described.

In addition, the oxide 230 includes a region 231, a region 232, and a region 234. Note that at least part of the region 231 includes a region in contact with the insulator 275. The region 232 includes at least a region overlapping with the insulator 272.

An insulator 277 is provided on part of the top surface of the oxide 230b (a portion overlapping with the region 232), the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 with the insulator 272 interposed therebetween. . With this structure, the insulator 275 having the excess oxygen region and the conductor 260 can be reliably isolated by the insulator 272 and the insulator 277. Therefore, oxidation of the conductor 260 functioning as the gate electrode due to oxygen from the insulator 275 can be suppressed.

The insulator 277 preferably includes an insulator having a low relative dielectric constant. For example, the insulator 277 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or a resin or the like. Alternatively, the insulator 277 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

The insulator 275 is provided so as to have at least a region in contact with the region 231 of the oxide 230. The insulator 275 preferably has an excess oxygen region. For example, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies is used as the insulator 275, an excess oxygen region is easily formed in the insulator 275 due to subsequent formation of the insulator 273. . When the insulator 275 includes the excess oxygen region, oxygen included in the region can be efficiently supplied to the oxide 230.

The insulator 273 is provided on the insulator 275. By depositing the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275. Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region.

For example, as the insulator 273, a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. Can do.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by a sputtering method can serve as an oxygen supply source and function as a barrier film for impurities such as hydrogen. For example, by using aluminum oxide formed by a sputtering method for the insulator 273, the insulator 273 supplies oxygen to the insulator 275, and impurities such as hydrogen from above the insulator 273 are exposed to the insulator 275. It can suppress mixing in the side.

Further, the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 282, the insulator 280, the insulator 273, and the insulator 275. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 282.

Note that the first conductor of the conductor 240a is formed in contact with the inner walls of the openings of the insulator 282, the insulator 280, the insulator 273, and the insulator 275. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, the first conductor of the conductor 240b is formed in contact with the inner walls of the openings of the insulator 282, the insulator 280, the insulator 273, and the insulator 275. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

Here, for example, when the openings are formed in the insulator 282, the insulator 280, the insulator 273, and the insulator 275, the region of the oxide 230 in which the resistance is reduced may be removed. In that case, as the conductor used for the first conductor of the conductor 240, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used. In other words, when the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or an oxygen vacancy is formed, and the resistance of the region 231 of the oxide 230 is reduced. Therefore, the contact resistance between the oxide 230 and the conductor 240 can be reduced by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240. The first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten.

In the case where the conductor 240 has a stacked structure, the conductor in contact with the insulator 275, the insulator 273, the insulator 280, and the insulator 282 is similar to the first conductor 205a of the conductor 205 and the like. It is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 282 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including the transistor 200D according to the present invention will be described with reference to FIGS. In FIGS. 45 to 50, (A) in each drawing shows a top view. Further, (B) in each drawing is a cross-sectional view corresponding to a portion indicated by a one-dot chain line in A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200D. Further, (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200D. Further, (D) in each drawing is a cross-sectional view taken along a dashed line A5-A6 in (A) in each drawing, and is also a cross-sectional view of a source region or a drain region of the transistor 200D. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.

43 is manufactured until the oxide 230c, the insulator 250, the conductor 260 (the conductor 260a and the conductor 260b), and the insulator 271 are formed. This is the same as the manufacturing method. Therefore, the method for manufacturing the semiconductor device according to FIGS. 32 to 35 can be referred to.

Next, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 271 (see FIG. 45). Note that the insulating film 272A in Embodiment 3 can be referred to for the material, the deposition method, and the like of the insulating film 272A.

In the case where aluminum oxide is provided using the ALD method as the insulating film 272A, the thickness of the insulating film 272A is preferably 0.5 nm to 3.0 nm. With this structure, excess oxygen included in the insulator 277 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an insulating film 277A is provided over the insulating film 272A (see FIG. 45). The insulating film 277A preferably includes an insulator having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with holes, or resin It is preferable to have. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having a hole for the insulating film 277A because an excess oxygen region can be easily formed in the insulating film 277 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Next, anisotropic etching is performed on the insulating film 272A and the insulating film 277A to form the insulator 272 and the insulator 277 on side surfaces of the oxide 230c, the insulator 250, and the conductor 260 (see FIG. 46). .)

As the anisotropic etching process, it is preferable to perform a dry etching process. Thus, the insulator 272 and the insulator 277 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface. Note that the insulator 222 can be used as an etching stopper film in the treatment.

Subsequently, a film is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b through the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 277. A film 242A is formed (see FIG. 47). Note that the film 242A has a thickness of 0.5 nm to 5 nm, preferably, 1 nm to 3 nm. As the film 242A, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used. The film 242A is a film containing a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. Note that the film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, it is preferable to perform heat treatment. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state. For example, as the heat treatment, treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the film 242A is formed.

By the heat treatment in an atmosphere containing nitrogen, the above-described metal element diffuses from the film 242A to the oxide 230, and the metal element can be added to the oxide 230. In addition, oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed by the film 242A. As a result, the vicinity of the interface of the oxide 230 with the film 242A becomes a metal compound, and the resistance is reduced. At that time, part of the oxide 230 and the metal element described above may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and has a higher resistance.

Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.

Further, in the case where a conductive region remains in the film 242A, the film 242A is oxidized by performing heat treatment in an oxidizing atmosphere, so that it becomes an insulator and has high resistance. By leaving the film 242A as an insulator, the film 242A can function as an interlayer film.

In the film formation step of the film 242A or heat treatment, oxygen in the region 231 and the region 232 is absorbed by the film 242A because oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 are absorbed. May occur. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Therefore, the region 231 and the region 232 of the oxide 230 are n-type and have low resistance.

Subsequently, the film 242A is removed (see FIG. 48). In the figure, the region where the resistance of the oxide 230 is reduced by the above-described treatment is indicated by hatching. Note that the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is not necessarily removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230 to become an insulator and have a high resistance, it may be left. . In that case, it may function as an interlayer film. In this step, a dry etching method or a wet etching method can be used. By removing the film 242A, hydrogen in the oxide 230 absorbed by the film 242A can be removed at the same time. Accordingly, hydrogen which is an impurity in the transistor 200D can be reduced.

Subsequently, insulation is performed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b through the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 277. A body 275 is formed (see FIG. 49). The insulator 275 preferably includes an insulator having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with holes, or resin It is preferable to have. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes for the insulator 275 because an excess oxygen region can be easily formed in the insulator 275 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Next, an insulator 273 is formed over the insulator 275 (see FIG. 49). The insulator 273 is preferably formed using aluminum oxide by a sputtering method. By using a sputtering method, an aluminum oxide film containing a large amount of oxygen and containing a small amount of impurities such as water or hydrogen can be formed.

Further, by forming a film in an oxygen gas atmosphere using a sputtering apparatus, oxygen can be introduced into the insulator 275 while the insulator 273 is formed. Accordingly, the oxygen in the insulator 273 is supplied to the insulator 275 using the insulator 273 as an oxygen supply source, and an excess oxygen region can be formed in the insulator 275.

As described above, when the insulator 275 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes, an excess oxygen region tends to be easily formed in the insulator 275. On the other hand, as compared with the above-described silicon oxide, the oxide 230 tends to hardly form an excess oxygen region even when an oxide film formed by a sputtering method is formed over the oxide 230. Therefore, for example, in the case where the oxide film using a sputtering method is formed as the insulator 275, an excess oxygen region can be selectively formed in the insulator 277. At this time, since an excess oxygen region is hardly formed in the oxide 230, the resistance reduction region in the oxide 230 can be prevented from increasing in resistance.

The insulator 275 in which the excess oxygen region is formed as described above can effectively supply oxygen from the excess oxygen region to the region 234 of the oxide 230.

With the above structure, each region of the oxide 230 can be formed in a self-aligning manner. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273 through the insulator 275, so that hydrogen in the oxide 230 can be reduced.

Next, the insulator 280 and the insulator 282 are sequentially formed on the insulator 273. Note that the insulator 280 in Embodiment 1 and the insulator 282 in Embodiment 3 can be referred to for materials, formation methods, and the like of the insulator 280 and the insulator 282, respectively.

Next, an opening reaching the oxide 230 is formed in the insulator 282, the insulator 280, the insulator 273, and the insulator 275 (see FIG. 50). The opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 240a and the conductor 240b are provided in contact with the side surface of the oxide 230.

Next, a conductive film to be a first conductor of the conductor 240 and a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when the openings are formed in the insulator 282, the insulator 280, the insulator 273, and the insulator 275, the region of the oxide 230 in which the resistance is reduced may be removed. Alternatively, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used as the first conductor of the conductor 240. Accordingly, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or an oxygen vacancy is formed in the region, and the contact region between the oxide 230 and the conductor 240 is reduced in resistance. Can be By reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured. Therefore, the first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium.

Next, by performing a CMP process, a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 282 is exposed. As a result, the conductive film 240a and the conductive body 240b having a flat upper surface can be formed by leaving the conductive film only in the openings (see FIG. 43).

Through the above steps, a semiconductor device including the transistor 200D can be manufactured. As illustrated in FIGS. 45 to 50, the transistor 200D can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

<Modification of semiconductor device>
Hereinafter, an example of a semiconductor device including the transistor 200D according to one embodiment of the present invention will be described with reference to FIGS.

FIG. 51A is a top view of a semiconductor device having a transistor 200D. FIG. 51B, FIG. 51C, and FIG. 51D are cross-sectional views of the semiconductor device. Here, FIG. 51B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 51A and also a cross-sectional view in the channel length direction of the transistor 200D. FIG. 51C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 51A and is a cross-sectional view in the channel width direction of the transistor 200D. FIG. 51D is a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 51A and is a cross-sectional view of the source region or the drain region of the transistor 200D. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

Note that, in the semiconductor device illustrated in FIG. 51, structures having the same functions as those of the semiconductor device (see FIG. 43) illustrated in <Structure example of semiconductor device> are denoted by the same reference numerals.

Hereinafter, the structure of the transistor 200D will be described with reference to FIG. Note that also in this item, the material described in detail in the above embodiment and <Structure Example of Semiconductor Device> can be used as a material of the transistor 200D.

In the semiconductor device shown in FIG. 51, the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and a surface parallel to the substrate surface have a taper angle. Specifically, as illustrated in FIG. 51B, the taper angle may be 45 ° to 80 °, preferably 50 ° to 70 °. When the insulator 224, the oxide 230a, and the oxide 230b have a tapered structure, anisotropic etching is performed on the insulating film 272A and the insulating film 277A (see FIGS. 45 and 46). Further, the side surfaces of the oxide 230a and the oxide 230b can be completely exposed.

Therefore, as compared with the semiconductor device having a structure having no tapered structure (see FIG. 43), the side surface of the oxide 230a and the oxide 230b also reliably contacts the film 242A (see FIG. 47). Become. Accordingly, the metal compound is reliably formed on the side surfaces of the oxide 230a and the oxide 230b, and the resistance can be reduced. That is, the region 231 can be reliably formed also on the side surface of the oxide 230. In addition, since the oxide 230a and the oxide 230b have a tapered structure, the coatability of the structure formed in an upper layer than the oxide 230a and the oxide 230b can be improved.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 5)
An example of a semiconductor device including the transistor 200E according to one embodiment of the present invention, which is different from the semiconductor device including the transistor described in Embodiment 3 will be described below.

Note that in the semiconductor device described in this embodiment, the structure having the same function as the structure of the semiconductor device described in any of the above embodiments may be denoted with the same reference sign. Therefore, a description is mainly given of differences from the semiconductor device described in the above embodiment, and a repetitive description is omitted. Further, in the case where there is no particular description of a material, a manufacturing method, or the like having a structure with the same symbol, the contents described in the above embodiment modes can be referred to for the material, the manufacturing method, and the like of the structure.

<Configuration Example 1 of Semiconductor Device>
FIG. 52 is a top view and a cross-sectional view of the transistor 200E and the periphery of the transistor 200E according to one embodiment of the present invention.

FIG. 52A is a top view of a semiconductor device including a transistor 200E. FIGS. 52B and 52C are cross-sectional views of the semiconductor device. Here, FIG. 52B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 52A and also a cross-sectional view in the channel length direction of the transistor 200E. FIG. 52C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 52A and is a cross-sectional view in the channel width direction of the transistor 200E. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The semiconductor device of one embodiment of the present invention includes the transistor 200E, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 280, and the insulator 282. In addition, a conductor 203 that is electrically connected to the transistor 200E and functions as a wiring, and a conductor 240 that functions as a plug are included.

Note that the conductor 203 is formed so as to be embedded in the insulator 212. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be approximately the same. Note that although the conductor 203 has a single layer structure, the present invention is not limited to this. For example, the conductor 203 may have a multilayer film structure of two or more layers. Moreover, when a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

The conductor 240 is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 282. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be approximately the same. Note that although the transistor 200E shows a structure in which the conductor 240 is a single layer, the present invention is not limited to this. For example, the conductor 240 may have a stacked structure of two or more layers. Details of the opening and the conductor 240 will be described later.

[Transistor 200E]
A transistor 200E illustrated in FIG. 52 includes an insulator 270 disposed over the conductor 260, at least the oxide 230c, the insulator 250, the insulator 272 disposed in contact with the side surface of the conductor 260, and the insulator. The transistor 200C described in Embodiment 3 is different from the transistor 200C in Embodiment 3 in that the insulator 275 is provided on the side surface of the conductor 260 through the H.272.

Further, in the transistor 200E, an oxide semiconductor is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

Since the transistor 200E using an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a low power consumption semiconductor device can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200E included in a highly integrated semiconductor device.

Here, the oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, tungsten, etc. in addition to the elements constituting the oxide semiconductor, thereby reducing the resistance. There is a case. Note that aluminum, titanium, tantalum, tungsten, or the like is preferably used. In order to add the metal element to the oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film and the like, thereby forming oxygen vacancies and oxidation. The vicinity of the interface of the physical semiconductor may have a low resistance.

The periphery of the oxygen deficiency formed in the vicinity of the interface has distortion. In the case where the film is formed by a sputtering method, if the rare gas is included in the sputtering gas, the rare gas may be mixed into the oxide semiconductor during the film formation. When a rare gas is mixed into an oxide semiconductor, distortion or structural disorder occurs in the vicinity of the interface and around the rare gas. Examples of the rare gas include He and Ar. Ar is more preferable than He because of its larger atomic radius. When Ar is mixed in the oxide semiconductor, distortion or structural disorder is preferably generated. In the region where these strains or structures are disordered, it is considered that the number of metal atoms with a small number of bonded oxygen increases. The increase in the number of metal atoms with a small number of bonded oxygen may reduce the resistance in the vicinity of the interface and around the rare gas.

Further, in the case where a crystalline oxide semiconductor is used as the oxide semiconductor, the crystallinity is broken in the region where the strain or the structure is disordered, and it may be observed as amorphous.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element diffuses from the metal film into the oxide semiconductor, and the metal element can be added to the oxide semiconductor.

In addition, hydrogen existing in the oxide semiconductor diffuses into a region where the resistance of the oxide semiconductor is reduced, and becomes relatively stable when it enters oxygen vacancies existing in the region where the resistance is reduced. In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. Has been found to be relatively stable. Therefore, the region of the oxide semiconductor whose resistance has been lowered by heat treatment is further reduced, and the oxide semiconductor which has not been reduced in resistance is highly purified (reduced impurities such as water and hydrogen) and thus has a higher resistance. Tend to.

In addition, in an oxide semiconductor, the carrier density increases when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen deficiency, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, a high resistance region and a low resistance region can be provided in the oxide semiconductor by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

Here, FIG. 60 shows an enlarged view of a region 239 including the oxide 230b which is selectively reduced in resistance and is surrounded by a broken line in FIG.

As shown in FIG. 60A, the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200E, a region 231 (region 231a and region 231b) functioning as a source region or a drain region, and a region 234. And a region 232 (region 232a and region 232b) provided between the region 231 and the region 231.

In FIGS. 52 and 60, the region 234, the region 231 and the region 232 are formed in the oxide 230b. However, the present invention is not limited to this. For example, these regions may also be formed in the oxide 230a and the oxide 230c. In FIGS. 52 and 60, the boundary of each region is displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 near the surface of the oxide 230b and recede toward the conductor 240a or the conductor 240b near the lower surface of the oxide 230b.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity, such as aluminum, ruthenium, titanium, tantalum, tungsten, chromium, and indium, and an impurity is added to a desired region. do it. Note that as the impurity, an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used. Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

Therefore, the region 231 has a high carrier density and a low resistance by increasing the content of the metal element that increases conductivity, the element that forms oxygen vacancies, or the element that is trapped by oxygen vacancies. be able to.

In order to reduce the resistance of the region 231, for example, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like may be formed in contact with the region 231 of the oxide 230. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is formed over the oxide 230 through at least the insulator 250, the conductor 260, the insulator 270, the insulator 272, and the insulator 275. It is preferable to provide it.

By providing a metal film, a nitride film containing a metal element, or an oxide film containing a metal element in contact with the region 231 of the oxide 230, the metal element diffuses from the film into the region 231 of the oxide 230. A metal compound is formed at 231 to reduce resistance. In addition, part of oxygen in the oxide 230 located near the interface between the region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element or in the vicinity of the interface is absorbed by the film, In some cases, oxygen vacancies are formed in the region 231 to reduce resistance. Note that in FIG. 60, a region where the resistance of the oxide 230 is reduced is represented by oblique lines as an example. Note that in this specification and the like, the range represented by the oblique lines is not limited to the range in FIG. For example, the low resistance region (or range) is formed in a region near the interface between the oxide 230 and the conductor 240 or a region in the region 231 from the upper surface of the oxide 230 to the lower surface of the oxide 230. There is a case. The same applies to other drawings.

Further, heat treatment may be performed in an atmosphere containing nitrogen in a state where the region 231 is in contact with a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. By the heat treatment, the metal element is diffused from the metal film to the region 231 of the oxide 230, and the metal element can be added to the region 231. At that time, the region 231 of the oxide 230 and the metal element may be alloyed. When the region 231 of the oxide 230 and the metal element are alloyed, the metal element added to the oxide semiconductor is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen), and has a higher resistance.

On the other hand, in the regions (region 234 and region 232) overlapping with the conductor 260 and the insulator 272 of the oxide 230, addition of a metal element is suppressed by the conductor 260 and the insulator 272. Further, in the region 234 and the region 232 of the oxide 230, oxygen atoms in the oxide 230 are suppressed from being absorbed into the metal film, the nitride film containing a metal element, or the oxide film containing a metal element. The

Further, the region 231 of the oxide 230 and the region 232 adjacent to the region 231 are absorbed by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element, whereby the region 231 and the region Oxygen deficiency may occur in 232. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the resistance of the region 231 and the region 232 of the oxide 230 is reduced.

Here, in the case where a metal film, a nitride film containing a metal element, or an oxide film containing a metal element has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Further, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element may be removed together with hydrogen absorbed from the oxide 230 in a later step.

Note that the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is not necessarily removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230 to become an insulator and have a high resistance, it may be left. . In that case, it may function as an interlayer film.

Further, for example, when a conductive region remains in a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, the metal film can be oxidized by performing heat treatment in an oxidizing atmosphere. It becomes an insulator and increases resistance. By leaving the metal film, the nitride film containing a metal element, or the oxide film containing a metal element as an insulator, it can function as an interlayer film.

Therefore, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is preferably provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. For example, when aluminum of 0.5 nm to 5 nm is oxidized by heat treatment, aluminum oxide of 0.7 nm to 8 nm may be formed.

Here, in a transistor including an oxide semiconductor, if an impurity and an oxygen vacancy exist in a region where a channel is formed in the oxide semiconductor, electric characteristics may be easily changed and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

An oxide film may be formed as the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide, an insulator with few impurities such as water or hydrogen can be formed. In the case of using a sputtering method, for example, it is preferable to form a film using a facing target type sputtering apparatus. Since the facing target type sputtering apparatus can form a film without exposing the film formation surface to a high electric field region between the facing targets, the film formation surface can be formed without being easily damaged by plasma. It is preferable because film formation damage to the oxide 230 can be reduced when forming the insulator to be the insulator 275.

During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

The ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, so that the sputtered particles are ejected from the target. The sputtered particles adhere to and deposit on the film formation surface to form a film. Further, some ions recoil by the target, pass through a film formed as recoil ions, and may be taken into the insulator 272 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 272. When the ions are taken into the insulator 272, a region into which the ions are taken is formed in the insulator 272. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 272. Therefore, the insulator 275 is preferably formed using aluminum oxide formed by a sputtering method.

52 and 60A, the insulator 275 is in contact with the insulator 272, and the insulator 272 has a region in contact with the insulator 224 and the oxide 230c. As described above, the insulator 272 including more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition can be provided. That is, excess oxygen in the insulator 272 diffuses into the region 234 of the oxide 230, whereby oxygen vacancies in the region 234 of the oxide 230 can be reduced.

In addition, aluminum oxide may extract hydrogen in the oxide 230 by performing heat treatment in contact with the oxide 230. Therefore, the hydrogen concentration in the oxide 230 can be reduced.

The oxide 230 can be selectively reduced in resistance by combining the above structure or the above steps.

That is, when the low resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260 functioning as a gate electrode or the insulator 272 as a mask. Therefore, when the plurality of transistors 200E are formed at the same time, variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200E is determined by the width of the conductor 260 and the film thickness of the insulator 272. By setting the width of the conductor 260 to the minimum processing dimension, the transistor 200E can be miniaturized. Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, the structure of a semiconductor device including the transistor 200E according to one embodiment of the present invention is different from the semiconductor device including the transistor 200A described in Embodiment 1 and the semiconductor device including the transistor 200C described in Embodiment 3. The point will be described.

As shown in FIG. 72, the electron affinity or the energy level Ec at the bottom of the conduction band is obtained from the ionization potential Ip, which is the difference between the vacuum level Evac and the energy level Ev at the top of the valence band, and the band gap Eg. Can do. The ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus. The energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.

In addition, the oxide 230 includes a region 231, a region 232, and a region 234. Note that at least part of the region 231 includes a region in contact with the insulator 273. The region 232 includes at least a region overlapping with the insulator 272.

An insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the top surface of the oxide 230c, whereby oxygen can be effectively supplied from the insulator 250 to the region 234 of the oxide 230b. . Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Further, a metal oxide may be provided on the insulator 250 in order to efficiently supply the excess oxygen of the insulator 250 to the oxide 230. Therefore, it is preferable that the metal oxide suppress oxygen diffusion from the insulator 250. By providing the metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Further, an insulator 270 that functions as a barrier film may be provided over the conductor 260b. As the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Accordingly, it is possible to suppress the conductor 260 from being oxidized by oxygen from above the insulator 270. Further, impurities such as water or hydrogen from above the insulator 270 can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.

The insulator 270 preferably has a function as a hard mask. By using the insulator 270 as a hard mask, when the conductor 260 is processed, the side surface of the conductor 260 is substantially vertical. Specifically, the angle formed between the side surface of the conductor 260 and the substrate surface is 75 ° or more and 100. The angle may be not more than °, preferably not less than 80 ° and not more than 95 °. By processing the conductor 260 into such a shape, the insulator 272 and the insulator 275 to be formed next can be formed into desired shapes.

The insulator 272 functioning as a barrier film and a buffer layer is provided in contact with the side surface of the oxide 230 c, the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270.

For example, the insulator 272 is preferably formed using an ALD method. By using the ALD method, a dense thin film can be formed.

As the insulator 272, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having holes Etc. are preferable. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step. For example, an excess oxygen region is easily formed in the insulating film to be the insulator 272 by forming an insulating film to be the insulator 272 after the formation of the insulating film to be the insulator 272 by depositing aluminum oxide by a sputtering method. be able to.

Alternatively, the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxygen in the insulator 250 can be prevented from diffusing to the outside. Further, entry of impurities such as hydrogen and water into the oxide 230 from an end portion of the insulator 250 or the like can be suppressed. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200E can be improved.

Further, by providing the insulator 272, the insulator 250 and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Accordingly, impurities such as water or hydrogen from above the transistor 200E can be prevented from entering the oxide 230 through the insulator 250 and the conductor 260. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulator.

In the case where aluminum oxide is provided using the ALD method as the insulator 272, the thickness of the insulator 272 is preferably 0.5 nm to 3.0 nm. With this structure, excess oxygen included in the insulator 275 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260.

Further, an insulator 275 is provided on the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 with the insulator 272 interposed therebetween. As described above, the insulator 272 preferably has an excess oxygen region by the formation of the insulator to be the insulator 275. Here, in the case where the insulator 224 is processed into an island shape, a structure in which the insulator 224 and the insulator 272 are in contact with each other outside the insulator 224 may be employed. With this structure, excess oxygen in the insulator 272 can be supplied to the oxide 230 through the insulator 224.

In addition, an insulator 280 that functions as an interlayer film is preferably provided so as to cover the oxide 230, the insulator 275, and the insulator 270. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that the insulator 282 may be provided over the insulator 280. The insulator 282 is preferably an insulator similar to the insulator 210.

The openings of the insulator 282 and the insulator 280 are formed so that the inner wall of the insulator 280 is in contact with the side surface of the insulator 275. In order to form in this way, it is preferable that the etching rate of the insulator 275 be significantly lower than that of the insulator 280 when the insulator 282 and the insulator 280 are opened. When the etching rate of the insulator 275 is 1, the etching rate of the insulator 280 is preferably 5 or more, more preferably 10 or more. By opening in this way, the opening can be formed in a self-aligned manner, the margin for alignment between the opening and the gate electrode is widened, and the distance between the opening and the gate electrode is designed to be small. Therefore, the semiconductor device can be highly integrated.

For example, FIG. 53B illustrates an example in which the position of the opening is shifted to the A2 side from the designed position. However, by using the structure of the transistor 200E, the opening position can be changed even when the opening position is shifted in this way. The electrical connection between the embedded conductor 240a and the region 231a and the electrical connection between the conductor 240b embedded in the opening and the region 231b are performed in a self-aligned manner, which is favorable. Note that FIG. 53B illustrates an example in which the opening is shifted to the A2 side, but the present invention is not limited to this. For example, the opening may be shifted to the A1 side.

Here, the conductor 240a and the conductor 240b are disposed in the openings formed in the insulator 282 and the insulator 280. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 282.

The conductor 240a is in contact with the region 231a that functions as one of the source region and the drain region of the transistor 200E, and the conductor 240b is in contact with the region 231b that functions as the other of the source region and the drain region of the transistor 200E. Therefore, the conductor 240a can function as one of the source electrode and the drain electrode, and the conductor 240b can function as the other of the source electrode and the drain electrode.

Note that a conductor 240a is formed in contact with the inner walls of the openings of the insulator 282 and the insulator 280. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, a conductor 240b is formed in contact with the inner walls of the openings of the insulator 282 and the insulator 280. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

FIG. 59 is a cross-sectional view taken along the dashed-dotted line A5-A6 in FIG. 52A, and is a cross-sectional view of a region where the conductor 240a in the channel width direction of the transistor 200E and the oxide 230 are in contact with each other. It is. Note that the region where the conductor 240b and the oxide 230 are in contact has the same structure.

59A, the conductor 240a and the conductor 240b are preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surface of the oxide 230. In particular, the conductor 240a and the conductor 240b are preferably in contact with both or one of the side surface on the A5 side and the side surface on the A6 side on the side surface intersecting the channel width direction of the oxide 230. That is, a region where the conductors 240a and 240b are in contact with the oxide 230 has a cross-sectional shape like a ridge (can be referred to as a ridge contact). Alternatively, the conductor 240a and the conductor 240b may be in contact with the side surface on the A1 side (A2 side) on the side surface intersecting the channel length direction of the oxide 230. The region where the conductors 240a and 240b are in contact with the oxide 230 is not limited to the example in FIG. 59A. For example, as illustrated in FIG. 59B, the conductor 240a and the conductor 240 b may have a region in contact with the top surface of the oxide 230 and the side surface of the oxide 230. Alternatively, the conductor 240a and the conductor 240b may be in contact with the side surface on the A1 side (A2 side) on the side surface intersecting the channel length direction of the oxide 230. FIG. 59B illustrates an example of a region in contact with the conductor 240a and the conductor 240b and the side surface on the A5 side of the oxide 230. As illustrated in FIG. The body 240b may have a region in contact with the side surface on the A6 side of the oxide 230. With such a structure, the area of a region where the conductor 240a and the conductor 240b and the oxide 230 are in contact with each other can be increased. Therefore, the conductor 240a and the conductor 240b, the oxide 230, This is preferable because the contact resistance can be lowered. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor. The conductor 240a and the conductor 240b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

As shown in FIG. 52B, in the transistor 200E, a parasitic capacitance is formed between the conductor 260 and the conductor 240a. Similarly, a parasitic capacitance is formed between the conductor 260 and the conductor 240b. The parasitic capacitance is reduced by increasing the film thickness in the channel length direction of the insulator disposed between the conductor 260 and the conductor 240a (conductor 240b).

Therefore, by providing the transistor 200E with the insulator 275 in addition to the insulator 272, parasitic capacitance can be reduced. The total film thickness (EOT: Equivalent Oxide Thickness) of the insulator 275 and the insulator 272 in the channel length direction is 10 nm to 50 nm, preferably 15 nm to 30 nm. As the insulator 275, for example, aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. By reducing the parasitic capacitance, the transistor 200E can be operated at high speed.

Here, as shown in FIG. 60B, for example, when the opening is formed in the insulator 280, the low-resistance region of the region 231 in the oxide 230 may be removed. In that case, as the conductor used for the conductor 240, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used. That is, when the oxide 230 and the conductor 240 are in contact with each other, a new low resistance region is formed in the oxide 230. By forming the low resistance region, the contact resistance between the oxide 230 and the conductor 240 can be reduced. The conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten. FIG. 60B shows the vicinity of a newly reduced resistance region surrounded by a dashed-dotted frame.

In the case where the conductor 240 has a stacked structure, the insulator 280 and the conductor in contact with the insulator 282 transmit impurities such as water or hydrogen to the conductor in the same manner as the first conductor of the conductor 205. It is preferable to use a conductive material having a suppressing function. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 282 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.

<Configuration Example 2 of Semiconductor Device>
54A and 54B are a top view and a cross-sectional view of the transistor 200F and the periphery of the transistor 200F according to one embodiment of the present invention.

FIG. 54A is a top view of a semiconductor device including a transistor 200F. 54B and 54C are cross-sectional views of the semiconductor device. Here, FIG. 54B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 54A and also a cross-sectional view in the channel length direction of the transistor 200F. FIG. 54C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 54A and is a cross-sectional view in the channel width direction of the transistor 200F. Note that in the top view of FIG. 54A, some elements are omitted for clarity.

[Transistor 200F]
As shown in FIG. 54, the transistor 200F includes an insulator 214 and an insulator 216 which are disposed over a substrate (not shown), and a conductor which is disposed so as to be embedded in the insulator 214 and the insulator 216. 205, insulator 216, insulator 220 disposed over conductor 205, insulator 222 disposed over insulator 220, insulator 224 disposed over insulator 222, insulation An oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed over the body 224, an insulator 250 disposed over the oxide 230, and a conductor disposed over the insulator 250. Body 260 (conductor 260a and conductor 260b), insulator 270 disposed on conductor 260, and at least oxide 230c, insulator 250, and conductor 260 side An insulator 272 disposed in contact with the insulator 272, an insulator 275 disposed on a side surface of the conductor 260 via the insulator 272, a side surface of the insulator 275, and an insulator 273 disposed on the oxide 230 , And an insulator 276 disposed on the insulator 273.

The side surface of the insulator 275 and the insulator 273 disposed on the oxide 230 and the insulator 276 disposed on the insulator 273 are different from the transistor 200E described above. Hereinafter, differences from the transistor 200E will be described.

As shown in FIG. 54B, an insulator 273 is in contact with part of the top surface and part of the side surface of the oxide 230. An insulator 276 is provided in contact with the insulator 273. That is, with such a structure over the region 231, for example, a silicon oxide film is used as the insulator 273, and an aluminum oxide film is formed as the insulator 276 by a sputtering method, whereby hydrogen contained in the insulator 280 is formed. May be prevented from diffusing into the oxide 230. The description of the transistor 200E can be referred to for other structures, effects, and the like.

<Configuration Example 3 of Semiconductor Device>
FIG. 55 is a top view and a cross-sectional view of the transistor 200G according to one embodiment of the present invention and the periphery of the transistor 200G.

FIG. 55A is a top view of a semiconductor device having a transistor 200G. FIGS. 55B and 54C are cross-sectional views of the semiconductor device. Here, FIG. 55B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 55A and also a cross-sectional view in the channel length direction of the transistor 200G. FIG. 55C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 55A and also a cross-sectional view in the channel width direction of the transistor 200G. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

[Transistor 200G]
As illustrated in FIG. 55, the transistor 200G includes an insulator 214 and an insulator 216 which are disposed over a substrate (not illustrated), and a conductor which is disposed so as to be embedded in the insulator 214 and the insulator 216. 205, insulator 216, insulator 220 disposed over conductor 205, insulator 222 disposed over insulator 220, insulator 224 disposed over insulator 222, insulation An oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed over the body 224, an insulator 250 disposed over the oxide 230, and a conductor disposed over the insulator 250. Body 260 (conductor 260a and conductor 260b), insulator 270 disposed on conductor 260, and at least oxide 230c, insulator 250, and conductor 260 side , The insulator 272 disposed on the side surface of the conductor 260 via the insulator 272, the side surface of the insulator 275, and the insulator 274 disposed on the side surface of the oxide 230c. And having.

It differs from the transistor 200E described above in that the insulator 274 is provided on the side surface of the insulator 275 and the side surface of the oxide 230c. Hereinafter, differences from the transistor 200E will be described.

As shown in FIG. 55B, the openings of the insulator 282 and the insulator 280 are formed so that the inner wall of the insulator 280 is in contact with the side surface of the insulator 274. In order to form in this way, it is preferable that the etching rate of the insulator 274 is significantly lower than that of the insulator 280 when the insulator 282 and the insulator 280 are opened. When the etching rate of the insulator 274 is 1, the etching rate of the insulator 280 is preferably 5 or more, more preferably 10 or more. By opening in this way, the opening can be formed in a self-aligned manner, the margin for alignment between the opening and the gate electrode is widened, and the distance between the opening and the gate electrode is designed to be small. Therefore, the semiconductor device can be highly integrated.

For example, even when the position of the opening is shifted to the A1 side or the A2 side from the design position, the structure of the transistor 200G allows the electric field between the conductor 240a embedded in the opening and the region 231a. Since the electrical connection between the electrical connection 240b and the region 231b embedded in the opening and the region 231b is performed in a self-aligned manner, the electrical connection is improved.

Here, the conductor 240a and the conductor 240b are disposed in the openings formed in the insulator 282 and the insulator 280. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 282.

The conductor 240a is in contact with the region 231a that functions as one of the source region and the drain region of the transistor 200G, and the conductor 240b is in contact with the region 231b that functions as the other of the source region and the drain region of the transistor 200G. Therefore, the conductor 240a can function as one of the source electrode and the drain electrode, and the conductor 240b can function as the other of the source electrode and the drain electrode.

Note that a conductor 240a is formed in contact with the inner walls of the openings of the insulator 282 and the insulator 280. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, a conductor 240b is formed in contact with the inner walls of the openings of the insulator 282 and the insulator 280. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

As shown in FIG. 55B, in the transistor 200G, a parasitic capacitance is formed between the conductor 260 and the conductor 240a. Similarly, a parasitic capacitance is formed between the conductor 260 and the conductor 240b. The parasitic capacitance is reduced by increasing the film thickness in the channel length direction of the insulator disposed between the conductor 260 and the conductor 240a (conductor 240b).

The parasitic capacitance can be reduced by providing the transistor 200G with the insulator 274 in addition to the insulator 272 and the insulator 275. The film thickness in the channel length direction of the insulator disposed between the conductor 260 and the conductor 240a (conductor 240b) is the same as the channel length direction of the insulator 275 and the channel length direction of the insulator 272. In addition to the film thickness, the total value of the thickness of the insulator 274 in the channel length direction is obtained, so that the parasitic capacitance can be further reduced. The film thickness (EOT: Equivalent Oxide Thickness) of all of these insulators in the channel length direction is 10 nm to 50 nm, preferably 15 nm to 30 nm. As the insulator 274, for example, aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. By reducing the parasitic capacitance in this manner, the transistor 200G can be operated at high speed. The description of the transistor 200E can be referred to for other structures, effects, and the like.

<Configuration Example 4 of Semiconductor Device>
FIG. 56 is a top view and a cross-sectional view of the transistor 200H and the periphery of the transistor 200H according to one embodiment of the present invention.

FIG. 56A is a top view of a semiconductor device including a transistor 200H. FIGS. 56B and 56C are cross-sectional views of the semiconductor device. Here, FIG. 56B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 56A and also a cross-sectional view in the channel length direction of the transistor 200H. FIG. 56C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 56A and is a cross-sectional view in the channel width direction of the transistor 200H. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

[Transistor 200H]
As shown in FIG. 56, the transistor 200H includes an insulator 214 and an insulator 216 which are disposed over a substrate (not shown), and a conductor which is disposed so as to be embedded in the insulator 214 and the insulator 216. 205, insulator 216, insulator 220 disposed over conductor 205, insulator 222 disposed over insulator 220, insulator 224 disposed over insulator 222, insulation An oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed over the body 224, an insulator 250 disposed over the oxide 230, and a conductor disposed over the insulator 250. Body 260 (conductor 260a and conductor 260b), insulator 270 disposed on conductor 260, and at least oxide 230c, insulator 250, and conductor 260 side An insulator 272 disposed in contact with the insulator 272, an insulator 275 disposed on a side surface of the conductor 260 via the insulator 272, a side surface of the insulator 275, and an insulator 273 disposed on the oxide 230 And an insulator 276 disposed on the insulator 273 and an insulator 274 disposed on a side surface of the insulator 275 with the insulator 273 and the insulator 276 interposed therebetween.

It differs from the transistor 200F described above in that the insulator 274 is provided on the side surface of the insulator 275 with the insulator 273 and the insulator 276 interposed therebetween. Hereinafter, differences from the transistor 200F will be described.

56B, the openings of the insulator 282, the insulator 280, the insulator 276, and the insulator 273 are formed so that the inner wall of the insulator 280 is in contact with the side surface of the insulator 274. In order to form in this way, the opening rate of the insulator 274 when the insulator 282 and the insulator 280 are opened should be significantly lower than the etching rate of the insulator 280, the insulator 276, and the insulator 273. Is preferred. When the etching rate of the insulator 274 is 1, the etching rates of the insulator 280, the insulator 276, and the insulator 273 are preferably 5 or more, and more preferably 10 or more. By opening in this way, the opening can be formed in a self-aligned manner, the margin for alignment between the opening and the gate electrode is widened, and the distance between the opening and the gate electrode is designed to be small. Therefore, the semiconductor device can be highly integrated.

For example, even when the position of the opening is shifted to the A1 side or the A2 side from the designed position, by using the structure of the transistor 200H, electrical connection between the conductor 240a embedded in the opening and the region 231a can be achieved. Since the electrical connection between the electrical connection 240b and the region 231b embedded in the opening and the region 231b is performed in a self-aligned manner, the electrical connection is improved.

Here, the conductor 240a and the conductor 240b are arranged in openings formed in the insulator 282, the insulator 280, the insulator 276, and the insulator 273. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 282.

The conductor 240a is in contact with the region 231a that functions as one of the source region and the drain region of the transistor 200H, and the conductor 240b is in contact with the region 231b that functions as the other of the source region and the drain region of the transistor 200H. Therefore, the conductor 240a can function as one of the source electrode and the drain electrode, and the conductor 240c can function as the other of the source electrode and the drain electrode.

Note that a conductor 240a is formed in contact with the inner walls of the openings of the insulator 282, the insulator 280, the insulator 276, and the insulator 273. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, a conductor 240b is formed in contact with the inner walls of the openings of the insulator 282, the insulator 280, the insulator 276, and the insulator 273. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

As shown in FIG. 56B, in the transistor 200H, a parasitic capacitance is formed between the conductor 260 and the conductor 240a. Similarly, a parasitic capacitance is formed between the conductor 260 and the conductor 240b. The parasitic capacitance is reduced by increasing the film thickness in the channel length direction of the insulator disposed between the conductor 260 and the conductor 240a (conductor 240b).

The parasitic capacitance can be reduced by providing the transistor 200H with the insulator 273, the insulator 276, and the insulator 274 in addition to the insulator 272 and the insulator 275. The film thickness in the channel length direction of the insulator disposed between the conductor 260 and the conductor 240a (conductor 240b) is the same as the channel length direction of the insulator 275 and the channel length direction of the insulator 272. In addition to the film thickness, the total value of the film thicknesses of the insulator 273, the insulator 276, and the insulator 274 in the channel length direction can be further reduced. The film thickness (EOT: Equivalent Oxide Thickness) of all of these insulators in the channel length direction is 10 nm to 50 nm, preferably 15 nm to 30 nm. As the insulator 274, for example, aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. By reducing the parasitic capacitance in this manner, the transistor 200H can be operated at high speed. The description of the transistor 200F can be referred to for other structures and effects.

<Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used for the semiconductor device will be described. Note that, in the structure of the semiconductor device described in this embodiment, in the case where there is no particular description of a material having a structure denoted by the same reference numeral as that of the structure described in the previous embodiment, The constituent materials described can be taken into consideration.

<< Insulator >>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

For example, as the insulator 275 and the insulator 276, a metal containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium An oxide can be used.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be increased by increasing the film thickness. Therefore, by adjusting the film thickness of hafnium oxide, appropriate addition amounts of hydrogen and nitrogen can be adjusted.

The insulator 272, the insulator 273, and the insulator 274 preferably have an insulator with a low relative dielectric constant. For example, the insulator 272, the insulator 273, and the insulator 274 were added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and nitrogen. It is preferable to include silicon oxide, silicon oxide having holes, resin, or the like. Alternatively, the insulator 272, the insulator 273, and the insulator 274 are added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen added. It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including the transistor 200E according to the present invention will be described with reference to FIGS. In FIGS. 61 to 71, (A) in each drawing shows a top view. Further, (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line in A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200E. Further, (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200E. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. Note that the insulator 210 in Embodiment 1 can be referred to for the material, the deposition method, and the like of the insulator 210.

Next, a conductive film to be the conductor 203 is formed over the insulator 210. The conductive film to be the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film to be the conductor 203 can be a multilayer film. In this embodiment, tungsten is formed as the conductive film to be the conductor 203.

Next, the conductive film to be the conductor 203 is processed using a lithography method, and the conductor 203 is formed.

Note that a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the conductive film to be the conductor 203, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape. A hard mask can be formed. Etching of the conductive film to be the conductor 203 may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the conductive film to be the conductor 203 is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

Next, an insulating film to be the insulator 212 is formed over the insulator 210 and the conductor 203. The insulating film to be the insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed by a CVD method as the insulating film to be the insulator 212.

Here, the thickness of the insulating film to be the insulator 212 is preferably greater than or equal to the thickness of the conductor 203. For example, when the thickness of the conductor 203 is 1, the thickness of the insulating film to be the insulator 212 is 1 or more and 3 or less. In this embodiment, the thickness of the conductor 203 is 150 nm, and the thickness of the insulating film to be the insulator 212 is 350 nm.

Next, by performing a CMP process on the insulating film to be the insulator 212, a part of the insulating film to be the insulator 212 is removed, and the surface of the conductor 203 is exposed. Accordingly, the conductor 203 and the insulator 212 having a flat upper surface can be formed (see FIG. 61).

Here, a method for forming the conductor 203 different from the above will be described below.

An insulator 212 is formed on the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an opening reaching the insulator 210 is formed in the insulator 212. The opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing. The insulator 210 is preferably selected from an insulator that functions as an etching stopper film when the insulator 212 is etched to form a groove. For example, in the case where a silicon oxide film is used for the insulator 212 for forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 210.

After the opening is formed, a conductive film to be the conductor 203 is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, the conductive film to be the conductor 203 has a multilayer structure. First, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride for the lower layer of the conductive film to be the conductor 203, even if a metal such as copper that is easily diffused is used as the upper conductive film of the conductive film to be the conductor 203 described later, the metal Can be prevented from diffusing out of the conductor 203.

Next, an upper conductive film is formed as the conductive film 203. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the upper conductive film of the conductive film to be the conductor 203.

Next, by performing CMP treatment, the upper layer of the conductive film to be the conductor 203 and a part of the lower layer of the conductive film to be the conductor 203 are removed, and the insulator 212 is exposed. As a result, the conductive film to be the conductor 203 remains only in the opening. Accordingly, the conductor 203 having a flat upper surface can be formed. Note that part of the insulator 212 may be removed by the CMP treatment. The above is a different method for forming the conductor 203.

Next, the insulator 214 and the insulator 216 are sequentially formed over the insulator 212 and the conductor 203. Note that the insulator 214 and the insulator 216 in Embodiment 1 can be referred to for the material and the deposition method of the insulator 214 and the insulator 216, respectively.

Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing.

After the opening is formed, a conductive film to be the conductor 205a is formed. The conductive film to be the conductor 205a preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride is formed by a sputtering method as the conductive film to be the conductor 205a.

Next, a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, titanium nitride is formed by a CVD method as a conductive film to be the conductor 205b, and tungsten is formed by a CVD method on the titanium nitride.

Next, by performing CMP treatment, the conductive film to be the conductor 205a and the conductive film to be the conductor 205b are partially removed, and the insulator 216 is exposed. As a result, the conductive film to be the conductor 205a and the conductive film to be the conductor 205b remain only in the opening. Accordingly, the conductor 205 including the conductor 205a and the conductor 205b with a flat upper surface can be formed (see FIG. 61). Note that part of the insulator 216 may be removed by the CMP treatment.

Next, the insulator 220, the insulator 222, the insulating film 224A, the oxide film 230A to be the oxide 230a, and the oxide film 230B to be the oxide 230b are sequentially formed over the insulator 216 and the conductor 205 (see FIG. 61). Note that the material and the film formation method of the insulator 220 and the insulator 222 can refer to the insulator 220 and the insulator 222 in Embodiment 1, respectively, and the material and the film formation method of the insulating film 224A can be referred to. Can refer to the insulating film 224A of Embodiment 3, and the materials, formation methods, and the like of the oxide film 230A and the oxide film 230B refer to the oxide film 230A and the oxide film 230B of Embodiment 1, respectively. be able to.

Next, the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b. Note that in this step, the insulating film 224A may be processed into an island shape (insulator 224). In that case, the insulator 222 can be used as an etching stopper film (see FIG. 62).

Here, the oxide 230 a and the oxide 230 b are formed so that at least a part thereof overlaps with the conductor 205. The side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200E are provided, the area can be reduced and the density can be increased. Alternatively, the angle formed by the side surfaces of the oxides 230a and 230b and the upper surface of the insulator 222 may be a small angle. In that case, the angle formed between the side surfaces of the oxides 230a and 230b and the upper surface of the insulator 222 is preferably greater than or equal to 60 ° and less than 70 °. With such a shape, the insulator 272 and the insulator 275 can be prevented from being formed on the side surfaces of the oxide 230a and the oxide 230b in a later process.

Further, a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the oxide 230b. By not having a corner at the end, the coverage of the film in the subsequent film forming process is improved.

Note that the oxide film may be processed using a lithography method. For the processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.

Further, by performing a process such as dry etching, impurities due to an etching gas or the like may adhere to or diffuse on the surface or inside of the oxide 230a and the oxide 230b. Examples of impurities include fluorine and chlorine.

¡Clean to remove the above impurities. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.

As the wet cleaning, cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.

Next, an oxide film 230C is formed over the insulating film 224A, the oxide 230a, and the oxide 230b (see FIG. 63). Note that the oxide film 230C of Embodiment 1 can be referred to for the material, the deposition method, and the like of the oxide film 230C.

Subsequently, an insulating film 250A, a conductive film 260A, a conductive film 260B, and an insulating film 270A are sequentially formed over the oxide film 230C (see FIG. 63).

First, an insulating film 250A is formed. Note that the insulating film 250A in Embodiment 1 can be referred to for a material, a formation method, and the like of the insulating film 250A.

Here, a metal oxide film may be formed on the insulating film 250A. As the metal oxide film, an In—Ga—Zn oxide is formed by a sputtering method. As a method for forming the metal oxide film, a sputtering method is preferably used in an atmosphere containing oxygen gas. By forming the metal oxide film in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. The excess oxygen added to the insulating film 250 </ b> A can compensate oxygen vacancies in the oxide 230 by supplying oxygen to the oxide 230.

Here, as a means for forming the metal oxide film, the insulating film 250A and the insulating film 224A are formed while forming the metal oxide film by forming a film in an oxygen gas atmosphere using a sputtering apparatus. Oxygen can be introduced into the. In addition, by using one or both of aluminum and hafnium having barrier properties for the metal oxide film, excess oxygen introduced into the insulating film 250A can be effectively contained.

Next, a conductive film 260A and a conductive film 260B are formed. Note that the conductive film 260A and the conductive film 260B in Embodiment 1 can be referred to for the materials, formation methods, and the like of the conductive film 260A and the conductive film 260B, respectively.

For example, a metal nitride may be formed as the conductive film 260A by a sputtering method. For example, in the case where an oxide semiconductor typified by an In—Ga—Zn oxide is used as the metal oxide film, the metal oxide film has a high carrier density by being supplied with nitrogen or hydrogen. That is, it functions as an oxide conductor (OC). Therefore, by forming a metal nitride as the conductive film 260A by a sputtering method, a constituent element (particularly nitrogen) in the metal nitride is diffused into the metal oxide film previously formed, and the metal oxide film has a low thickness. Make resistance. Further, the resistance of the metal oxide film is reduced due to damage (for example, sputtering damage) during the formation of the conductive film 260A. Therefore, the carrier density of the metal oxide film is increased, and the conductivity of the metal oxide film is increased.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed. By this heat treatment, excess oxygen is added from the metal oxide film to the insulating film 250A, and an excess oxygen region can be easily formed in the insulating film 250A.

The insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, the oxidation of the conductor 260 can be suppressed. Further, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed. In this embodiment mode, the insulating film 270A has a two-layer structure, aluminum oxide is formed by an ALD method, and then silicon oxide is formed by a CVD method.

Next, the insulating film 270A is etched to form the insulator 270. Here, the insulator 270 functions as a hard mask. By providing the insulator 270, the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the conductor 260a, and the side surface of the conductor 260b can be formed substantially perpendicular to the top surface of the substrate.

Next, using the insulator 270 as a mask, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are etched to form the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b). ) (See FIG. 64).

Further, the oxide 230c, the insulator 250, the conductor 260, and the insulator 270 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.

Further, the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 are preferably in the same plane.

In addition, the same surface shared by the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 is preferably substantially perpendicular to the upper surface of the substrate. That is, in the cross-sectional shape, it is preferable that the angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 be an acute angle and large. Note that in the cross-sectional shape, an angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the upper surface of the oxide 230 may be an acute angle. In that case, the angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 is preferably as large as possible.

Next, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 270 (see FIG. 65). The insulating film 272A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by an ALD method having excellent coverage. By using the ALD method, the insulating film 272 </ b> A having a uniform thickness is formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 even in the step portion formed by the conductor 260 and the like. be able to. In addition, a dense thin film can be formed by using the ALD method.

As the insulating film 272A, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or It is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

On the other hand, aluminum oxide having a barrier property or the like may be provided as the insulating film 272A. For example, in the case where the conductor 260 is a metal film that is easily oxidized, an insulator having a barrier property can be used to suppress the conductor 260 from being oxidized by oxygen from above the insulating film 272A. Thereby, it can suppress that the resistance value of the conductor 260 goes up.

In the case where aluminum oxide is provided using the ALD method as the insulating film 272A, the thickness of the insulating film 272A is preferably 0.5 nm to 3.0 nm. With this structure, excess oxygen included in the insulator 275 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an insulating film 275A is formed. The insulating film 275A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is formed as the insulating film 275A by a sputtering method. Through this film formation, oxygen can be added to the insulating film 272A. The oxygen is added to the oxide 230 through the insulating film 272A, so that defects in the oxide 230 can be repaired (see FIG. 66).

Next, anisotropic etching is performed on the insulating film 272A and the insulating film 275A to form the insulator 272 and the insulator 275 (see FIG. 67).

As the anisotropic etching process, it is preferable to perform a dry etching process. Accordingly, the insulator 272 and the insulator 275 can be formed in a self-aligning manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.

Subsequently, a film 242A is formed over the insulator 222, the insulator 224, and the oxide 230 through the oxide 230c, the insulator 250, the conductor 260, the insulator 270, the insulator 272, and the insulator 275. (See FIG. 68). Note that the film 242A has a thickness of 0.5 nm to 5 nm, preferably, 1 nm to 3 nm. As the film 242A, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used. The film 242A is a film containing a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. Note that the film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment is performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state. For example, as the heat treatment, treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the film 242A is formed.

By the heat treatment in an atmosphere containing nitrogen, the above-described metal element diffuses from the film 242A to the oxide 230, and the metal element can be added to the oxide 230. In addition, oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed by the film 242A. As a result, the vicinity of the interface of the oxide 230 with the film 242A becomes a metal compound, and the resistance is reduced. At that time, part of the oxide 230 and the metal element described above may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters into oxygen vacancies existing in the region 231, a relatively stable state is obtained. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen), and has a higher resistance.

Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.

Further, in the case where a conductive region remains in the film 242A, the film 242A is oxidized by performing heat treatment in an oxidizing atmosphere, so that it becomes an insulator and has high resistance. By leaving the film 242A as an insulator, the film 242A can function as an interlayer film.

In the film formation step of the film 242A or heat treatment, oxygen in the region 231 and the region 232 is absorbed by the film 242A because oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 are absorbed. May occur. When hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 and the region 232 increases. Accordingly, the region 231 and the region 232 of the oxide 230 are n-type and have low resistance.

Subsequently, the film 242A is removed. Note that the metal film, the nitride film containing a metal element, or the oxide film containing a metal element is not necessarily removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230 to become an insulator and have a high resistance, it may be left. . In that case, it may function as an interlayer film. In this step, a dry etching method or a wet etching method can be used. By removing the film 242A, hydrogen in the oxide 230 absorbed by the film 242A can be removed at the same time. Accordingly, hydrogen which is an impurity in the transistor 200E can be reduced (see FIG. 69).

Next, an insulator 280 is formed. Note that the insulator 280 of Embodiment 1 can be referred to for a material, a formation method, and the like of the insulator 280.

Next, an insulating film to be the insulator 282 may be formed over the insulator 280. The insulating film to be the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 282, an aluminum oxide film is preferably formed by a sputtering method, for example. An aluminum oxide film formed by a sputtering method may extract hydrogen from a deposition target structure. Therefore, in some cases, the diffusion of hydrogen included in the insulator 280 to the oxide 230 can be suppressed by forming an aluminum oxide film by a sputtering method.

Next, an opening reaching the region 231 of the oxide 230 is formed in the insulator 280 and the insulator 282 (see FIG. 70). The opening may be formed using a lithography method. Here, the opening is formed so that the conductor 240 is provided in contact with the side surface of the insulator 275. As the opening condition, it is preferable that the etching rate of the insulator 280 be higher than the etching rate of the insulator 275, that is, the etching rate of the insulator 275. When the etching rate of the insulator 275 is 1, the etching rate of the insulator 280 is preferably 5 or more, more preferably 10 or more. With such an opening condition, the opening can be disposed in the region 231 in a self-aligned manner, so that a fine transistor can be manufactured. Further, in the lithography process, an allowable range for the positional deviation between the conductor 260 and the opening is increased, so that an improvement in yield can be expected.

For example, even if the position of the opening is shifted to the A1 side or the A2 side from the design position, the electrical connection between the conductor 240a embedded in the opening and the region 231a in a later process and the conductor 240b embedded in the opening And the region 231b are electrically connected to each other in a self-aligned manner.

Next, conductive films to be the conductors 240a and 240b are formed. The conductive film to be the conductor 240a and the conductor 240b preferably has a stacked structure including a conductor having a function of suppressing transmission of impurities such as water or hydrogen. For example, a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used. The conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when the openings are formed in the insulator 280 and the insulator 282, the region of the oxide 230 in which the resistance is reduced may be removed. When a conductive film to be the conductor 240a and the conductor 240b is formed in the opening, since the oxide 230 and the conductive film to be the conductor 240a and the conductor 240b are in contact with each other, a metal compound or Oxygen vacancies are formed, and the resistance of the contact region between the oxide 230 and the conductive film to be the conductor 240a and the conductor 240b can be reduced. By reducing the resistance of the contact region, sufficient ohmic contact between the oxide 230 and the conductors 240a and 240b can be ensured. Therefore, the conductive film to be the conductor 240a and the conductor 240b preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium.

Next, by performing a CMP process, a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 282 is exposed. As a result, the conductive film remains only in the opening, whereby the conductor 240a and the conductor 240b having a flat upper surface can be formed (see FIGS. 71 and 52).

Alternatively, the conductor 240a and the conductor 240b may be formed after aluminum oxide is formed on the side wall of the opening. By forming aluminum oxide on the side wall portion of the opening, permeation of oxygen from the outside can be suppressed and oxidation of the conductors 240a and 240b can be prevented. Further, impurities such as water and hydrogen can be prevented from diffusing outside from the conductor 240a and the conductor 240b. The aluminum oxide can be formed by forming an aluminum oxide film in the opening using an ALD method or the like and performing anisotropic etching.

Through the above steps, a semiconductor device including the transistor 200E can be manufactured. As illustrated in FIGS. 61 to 71, the transistor 200E can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.

Note that FIG. 57 illustrates a structural example in which the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is small. With such a shape, since the insulator 272 and the insulator 275 are not formed on the side surfaces of the oxide 230a and the oxide 230b, the region 231 which is a low resistance region of the oxide 230 is formed on the side surface of the oxide 230a. Can also be formed.

FIG. 58 shows an example of a structure in which the film 242A remains. The region other than the region in contact with the oxide 230 of the film 242A is increased in resistance and left as the insulator 242B, so that the film can function as an interlayer film.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 6)
Hereinafter, hydrogen in an In—Ga—Zn oxide (in some cases, referred to as IGZO) that can be used as an oxide semiconductor for the transistor of one embodiment of the present invention will be described.

<1. Transfer of hydrogen atoms>
Here, the ease of movement of hydrogen atoms in the IGZO crystal was evaluated from the viewpoint of the activation barrier on the movement path of hydrogen atoms. Note that hopping from one oxygen to another and movement on one oxygen were assumed as the movement mode of hydrogen atoms.

FIG. 73 shows a schematic diagram of a region division in the InGaZnO ₄ crystal in which the migration path of hydrogen atoms was examined. Here, the path (in the ab plane direction) and each region in the InO ₂ region, the (Ga, Zn) O region, and the region between the InO ₂ surface and the (Ga, Zn) O surface shown in FIG. The traversing path (c-axis direction) was examined.

The evaluation of the activation barrier was performed using the first-principles electronic state / molecular dynamics calculation package VASP (Vienna ab initio simulation package), and the NEB (Nudged Elastic Band) method, which is a chemical reaction path search method, was used. The NEB method is a technique for finding a state where the required energy is the lowest among the states connecting the two states from the initial state and the final state. The activation barrier was the difference between the maximum energy in the pathway and the energy of the most stable structure on the pathway.

<< Area between InO ₂ plane and (Ga, Zn) O plane >>
FIG. 74 shows a movement path of hydrogen atoms in a region between the InO ₂ plane and the (Ga, Zn) O plane and an activation barrier on the path. However, the most stable structure on the path was used as a reference, and the energy of the structure was used as the energy origin. 74A and 74C show the movement of hydrogen atoms, which are referred to as path A and path B, respectively. Note that in FIGS. 74A to 74D, the numbers indicate the order of movement of hydrogen atoms. The path A is a linear path with respect to the path from 3 to 4 for the hydrogen atoms. On the other hand, in the path B, the path through which hydrogen atoms go from 3 to 4 is a path through 5.

FIG. 74B shows the calculation result of the activation barrier in the path A (path where hydrogen atoms move from 1 to 4), and FIG. 5 shows the calculation result of the activation barrier in the route traveling via 5). Note that the horizontal axis in FIGS. 74B and 74D is a hydrogen transfer path, and the unit is an arbitrary unit.

The activation barrier on path A shown in FIG. 74 (B) was 1.12 eV, and the activation barrier on path B shown in FIG. 74 (D) was 0.23 eV. Since the activation barrier on the path B is smaller than the path A, it is considered that the path B having a low barrier on the path is likely to occur when the hydrogen atoms go from 3 to 4. That is, when hydrogen atoms move in the region between the InO ₂ surface and the (Ga, Zn) O surface, it is presumed that the path B having a low barrier on the path is likely to occur.

<< (Ga, Zn) O region >>
Next, FIG. 75 shows a movement path of hydrogen atoms in the (Ga, Zn) O region and an activation barrier on the path. However, the most stable structure on the path was used as a reference, and this structure was used as the origin of energy. FIG. 75A shows the movement of hydrogen atoms in the (Ga, Zn) O region. In FIG. 75A, numerals indicate the order of movement of hydrogen atoms. FIG. 75 (B) shows the calculation result of the activation barrier in the path in which hydrogen atoms move from 1 to 4 in FIG. 75 (A).

FIG. 75B shows that the activation barrier on the hydrogen atom migration path in the (Ga, Zn) O region is 0.16 eV, which is smaller than the activation barrier shown in FIG. I understand. Considering only the height of the barrier, when hydrogen atoms are present in the (Ga, Zn) O region, compared to the case where they are present in the region between the InO ₂ surface and the (Ga, Zn) O surface, The movement of hydrogen atoms is expected to occur easily.

<< InO ₂ region >>
Next, FIG. 76 shows a movement path of hydrogen atoms in the InO ₂ region and an activation barrier on the path. However, the most stable structure on the path was used as a reference, and this structure was used as the origin of energy. FIG. 76A shows a state of movement of hydrogen atoms in the InO ₂ region. In FIG. 76A, the numbers indicate the order of movement of hydrogen atoms. FIG. 76 (B) shows the calculation result of the activation barrier in the path in which hydrogen atoms move from 1 to 4 in FIG. 76 (A).

From FIG. 76B, the activation barrier when hydrogen atoms move from one oxygen to another in the InO ₂ region was 1.2 eV or more. That is, it can be seen that the activation barrier on the migration path of hydrogen atoms in the InO ₂ region is very large as compared with the activation barrier shown in FIGS. 74 (D) and 75 (B). Therefore, it is considered that hydrogen atoms are less likely to move in the InO ₂ region than in other regions.

Next, FIG. 77 shows a movement path of hydrogen atoms along the c-axis direction and an activation barrier on the path. However, the most stable structure on the path was used as a reference, and this structure was used as the energy origin. FIG. 77A shows the movement of hydrogen atoms along the c-axis direction. In FIG. 77A, numerals indicate the order of movement of hydrogen atoms. FIG. 77 (B) shows the calculation result of the activation barrier in the path in which hydrogen atoms move from 1 to 8 in FIG. 77 (A).

From FIG. 77 (B), the activation barrier in the path of hydrogen atoms moving from 2 to 5 was 0.9 eV. That is, it can be seen that there is a large activation barrier when hydrogen atoms enter or leave the (Ga, Zn) O region. This is thought to be because the movement path of hydrogen atoms is blocked by the bonds between metal atoms and oxygen atoms. In addition, from FIG. 77B, the activation barrier in the path in which hydrogen atoms move from 7 to 8 was about 1.5 eV. That is, the presence of a large activation barrier is confirmed even by the movement of hydrogen atoms in the InO ₂ region. For this reason, it is expected that continuous movement of hydrogen atoms in the c-axis direction hardly occurs. One possible cause of the large activation barrier is the large In ion radius.

Here, the movement frequency (Γ) was calculated from the activation barrier obtained by the calculation and the following Equation 1.

Here, E _a is an activation barrier, k _B is a Boltzmann constant, T is an absolute temperature, and ν is a frequency factor.

Finally, Table 1 shows the movement frequency estimated from the maximum value (maximum barrier) of the activation barrier on each route.

At both 27 ° C. and 450 ° C., the frequency of movement in the ab plane direction in the region between the InO ₂ surface and the (Ga, Zn) O surface and in the (Ga, Zn) O region is the highest, while c in the InO ₂ region It was found that the frequency of movement in the axial direction tends to be low. That is, it is suggested that in a complete crystal system, hydrogen preferentially diffuses along the ab plane. However, it was found that in the heat treatment at 450 ° C., hydrogen diffuses sufficiently in the IGZO film.

<2. Site where oxygen deficiency _VO is easy to create>
Since the strength of the bond between the metal atom and the oxygen atom varies depending on the type and valence of the metal, the ease of oxygen deficiency V _{O in} IGZO depends on the type, number, distance, etc. of the metal that becomes the bond partner of the oxygen atom. It is estimated that a difference will occur. Therefore, the ease of oxygen deficiency was calculated for the InGaZnO ₄ crystal model.

InGaZnO ₄ crystal model (112 atoms) was used for the calculation. This model is shown in FIG. Ga and Zn in the (Ga, Zn) O region were arranged so as to be stable in terms of energy. At this time, there are four types of oxygen sites based on the binding partner and the number (1 to 4 shown in FIG. 78). It shows in Table 2 about each oxygen site.

The oxygen deficiency model was created by extracting one oxygen atom from the oxygen site from the above model, and the calculation was performed to stabilize (or also optimize) the structure of the oxygen deficiency model. Subsequently, the total energy was compared for the optimized structure. Table 3 shows the calculation conditions.

全 Comparison of the total energy for the optimized structure. FIG. 79 shows the relative value of the total energy with reference to the total energy of the oxygen deficiency model at the oxygen site 4 (0.0 eV). From FIG. 79, it is estimated that oxygen vacancies are easily formed at the oxygen sites 4 and the oxygen sites 2 are also relatively easily formed. On the other hand, it is estimated that the oxygen site 1 and the oxygen site 3 are less likely to be formed than the oxygen site 2 and the oxygen site 4.

<3. Ease of formation and stability of H 2 _O >
In IGZO, the calculation results show that hydrogen diffuses particularly during heat treatment, <1. This has been explained in <Transfer of hydrogen atom>. Therefore, if the oxygen deficiency V _O is present, hydrogen in an oxygen-deficient V _O has been calculated for one get out of oxygen vacancies V _O. Here, a state where a hydrogen atom is present in the oxygen deficient V 2 _O is represented as H 2 _O (sometimes referred to as V 2 _O H).

For the calculation, an InGaZnO ₄ crystal model shown in FIG. 78 was used. Here, escape hydrogen atom in the oxygen vacancy V _O from V _O, activation barrier in the movement path of the hydrogen atoms to bind oxygen atom (E _a), was calculated using the NEB method. Table 4 shows the calculation conditions.

The calculation result that the oxygen site where oxygen deficiency V 2 _O is most likely to form is the oxygen site 4 shown in FIG. This is explained in “Site where oxygen deficiency V 2 _O easily occurs”. Therefore, when the oxygen deficiency V _O is present at an oxygen site (4 shown in FIG. 78) bonded to one Ga and two Zn located in the ab plane direction, the hydrogen atom in the oxygen deficiency V _O is A calculation was made as to whether to escape from the oxygen deficient V 2 _O.

FIG. 80A shows an initial state model, and FIG. 80B shows a final state model. Note that the initial state here is a state in which hydrogen atoms are present in the oxygen deficiency V 2 _O (H 2 _{O 3} ), and the final state is an oxygen deficiency V 2 _O , one Ga and two Zn It is a structure having a state in which bonded oxygen atoms and hydrogen atoms are bonded (HO). In addition, FIG. 81 shows an activation barrier in a path through which hydrogen atoms move from the initial state to the final state. In FIG. 81, the left end of the horizontal axis is the initial state, and the right end of the horizontal axis is the final state. Further, the points plotted between the initial state and the final state represent positions through which hydrogen atoms have moved. The unit of the horizontal axis is arbitrary. Here, the total energy in the initial state was set as a reference (0.0 eV).

The calculated value of the oxygen vacancies _{V O} activation barrier to hydrogen atoms escape from _{V O} in _{(E a)} was about 1.70 eV.

Then, from the calculated with resulting activation barrier (E _a) and the above equation 1, per hour, the hydrogen atoms in the oxygen vacancy V _O is to calculate an average number of times to get out of oxygen vacancy V _O.

Assuming the frequency factor ^{ν = 10 13 [1 / sec} ], at room temperature and 250 ° C., the hydrogen atoms in the oxygen vacancy _{V O} is to calculate an average number of times to get out of oxygen vacancy _{V O.} The average number of times hydrogen atoms move from the model shown in FIG. 80A to the model shown in FIG. ^80B was about 1 × 10 ⁻¹² [times] at room temperature. Therefore, at room temperature, the probability that hydrogen atoms in the oxygen vacancy V _O exits from the oxygen vacancies V _O is very low, the state of H _O is suggested to be stable. Further, the average number of times hydrogen atoms moved from the model shown in FIG. 80A to the model shown in FIG. 80B was about 2 [times] at 250 ° C. Therefore, when the baking for one hour at 250 ° C. or higher, it is suggested the hydrogen atoms in the oxygen vacancy V _O is possible to get out of oxygen vacancy V _O.

From the above, it was found that hydrogen in the oxygen deficiency V _O existing in the channel formation region escapes from the oxygen deficiency V _O by the heat treatment. Further, it has been found that hydrogen escaped from the oxygen deficiency diffuses into the low resistance region, enters the oxygen deficiency V _O existing in the low resistance region, and easily becomes H 2 _O. Therefore, the channel formation region is highly purified (reduction of impurities such as water and hydrogen) by heat treatment, and normally-off transistor characteristics are obtained.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 7)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

<Configuration example of semiconductor device>
82A, 82B, and 82C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a memory device including one capacitor and at least one transistor is referred to as a cell.

82A is a top view of the cell 600 including the transistor 200 and the capacitor 100. FIG. 82B and 82C are cross-sectional views of the cell 600. FIG. Here, FIG. 82B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 82A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 82C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 82A and also a cross-sectional view in the channel width direction of the transistor 200. In the top view in FIG. 82A, some elements are omitted for clarity.

[Cell 600]
The semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulator 280 functioning as an interlayer film. In addition, a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and functions as a plug is provided.

A cell 600 illustrated in FIG. 82 includes the transistor 200 and the capacitor 100 in the same layer, so that part of the structure of the transistor 200 is used in combination with part of the structure of the capacitor 100. be able to. That is, part of the structure of the transistor 200 may function as part of the structure of the capacitor 100.

Further, by superimposing a part or the whole of the capacitor 100 on the transistor 200, the total area of the projected area of the transistor 200 and the projected area of the capacitor 100 can be reduced.

Further, the conductor 240b functioning as a plug or wiring electrically connected to the transistor 200 and the conductor 207 are provided below the region where the capacitor 100 and the transistor 200 overlap with each other, whereby the cell 600 can be miniaturized. Or high integration becomes easy. Further, since the conductor 207 can be formed in the same process as the conductor 205 which is one of the components of the transistor 200, the process can be shortened. Further, in the capacitor 100, similarly to the transistor 200, a conductor that functions as a wiring may be provided in contact with the lower surface of the conductor 207.

Note that in the capacitor 100, the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on a required capacitance value.

For example, the area of the capacitive element 100 is determined by the area where the region 231b of the oxide 230 and the conductor 120 overlap. Therefore, in the case where the capacitance value necessary for the cell 600 cannot be obtained with the capacitor 100 illustrated in FIGS. 82A and 82B, the width in the A3-A4 direction in the region 231b of the oxide 230a and the oxide 230b Can be made larger than the width in the A3-A4 direction in the region 234 of the oxide 230a and the oxide 230b, whereby the capacitance value can be increased.

For example, the length in the A1-A2 direction in the region 231b of the oxide 230 may be longer than the length in the A1-A2 direction in the conductor 120. In that case, the conductor 240b can be embedded in the insulator 280. That is, the oxide 230 region 231b and the conductor 240b may be provided in contact with each other in a region where the oxide 230 region 231b and the conductor 120 do not overlap. Therefore, the process can be shortened by forming the conductor 240a and the conductor 240b in the same process.

The miniaturization or high integration is possible by having the above structure. In addition, the degree of freedom in design can be increased. The transistor 200 is formed in the same process as the capacitor 100. Therefore, since the process can be shortened, productivity can be improved.

[Transistor 200]
As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. The transistor 200 illustrated in FIGS. 82A and 82B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

[Capacitance element 100]
As shown in FIG. 82, the capacitor 100 has a structure in common with the transistor 200. In this embodiment, an example of the capacitor 100 in which the region 231 b provided in the oxide 230 of the transistor 200 functions as one of the electrodes of the capacitor 100 is described.

The capacitor 100 includes a region 231b of the oxide 230, an insulator 278 on the region 231b, and a conductor 120 on the insulator 278. Furthermore, it is preferable that the conductor 120 be disposed over the insulator 278 so that at least part of it overlaps with the region 231 b of the oxide 230. Further, it is preferable that the conductor is disposed on and in contact with the conductor 120.

The region 231 b of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 120 functions as the other of the electrodes of the capacitor 100. The insulator 278 functions as a dielectric of the capacitor 100. The region 231b of the oxide 230 has a reduced resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100.

As the insulator 278, an insulator having a high relative dielectric constant is preferably used, and an insulator that can be used for the insulator 222 or the like may be used. For example, an insulator including one or both of aluminum and hafnium can be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator 278 may have a stacked structure, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. Therefore, two or more layers may be selected to form a laminated structure. For example, it is preferable that hafnium oxide, aluminum oxide, and hafnium oxide are sequentially formed by an ALD method to form a stacked structure. The film thicknesses of hafnium oxide and aluminum oxide are 0.5 nm to 5 nm, respectively. With such a stacked structure, the capacitor element 100 having a large capacitance value and a small leakage current can be obtained.

82 shows the structure in which the insulator 278 is provided as the dielectric of the capacitor 100, but the present invention is not limited to this. For example, in addition to the insulator 278, an insulator may be separately stacked and used as a dielectric of the capacitor 100.

The conductor 120 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Although not illustrated, the conductor 120 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

<Structure of cell array>
Here, FIG. 83 and FIG. 84 show an example of the cell array of this embodiment. For example, a cell array can be formed by arranging the transistor 200 including the transistor 200 and the capacitor 100 illustrated in FIG. 82 in a matrix or matrix.

FIG. 83A is a circuit diagram showing an embodiment in which the cells 600 shown in FIG. 82 are arranged in a matrix. In FIG. 83A, one of a source and a drain of a transistor included in a cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of a source and a drain of a transistor included in the cell 600 arranged in the column direction. On the other hand, the first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. Vth of the transistor can be controlled by a potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.

FIG. 83B shows a circuit 610 including the cell 600a electrically connected to WL04 and BL02 and the cell 600b electrically connected to WL03 and BL02 as part of the row in FIG. It is sectional drawing extracted. FIG. 83B is a cross-sectional view of the cell 600a and the cell 600b.

The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600b includes a transistor 200b and a capacitor 100b.

One of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b are both electrically connected to BL02.

With the above configuration, the area occupied by the cell array can be further reduced by using a common wiring electrically connected to one of the source and the drain.

FIG. 84A is a circuit diagram showing a mode different from FIG. 83A in a circuit in which the cells 600 shown in FIG. 82 are arranged in a matrix. In FIG. 84A, the first gate of the transistor included in the cell 600 arranged in the row direction is electrically connected to the common WL (WL01, WL02, WL03). In addition, one of a source and a drain of a transistor included in a cell arranged in the column direction is electrically connected to a common BL (BL01 to BL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. Vth of the transistor can be controlled by a potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL. Here, as illustrated in FIG. 84A, the second electrode having the capacity of the cell 600 is electrically connected to the common PL with the second electrode having the capacity of the cell 600 adjacent to the cell 600. It is good also as a structure.

84B shows a circuit 620 including the cell 600a electrically connected to WL02 and BL03 and the cell 600b electrically connected to WL02 and BL04 as part of the row in FIG. 84A. It is sectional drawing extracted. FIG. 84B is a cross-sectional view of the cell 600a and the cell 600b.

The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600b includes a transistor 200b and a capacitor 100b.

The second electrode of the capacitor 100a and the second electrode of the capacitor 100b use a common conductor, and the conductor is electrically connected to the PL.

Further, the cell 600 may be arranged not only in a plane but also in a stacked manner. FIG. 85 is a cross-sectional view of a structure in which n + 1 layers of a cell array including the circuit 610 are stacked. As shown in FIG. 85, by stacking a plurality of cell arrays, cells can be integrated and arranged without increasing the exclusive area of the cell array. That is, a 3D cell array can be configured.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 8)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described in Embodiment 7 will be described.

Note that in the example of the semiconductor device illustrated in FIGS. 86 to 89, the structure having the same function as the structure of the example of the semiconductor device described in Embodiment 7 is denoted by the same reference numeral. In the following description, parts different from the example of the semiconductor device described in Embodiment 7 will be mainly described, and the contents described in Embodiment 7 can be referred to for other parts.

<Configuration example of semiconductor device>
86A, 86B, and 86C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a memory device including one capacitor and at least one transistor is referred to as a cell.

86A is a top view of the cell 600 including the transistor 200 and the capacitor 100. FIG. 86B and 86C are cross-sectional views of the cell 600. FIG. Here, FIG. 86B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 86A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 86C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 86A and is a cross-sectional view in the channel width direction of the transistor 200. In the top view in FIG. 86A, some elements are omitted for clarity.

[Cell 600]
The semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulator 280 functioning as an interlayer film. In addition, a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and functions as a plug is provided.

[Transistor 200]
As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. A transistor 200 illustrated in FIG. 86 is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

[Capacitance element 100]
As illustrated in FIG. 86, the capacitor 100 has a structure in common with the transistor 200. In this embodiment, the region 231 b provided in the oxide 230 of the transistor 200 is described as an example of the capacitor 100 that functions as one of the electrodes of the capacitor 100.

The capacitor element 100 includes a region 231b of the oxide 230, an insulator 275 over the region 231b, an insulator 273 over the insulator 275, and a conductor 120 over the insulator 273. Furthermore, it is preferable that the conductor 120 be disposed over the insulator 273 so that at least a part thereof overlaps with the region 231 b of the oxide 230. Further, it is preferable that the conductor is disposed on and in contact with the conductor 120.

The region 231 b of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 120 functions as the other of the electrodes of the capacitor 100. The insulator 275 and the insulator 273 function as a dielectric of the capacitor 100. The region 231b of the oxide 230 has a reduced resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100.

In FIG. 86, the structure in which the insulator 275 and the insulator 273 are provided as the dielectric of the capacitor 100 is shown; however, the present invention is not limited to this. For example, in addition to the insulator 275 and the insulator 273, a structure in which a dielectric insulator is separately stacked may be employed.

<Structure of cell array>
Here, an example of the cell array of this embodiment is illustrated in FIGS. For example, a cell array can be formed by arranging the transistor 200 and the cell 600 including the capacitor 100 illustrated in FIG. 86 in a matrix or matrix.

FIG. 87A is a circuit diagram showing an embodiment in which the cells 600 shown in FIG. 86 are arranged in a matrix. In FIG. 87A, one of a source and a drain of a transistor included in a cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of a source and a drain of a transistor included in a cell arranged in the column direction. On the other hand, the first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. Vth of the transistor can be controlled by a potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.

87B illustrates a circuit 610 including the cell 600a electrically connected to WL04 and BL02 and the cell 600b electrically connected to WL03 and BL02 as part of the row in FIG. 87A. It is sectional drawing extracted. FIG. 87B is a cross-sectional view of the cell 600a and the cell 600b.

FIG. 88 (A) is a circuit diagram showing a mode different from FIG. 87 (A) in a circuit in which the cells 600 shown in FIG. 86 are arranged in a matrix. In FIG. 88A, the first gate of the transistor included in the cell 600 arranged in the row direction is electrically connected to the common WL (WL01, WL02, WL03). In addition, one of a source and a drain of a transistor included in a cell arranged in the column direction is electrically connected to a common BL (BL01 to BL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. Vth of the transistor can be controlled by a potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL. Here, as shown in FIG. 88A, the second electrode having the capacity of the cell 600 is electrically connected to the common PL with the second electrode having the capacity of the cell 600 adjacent to the cell 600. It is good also as a structure.

FIG. 88B shows a circuit 620 including the cell 600a electrically connected to WL02 and BL03 and the cell 600b electrically connected to WL02 and BL04 as part of the row in FIG. 88A. It is sectional drawing extracted. FIG. 88B is a cross-sectional view of the cell 600a and the cell 600b.

Further, the cell 600 may be arranged not only in a plane but also in a stacked manner. FIG. 89 is a cross-sectional view of a configuration in which n + 1 layers of a cell array including the circuit 610 are stacked. As shown in FIG. 89, by stacking a plurality of cell arrays, the cells can be integrated and arranged without increasing the exclusive area of the cell array. That is, a 3D cell array can be configured.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 9)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described in Embodiment 7 will be described.

Note that in the example of the semiconductor device illustrated in FIGS. 90 to 97, the structure having the same function as the structure of the example of the semiconductor device described in Embodiment 7 is denoted by the same reference numeral. In the following description, parts different from the example of the semiconductor device described in Embodiment 7 will be mainly described, and the contents described in Embodiment 7 can be referred to for other parts.

<Configuration example of semiconductor device>
90A, 90B, and 90C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a memory device including one capacitor and at least one transistor is referred to as a cell.

FIG. 90A is a top view of the cell 600 including the transistor 200 and the capacitor 100. FIG. 90B and 90C are cross-sectional views of the cell 600. FIG. Here, FIG. 90B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 90A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 90C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 90A and is a cross-sectional view in the channel width direction of the transistor 200. In the top view of FIG. 90A, some elements are omitted for clarity.

[Cell 600]
The semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulator 280 and the insulator 282 which function as an interlayer film. In addition, a conductor 240 (a conductor 240a, a conductor 240b, and a conductor 240c) that is electrically connected to the transistor 200 and functions as a plug is included.

Note that in the capacitor 100, the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on a required capacitance value.

For example, the area of the capacitor 100 is determined by the area in which the region 231 b of the oxide 230 overlaps with the conductor 120 with the insulator 278 interposed therebetween. Therefore, in the case where the capacitance value necessary for the cell 600 cannot be obtained with the capacitor 100 illustrated in FIGS. 90A and 90B, the width of the region 231b in the A3-A4 direction is set to be A3-A4 of the region 234. By making it larger than the width in the direction, the capacitance value can be increased.

Further, for example, the length of the region 231b in the A1-A2 direction may be longer than the length of the conductor 120 in the A1-A2 direction. In that case, the conductor 240b can be embedded in the insulator 280 and the insulator 282. That is, the region 231b and the conductor 240b may be provided in contact with each other in a region where the region 231b and the conductor 120 do not overlap. Therefore, the process can be shortened by forming the conductor 240a, the conductor 240b, and the conductor 240c in the same process.

In addition, with such a structure, for example, in FIG. 90B, even if the position of the opening is shifted to the A1 side or the A2 side from the designed position, the conductor 240a and the region 231a embedded in the opening And the electrical connection between the conductor 240c embedded in the opening and the conductor 120 are performed in a self-aligned manner, which is favorable. FIG. 91 shows an example in which the opening is shifted to the A2 side.

The miniaturization or high integration is possible by having the above structure. In addition, the degree of freedom in design can be increased. The transistor 200 is formed in the same process as the capacitor 100. Therefore, since the process can be shortened, productivity can be improved.

[Transistor 200]
As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. In addition, the transistor 200 illustrated in FIGS. 90A and 90B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

[Capacitance element 100]
As shown in FIG. 90, the capacitor 100 has a structure in common with the transistor 200. In this embodiment, the region 231 b provided in the oxide 230 of the transistor 200 is described as an example of the capacitor 100 that functions as one of the electrodes of the capacitor 100.

The capacitor 100 includes a region 231b of the oxide 230, an insulator 278 on the region 231b, and a conductor 120 on the insulator 278. The conductor 120 is preferably provided over the insulator 278 so that at least a part thereof overlaps with the region 231 b of the oxide 230. In addition, the conductor 240c is preferably disposed in contact with the conductor 120.

As shown in FIG. 90A, the side surface of the insulator 278 matches the side surface of the conductor 120 when viewed from above, but the present invention is not limited to this. For example, the insulator 278 may cover the transistor 200 without patterning the insulator 278.

<Structure of cell array>
Here, an example of the cell array of this embodiment is illustrated in FIGS. For example, the cell array can be formed by arranging the transistor 200 including the transistor 200 and the capacitor 100 illustrated in FIG. 90 in a matrix or matrix.

FIG. 92A is a circuit diagram showing an embodiment in which the cells 600 shown in FIG. 90 are arranged in a matrix. In FIG. 92A, one of a source and a drain of a transistor included in a cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of a source and a drain of a transistor included in a cell arranged in the column direction. On the other hand, the first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. The threshold value of the transistor can be controlled by the potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.

FIG. 92B shows a circuit 610 including the cell 600a electrically connected to WL04 and BL02 and the cell 600b electrically connected to WL03 and BL02 as part of the row in FIG. 92A. It is sectional drawing extracted. FIG. 92B is a cross-sectional view of the cell 600a and the cell 600b.

Further, with such a structure, for example, in FIG. 92B, even when the position of the opening is shifted to the A1 side or the A2 side from the designed position, the conductor embedded in the opening and the capacitor 100a Electrical connection with one of the electrodes, electrical connection between the conductor embedded in the opening and one electrode of the capacitor 100b, and conductor and transistor embedded in the opening connected to BL02 The electrical connection with one of the source and the drain of the transistor 200a and the transistor 200b is performed in a self-alignment manner, which is favorable. FIG. 93 shows an example in which the opening is shifted to the A2 side.

FIG. 94 is a circuit diagram showing an embodiment in which the cells 600 shown in FIG. 90 are arranged in a matrix with a configuration different from that shown in FIG. In the cell array shown in FIG. 94, the wiring BL is extended in the row direction, and the wiring WL is extended in the column direction.

As shown in FIG. 94, one of the source and drain of the transistor 200a and the transistor 200b constituting the cell is electrically connected to a common wiring BL (BL01, BL02, BL03). The wiring BL is also electrically connected to one of a source and a drain of the transistor 200a and the transistor 200b included in the cell 600 arranged in the row direction. On the other hand, the first gate of the transistor 200a and the first gate of the transistor 200b included in the cell 600 are electrically connected to different wirings WL (WL01 to WL06). Further, these wirings WL are electrically connected to the first gate of the transistor 200a and the first gate of the transistor 200b included in the cell 600 arranged in the column direction.

Further, the transistor 200a and the transistor 200b included in each cell 600 may be provided with a second gate BG. The second gate BG and the wiring BGL are electrically connected, and the threshold value of the transistor can be controlled by a potential applied to the wiring BGL. In addition, the conductor 120a of the capacitor 100a and the conductor 120b of the capacitor 100b included in the cell 600 are electrically connected to different wirings VL, respectively.

FIG. 95 is a cross-sectional view corresponding to a portion indicated by a dotted line in the circuit diagram shown in FIG. As shown in FIG. 95, the wiring BL02 and the wirings WL03 to WL06 are orthogonal to each other. As shown in FIG. 95, the wiring BL02 and the wiring VL are orthogonal to each other. The wiring VL is provided so as to be shared between adjacent memory cells.

FIG. 96A is a circuit diagram showing a mode different from FIG. 92A in a circuit in which the cells 600 shown in FIG. 90 are arranged in a matrix. In FIG. 96A, a first gate of a transistor included in the cell 600 arranged in the row direction is electrically connected to a common WL (WL01, WL02, WL03). In addition, one of a source and a drain of a transistor included in a cell arranged in the column direction is electrically connected to a common BL (BL01 to BL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. The threshold value of the transistor can be controlled by the potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL. Here, as illustrated in FIG. 96A, the second electrode having the capacity of the cell 600 is electrically connected to the common PL with the second electrode having the capacity of the cell 600 adjacent to the cell 600. It is good also as a structure.

FIG. 96B illustrates a circuit 620 including the cell 600a electrically connected to WL02 and BL03 and the cell 600b electrically connected to WL02 and BL04 as part of the row in FIG. It is sectional drawing extracted. FIG. 96B is a cross-sectional view of the cell 600a and the cell 600b.

Further, the cell 600 may be arranged not only in a plane but also in a stacked manner. FIG. 97 shows a cross-sectional view of a structure in which n + 1 layers of a cell array including the circuit 610 are stacked. As shown in FIG. 97, by stacking a plurality of cell arrays, the cells can be integrated and arranged without increasing the exclusive area of the cell array. That is, a 3D cell array can be configured.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 10)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Storage device 1>
The memory device illustrated in FIGS. 98 and 99 includes the transistor 300, the transistor 200, and the capacitor 100. FIG. 98 is a cross-sectional view of the transistor 200 and the transistor 300 in the channel length direction. FIG. 99 is a cross-sectional view of the transistor 300 in the vicinity of the transistor 300 in the channel width direction.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

98, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. In the memory device illustrated in FIG. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. Yes. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

The memory device shown in FIG. 98 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.

Describes the writing and holding of information. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 1003 is supplied to the node SN that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, whereby charge is held at the node SN (holding).

When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the wiring 1005 in a state where a predetermined potential (constant potential) is applied to the wiring 1001, the wiring 1002 has a potential corresponding to the amount of charge held in the node SN. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is _supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the wiring 1005 necessary for bringing the transistor 300 into a “conductive state”. Therefore, by _setting the potential of the wiring 1005 to the potential V _O between V _{th_H} and V _{th_L} , the charge given to the node SN can be determined. For example, in writing, when a high-level charge is _{supplied to} the node SN, the transistor 300 is turned “on” when the potential of the wiring 1005 becomes V _O (> V _{th_H} ). On the other hand, when a low-level charge is applied to the node SN, the transistor 300 remains in a “non-conduction state” even when the potential of the wiring 1005 becomes V _O (<V _{th_L} ). Therefore, by determining the potential of the wiring 1002, information held in the node SN can be read.

<Structure of storage device 1>
A memory device according to one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

The transistor 300 is provided over a substrate 311, and includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314 a that functions as a source region or a drain region, and a low resistance region 314 b. Have

In the transistor 300, as shown in FIG. 99, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with a conductor 316 with an insulator 315 interposed therebetween. In this manner, when the transistor 300 is of the Fin type, an effective channel width is increased, whereby the on-state characteristics of the transistor 300 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

Note that the transistor 300 illustrated in FIGS. 98A and 98B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are stacked in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

The insulator 322 may have a function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve planarity.

The insulator 324 is preferably formed using a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 into a region where the transistor 200 is provided.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of hydrogen desorption can be analyzed using, for example, TDS. For example, the amount of hydrogen desorbed from the insulator 324 is calculated by converting the amount of desorption converted to hydrogen atoms per area of the insulator 324 in the range of the surface temperature of the film from 50 ° C. to 500 ° C. in TDS analysis. 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

In addition, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, a conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 98, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 98, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, as the insulator 360, an insulator having a barrier property against hydrogen is preferably used as the insulator 360. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 98, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 98, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described above, the memory device according to this embodiment is It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384 and the conductor 386. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

For example, the insulator 210 and the insulator 214 are each formed using a film having a barrier property such that hydrogen or an impurity does not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

Further, as the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

For example, the insulator 212 and the insulator 216 can be formed using the same material as the insulator 320. In addition, by using a material having a relatively low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

In addition, in the insulator 210, the insulator 212, the insulator 214, and the insulator 216, a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A transistor 200 is provided above the insulator 216. Note that as the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. A transistor 200 illustrated in FIG. 98 is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

An insulator 280 is provided above the transistor 200.

An insulator 282 is provided on the insulator 280. The insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214. For example, the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

Further, an insulator 286 is provided on the insulator 282. The insulator 286 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.

In addition, a conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 280, the insulator 282, and the insulator 286.

The conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Subsequently, the capacitive element 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.

Alternatively, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 has a function as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

The conductor 112 and the conductor 110 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

98, the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

Further, an insulator 130 is provided as a dielectric of the capacitor 100 over the conductor 112 and the conductor 110. Examples of the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination | stacking or single layer.

For example, a material having a high dielectric strength such as silicon oxynitride may be used for the insulator 130. With this configuration, the capacitor 100 includes the insulator 130, whereby the dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

The conductor 120 is provided on the insulator 130 so as to overlap with the conductor 110. Note that the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Storage device 2>
A semiconductor device illustrated in FIG. 100 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device will be described with reference to FIG.

FIG. 100A illustrates a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 100B is a cross-sectional view of the semiconductor device in which the wiring 1003 to the wiring 1010 illustrated in FIG.

The transistor 200 and the transistor 400 formed on the substrate (not shown) have different configurations. For example, the transistor 400 may have a lower drain current when the bottom gate voltage and the top gate voltage are 0 V than the transistor 200. With the transistor 400 serving as a switching element, the potential of the bottom gate of the transistor 200 can be controlled. Accordingly, after the node connected to the bottom gate of the transistor 200 is set to a desired potential, the transistor 400 is turned off, whereby the charge of the node connected to the bottom gate of the transistor 200 is prevented from being lost. it can.

As shown in FIG. 100, the transistor 200 has a gate electrically connected to the wiring 1004, one of a source and a drain is electrically connected to the wiring 1003, and the other of the source and the drain is electrically connected to one of the electrodes of the capacitor 100. In addition, the other electrode of the capacitor 100 is electrically connected to the wiring 1005. In addition, the drain of the transistor 400 is electrically connected to the wiring 1010. In addition, as illustrated in FIGS. 100A and 100B, the bottom gate of the transistor 200 and the source, top gate, and bottom gate of the transistor 400 are connected through a wiring 1006, a wiring 1007, a wiring 1008, and a wiring 1009. Are electrically connected.

Here, by applying a potential to the wiring 1004, the on state and the off state of the transistor 200 can be controlled. When the transistor 200 is turned on and a potential is applied to the wiring 1003, electric charge can be supplied to the capacitor 100 through the transistor 200. At this time, the charge supplied to the capacitor 100 can be held by turning off the transistor 200. The wiring 1005 can be controlled to have a potential at a connection portion between the transistor 200 and the capacitor 100 by capacitive coupling by applying an arbitrary potential. For example, when the ground potential is applied to the wiring 1005, the charge is easily held. Further, by applying a negative potential to the wiring 1010, a negative potential is applied to the bottom gate of the transistor 200 through the transistor 400, the threshold voltage of the transistor 200 is made higher than 0 V, and the off-state current is reduced. , Icut can be made very small. Here, Icut refers to the drain current when the voltage applied to the top gate is 0V.

When the top gate and the bottom gate of the transistor 400 are diode-connected to the source and the source of the transistor 400 is connected to the bottom gate of the transistor 200, the bottom gate voltage of the transistor 200 can be controlled by the wiring 1010. . When the negative potential of the bottom gate of the transistor 200 is held, the voltage between the top gate and the source of the transistor 400 and the voltage between the bottom gate and the source are 0V. Since the Icut of the transistor 400 is very small and the threshold voltage is higher than that of the transistor 200, this configuration maintains the negative potential of the bottom gate of the transistor 200 for a long time without supplying power to the transistor 400. be able to.

Furthermore, by maintaining the negative potential of the bottom gate of the transistor 200, the Icut of the transistor 200 can be made extremely small without supplying power to the transistor 200. That is, electric charge can be held in the capacitor 100 for a long time without supplying power to the transistor 200 and the transistor 400. For example, by using such a semiconductor device as a memory element, long-term memory retention can be performed without power supply. Therefore, a memory device that has a low refresh operation frequency or does not require a refresh operation can be provided.

Note that the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 is not limited to that illustrated in FIGS. The connection relationship can be changed as appropriate according to the required circuit configuration.

<Structure of storage device 2>
FIG. 100B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device illustrated in FIG. 100, structures having the same functions as those of the semiconductor device described in the above embodiment and <Structure of the memory device 1> and the structure of the memory device are denoted by the same reference numerals. To do.

The memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 200 and the transistor 400.

Note that as the capacitor 100 and the transistor 200, the capacitors and transistors included in the semiconductor device and the memory device described in the above embodiment and FIGS. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIGS. 100A and 100B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductors 460a and 460b) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, an insulator 470 in contact with the conductor 460, and the conductor 460. An insulator 475 provided on a side surface, an insulator 220 functioning as a gate insulating layer, an insulator 222, an insulator 424, and an insulator 450, an oxide 430c including a region where a channel is formed, a source or a drain The oxide 431a and the oxide 431b functioning as one of the above, and the oxide 432a and the oxide 432b functioning as the other of the source or the drain. In addition, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 functioning as a wiring.

In the transistor 400, the conductor 405 is the same layer as the conductor 205. The insulator 424 is the same layer as the insulator 224. The oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The metal oxide 452 is the same layer as the metal oxide 252. The conductor 460 is the same layer as the conductor 260. The insulator 470 is the same layer as the insulator 270. The insulator 471 is the same layer as the insulator 271. The insulator 475 is the same layer as the insulator 275.

In the oxide 430c functioning as the active layer of the transistor 400, oxygen vacancies are reduced and impurities such as hydrogen or water are reduced, like the oxide 230 and the like. Accordingly, the threshold voltage of the transistor 400 can be made higher than 0V, the off current can be reduced, and the drain current when the bottom gate voltage and the top gate voltage are 0V can be made extremely small.

As described above, the oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. Thus, the oxide 431a, the oxide 432a, the oxide 431b, and the oxide 432b are formed with low resistance regions corresponding to the region 231a and the region 231b.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
A semiconductor device illustrated in FIG. 101 is a memory device including the transistor 300, the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one mode as a storage device will be described with reference to FIG.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and the transistor described in the above embodiment can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

101, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. Yes. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. . The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the top gate of the transistor 400, the wiring 1009 is electrically connected to the bottom gate of the transistor 400, and the wiring 1010 is connected to the transistor 400. It is electrically connected to the drain. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

The semiconductor device shown in FIG. 101 has the characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.

Describes the writing and holding of information. First, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 1003 is supplied to the node SN that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node SN (holding).

When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 1005 in a state where a predetermined potential (constant potential) is applied to the first wiring 1001, the second wiring 1002 has a charge held in the node SN. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is _supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage means a potential of the fifth wiring 1005 necessary for bringing the transistor 300 into a “conducting state”. Therefore, by _setting the potential of the fifth wiring 1005 to a potential V _O between V _{th_H} and V _{th_L} , the charge given to the node SN can be determined. For example, in writing, when a high-level charge is _{supplied to} the node SN, the transistor 300 is turned “on” when the potential of the fifth wiring 1005 becomes V _O (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node SN, the transistor 300 remains in a “non-conductive state” even when the potential of the fifth wiring 1005 becomes V _O (<V _{th_L} ). Therefore, by determining the potential of the second wiring 1002, the information held in the node SN can be read.

<Structure of storage device 3>

FIG. 101 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. 101 has the same function as the structure of the semiconductor device and the storage device described in the above embodiment, <Structure of storage device 1>, and <Structure of storage device 2>. The same symbols are added to the structures having the same.

The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 98 to 100 may be used. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 101A and 101B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

In the memory device illustrated in FIG. 101, the opening portion 500 is formed in the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, the insulator 273, the insulator 274, and the insulator 280. An example is shown in which the insulator 210 and the insulator 282 are connected. With such a structure, the transistor 200 and the transistor 400 are surrounded by the insulator 210 and the insulator 282 and thus are not easily affected by impurities such as water and hydrogen. In addition, release of oxygen in the oxide or the insulator to the outside is reduced. A memory device having such a structure is preferable because reliability is improved. Note that the opening 500 is not necessarily provided.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

FIG. 102 shows an example of the memory cell array of this embodiment. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

Note that the memory device illustrated in FIG. 102 is a semiconductor device which forms a memory cell array by arranging the memory devices illustrated in FIGS. 98 and 101 in a matrix. Note that one transistor 400 can control the bottom gate voltages of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.

Therefore, the transistor 400 shown in FIG. 101 is omitted from FIG. FIG. 102 is a cross-sectional view of a part of a row in the case where the memory devices illustrated in FIGS. 98 and 101 are arranged in a matrix.

FIG. 102 differs from FIG. 101 in the structure of the transistor 300. In the transistor 300 illustrated in FIG. 102, a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also referred to as a Fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

102, the memory cell 650a and the memory cell 650b are arranged adjacent to each other. The memory cell 650a and the memory cell 650b each include the transistor 300, the transistor 200, and the capacitor 100, and are electrically connected to the wiring 1001, the wiring 1002, the wiring 1003, the wiring 1004, the wiring 1005, and the wiring 1006. Similarly, in the memory cell 650a and the memory cell 650b, a node where the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is referred to as a node SN. Note that the wiring 1002 is a wiring common to the adjacent memory cells 650a and 650b.

When memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, when the memory cell array has a NOR structure, only information on a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 becomes “non-conductive” regardless of the charge applied to the node SN, that is, a potential lower than V _{th_H} is applied to the wiring 1005 connected to the memory cell from which information is not read. That's fine. Alternatively, for example, when the memory cell array has a NAND structure, only information on a desired memory cell can be read by turning on the transistor 300 of the memory cell from which information is not read. In this case, if a potential at which the transistor 300 becomes “conductive” regardless of the charge applied to the node SN, that is, a potential higher than V _{th_L} is applied to the wiring 1005 connected to the memory cell from which information is not read. Good.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 11)
In this embodiment, one embodiment of a semiconductor device, which is different from one embodiment of the semiconductor device described in Embodiment 10, will be described with reference to FIGS.

Note that in one embodiment of the semiconductor device illustrated in FIGS. 103 to 106, the structure having the same function as the structure of one embodiment of the semiconductor device described in Embodiment 10 is denoted by the same reference numeral. In the following description, portions different from one embodiment of the semiconductor device described in Embodiment 10 are mainly described, and the contents described in Embodiment 10 can be referred to for other portions.

<Storage device 1>
The memory device illustrated in FIG. 103 includes a transistor 300, a transistor 200, and a capacitor 100. 103 is a cross-sectional view of the transistor 200 and the transistor 300 in the channel length direction.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

The memory device illustrated in FIG. 103 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read. Note that the description of the above embodiment can be referred to for information writing, holding, and reading.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. The transistor 200 illustrated in FIGS. 103A and 103B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Storage device 2>
A semiconductor device illustrated in FIG. 104 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device will be described with reference to FIG.

FIG. 104A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 104B is a cross-sectional view of the semiconductor device in which the wiring 1003 to the wiring 1010 shown in FIG.

<Structure of storage device 2>
FIG. 104B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device illustrated in FIG. 104, structures having the same functions as those of the semiconductor device and the structure of the memory device described in the above embodiment and <Structure of the memory device 1> are denoted by the same reference numerals. To do.

The memory device of one embodiment of the present invention includes the transistor 200, the transistor 400, and the capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 200 and the transistor 400.

Note that as the capacitor 100 and the transistor 200, the capacitors and transistors included in the semiconductor device and the memory device described in the above embodiment and FIGS. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIGS. 104A and 104B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductors 460a and 460b) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, an insulator 470 in contact with the conductor 460, and the conductor 460. An insulator 472 provided on a side surface, an insulator 220 functioning as a gate insulating layer, an insulator 222, an insulator 424, and an insulator 450, an oxide 430c having a region where a channel is formed, a source or a drain The oxide 431a and the oxide 431b functioning as one of the above, and the oxide 432a and the oxide 432b functioning as the other of the source or the drain. In addition, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 functioning as a wiring.

In the transistor 400, the conductor 405 is the same layer as the conductor 205. The insulator 424 is the same layer as the insulator 224. The oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The metal oxide 452 is the same layer as the metal oxide 252. The conductor 460 is the same layer as the conductor 260. The insulator 470 is the same layer as the insulator 270. The insulator 471 is the same layer as the insulator 271. The insulator 472 is the same layer as the insulator 272.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
A semiconductor device illustrated in FIG. 105 is a memory device including the transistor 300, the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device will be described with reference to FIG.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and the transistor described in the above embodiment can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

<Structure of storage device 3>

FIG. 105 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. 105 has the same function as the structure of the semiconductor device and the memory device described in the above embodiment, <Structure of memory device 1>, and <Structure of memory device 2>. The same symbols are added to the structures having the same.

The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 103 to 104 may be used. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 105A and 105B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

In the memory device illustrated in FIG. 105, the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, the insulator 275, the insulator 273, the insulator 274, and the insulator 280 include An example is shown in which an opening 500 is provided and the insulator 210 and the insulator 282 are connected. With such a structure, the transistor 200 and the transistor 400 are surrounded by the insulator 210 and the insulator 282 and thus are not easily affected by impurities such as water and hydrogen. In addition, release of oxygen in the oxide or the insulator to the outside is reduced. A memory device having such a structure is preferable because reliability is improved. Note that the opening 500 is not necessarily provided.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

FIG. 106 shows an example of the memory cell array of this embodiment. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

Note that the memory device illustrated in FIG. 106 is a semiconductor device which forms a memory cell array by arranging the memory devices illustrated in FIGS. 103 and 105 in a matrix. Note that one transistor 400 can control the bottom gate voltages of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.

Therefore, the transistor 400 shown in FIG. 105 is omitted from FIG. FIG. 106 is a cross-sectional view of part of a row in the case where the memory devices illustrated in FIGS. 103 and 105 are arranged in a matrix.

Note that the description of the transistor 300 illustrated in FIG. 102 can be referred to for the description of the transistor 300 illustrated in FIG.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 12)
In this embodiment, one embodiment of a semiconductor device will be described with reference to FIGS.

Note that in one embodiment of the semiconductor device illustrated in FIGS. 107 to 111, a structure having the same function as a structure of one embodiment of the semiconductor device described in the above embodiment is denoted by the same reference numeral. In the following description, parts different from one embodiment of the semiconductor device described in the above embodiment are mainly described, and the contents described in the above embodiment can be referred to for other parts. To do.

<Storage device 1>
The memory device illustrated in FIGS. 107 and 108 includes the transistor 300, the transistor 200, and the capacitor 100. 107 and 108 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

107 and 108, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. Yes. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

The memory device illustrated in FIGS. 107 and 108 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read. Note that the description of the above embodiment can be referred to for information writing, holding, and reading.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 illustrated in FIG. 107 is an example, and the present invention is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification of Storage Device 1>
Hereinafter, an example of a memory device according to one embodiment of the present invention will be described with reference to FIG.

108 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. FIG. 108, the structure having the same function as the structure of the semiconductor device and the structure of the memory device described in the above embodiment and <Memory device 1> is denoted by the same reference numeral. To do.

108 differs from the storage device shown in <Structure of storage device 1> in that the cell 600 described in the above embodiment is provided.

Specifically, the memory device illustrated in FIG. 108 is a cell that shares part of the structure of the capacitor 100 and part of the structure of the transistor 200 instead of providing the capacitor 100 and the transistor 200 independently. 600.

With the above structure, part or the whole of the cell 600 and the transistor 300 overlap with each other, whereby the total area of the projected areas of the memory device can be reduced. Accordingly, the cell 600 can be easily miniaturized or highly integrated. In addition, the process can be shortened.

<Storage device 2>
A semiconductor device illustrated in FIG. 109 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a memory device is described with reference to FIG.

109A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 109B is a cross-sectional view of the semiconductor device in which the wiring 1003 to the wiring 1010 illustrated in FIG. 109A are associated with each other.

<Structure of storage device 2>
FIG. 109B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device illustrated in FIG. 109, structures having the same functions as those of the semiconductor device and the structure of the memory device described in the above embodiment and <Structure of the memory device 1> are denoted by the same reference numerals. To do.

The memory device of one embodiment of the present invention includes the transistor 200, the transistor 400, and the capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 200 and the transistor 400.

Note that as the capacitor 100 and the transistor 200, the capacitor and the transistor included in the semiconductor device and the memory device described in the above embodiment and FIGS. 107 and 108 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIGS. 109A and 109B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 functioning as a top gate electrode (a conductor 460a and a conductor 460b), a conductor 405 functioning as a bottom gate electrode, an insulator 471 in contact with the conductor 460, and an insulator 472. , The insulator 473 arranged on the side surface of the conductor 460 with the insulator 472 interposed therebetween, the insulator 220 functioning as a gate insulating layer, the insulator 222, the insulator 224, and the insulator 450, and a channel are formed. It includes an oxide 430c having a region, an oxide 431a and an oxide 431b functioning as one of a source and a drain, and an oxide 432a and an oxide 432b functioning as the other of a source and a drain. In addition, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 functioning as a wiring.

In the transistor 400, the insulator 473 is the same layer as the insulator 273.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
A semiconductor device illustrated in FIG. 110 is a memory device including the transistor 300, the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device will be described with reference to FIG.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and the transistor described in the above embodiment can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

<Structure of storage device 3>

110 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. FIG. 110 has the same function as the structure of the semiconductor device and the memory device described in the above embodiment, <Structure of memory device 1>, and <Structure of memory device 2>. The same symbols are added to the structures having the same.

The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 110A and 110B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

110, the opening portion 500 is provided in the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, and the insulator 280, and the insulator 210 and the insulator 282 are connected to each other. An example is shown. With such a structure, the transistor 200 and the transistor 400 are surrounded by the insulator 210 and the insulator 282 and thus are not easily affected by impurities such as water and hydrogen. In addition, release of oxygen in the oxide or the insulator to the outside is reduced. A memory device having such a structure is preferable because reliability is improved. Note that the opening 500 is not necessarily provided.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

FIG. 111 shows an example of the memory cell array of this embodiment. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

Note that the memory device illustrated in FIG. 111 is a semiconductor device that forms a memory cell array by arranging the memory devices illustrated in FIGS. 107 and 110 in a matrix. Note that one transistor 400 can control the bottom gate potential of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.

Therefore, the transistor 400 shown in FIG. 110 is omitted from FIG. FIG. 111 is a cross-sectional view of a part of a row in the case where the memory devices illustrated in FIGS. 107 and 110 are arranged in a matrix.

In addition, FIG. 111 is different from FIG. 110 in the configuration of the transistor 300. In the transistor 300 illustrated in FIG. 111, a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also referred to as a Fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 13)
In this embodiment, one embodiment of a semiconductor device will be described with reference to FIGS.

Note that in one embodiment of the semiconductor device illustrated in FIGS. 112 to 116, a structure having the same function as a structure of one embodiment of the semiconductor device described in the above embodiment is denoted by the same reference numeral. In the following, different parts of the semiconductor device described in the above embodiment will be mainly described, and the contents described in the above embodiment may be referred to for other parts. To do.

<Storage device 1>
112 and 113 each include the transistor 300, the transistor 200, and the capacitor 100. The memory device illustrated in FIGS. 112 and 113 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. The transistor 200 illustrated in FIGS. 112A and 112B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification of Storage Device 1>
Hereinafter, an example of a memory device according to one embodiment of the present invention will be described with reference to FIG.

113 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. FIG. Note that in the memory device illustrated in FIG. 113, structures having the same functions as those of the semiconductor device described in the above embodiment and <Structure of the memory device 1> and the structure of the memory device are denoted by the same reference numerals. To do.

113 differs from the storage device shown in <Structure of storage device 1> in that the cell 600 described in the above embodiment is provided.

Specifically, in the memory device illustrated in FIG. 113, a cell sharing a part of the structure of the capacitor 100 and a part of the structure of the transistor 200 instead of providing the capacitor 100 and the transistor 200 independently. 600.

With the above structure, part or the whole of the cell 600 and the transistor 300 overlap with each other, whereby the total area of the projected areas of the memory device can be reduced. Accordingly, the cell 600 can be easily miniaturized or highly integrated. In addition, the process can be shortened.

<Storage device 2>
A semiconductor device illustrated in FIG. 114 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device is described with reference to FIG.

FIG. 114A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 114B shows a cross-sectional view of the semiconductor device in which the wiring 1003 to the wiring 1010 shown in FIG.

<Structure of storage device 2>
FIG. 114B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device in FIG. 114, structures that have the same functions as those of the semiconductor device described in the above embodiment and <Structure of the memory device 1> and the structure of the memory device are denoted by the same reference numerals. To do.

The memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 200 and the transistor 400.

Note that as the capacitor 100 and the transistor 200, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 112 and 113 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIGS. 114A and 114B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 functioning as a top gate electrode (a conductor 460a and a conductor 460b), a conductor 405 functioning as a bottom gate electrode, an insulator 471 in contact with the conductor 460, and an insulator 472. , The insulator 477 arranged on the side surface of the conductor 460 with the insulator 472 interposed therebetween, the insulator 220 functioning as a gate insulating layer, the insulator 222, the insulator 224, and the insulator 450, and a channel are formed. It includes an oxide 430c having a region, an oxide 431a and an oxide 431b functioning as one of a source and a drain, and an oxide 432a and an oxide 432b functioning as the other of a source and a drain. In addition, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 functioning as a wiring.

In the transistor 400, the insulator 477 is the same layer as the insulator 277.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
A semiconductor device illustrated in FIG. 115 is a memory device including the transistor 300, the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a memory device is described with reference to FIG.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and the transistor described in the above embodiment can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

<Structure of storage device 3>

115 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. FIG. 115 has the same function as the structure of the semiconductor device and the storage device described in the above embodiment, <Structure of storage device 1>, and <Structure of storage device 2>. The same symbols are added to the structures having the same.

The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 112 to 114 may be used. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 115A and 115B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

In the memory device illustrated in FIG. 115, the opening portion 500 is provided in the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 275, the insulator 273, and the insulator 280, and the insulator The example which connects 210 and the insulator 282 is shown. With such a structure, the transistor 200 and the transistor 400 are surrounded by the insulator 210 and the insulator 282 and thus are not easily affected by impurities such as water and hydrogen. In addition, release of oxygen in the oxide or the insulator to the outside is reduced. A memory device having such a structure is preferable because reliability is improved. Note that the opening 500 is not necessarily provided.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

FIG. 116 shows an example of the memory cell array of this embodiment. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

Note that the memory device illustrated in FIG. 116 is a semiconductor device which forms a memory cell array by arranging the memory devices illustrated in FIGS. 112 and 115 in a matrix. Note that one transistor 400 can control the bottom gate potential of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.

Therefore, the transistor 400 shown in FIG. 115 is omitted from FIG. FIG. 116 is a cross-sectional view of part of a row in the case where the memory devices illustrated in FIGS. 112 and 115 are arranged in a matrix.

FIG. 116 is different from FIG. 115 in the structure of the transistor 300. In the transistor 300 illustrated in FIGS. 116A and 116B, a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also referred to as a Fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 14)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

Note that in one embodiment of the semiconductor device illustrated in FIGS. 117 to 121, a structure having the same function as a structure of one embodiment of the semiconductor device described in the above embodiment is denoted by the same reference numeral. In the following, different parts of the semiconductor device described in the above embodiment will be mainly described, and the contents described in the above embodiment may be referred to for other parts. To do.

<Storage device 1>
117 and 118 each include the transistor 300, the transistor 200, and the capacitor 100. The memory device illustrated in FIGS. 117 and 118 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. In addition, the transistor 200 illustrated in FIGS. 117A and 117B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification of Storage Device 1>
In the following, an example of a memory device according to one embodiment of the present invention is described with reference to FIG.

118 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. FIG. 118, the structure having the same function as the structure of the semiconductor device and the structure of the memory device described in the above embodiment and <Structure of memory device 1> is denoted by the same reference numeral. To do.

118 differs from the storage device shown in <Structure of storage device 1> in that the cell 600 described in the above embodiment is provided.

Specifically, the memory device illustrated in FIG. 118 is a cell that shares part of the structure of the capacitor 100 and part of the structure of the transistor 200 instead of providing the capacitor 100 and the transistor 200 independently. 600.

With the above structure, part or the whole of the cell 600 and the transistor 300 overlap with each other, whereby the total area of the projected areas of the memory device can be reduced. Accordingly, the cell 600 can be easily miniaturized or highly integrated. In addition, the process can be shortened.

<Storage device 2>
A semiconductor device illustrated in FIG. 119 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one mode as a memory device is described with reference to FIG.

FIG. 119A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 119B is a cross-sectional view of the semiconductor device in which the wiring 1003 to the wiring 1010 illustrated in FIG. 119A correspond to each other.

<Structure of storage device 2>
FIG. 119B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. 119, the structure having the same function as that of the semiconductor device described in the above embodiment and <Structure of memory device 1> and the structure of the memory device are denoted by the same reference numerals in the memory device illustrated in FIG. To do.

The memory device of one embodiment of the present invention includes the transistor 200, the transistor 400, and the capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 200 and the transistor 400.

Note that as the capacitor 100 and the transistor 200, the capacitors and transistors included in the semiconductor device and the memory device described in the above embodiment, FIGS. 117 and 118 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIG. 119 are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 functioning as a top gate electrode (a conductor 460a and a conductor 460b), a conductor 405 functioning as a bottom gate electrode, an insulator 470 in contact with the conductor 460, and an insulator 472. And the insulator 475 arranged on the side surface of the conductor 460 with the insulator 472 interposed therebetween, the insulator 220 functioning as a gate insulating layer, the insulator 222, the insulator 224, and the insulator 450, and a channel are formed. It includes an oxide 430c having a region, an oxide 431a and an oxide 431b functioning as one of a source and a drain, and an oxide 432a and an oxide 432b functioning as the other of a source and a drain. In addition, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 functioning as a wiring.

In the transistor 400, the insulator 470 is the same layer as the insulator 270. The insulator 472 is the same layer as the insulator 272.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
A semiconductor device illustrated in FIG. 120 is a memory device including the transistor 300, the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device will be described with reference to FIG.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and the transistor described in the above embodiment can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

<Structure of storage device 3>

120 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. FIG. 120 has the same function as the structure of the semiconductor device and the memory device described in the above embodiment, <Structure of memory device 1>, and <Structure of memory device 2>. The same symbols are added to the structures having the same.

The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 117 to 119 may be used. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 120A and 120B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

120, an opening 500 is provided in the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, and the insulator 280, and the insulator 210 and the insulator 282 are connected to each other. An example is shown. With such a structure, the transistor 200 and the transistor 400 are surrounded by the insulator 210 and the insulator 282 and thus are not easily affected by impurities such as water and hydrogen. In addition, release of oxygen in the oxide or the insulator to the outside is reduced. A memory device having such a structure is preferable because reliability is improved. Note that the opening 500 is not necessarily provided.

By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

FIG. 121 shows an example of the memory cell array of this embodiment. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

Note that the memory device illustrated in FIG. 127 is a semiconductor device which forms a memory cell array by arranging the memory devices illustrated in FIGS. 117 and 120 in a matrix. Note that one transistor 400 can control the bottom gate voltages of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.

Therefore, the transistor 400 shown in FIG. 120 is omitted from FIG. FIG. 121 is a cross-sectional view of a part of a row in the case where the memory devices illustrated in FIGS. 117 and 120 are arranged in a matrix.

121 is different from FIG. 120 in the configuration of the transistor 300. In the transistor 300 illustrated in FIG. 121, a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also referred to as a Fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 15)
In this embodiment, an inverter circuit using the semiconductor device described in the above embodiment is described. Note that in this specification, a high power supply voltage may be referred to as an H level (or VDD), and a low power supply voltage may be referred to as an L level (or GND).

<Configuration example of inverter circuit>
A circuit INV illustrated in FIG. 122A includes a capacitor C1, and a transistor M1, a transistor M2, and a transistor M3 connected in series. The circuit INV has a function as an inverter circuit.

Transistors M1 to M3 are n-channel transistors. Since the circuit INV includes only n-channel transistors, manufacturing cost can be reduced as compared with an inverter circuit including CMOS transistors.

As the transistors M1 to M3, the transistor 200 included in the semiconductor device described in the above embodiment is preferably used.

The transistor M1 has a first gate and a second gate that are electrically connected to each other. The first gate and the second gate have regions overlapping each other with a semiconductor layer interposed therebetween. The same applies to the transistors M2 and M3. The first gate may be referred to as a top gate and the second gate may be referred to as a bottom gate.

The circuit INV has a terminal IN, a terminal OUT, a terminal CLK, and a terminal CLKB. The terminal IN functions as an input terminal, and the terminal OUT functions as an output terminal. A clock signal is input to the terminal CLK, and an inverted signal of the clock signal input to the terminal CLK is input to the terminal CLKB.

The circuit INV is supplied with VDD and VSS as power supply voltages. VDD is a high power supply voltage and is input to the drain of the transistor M1. VSS is a low power supply voltage and is input to the source of the transistor M3.

In the transistor M1, the top gate and the bottom gate are electrically connected to the terminal CLK, and the source is electrically connected to the drain of the transistor M2.

In the transistor M2, the top gate and the bottom gate are electrically connected to the terminal CLKB, and the source is electrically connected to the drain of the transistor M3.

In the transistor M3, the top gate and the bottom gate are electrically connected to the terminal IN.

The first terminal of the capacitive element C1 is electrically connected to the source of the transistor M1. VSS is input to the second terminal of the capacitive element C1.

The terminal OUT is electrically connected to the source of the transistor M1, the drain of the transistor M2, and the first terminal of the capacitor C1.

Note that the capacitance element C1 may be replaced with a parasitic capacitance of a wiring or a gate capacitance of a transistor. In that case, the area occupied by these semiconductor devices can be reduced.

Next, the operation of the circuit INV will be described.

FIG. 122B is a timing chart for explaining the operation of the circuit INV. Each represents a change in potential of the terminal IN, the terminal CLK, the terminal CLKB, and the terminal OUT. FIG. 122B is classified into three periods of a period P1, a period P2, and a period P3.

The terminal IN is given H level during the periods P1 to P3. That is, the transistor M3 is on in the periods P1 to P3.

In the period P1, the potential VH is input to the terminal CLK, and the potential VL is input to the terminal CLKB. Transistor M1 is turned on and transistor M2 is turned off. At this time, VDD is supplied to the capacitor C1, and the capacitor C1 starts to be charged (precharge).

Note that VH is preferably equal to or higher than a voltage (VDD + Vth) obtained by adding VDD and the threshold voltage (Vth) of the transistor M1. By doing so, VDD can be accurately transmitted to the terminal OUT. VL may be a low power supply voltage (or GND). Note that VH is sometimes called a high potential and VL is sometimes called a low potential.

In the period P2, VL is input to the terminal CLK and VH is input to the terminal CLKB. Transistor M1 is turned off and transistor M2 is turned on. At this time, since the transistor M3 is on, the first terminal of the capacitor C1 and the source of the transistor M3 are brought into conduction, and the capacitor C1 starts discharging. Finally, the terminal OUT outputs the L level. That is, the terminal OUT outputs an inverted signal of the signal input to the terminal IN.

In the period P3, VH is input to the terminal CLK and VL is input to the terminal CLKB. Transistor M1 is turned on and transistor M2 is turned off. Similar to the period P1, the capacitive element C1 starts precharging again.

When the input of the terminal IN in the periods P1 to P3 is set to the L level, the terminal OUT outputs the H level in the period P2. That is, the terminal OUT outputs an inverted signal of the signal input to the terminal IN.

From the above, it can be seen that the circuit INV precharges the capacitor C1 when the terminal CLK is VH and operates as an inverter circuit when the terminal CLK is VL.

It can also be seen that the circuit INV functions as a dynamic logic circuit that operates by repeatedly charging and discharging the capacitive element C1. The transistor M1 functions as a precharging transistor that charges the capacitor C1, and the transistor M2 functions as a discharging transistor that discharges the charge accumulated in the capacitor C1.

As the transistors M1 to M3, transistors with low off-state current are preferably used. As a transistor with low off-state current, a transistor using a metal oxide or an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) can be given. Note that the small off-state current here means that the off-state current of the transistor is preferably 10 ⁻¹⁸ A / μm or less, more preferably 10 ⁻²¹ A / μm or less, and further preferably 10 ⁻²⁴ A / μm or less. Say.

By using OS transistors as the transistors M1 to M3, the circuit INV can reduce the through current. As a result, the circuit INV can reduce power consumption.

Further, by using OS transistors as the transistors M1 to M3, the charge precharged in the capacitor C1 is not lost due to the leakage current. As a result, the circuit INV can transmit data more accurately.

In the transistor M1, by electrically connecting the top gate and the bottom gate, a gate voltage can be simultaneously applied to the semiconductor layer from the top gate and the bottom gate, and the on-current can be increased. The same applies to the transistor M2 and the transistor M3. As a result, the circuit INV can realize an inverter circuit having a high operating frequency.

The circuit INV may electrically connect the terminal IN to the top gate and the bottom gate of the transistor M2, and electrically connect the terminal CLKB to the top gate and the bottom gate of the transistor M3.

Further, the bottom gates of the transistors M1 to M3 may be applied with a different potential from the top gate. For example, a common fixed potential may be applied to the bottom gates of the transistors M1 to M3. By doing so, the circuit INV can control the threshold voltages of the transistors M1 to M3.

Further, the circuit INV may omit all the bottom gates of the transistors M1 to M3 in some cases. In that case, the circuit INV can simplify the manufacturing process.

As described above, the circuit INV can provide an inverter circuit including a unipolar transistor with low power consumption. In addition, an inverter circuit including a unipolar transistor with a high operating frequency can be provided.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 16)
In this embodiment, with reference to FIGS. 123 to 125, a transistor in which an oxide is used for a semiconductor (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention is applied. As an example of the apparatus, NOSRAM will be described. NOSRAM (registered trademark) is an abbreviation of “Nonvolatile Oxide Semiconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Hereinafter, a memory device using an OS transistor such as NOSRAM may be referred to as an OS memory.

In NOSRAM, a memory device using an OS transistor for a memory cell (hereinafter referred to as “OS memory”) is applied. The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

<< NOSRAM 1600 >>
FIG. 123 shows a configuration example of NOSRAM. A NOSRAM 1600 illustrated in FIG. 123 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.

The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (eight values) data.

The controller 1640 comprehensively controls the entire NOSRAM 1600, and writes data WDA [31: 0] and reads data RDA [31: 0]. The controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.

The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.

The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.

DAC 1663 converts 3-bit digital data into analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.

The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL. A function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.

The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.

Note that the configurations of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Depending on the configuration or driving method of the memory cell array 1610, the arrangement of these drivers and wirings connected to the drivers may be changed, or the functions of these drivers and wirings connected to the drivers may be changed. Or you may add. For example, the bit line BL may have a part of the function of the source line SL.

In the above description, the amount of information stored in each memory cell 1611 is 3 bits. However, the structure of the memory device described in this embodiment is not limited thereto. The amount of information held in each memory cell 1611 may be 2 bits or less, or 4 bits or more. For example, when the amount of information held in each memory cell 1611 is 1 bit, the DAC 1663 and the ADC 1672 may be omitted.

<Memory cells 1611 to 1614>
124A is a circuit diagram illustrating a structural example of the memory cell 1611. FIG. The memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, the word line RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor. The capacitor C61 is a storage capacitor for holding the potential of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

Since the write transistor of the memory cell 1611 includes the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

In the example of FIG. 124A, the bit line is a common bit line for writing and reading, but as shown in FIG. 124B, the bit line WBL functioning as the writing bit line and the reading bit line And a bit line RBL that functions as:

124 (C) to 124 (E) show other configuration examples of the memory cell. 124C to 124E show an example in which a write bit line WBL and a read bit line RBL are provided. As shown in FIG. 124A, the writing and reading are shared. A bit line may be provided.

A memory cell 1612 shown in FIG. 124C is a modified example of the memory cell 1611 in which the read transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

In the memory cell 1611 and the memory cell 1612, the OS transistor MO61 may be an OS transistor without a bottom gate.

A memory cell 1613 illustrated in FIG. 124D is a 3T gain cell, and is electrically connected to the word line WWL, the word line RWL, the bit line WBL, the bit line RBL, the source line SL, the wiring BGL, and the wiring PCL. Yes. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.

A memory cell 1614 shown in FIG. 124E is a modified example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (transistor MN62 and transistor MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.

The OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a bottom gate or a transistor with a bottom gate.

In the above description, a so-called NOR-type storage device in which the memory cells 1611 and the like are connected in parallel has been described; however, the storage device described in this embodiment is not limited thereto. For example, a so-called NAND memory device in which memory cells 1615 as described below are connected in series may be used.

FIG. 125 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610. A memory cell array 1610 illustrated in FIG. 125 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitor C63. Here, the transistor MN64 is composed of, for example, an n-channel Si transistor. Without being limited thereto, the transistor MN64 may be a p-channel Si transistor or an OS transistor.

Hereinafter, the memory cell 1615a and the memory cell 1615b illustrated in FIG. 125 will be described as an example. Here, the reference numerals of the wirings or circuit elements connected to either the memory cell 1615a or the memory cell 1615b are denoted by a or b.

In the memory cell 1615a, the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitor C63a are electrically connected. The bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. The word line WWLa and the gate of the OS transistor MO63a are electrically connected. In addition, the wiring BGLa and the bottom gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other electrode of the capacitor C63a are electrically connected.

The memory cell 1615b can be provided symmetrically with the memory cell 1615a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit elements included in the memory cell 1615b are also connected to the wiring in the same manner as the memory cell 1615a.

Further, the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL. The source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615. In this manner, in the NAND type memory cell array 1610, the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.

In the memory device having the memory cell array 1610 shown in FIG. 125, a write operation and a read operation are performed for each of a plurality of memory cells (hereinafter referred to as memory cell columns) connected to the same word line WWL (or word line RWL). Do. For example, the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, so that the OS transistor MO63 of the memory cell column to be written is turned on. As a result, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 and the electrode of the capacitor C63 in the designated memory cell column, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 in the memory cell column is turned off, a predetermined charge given to the gate can be held. In this manner, data can be written into the memory cell 1615 in the designated memory cell column.

Also, for example, the read operation can be performed as follows. First, a potential that turns on the transistor MN64 is applied to the word line RWL that is not connected to the memory cell column to be read regardless of the charge applied to the gate of the transistor MN64, and the memory cell column to be read is read. The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column from which reading is performed, so that the on state or the off state of the transistor MN64 is selected by the charge of the gate of the transistor MN64. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is set in an operating state. Here, since the plurality of transistors MN64 between the source line SL and the bit line RBL are turned on except for the memory cell column to be read, the conductance between the source line SL and the bit line RBL is read. It is determined by the state (ON state or OFF state) of the transistor MN64 in the memory cell column. Since the conductance of the transistor varies depending on the charge of the gate of the transistor MN64 of the memory cell column to be read, the potential of the bit line RBL takes a different value accordingly. By reading the potential of the bit line RBL by the reading circuit, information can be read from the memory cell 1615 of the designated memory cell column.

Since the data is rewritten by charging / discharging the capacitive element C61, the capacitive element C62, or the capacitive element C63, the NOSRAM 1600 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.

In the case where the semiconductor device described in any of the above embodiments is used for the memory cell 1611, the memory cell 1612, the memory cell 1613, the memory cell 1614, and the memory cell 1615, the transistor 200 is used as the OS transistor MO61, the OS transistor MO62, and the OS transistor MO63. The capacitor 100 can be used as the element C61, the capacitor C62, and the capacitor C63, and the transistor 300 can be used as the transistor MP61, the transistor MP62, the transistor MP63, the transistor MN61, the transistor MN62, the transistor MN63, and the transistor MN64. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be further integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 17)
In this embodiment, DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS. 126 and 127. DOSRAM (registered trademark) is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells. OS memory is applied to DOSRAM as well as NOSRAM.

<< DOSRAM 1400 >>
FIG. 126 shows a configuration example of the DOSRAM. As illustrated in FIG. 126, the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).

The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and a global bit line GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. The global bit line GBLL and the global bit line GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.

The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to 1425 <N-1>. FIG. 127A illustrates a configuration example of the local memory cell array 1425. The local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a plurality of bit lines BLR. In the example of FIG. 127A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.

127B shows an example of a circuit configuration of a pair of memory cells 1445a and 1445b connected to a common bit line BLL (bit line BLR). The memory cell 1445a includes a transistor MW1a, a capacitor CS1a, a terminal B1a, and a terminal B2a, and is connected to the word line WLa and the bit line BLL (bit line BLR). The memory cell 1445b includes a transistor MW1b, a capacitor CS1b, a terminal B1b, and a terminal B2b, and is connected to the word line WLb and the bit line BLL (bit line BLR). Note that in the following description, when either the memory cell 1445a or the memory cell 1445b is not particularly limited, the symbol a or b may not be attached to the memory cell 1445 and the structure attached thereto.

The transistor MW1a has a function of controlling charge / discharge of the capacitor CS1a, and the transistor MW1b has a function of controlling charge / discharge of the capacitor CS1b. The gate of the transistor MW1a is electrically connected to the word line WLa, the first terminal is electrically connected to the bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1a. Has been. The gate of the transistor MW1b is electrically connected to the word line WLb, the first terminal is electrically connected to the bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1b. It is connected to the. Thus, the bit line BLL (bit line BLR) is used in common for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.

The transistor MW1 has a function of controlling charging / discharging of the capacitive element CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant potential (for example, a low power supply potential) is input to the terminal B2.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1445a and the memory cell 1445b, the transistor 200a is used as the transistor MW1a, the transistor 200b is used as the transistor MW1b, the capacitor 100a is used as the capacitor CS1a, and the capacitor is used as the capacitor CS1b. 100b can be used. Thus, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.

The transistor MW1 has a bottom gate, and the bottom gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the potential of the terminal B1. For example, the potential of the terminal B1 may be a fixed potential (for example, a negative constant potential), or the potential of the terminal B1 may be changed in accordance with the operation of the DOSRAM 1400.

The bottom gate of the transistor MW1 may be electrically connected to the gate, the first terminal, or the second terminal of the transistor MW1. Alternatively, the bottom gate is not necessarily provided in the transistor MW1.

The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> to 1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference between the bit line pair, and a function of holding this potential difference. The switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.

Here, the bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.

(Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.

The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413. The plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.

(Column circuit 1415)
The column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.

An outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address signal. The local sense amplifier array 1426 amplifies and holds the written data. In the specified local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.

An outline of the reading operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data. The switch array 1444 writes the data in the column specified by the address signal among the data held in the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.

Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.

The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.

Since the MC-SA array 1420 has a laminated structure, the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when accessing the DOSRAM 1400 is reduced, and the power consumption can be reduced.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 18)
In this embodiment, an FPGA (field programmable gate array) is described as an example of a semiconductor device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS. . In the FPGA of this embodiment, an OS memory is applied to the configuration memory and the register. Here, such FPGA is referred to as “OS-FPGA”.

<< OS-FPGA >>
FIG. 128A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 128A is capable of NOFF (normally off) computing that performs context switching by a multi-context structure and fine-grain power gating for each PLE. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

The programmable area 3115 has two input / output blocks (IOBs) 3117 and a core 3119. The IOB 3117 has a plurality of programmable input / output circuits. The core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. The LAB 3120 includes a plurality of PLE 3121s. FIG. 128B illustrates an example in which the LAB 3120 includes five PLE 3121s. As shown in FIG. 128C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.

SB3131 will be described with reference to FIGS. 129 (A) to 129 (C). Data, dataab, signal context [1: 0], and signal word [1: 0] are input to SB 3131 illustrated in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.

The SB 3131 includes a PRS (programmable routing switch) 3133 [0] and a PRS 3133 [1]. The PRS 3133 [0] and the PRS 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.

FIG. 129B shows a circuit configuration example of PRS3133 [0]. PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration. PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal. The signal context [0] and the signal word [0] are input to the PRS 3133 [0], and the signal context [1] and the signal word [1] are input to the PRS 3133 [1]. For example, in the SB 3131, when the signal context [0] becomes “H”, the PRS 3133 [0] becomes active.

PRS3133 [0] has CM3135 and Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM 3135. The CM 3135 includes a memory circuit 3137 and a memory circuit 3137B. The memory circuit 3137 and the memory circuit 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit 3137B includes a capacitor CB31, an OS transistor MOB31, and an OS transistor MOB32.

When the semiconductor device described in any of the above embodiments is used for the SAB 3130, the transistor 200 can be used as the OS transistor MO31 and the OS transistor MOB31, and the capacitor 100 can be used as the capacitor C31 and the capacitor CB31. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.

The OS transistor MO31, OS transistor MO32, OS transistor MOB31, and OS transistor MOB32 each have a bottom gate, and these bottom gates are each electrically connected to a power supply line that supplies a fixed potential.

The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. The nodes N32 and NB32 are charge holding nodes of the CM 3135. The OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.

The logic of data held in the memory circuit 3137 and the memory circuit 3137B has a complementary relationship. Therefore, either the OS transistor MO32 or the OS transistor MOB32 becomes conductive.

An example of the operation of PRS 3133 [0] will be described with reference to FIG. Configuration data has already been written in the PRS 3133 [0], the node N32 of the PRS 3133 [0] is “H”, and the node NB32 is “L”.

PRS3133 [0] is inactive while the signal context [0] is “L”. During this period, even if the input terminal (input) of the PRS 3133 [0] transits to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal (output) of the PRS 3133 [0] is also “L”. "Is maintained.

PRS 3133 [0] is active while signal context [0] is “H”. When the signal context [0] changes to “H”, the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.

When the input terminal changes to “H” during the period in which PRS 3133 [0] is active, the OS transistor MO32 of the memory circuit 3137 is a source follower, so that the gate voltage of the Si transistor M31 increases due to boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.

In the PRS 3133 having a multi-context function, the CM 3135 also has a multiplexer function.

FIG. 130 shows a configuration example of the PLE 3121. The PLE 3121 includes a lookup table block (LUT block) 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to select and output internal data according to inputs inA, inB, inC, and inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.

The PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.

In order to realize NOFF computing, the register block 3124 is composed of a nonvolatile register. The nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.

The register block 3124 includes OS-FF 3140 [1] and OS-FF 3140 [2]. The signal user_res, the signal load, and the signal store are input to the OS-FF 3140 [1] and the OS-FF 3140 [2]. The clock signal CLK1 is input to the OS-FF 3140 [1], and the clock signal CLK2 is input to the OS-FF 3140 [2]. FIG. 131A illustrates a configuration example of the OS-FF 3140.

The OS-FF 3140 includes an FF 3141 and a shadow register 3142. The FF 3141 includes a node CK, a node R, a node D, a node Q, and a node QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. Nodes Q and QB have a complementary logic relationship.

The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.

The shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, an Si transistor M37, an Si transistor MB37, a memory circuit 3143, and a memory circuit 3143B. The memory circuit 3143 and the memory circuit 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. The nodes N36 and NB36 are the gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes. The nodes N37 and NB37 are the gates of the Si transistor M37 and the Si transistor MB37.

When the semiconductor device described in any of the above embodiments is used for the LAB 3120, the transistor 200 can be used as the OS transistor MO35 and the OS transistor MOB35, and the capacitor 100 can be used as the capacitor C36 and the capacitor CB36. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.

The OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 each have a bottom gate, and each bottom gate is electrically connected to a power supply line that supplies a fixed potential.

An example of an operating method of the OS-FF 3140 will be described with reference to FIG.

(Backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data in the FF 3141. The node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. The data of the node Q and the node QB of the FF 3141 is lost, but the shadow register 3142 holds the backed up data even when the power is turned off.

(Recovery)
The power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.

By combining the fine-grain power gating and the backup / recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.

An error that can occur in a memory circuit is a soft error due to the incidence of radiation. A soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair. An OS memory using an OS transistor has high soft error resistance. Therefore, the OS-FPGA 3110 with high reliability can be provided by installing the OS memory.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 19)
In this embodiment, an AI system to which the semiconductor device described in any of the above embodiments is applied will be described with reference to FIGS.

FIG. 132 is a block diagram illustrating a configuration example of the AI system 4041. The AI system 4041 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014. As the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.

The control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a SRAM (Static Random Access MemoryPROM 40 Memory, Memory Memory 4024). A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.

The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.

The calculation unit 4010 can execute learning or inference using a neural network.

The analog operation circuit 4011 has an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.

The analog arithmetic circuit 4011 is preferably formed using an OS transistor. An analog operation circuit 4011 using an OS transistor has an analog memory, and can perform a product-sum operation necessary for learning or inference with low power consumption.

The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021. The DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.

Calculating using a neural network may have over 1000 input data. When the input data is stored in the SRAM, the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions. The DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.

NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetorescent Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.

Further, the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.

The NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit. In this specification, the analog data refers to data having a resolution of 3 bits (8 values) or more. The multi-value data described above may be included in the analog data.

Data and parameters used for the calculation of the neural network can be temporarily stored in the NOSRAM 4013. The data and parameters may be stored in the memory provided outside the AI system 4041 via the CPU 4021. However, the data and parameters provided by the internal NOSRAM 4013 are faster and consume less power. Can be stored. Further, since the bit line of the NOSRAM 4013 can be made longer than that of the DOSRAM 4012, the storage capacity can be increased.

The FPGA 4014 is an FPGA using an OS transistor. The AI system 4041 uses a FPGA 4014, which will be described later in hardware, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM). A neural network connection, such as a deep belief network (DBN), can be constructed. By configuring the above-mentioned neural network connection with hardware, it can be executed at higher speed.

FPGA 4014 is an OS-FPGA. The OS-FPGA can reduce the area of the memory compared to the FPGA configured with SRAM. Therefore, even if a context switching function is added, the area increase is small. The OS-FPGA can transmit data and parameters at high speed by boosting.

In the AI system 4041, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption. In addition, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

Note that the arithmetic unit 4010 need not have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided depending on the problem that the AI system 4041 wants to solve.

The AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). DBN) etc. can be performed. The PROM 4025 can store a program for executing at least one of these methods. Also, a part or all of the program may be stored in the NOSRAM 4013.

Many existing programs that exist as libraries are predicated on GPU processing. Therefore, the AI system 4041 preferably includes a GPU 4022. The AI system 4041 can execute a product-sum operation that is rate-limiting among the product-sum operations used in learning and inference by the arithmetic unit 4010, and can execute other product-sum operations by the GPU 4022. By doing so, learning and inference can be performed at high speed.

The power supply circuit 4027 not only generates a low power supply potential for a logic circuit but also generates a potential for analog operation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.

The PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.

CPU 4021 and GPU 4022 preferably have OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.

The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential for controlling the clock oscillation period.

The AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM. The memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.

Part or all of the circuit shown in the control unit 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.

In many cases, data used for neural network calculations is stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.

Since learning and inference using a neural network often handle audio and video, the AI system 4041 has an audio codec 4032 and a video codec 4033. The audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data, and the video codec 4033 encodes and decodes video data.

The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).

The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably includes a communication module 4035.

The analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory. However, the flash memory has a limited number of rewritable times. In addition, it is very difficult to form a multi-level flash memory in an embedded manner (an arithmetic circuit and a memory are formed on the same die).

Further, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy. Furthermore, since the device has two terminals, circuit design for separating data writing and reading becomes complicated.

Further, the analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has a problem in terms of storage accuracy.

In view of the above, the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 20)
<Application example of AI system>
In this embodiment, application examples of the AI system described in the above embodiment will be described with reference to FIGS.

FIG. 133 (A) shows an AI system 4041A in which the AI system 4041 described in FIG. 132 is arranged in parallel and signals can be transmitted and received between systems via a bus line.

The AI system 4041A illustrated in FIG. 133A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.

FIG. 133B shows an AI system 4041B in which the AI system 4041 described in FIG. 132 is arranged in parallel as in FIG. 133A, and signals can be transmitted and received between systems via a network. is there.

The AI system 4041B illustrated in FIG. 133B includes a plurality of AI systems 4041_1 to 4041_n. The AI systems 4041_1 to 4041_n are connected to each other via a network 4099.

The network 4099 may have a configuration in which a communication module is provided in each of the AI system 4041_1 to the AI system 4041_n to perform wireless or wired communication. The communication module can communicate via an antenna. For example, the Internet, Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (Campure Area Network, MAN (MetropoliAwareNetwork), MAN (MetropoliAureNetwork), which are the foundations of the World Wide Web (WWW). Each electronic device can be connected to a computer network such as Network) or GAN (Global Area Network) to perform communication. When performing wireless communication, as communication protocols or communication technologies, LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolvement, CDMA Emulsion, CDMA Emulsion) , Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.

133A and 133B, analog signals obtained by an external sensor or the like can be processed by separate AI systems. For example, information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information, can be acquired by various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor, and analog signals can be processed by separate AI systems. it can. By performing signal processing or learning in each separate AI system, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 21)
In this embodiment, an example of an IC in which the AI system described in the above embodiment is incorporated is described.

The AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.

FIG. 134 shows an example of an IC incorporating an AI system. An AI system IC 7000 shown in FIG. 134 includes a lead 7001 and a circuit portion 7003. The AI system IC 7000 is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004). The circuit portion 7003 is provided with the various circuits described in the above embodiment in one die. As described in the above embodiment, the circuit portion 7003 has a stacked structure and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.

In FIG. 134, QFP (Quad Flat Package) is applied to the package of the AI system IC 7000, but the package mode is not limited to this.

Digital processing circuits such as a CPU, analog arithmetic circuits using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. it can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not need to increase the manufacturing process even if the number of elements constituting the IC is increased, and the AI system can be incorporated at low cost.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 22)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. 135 to 137 illustrate specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.

A robot 2100 illustrated in FIG. 135A includes a computing device 2110, an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a moving mechanism 2108.

The microphone 2102 has a function of detecting a user's speaking voice and environmental sound. The speaker 2104 has a function of emitting sound. The robot 2100 can communicate with the user using the microphone 2102 and the speaker 2104.

The display 2105 has a function of displaying various information. The robot 2100 can display information desired by the user on the display 2105. The display 2105 may be equipped with a touch panel.

The upper camera 2103 and the lower camera 2106 have a function of imaging the surroundings of the robot 2100. The obstacle sensor 2107 can detect the presence or absence of an obstacle in the traveling direction when the robot 2100 moves forward using the moving mechanism 2108. The robot 2100 can recognize the surrounding environment using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107, and can move safely.

135 (B) includes an arithmetic device 2121, a propeller 2123, and a camera 2122, and has a function of flying independently.

In the flying object 2120, the electronic components can be used for the arithmetic device 2121 and the camera 2122.

FIG. 135 (C) is an external view showing an example of an automobile. The automobile 2980 has a camera 2981 and the like. The automobile 2980 includes various sensors such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 2980 can analyze an image taken by the camera 2981, determine surrounding traffic conditions such as the presence or absence of a pedestrian, and perform automatic driving.

FIG. 135 (D) shows a situation in which the portable electronic device 2130 performs simultaneous interpretation in communication between a plurality of people who speak in different languages.

The portable electronic device 2130 includes a microphone, a speaker, and the like, and has a function of recognizing a user's speaking voice and translating it into a language spoken by the other party.

In FIG. 135D, the user has a portable microphone 2131. The portable microphone 2131 has a wireless communication function and a function of transmitting detected sound to the portable electronic device 2130.

FIG. 136 (A) is a schematic cross-sectional view showing an example of a pacemaker.

The pacemaker body 5300 has at least a battery 5301a, a battery 5301b, a regulator, a control circuit, an antenna 5304, a wire 5302 to the right atrium, and a wire 5303 to the right ventricle.

The pacemaker body 5300 is placed in the body by surgery, and two wires pass through the human subclavian vein 5305 and superior vena cava 5306, one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. To be.

Further, power can be received by the antenna 5304, and the power is charged in the battery 5301a and the battery 5301b, so that the pacemaker replacement frequency can be reduced. Since the pacemaker body 5300 has a plurality of batteries, it is highly safe, and even if one fails, the other can function, and thus functions as an auxiliary power source.

In addition to an antenna 5304 that can receive power, an antenna that can transmit physiological signals may be provided. For example, physiological signals such as a pulse, a respiratory rate, a heart rate, and a body temperature can be confirmed by an external monitor device. A system for monitoring cardiac activity may be configured.

A sensor 5900 shown in FIG. 136 (B) is attached to a human body using an adhesive pad or the like. The sensor 5900 gives a signal to the electrode 5931 or the like attached to the human body via the wiring 5932 to acquire biological information such as a heart rate and an electrocardiogram. The acquired information is transmitted as a wireless signal to a terminal such as a reader.

FIG. 137 is a schematic diagram showing an example of a cleaning robot.

The cleaning robot 5100 includes a display 5101 disposed on the top surface, a plurality of cameras 5102 disposed on the side surface, brushes 5103, and operation buttons 5104. Although not shown, the lower surface of the cleaning robot 5100 is provided with a tire, a suction port, and the like. In addition, the cleaning robot 5100 includes various sensors such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, and a gyro sensor. Moreover, the cleaning robot 5100 includes a wireless communication unit.

The cleaning robot 5100 is self-propelled, can detect the dust 5120, and can suck the dust from the suction port provided on the lower surface.

In addition, the cleaning robot 5100 can analyze the image taken by the camera 5102 and determine whether there is an obstacle such as a wall, furniture, or a step. In addition, when an object that is likely to be entangled with the brush 5103 such as wiring is detected by image analysis, the rotation of the brush 5103 can be stopped.

The display 5101 can display the remaining amount of the battery, the amount of dust sucked, and the like. The route on which the cleaning robot 5100 has traveled may be displayed on the display 5101. Alternatively, the display 5101 may be a touch panel, and the operation buttons 5104 may be provided on the display 5101.

The cleaning robot 5100 can communicate with a portable electronic device 5140 such as a smartphone. An image captured by the camera 5102 can be displayed on the portable electronic device 5140. Therefore, the owner of the cleaning robot 5100 can know the state of the room even when away from home. In addition, the display on the display 5101 can be confirmed with a portable electronic device 5140 such as a smartphone.

For example, a memory device using the semiconductor device of one embodiment of the present invention can hold the above-described control information of an electronic device, a control program, and the like for a long time. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

In addition, for example, an IC in which the AI system is incorporated can be used in the arithmetic device of the electronic device described above. Accordingly, the electronic device described in this embodiment can perform an accurate operation according to the situation with low power consumption by using the AI system.

This embodiment can be implemented in appropriate combination with the configurations described in the other embodiments and examples.

(Embodiment 23)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIGS. 138 and 139 illustrate specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.

A robot 2000 shown in FIG. 138A includes an arithmetic device 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a moving mechanism 2011, and can take still images and moving images while moving. Such a robot can be used as a security system or a monitoring system.

The robot 2000 may further include a communication unit 2006, a speaker 2007, a microphone 2008, a display unit 2009, a light emitting unit 2010, and the like.

The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001. For the arithmetic device 2001, an IC in which the AI system according to one embodiment of the present invention is incorporated can be used. The sensor 2002 has a function as a camera that captures the surroundings of the robot 2000. The light 2003 can be used as a light when the sensor 2002 captures the surroundings of the robot 2000. Note that when the sensor 2002 captures a still image, the light 2003 preferably functions as a flashlight. The sensor 2002 is connected to the robot main body via a lift 2004. The height of the sensor 2002 can be adjusted by a lift 2004. The lift 2004 is preferably telescopic. The lift 2004 may be a foldable type constituted by a plurality of booms. In addition, since the robot 2000 is provided with a driving unit 2005 and a moving mechanism 2011 connected to the driving unit 2005, an imaging range by the sensor 2002, that is, a monitoring range is widened, which is preferable.

The communication unit 2006 can transmit information captured by the sensor 2002 to an administrator or a server owned by the administrator. In addition, the information captured by the sensor 2002 is analyzed by the arithmetic unit 2001, and when it is determined that an emergency such as a crime, an accident, or a fire, the security company, the police, the fire department, the medical institution, the land or building owner You can contact me. The speaker 2007 can transmit information to the surroundings of the robot, such as warning a criminal, asking an injured person or a suddenly ill person, and guiding evacuation. The microphone 2008 can be used to acquire sound around the robot 2000. Further, the robot 2000 can have a function as a telephone by being used in combination with the communication unit 2006 and the speaker 2007. A person around the robot 2000 can talk with an administrator or any person. The display unit 2009 can display arbitrary information. In case of an emergency, disaster information and evacuation routes can be displayed. Further, when used in combination with the communication unit 2006, the speaker 2007, and the microphone 2008, the robot 2000 can have a function as a videophone. A person around the robot 2000 can talk with an administrator or an arbitrary person while watching the display unit 2009.

The light emitting unit 2010 can indicate the traveling direction or stop state of the robot 2000 with characters or light. It may also indicate an emergency situation.

FIG. 138 (B) is a block diagram showing the configuration of the robot 2000. The arithmetic device 2001 performs lighting 2003 on / off and brightness adjustment based on information such as an image obtained by the sensor 2002. Further, the height of the lift 2004 is adjusted, or the drive unit 2005 is controlled, and the robot 2000 and the sensor 2002 are aligned. In addition, the operation status of the drive unit 2005 can be indicated using the light emitting unit 2010. Further, by using the communication unit 2006, information around the robot 2000 obtained from the sensor 2002 and the microphone 2008 can be transmitted to the manager or a server owned by the manager. Further, information can be transmitted to the surroundings of the robot 2000 using the speaker 2007 and the display unit 2009 based on the judgment of the arithmetic device 2001 or the administrator.

When a sensor capable of imaging even when the surrounding is dark is used as the sensor 2002, the light 2003 may not be provided. As such a sensor, an image sensor using selenium (Se) as a light receiving portion can be used.

Such a robot 2000 can be used for security of commercial facilities and offices. Information obtained from the sensor 2002 or the microphone 2008 is stored in the arithmetic device 2001 or a server. The stored information is analyzed by the AI system to determine whether there is an abnormality such as a lost or damaged article, a suspicious person invading, or a disaster such as a fire. Deep learning may be used for information analysis. If it is determined that an abnormality has occurred, the robot 2000 contacts the administrator and transmits information to the surroundings, and records the surrounding conditions.

Further, the robot 2000 may be used for monitoring the growth status of crops. The robot 2000 installed in the rice field or the field monitors the leaves, or the shape, size, and color of the crop by using the sensor 2002, and determines whether the disease is ill or the pest is not attached. Since the robot 2000 is provided with the moving mechanism 2011, it is possible to monitor the growth status of a wide range of agricultural products. Further, since the robot 2004 is provided with a lift 2004, it is possible to monitor leaves and fruits of any height regardless of the type of crops and the growth situation. The monitoring result is sent to the producer using the communication means 2006, and the producer can determine the type and amount of fertilizer and pesticide necessary for the crop and the application time. Further, the monitoring result may be analyzed by the AI system using the arithmetic device 2001, and the type, amount, and application time of the fertilizer and pesticide necessary for the crop may be determined and notified to the producer. Deep learning may be used for analyzing the monitoring result.

FIG. 139 (A) shows a sorting system 3000 using a robot 3001. The robot 3001 includes an arithmetic device 3002, a boom 3003, and an arm 3004. The robot 3001 may include a wired or wireless communication unit 3011. In addition, the sorting system 3000 includes a housing 3008 having a sensor 3009. The housing 3008 has a communication unit 3010. The housing 3008 is provided on the sorting system 3000 or the ceiling, wall, and beam (none of which are shown) of the sorting work area. The housing 3008 may be provided in the robot 3001. For example, the boom 3003 or the arm 3004 may be provided. When the housing 3008 is provided in the robot 3001, the information obtained by the sensor 3009 may be sent to the arithmetic device 3002 and processed without passing through the communication unit 3010 and the communication unit 3011.

The boom 3003 is movable, and the arm 3004 can be disposed at a desired position. The arm 3004 may be a telescopic type. The arm 3004 may be moved by the boom 3003 after the arm placed on the desired article 3007 is extended, the desired article 3007 is gripped, and the arm 3004 is contracted.

The sorting system 3000 can move the article 3007 in the container 3005 to the container 3006. The container 3005 and the container 3006 may have the same shape or different shapes. In addition, a plurality of articles 3007 placed in one container 3005 may be distributed and moved to a plurality of containers 3006.

As the container 3005 and the container 3006, a container, a cardboard box, a box for packing products, a case, a film or a bag, a food storage bat, a lunch box, or the like is used. Further, at least one of the container 3005 and the container 3006 may be a cooking utensil such as a pan or a frying pan.

The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 3002. For the arithmetic device 3002, an IC in which the AI system according to one embodiment of the present invention is incorporated can be used.

The sensor 3009 reads the position of the container 3005, the position of the container 3006, the state of the container 3005, and the state of the article 3007 in the container 3005, and transmits information to the arithmetic device 3002 using the communication unit 3010. Information is transmitted wirelessly or by wire. Further, the information may be transmitted by wire without using the communication unit 3010. The arithmetic device 3002 analyzes the transmitted information. Here, the state of the article 3007 indicates the shape, number, overlap of the articles 3007, and the like. The arithmetic device 3002 performs analysis based on information from the sensor 3009 and derives detailed information of the article 3007. Compared with data stored in the arithmetic device 3002 or a server communicable with the robot 3001, the three-dimensional shape and hardness (softness) of the article 3007 are derived. Further, the shape of the arm 3004 can be changed based on the three-dimensional shape and hardness (softness) of the article 3007.

In order to derive detailed information of the article 3007, analysis using an AI system can be used. Deep learning may be used for information analysis.

FIG. 139 (B) shows an arm that can move the pair of plates 3021 in the horizontal direction and sandwich the article 3007 therebetween. The article 3007 can be sandwiched by the pair of plates 3021 moving in the horizontal direction toward the center. Such an arm can grasp the article 3007 by a surface and is suitable for grasping the article 3007 having a columnar shape such as a cube or a rectangular parallelepiped. FIG. 139C illustrates an arm in which a plurality of bars 3022 can move in the horizontal direction and sandwich an article 3007. The articles 3007 can be sandwiched by the plurality of bars 3022 moving in the horizontal direction toward the center. Such an arm can grasp the article 3007 with a point, and is suitable for grasping the article 3007 having a spherical shape, or when the shape of the article 3007 is not constant, that is, the article 3007 having an irregular shape. Note that although the number of the bars 3022 is four in FIG. 139C, this embodiment is not limited to this. There may be three bars 3022 or five or more bars. FIG. 139D illustrates an arm that can sandwich the article 3007 when the pair of plates 3023 rotate around a common axis so as to approach each other. Such an arm can grasp the article 3007 by a surface and is suitable for grasping the article 3007 having a thin film shape such as paper or film. FIG. 139E illustrates an arm that can sandwich the article 3007 by a pair of hook-shaped plates 3024 rotating around a common axis so that the tips of each other approach each other. Such an arm can catch the article 3007 with dots or lines, and is suitable for grasping an article 3007 having a thin film shape, such as paper or film, or an article 3007 having a smaller granular shape. . Further, as shown in FIG. 139 (F), a spatula 3025 may be attached to the tip of the arm, and an article 3007 having a smaller granular shape may be scooped.

The arms shown in FIGS. 139A to 139F are examples, and one embodiment of the present invention is not limited to these shapes. The description of the use of each arm is also an example, and one embodiment of the present invention is not limited to these descriptions.

The robot 3001 moves the boom 3003 based on a signal from the arithmetic device 3002, and moves the arm 3004 onto a desired article 3007 in the container 3005. In the case of the extendable arm 3004, the arm 3004 is extended and the tip of the arm 3004 is lowered to the height of the article 3007. The tip of the arm is moved and the desired article 3007 is gripped. While holding the article 3007, the arm is contracted. The boom 3003 is moved again, and the arm 3004 is moved to a desired position on the container 3006. At this time, the arm 3004 may be rotated in order to adjust the angle of the article 3007 with respect to the container 3006. The arm 3004 is extended, the article 3007 is placed in the container 3006, and the arm 3004 releases the article 3007. By repeating the above operation, the robot 3001 can move the article 3007 from the container 3005 to the container 3006.

Since the position information of the container 3005 and the container 3006 and the state of the article 3007 are analyzed using the AI system, the article 3007 can be reliably moved regardless of the shape and rigidity of the article 3007. Examples of the article 3007 include not only articles packed in cubes, rectangular parallelepipeds, or boxes or cases of any shape, but also processed foods such as eggs, hamburgers and croquettes, and irregular vegetables such as potatoes and tomatoes. Foods such as, machine parts such as screws and nuts, and thin films such as paper and films. Since the sorting system 3000 shown in this embodiment can change the shape of the arm in consideration of the shape and rigidity of the article 3007, the article 3007 exemplified above can be used as a container regardless of the shape and rigidity. The container 3006 can be moved from 3005.

For example, a memory device using the semiconductor device of one embodiment of the present invention can hold the above-described control information of an electronic device, a control program, and the like for a long time. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

In addition, for example, an IC in which the AI system is incorporated can be used in the arithmetic device of the electronic device described above. Thus, the electronic device described in this embodiment can perform an accurate operation according to the situation with low power consumption by the Al system.

This embodiment can be implemented in appropriate combination with the configurations described in the other embodiments and examples.

In this example, the transition of the sheet resistance of the oxide when a metal compound was formed on the oxide was measured. The sheet resistance measuring instrument has a measurement upper limit of 6.0 × 10 ⁶ Ω / sq. The thing which is is used. The transition of the sheet resistance of the oxide is shown in FIG. The sample used for evaluation of transition of sheet resistance will be described below.

A method for manufacturing Sample 1 will be described. The surface of the substrate containing silicon was heat-treated in a hydrogen chloride (HCl) atmosphere to form a 100 nm silicon oxide film on the substrate. Next, an oxide with a thickness of 5 nm is formed over the silicon oxide film by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. An oxide with a thickness of 15 nm was formed using a target of Zn: 4: 2: 4.1 [atomic ratio]. Next, the formed oxide is subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and then continuously subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere. The heat treatment of was carried out. When the sheet resistance of the oxide of Sample 1 was measured, it was overranged, and the oxide sheet resistance was 6.0 × 10 ⁶ Ω / sq. It turns out that it is above.

Next, a manufacturing method of Sample 2 will be described. Similar to Sample 1, a silicon oxide film and an oxide were formed over the substrate, and first heat treatment was performed. After the first heat treatment, a metal compound having a thickness of 2 nm was formed over the oxide by a sputtering method using a target of Ti: Al = 1: 1 [atomic ratio] in an atmosphere containing nitrogen. The obtained metal compound contains titanium, aluminum, and nitrogen, and can be expressed as TiAlNx. When the sheet resistance of the oxide of Sample 2 was measured, it was 3.8 × 10 ³ Ω / sq. Met. By forming a metal compound on the oxide, the sheet resistance value of the oxide was reduced.

Next, a method for manufacturing Sample 3 will be described. Similar to Sample 2, a silicon oxide film and an oxide were formed over the substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, a second heat treatment was performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere. When the sheet resistance of the oxide of Sample 3 was measured, it was 2.9 × 10 ³ Ω / sq. Met. Although there was almost no change in the sheet resistance value of the oxide reduced by the formation of the metal compound, the sheet resistance value of the oxide of Sample 3 was reduced as compared with Sample 2.

Next, a method for manufacturing Sample 4 will be described. Similarly to Sample 3, a silicon oxide film and an oxide were formed over the substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, a second heat treatment was performed. After the second heat treatment, an aluminum oxide film with a thickness of 20 nm was formed by a sputtering method using a target containing aluminum oxide (Al ₂ O ₃ ) in an atmosphere containing argon and oxygen. It is considered that oxygen (excess oxygen) is supplied to the oxide by the formation of aluminum oxide. Here, when oxygen is supplied to the oxide, the resistance value of the oxide increases and may approach the I-type semiconductor. When the sheet resistance of the oxide of Sample 4 was measured, it was 1.9 × 10 ³ Ω / sq. Met. In Sample 4, the oxide sheet resistance was measured after removing the aluminum oxide. In the oxide having a reduced sheet resistance value due to the formation of the metal compound, the increase in the sheet resistance value due to the formation of aluminum oxide was not observed, and the sheet resistance value of the oxide of the sample 4 was reduced as compared with the sample 3. .

Next, a method for manufacturing Sample 5 will be described. Similarly to Sample 4, a silicon oxide film and an oxide were formed over the substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, a second heat treatment was performed. Aluminum oxide was formed after the second heat treatment. After the formation of aluminum oxide, a third heat treatment is performed, in which a heat treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and a heat treatment is continuously performed at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere. did. It is conceivable that oxygen contained in aluminum oxide diffuses into the oxide by the third heat treatment. When the sheet resistance of the oxide of Sample 5 was measured, it was 1.5 × 10 ³ Ω / sq. Met. In Sample 5, the oxide sheet resistance was measured after removing the aluminum oxide. In the oxide whose sheet resistance value was reduced by the formation of the metal compound, formation of aluminum oxide and an increase in sheet resistance value due to the third heat treatment were not observed. In addition, the sheet resistance value of the oxide of Sample 5 was reduced as compared with Sample 3 and Sample 4.

This example can be implemented in appropriate combination with the configurations described in the other embodiments and examples.

In this example, the result of evaluating the hydrogen concentration in an oxide of a sample in which a metal compound is provided on an oxide and the metal oxide is provided on the metal compound will be described. For evaluation of hydrogen concentration, SSDP (Substrate Side Depth Profile) -SIMS analysis was used.

Hereinafter, a method for manufacturing Sample 6 and Sample 7 used in SSDP-SIMS analysis will be described.

A method for manufacturing Sample 6 will be described. The surface of the substrate containing silicon was heat-treated in a hydrogen chloride (HCl) atmosphere to form a 100 nm silicon oxide film on the substrate. Next, an oxide with a thickness of 50 nm was formed over the silicon oxide film by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, the formed oxide is subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and then continuously subjected to a first heat treatment at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere. It was. After the first heat treatment, a metal compound having a thickness of 2 nm was formed over the oxide by a sputtering method using a target of Ti: Al = 1: 1 [atomic ratio] in an atmosphere containing nitrogen. Next, after the formation of the metal compound, a second heat treatment was performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere. After the second heat treatment, Sample 6 was obtained by forming a 20 nm-thick aluminum oxide film in an atmosphere containing argon and oxygen using a target containing aluminum oxide (Al ₂ O ₃ ) by a sputtering method.

Next, a method for producing Sample 7 will be described. Similarly to Sample 6, a silicon oxide film and an oxide were formed over the substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, a second heat treatment was performed. Aluminum oxide was formed after the second heat treatment. After the formation of aluminum oxide, a heat treatment was performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and a third heat treatment was continuously performed at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere.

FIG. 141 shows the results of detecting hydrogen by performing SSDP-SIMS analysis on Sample 6 and Sample 7 manufactured as described above. In FIG. 141, the horizontal axis represents the depth (Depth) [nm], and the vertical axis represents the hydrogen concentration (H concentration) [atoms / cm ³ ]. The hydrogen concentration of sample 6 is indicated by a broken line, and the hydrogen concentration of sample 7 is indicated by practice. In addition, the background level of the hydrogen concentration in the SSDP-SIMS analysis is 3.8 × 10 ¹⁸ atoms / cm ³ , and is indicated by a long broken line in the graph. The SSDP-SIMS analysis of Sample 6 and Sample 7 was performed by digging a sample from the silicon wafer side. Moreover, the SSDP-SIMS analysis of the sample 6 and the sample 7 quantified the oxide (it describes with IGZO in the figure), and converted the hydrogen concentration of the oxide (IGZO). The SIMS analysis was performed using a quadrupole mass spectrometer (ADEPT 1010) manufactured by ULVAC-PHI. The detection area of sample 6 and sample 7 was 60 μm × 60 μm.

141, as shown in FIG. 141, in sample 6, hydrogen is detected in the oxide (IGZO). On the other hand, in the sample 7 subjected to the heat treatment, the hydrogen concentration in the oxide (IGZO) is reduced, and in particular, the hydrogen concentration on the metal compound side is reduced to the background level.

As described above, the hydrogen concentration in the oxide was reduced by performing the heat treatment on the sample in which the metal compound was provided on the oxide and the metal oxide was provided on the metal compound. This evaluation suggests that hydrogen in the oxide is extracted by the metal oxide through the metal compound. That is, it was suggested that by providing a metal oxide in the vicinity of the oxide, hydrogen in the oxide is extracted to the metal oxide. Thus, the phenomenon in which the metal oxide abstracts hydrogen from the oxide can be referred to as gettering.

This example can be implemented in appropriate combination with the configurations described in the other embodiments and examples.

In this example, a transistor 200A having a metal compound illustrated in FIG. 1 which is one embodiment of the present invention was manufactured (referred to as Sample 1A), and the electrical characteristics were measured.

Hereinafter, a method for producing Sample 1A will be described.

First, a silicon oxide film having a thickness of 400 nm was formed on a p-type silicon single crystal wafer by a thermal oxidation method. An aluminum oxide film having a thickness of 40 nm was formed as the insulator 210 over the silicon oxide film by a sputtering method.

A tungsten film with a thickness of 150 nm was formed as a conductive film to be the conductor 203 over the insulator 210 by a sputtering method. Next, a part of the conductive film was etched by a lithography method. The etching was dry etching.

Next, as an insulating film to be the insulator 212, a silicon oxynitride film was formed to a thickness of 350 nm by a CVD method. Next, the insulating film was polished by a first CMP process until the upper surface of the conductive film was reached, so that a conductor 203 having a function as a plug electrode and a wiring layer, and an insulator 212 were formed.

Next, a silicon oxynitride film having a thickness of 160 nm was formed as the insulator 216 by a CVD method.

A tungsten film with a thickness of 35 nm was formed on the insulator 216 by sputtering. Next, the tungsten film was processed by a lithography method to form a hard mask having the tungsten film.

Next, the insulator 216 was processed by the damascene method using the hard mask, thereby forming a contact hole and a groove to be a wiring. A tantalum nitride film is formed in the contact hole and the groove by a sputtering method as a conductive film to be the first conductor of the conductor 205, and over the conductive film to be the first conductor of the conductor 205 A titanium nitride film is formed by an ALD method as a conductive film to be the second conductor of the conductor 205, and the third conductor 205 is formed on the conductive film to be the second conductor of the conductor 205. As a conductive film to be a conductive material, a tungsten film was formed by a CVD method.

Next, part of the conductive film to be the conductor 205 and the hard mask are polished by the second CMP process until the top surface of the insulator 216 is reached, and the conductor 205 is placed in the contact hole and in the groove. A buried electrode, a plug electrode, a wiring layer, and a second gate electrode were formed.

Next, a silicon oxynitride film is formed as the insulator 220 with a thickness of 10 nm by a CVD method, and a hafnium oxide film is formed as the insulator 222 with a thickness of 10 nm by an ALD method. As 224, a silicon oxynitride film was formed to a thickness of 10 nm by a CVD method. The insulator 220, the insulator 222, and the insulator 224 function as a second gate insulating film.

Next, the first heat treatment was performed. The first heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, an oxide film 230A and an oxide film 230B were continuously formed. As the oxide film 230A, an In—Ga—Zn oxide film with a thickness of 5 nm was formed by a sputtering method. The oxide film 230A was formed using an In: Ga: Zn = 1: 3: 4 [atomic ratio] target under the conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C.

As the oxide film 230B, an In—Ga—Zn oxide film with a thickness of 15 nm was formed by a sputtering method. For the oxide film 230B, a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] is used, and an argon gas flow rate of 40 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130 ° C. The film was formed.

Next, a second heat treatment was performed. In the second heat treatment, treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen, and then, a treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing oxygen.

Next, a tungsten film with a thickness of 10 nm was formed on the oxide film 230B by sputtering. Next, the tungsten film was processed by a lithography method to form a hard mask having the tungsten film.

Next, the oxide film 230B and a part of the oxide film 230A were sequentially etched by lithography using the hard mask to form the oxide 230a and the oxide 230b. The etching was performed using a dry etching method. Thereafter, the hard mask was removed using a dry etching method.

Next, as the oxide film 230C, an In—Ga—Zn oxide film with a thickness of 5 nm was formed by a sputtering method. The oxide film 230C was formed using an In: Ga: Zn = 1: 3: 4 [atomic ratio] target under the conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C.

Next, a part of the oxide film 230C was etched by lithography to form an oxide 230c. For this etching, a wet etching method was used.

Next, as the insulating film 250A, a silicon oxynitride film was formed to a thickness of 10 nm by a CVD method.

Next, as the metal oxide film 252A, an In—Ga—Zn oxide with a thickness of 10 nm was formed by a sputtering method. The metal oxide film 252A is formed using an In: Ga: Zn = 4: 2: 4.1 [atomic ratio] target under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C. did.

Next, a titanium nitride film is formed to a thickness of 10 nm as a conductive film 260A over the metal oxide film 252A by a sputtering method, and a tungsten film is formed as a conductive film 260B over the conductive film 260A as a conductive film 260B. The film was formed with a thickness of 30 nm. The conductive film 260A and the conductive film 260B were continuously formed.

Next, an aluminum oxide film having a thickness of 7 nm was formed as the insulating film 270A on the conductive film 260B by ALD.

Next, a silicon oxynitride film having a thickness of 100 nm was formed as an insulating film 271A over the insulating film 270A by a CVD method.

Next, the insulating film 271A, the insulating film 270A, the conductive film 260B, and part of the conductive film 260A are sequentially etched by a lithography method, so that the insulator 271, the insulator 270, and the conductor 260 (the conductor 260b, and A conductor 260a) was formed. The insulating film 271A, the insulating film 270A, the conductive film 260B, and the conductive film 260A were etched by a dry etching method.

Next, a part of the metal oxide film 252A was etched by a lithography method to form a metal oxide 252. The metal oxide film 252A was etched using a wet etching method. The metal oxide 252 and the conductor 260 have a function as a first gate electrode.

Next, a part of the insulating film 250A was etched by lithography to form an insulator 250 having a function as a first gate insulator. The insulating film 250A was etched using a dry etching method.

Next, as the insulating film 275A, a silicon oxynitride film with a thickness of 15 nm was formed by a CVD method.

Next, a part of the insulating film 275A was etched to form an insulator 275. The insulating film 275A was etched using a dry etching method.

Next, as the film 242A, a metal compound containing titanium, aluminum, and nitrogen (referred to as TiAlNx) was formed to a thickness of 2 nm by a sputtering method. TiAlNx was formed using a target of Ti: Al = 1: 1 [atomic ratio] under the conditions of an argon gas flow rate of 41 sccm, a nitrogen gas flow rate of 9 sccm, a pressure of 0.4 Pa, and a substrate temperature of room temperature.

Next, a third heat treatment was performed to form a layer 242. The third heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, as the insulator 273, an aluminum oxide film with a thickness of 10 nm was formed by sputtering using an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250 ° C.

Next, a fourth heat treatment was performed. In the fourth heat treatment, treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen, and then, a treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing oxygen.

Next, as the insulator 274, a silicon nitride film was formed to a thickness of 40 nm by CVD using a silane (SiH ₄ ) gas flow rate of 5 sccm, a nitrogen gas flow rate of 125 sccm, and a substrate temperature of 300 ° C.

Next, as the insulator 280, a silicon oxynitride film with a thickness of 470 nm was formed by a CVD method. Next, a third CMP process was performed, the insulator 280 was polished, and the surface of the insulator 280 was planarized.

Next, an aluminum oxide film having a thickness of 40 nm is formed over the insulator 280 as an insulator 282 by sputtering using an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250 ° C. A film was formed.

Next, a fifth heat treatment was performed. The fifth heat treatment was performed at a temperature of 350 ° C. for 1 hour in an atmosphere containing oxygen.

Next, as the insulator 284, a silicon oxynitride film with a thickness of 150 nm was formed by a CVD method.

Next, a tungsten film with a thickness of 90 nm was formed on the insulator 284 by sputtering. Next, the tungsten film was processed by a lithography method to form a hard mask having the tungsten film.

Next, a contact hole reaching the conductor 205 or 203, a contact hole reaching the conductor 260, and a contact hole reaching the oxide 230b were formed by lithography using the hard mask.

Next, a tungsten film is formed to a thickness of 10 nm by a sputtering method as a conductive film to be the first conductor of the conductor 240, and nitrided as a conductive film to be the second conductor of the conductor 240. A titanium film was formed to a thickness of 20 nm by an ALD method, and a tungsten film was formed to a thickness of 250 nm by a CVD method as a conductive film to be the third conductor of the conductor 240.

Next, a fourth CMP process is performed, and the conductive film to be the conductor 240 and the hard mask are polished until they reach the insulator 284 to form plugs in which the conductor 240 is embedded in each contact hole. did.

Next, by sputtering, the first titanium film has a thickness of 20 nm, the first titanium nitride film has a thickness of 30 nm, the aluminum film has a thickness of 100 nm, and the second titanium film has a thickness of 5 nm. A second titanium nitride film having a thickness of 45 nm was continuously formed.

Next, the first titanium film, the second titanium nitride film, the aluminum film, the second titanium film, and the second titanium nitride film were processed by lithography to form a wiring layer.

Next, a photosensitive polyimide film having a thickness of 1.6 μm was formed by a coating method, and a portion of the photosensitive polyimide film to be a measurement terminal (measurement pad) was removed by a lithography method.

Finally, the photosensitive polyimide film was heat treated at a temperature of 300 ° C. for 1 hour.

Thus, Sample 1A was produced.

Next, the electrical characteristics of Sample 1A were measured. The source-drain voltage (hereinafter referred to as the drain voltage Vd) is set to 0.1 V and 1.2 V, and the source-gate voltage (hereinafter referred to as the gate voltage Vg) is changed from −3.3 V to +3.3 V. The change in the source-drain current (hereinafter referred to as the drain current Id) was measured. That is, Id-Vg characteristics were measured. The gate voltage Vg indicates the voltage of the first gate electrode (top gate electrode), and the same applies hereinafter. In this measurement, the voltage of the second gate electrode (back gate electrode) was set to 0V. In this measurement, the Id-Vg characteristic of the transistor of sample 1A was measured. FIG. 142 shows the Id-Vg characteristic of Sample 1A.

Sample 1A was found to obtain transistor characteristics. Therefore, as described in the above embodiment, a semiconductor device having favorable electrical characteristics can be manufactured by providing a metal compound in a transistor.

This example can be implemented in appropriate combination with the configurations described in the other embodiments and examples.

In this example, a transistor 200A having a metal compound illustrated in FIG. 1, which is one embodiment of the present invention, was manufactured (referred to as Sample 2A), and electrical characteristics were measured.

Hereinafter, a method for producing Sample 2A will be described.

First, a silicon oxide film having a thickness of 400 nm was formed on a p-type silicon single crystal wafer by a thermal oxidation method. An aluminum oxide film having a thickness of 40 nm was formed as the insulator 210 over the silicon oxide film by a sputtering method.

A tungsten film with a thickness of 150 nm was formed as a conductive film to be the conductor 203 over the insulator 210 by a sputtering method. Next, a part of the conductive film was etched by a lithography method. The etching was dry etching.

Next, a silicon oxynitride film with a thickness of 350 nm was formed as an insulating film to be the insulator 212 over the insulator 210 and the conductive film by a CVD method. Next, the insulating film is polished by the first CMP process until the upper surface of the conductive film is reached, and the conductor 203 having a function as a plug electrode, a wiring layer, and a second gate electrode, and the insulator 212 was formed.

Next, a silicon oxynitride film is formed as the insulator 220 with a thickness of 10 nm by a CVD method, and a hafnium oxide film is formed as the insulator 222 with a thickness of 10 nm by an ALD method. As 224, a silicon oxynitride film was formed to a thickness of 10 nm by a CVD method. The insulator 220, the insulator 222, and the insulator 224 function as a second gate insulating film.

Next, the first heat treatment was performed. The first heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, an oxide film 230A and an oxide film 230B were continuously formed. As the oxide film 230A, an In—Ga—Zn oxide film with a thickness of 5 nm was formed by a sputtering method. The oxide film 230A was formed using an In: Ga: Zn = 1: 3: 4 [atomic ratio] target under the conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C.

As the oxide film 230B, an In—Ga—Zn oxide film with a thickness of 15 nm was formed by a sputtering method. For the oxide film 230B, a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] is used, and an argon gas flow rate of 40 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130 ° C. The film was formed.

Next, a second heat treatment was performed. In the second heat treatment, treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen, and then, a treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing oxygen.

Next, a tungsten film with a thickness of 10 nm was formed on the oxide film 230B by sputtering. Next, the tungsten film was processed by a lithography method to form a hard mask having the tungsten film.

Next, the oxide film 230B and a part of the oxide film 230A were sequentially etched by lithography using the hard mask to form the oxide 230a and the oxide 230b. The etching was performed using a dry etching method. Thereafter, the hard mask was removed using a dry etching method.

Next, as the oxide film 230C, an In—Ga—Zn oxide film with a thickness of 5 nm was formed by a sputtering method. The oxide film 230C was formed using an In: Ga: Zn = 1: 3: 4 [atomic ratio] target under the conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C.

Next, a part of the oxide film 230C was etched by lithography to form an oxide 230c. For this etching, a wet etching method was used.

Next, as the insulating film 250A, a silicon oxynitride film was formed to a thickness of 10 nm by a CVD method.

Next, as the metal oxide film 252A, an In—Ga—Zn oxide with a thickness of 10 nm was formed by a sputtering method. The metal oxide film 252A is formed using an In: Ga: Zn = 4: 2: 4.1 [atomic ratio] target under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C. did.

Next, a titanium nitride film is formed to a thickness of 10 nm as a conductive film 260A over the metal oxide film 252A by a sputtering method, and a tungsten film is formed as a conductive film 260B over the conductive film 260A as a conductive film 260B. The film was formed with a thickness of 30 nm. The conductive film 260A and the conductive film 260B were continuously formed.

Next, an aluminum oxide film having a thickness of 7 nm was formed as the insulating film 270A on the conductive film 260B by ALD.

Next, a silicon oxynitride film having a thickness of 100 nm was formed as an insulating film 271A over the insulating film 270A by a CVD method.

Next, the insulating film 271A, the insulating film 270A, the conductive film 260B, and part of the conductive film 260A are sequentially etched by a lithography method, so that the insulator 271, the insulator 270, and the conductor 260 (the conductor 260b, and A conductor 260a) was formed. The insulating film 271A, the insulating film 270A, the conductive film 260B, and the conductive film 260A were etched by a dry etching method.

Next, a part of the metal oxide film 252A was etched by a lithography method to form a metal oxide 252. The metal oxide film 252A was etched using a wet etching method. The metal oxide 252 and the conductor 260 have a function as a first gate electrode.

Next, a part of the insulating film 250A was etched by lithography to form an insulator 250 having a function as a first gate insulator. The insulating film 250A was etched using a dry etching method.

Next, as the insulating film 275A, a silicon oxynitride film with a thickness of 15 nm was formed by a CVD method.

Next, a part of the insulating film 275A was etched to form an insulator 275. The insulating film 275A was etched using a dry etching method.

Next, as the film 242A, an aluminum film with a thickness of 2 nm was formed by a sputtering method. The film 242A was formed using an Al target under the conditions of an argon gas flow rate of 50 sccm, a pressure of 0.4 Pa, and a substrate temperature of room temperature.

Next, a third heat treatment was performed to form a layer 242. The third heat treatment was performed at a temperature of 350 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, the layer 242 was removed using a wet etching method.

Next, as the insulator 273, an aluminum oxide film with a thickness of 10 nm was formed by sputtering using an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250 ° C.

Next, a fourth heat treatment was performed. The fourth heat treatment was performed at a temperature of 350 ° C. for one hour in an atmosphere containing oxygen.

Next, as the insulator 274, a silicon nitride film was formed to a thickness of 40 nm by CVD using a silane (SiH ₄ ) gas flow rate of 5 sccm, a nitrogen gas flow rate of 125 sccm, and a substrate temperature of 300 ° C.

Next, as the insulator 280, a silicon oxynitride film with a thickness of 470 nm was formed by a CVD method. Next, a second CMP treatment was performed, the insulator 280 was polished, and the surface of the insulator 280 was planarized.

Next, an aluminum oxide film having a thickness of 40 nm is formed over the insulator 280 as an insulator 282 by sputtering using an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250 ° C. A film was formed.

Next, a fifth heat treatment was performed. The fifth heat treatment was performed at a temperature of 350 ° C. for 1 hour in an atmosphere containing oxygen.

Next, as the insulator 284, a silicon oxynitride film with a thickness of 150 nm was formed by a CVD method.

Next, a tungsten film with a thickness of 90 nm was formed on the insulator 284 by sputtering. Next, the tungsten film was processed by a lithography method to form a hard mask having the tungsten film.

Next, a contact hole reaching the conductor 203, a contact hole reaching the conductor 260, and a contact hole reaching the oxide 230b were formed by lithography using the hard mask.

Next, a tungsten film is formed to a thickness of 10 nm by a sputtering method as a conductive film to be the first conductor of the conductor 240, and nitrided as a conductive film to be the second conductor of the conductor 240. A titanium film is formed to a thickness of 20 nm by the ALD method. As a conductive film to be the third conductor of the conductor 240, a tungsten film was formed to a thickness of 250 nm by a CVD method.

Next, a third CMP process is performed to polish the conductive film to be the conductor 240 and the hard mask until the insulator 284 is reached, thereby forming plugs in which the conductor 240 is embedded in each contact hole. did.

Next, by sputtering, the first titanium film has a thickness of 20 nm, the first titanium nitride film has a thickness of 30 nm, the aluminum film has a thickness of 100 nm, and the second titanium film has a thickness of 5 nm. A second titanium nitride film having a thickness of 45 nm was continuously formed.

Next, the first titanium film, the first titanium nitride film, the aluminum film, the second titanium film, and the second titanium nitride film were processed by lithography to form a wiring layer.

Next, a photosensitive polyimide film having a thickness of 1.6 μm was formed by a coating method, and a portion of the photosensitive polyimide film to be a measurement terminal (measurement pad) was removed by a lithography method.

Finally, the photosensitive polyimide film was heat treated at a temperature of 300 ° C. for 1 hour.

Thus, sample 2A was produced.

Next, the electrical characteristics of Sample 2A were measured. The source-drain voltage (hereinafter referred to as the drain voltage Vd) is set to 0.1 V and 1.2 V, and the source-gate voltage (hereinafter referred to as the gate voltage Vg) is changed from −3.3 V to +3.3 V. The change in the source-drain current (hereinafter referred to as the drain current Id) was measured. That is, Id-Vg characteristics were measured. The gate voltage Vg indicates the voltage of the first gate electrode (top gate electrode), and the same applies hereinafter. In this measurement, the voltage of the second gate electrode (back gate electrode) was set to 0V. In this measurement, the Id-Vg characteristic of the transistor of Sample 2A was measured. FIG. 143 shows the Id-Vg characteristic of Sample 2A.

Sample 2A was found to obtain transistor characteristics. Therefore, as described in the above embodiment, a semiconductor device having favorable electrical characteristics can be manufactured by providing a metal compound in a transistor.

This example can be implemented in appropriate combination with the configurations described in the other embodiments and examples.

100: capacitive element, 100a: capacitive element, 100b: capacitive element, 110: conductor, 112: conductor, 120: conductor, 120a: conductor, 120b: conductor, 130: insulator, 150: insulator, 200: transistor, 200a: transistor, 200A: transistor, 200b: transistor, 200B: transistor, 200C: transistor, 200D: transistor, 200E: transistor, 200F: transistor, 200G: transistor, 200H: transistor, 203: conductor, 203a : Conductor, 203b: conductor, 205: conductor, 205a: conductor, 205b: conductor, 207: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218 : Conductor, 220: Insulator, 222: Insulation 224: insulator, 224A: insulating film, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 231: region 231a: region, 231b: region, 232: region, 232a: region, 232b: region, 234: region, 239: region, 240: conductor, 240a: conductor, 240b: conductor, 240c: conductor, 242: Layer, 242A: film, 242B: insulator, 246: conductor, 248: conductor, 250: insulator, 250A: insulating film, 252: metal oxide, 252A: metal oxide film, 260: conductor, 260a: Conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 270: insulator, 270A: insulating film, 271: insulator, 271A: insulating film, 272 Insulator, 272A: Insulating film, 273: Insulator, 273A: Insulating film, 274: Insulator, 275: Insulator, 276A: Insulator, 276a: Insulator, 276b: Insulator, 277: Insulator, 277A: insulating film, 278: insulator, 280: insulator, 282: insulator, 284: insulator, 286: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance Region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: Insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 3 74: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 400: transistor, 403: conductor, 405: conductor, 424: insulator, 430c : Oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 450: insulator, 452: metal oxide, 460: conductor, 460a: conductor, 460b: conductor, 470: insulator, 471: insulator, 472: insulator, 473: insulator, 475: insulator, 477: insulator, 500: opening, 600: cell, 600a: cell, 600b: cell, 610: circuit 620: circuit, 650a: memory cell, 650b: memory cell, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring 1007: wiring, 1008: wiring, 1009: wiring, 1010: wiring, 1400: DOSRAM, 1405: controller, 1410: row circuit, 1411: decoder, 1412: word line driver circuit, 1413: column selector, 1414: sense amplifier driver Circuit, 1415: column circuit, 1416: global sense amplifier array, 1417: input / output circuit, 1420: MC-SA array, 1422: memory cell array, 1423: sense amplifier array, 1425: local memory cell array, 1426: local sense amplifier array , 1444: switch array, 1445: memory cell, 1445a: memory cell, 1445b: memory cell, 1446: sense amplifier, 1447: global sense amplifier, 1600: NOSRAM, 161 : Memory cell array, 1611: Memory cell, 1612: Memory cell, 1613: Memory cell, 1614: Memory cell, 1615: Memory cell, 1615a: Memory cell, 1615b: Memory cell, 1640: Controller, 1650: Row driver, 1651: Row decoder, 1652: word line driver, 1660: column driver, 1661: column decoder, 1662: driver, 1663: DAC, 1670: output driver, 1671: selector, 1672: ADC, 1673: output buffer, 2000: robot, 2001 : Arithmetic device, 2002: sensor, 2003: light, 2004: lift, 2005: drive unit, 2006: communication means, 2007: speaker, 2008: microphone, 2009: display unit, 2010: light emitting unit, 2011: Moving mechanism, 2100: Robot, 2101: Illuminance sensor, 2102: Microphone, 2103: Upper camera, 2104: Speaker, 2105: Display, 2106: Lower camera, 2107: Obstacle sensor, 2108: Moving mechanism, 2110: Computing device, 2120: Aircraft, 2121: Computing device, 2122: Camera, 2123: Propeller, 2130: Portable electronic device, 2131: Portable microphone, 2980: Car, 2981: Camera, 3000: System, 3001: Robot, 3002: Computing device 3003: Boom, 3004: Arm, 3005: Container, 3006: Container, 3007: Article, 3008: Housing, 3009: Sensor, 3010: Communication means, 3011: Communication means, 3021: Plate, 3022: Bar, 3023: Board, 302 : Board, 3025: Spatula, 3110: OS-FPGA, 3111: Controller, 3112: Word driver, 3113: Data driver, 3115: Programmable area, 3117: IOB, 3119: Core, 3120: LAB, 3121: PLE, 3123: LUT block, 3124: register block, 3125: selector, 3126: CM, 3127: power switch, 3128: CM, 3130: SAB, 3131: SB, 3133: PRS, 3135: CM, 3137: memory circuit, 3137B: memory circuit 3140: OS-FF, 3141: FF, 3142: Shadow register, 3143: Memory circuit, 3143B: Memory circuit, 3188: Inverter circuit, 3189: Inverter circuit, 4010: Arithmetic unit, 4011 Analog arithmetic circuit, 4012: DOSRAM, 4013: NOSRAM, 4014: FPGA, 4020: control unit, 4021: CPU, 4022: GPU, 4023: PLL, 4025: PROM, 4026: memory controller, 4027: power supply circuit, 4028: PMU 4030: Input / output unit, 4031: External storage control circuit, 4032: Audio codec, 4033: Video codec, 4034: General-purpose input / output module, 4035: Communication module, 4041: AI system, 4041_n: AI system, 4041_1: AI system 4041A: AI system, 4041B: AI system, 4098: bus line, 4099: network, 5100: cleaning robot, 5101: display, 5102: camera, 5103: brush, 5104 : Operation button 5120: Garbage 5140: Portable electronic device 5300: Pacemaker body 5301a: Battery 5301b: Battery 5302: Wire 5303: Wire 5304: Antenna 5305: Subclavian vein 5306: Superior vena cava 5900: Sensor, 5931: Electrode, 5932: Wiring, 7000: AI system IC, 7001: Lead, 7002: Printed circuit board, 7003: Circuit part, 7004: Mounting board, 7031: Si transistor layer, 7032: Wiring layer, 7033 : OS transistor layer

Claims (22)

A semiconductor device having an oxide in a channel formation region,
The semiconductor device has a transistor and a wiring,
The transistor is
The oxide on the first insulator;
A second insulator on the oxide;
A first conductor on the second insulator;
A third insulator on the first conductor;
A fourth insulator in contact with the second insulator, the first conductor, and the third insulator;
A fifth insulator in contact with the fourth insulator;
The oxide is
A first region overlapping the second insulator;
A second region overlapping the fourth insulator;
A third region in contact with the second region,
The third region has a lower oxygen concentration than the first region and the second region,
The second region has a lower oxygen concentration than the first region,
The wiring is in contact with the fifth insulator and electrically connected to the third region;
A semiconductor device. A semiconductor device having an oxide in a channel formation region,
The semiconductor device has a transistor and a wiring,
The transistor is
The oxide on the first insulator;
A second insulator and a first film on the oxide;
A first conductor on the second insulator;
A third insulator on the first conductor;
A fourth insulator in contact with the second insulator, the first conductor, and the third insulator;
A fifth insulator in contact with the fourth insulator;
The oxide is
A first region overlapping the second insulator;
A second region overlapping the fourth insulator;
A third region in contact with the second region,
The first film is provided in contact with the third region;
The third region has a lower oxygen concentration than the first region and the second region,
The second region has a lower oxygen concentration than the first region,
The wiring is in contact with the fifth insulator and electrically connected to the third region;
A semiconductor device. In claim 1 or claim 2,
The oxide includes In, the element M, and Zn,
A semiconductor device, wherein M is Al, Ga, Y, or Sn. In claim 3,
In the oxide, the value of In is larger than the value of the element M in the atomic ratio.
A semiconductor device. In claim 1 or claim 2,
The third region has a higher carrier density than the second region,
The second region has a higher carrier density than the first region.
A semiconductor device. In claim 1 or claim 2,
The semiconductor device, wherein the third region includes at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten. In claim 6,
The semiconductor device is characterized in that the third region further contains nitrogen. In claim 1 or claim 2,
The semiconductor device, wherein the first region has a hydrogen concentration lower than that of the second region. In claim 1 or claim 2,
The semiconductor device, wherein the first region has a lower hydrogen concentration than the second region and the third region. In claim 1 or claim 2,
The fifth insulator is:
Including metal oxides,
A semiconductor device. In claim 1 or claim 2,
The transistor is
A semiconductor device which is a normally-off type. In claim 2,
The semiconductor device, wherein the first film has a portion mixed with the third region. In claim 2 or claim 12,
The semiconductor device, wherein the first film includes at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten. In claim 2 or claim 12,
The semiconductor device, wherein the first film contains aluminum and titanium. In claim 13,
The semiconductor device, wherein the first film further includes one or both of nitrogen and oxygen. In claim 2 or claim 12,
The semiconductor device is characterized in that the first film is 0.5 nm or more and less than 5 nm. Forming a first insulator on the substrate;
Forming an oxide layer on the first insulator;
A first insulating film, a first conductive film, and a second insulating film are sequentially formed on the oxide layer,
Processing the first insulating film, the first conductive film, and the second insulating film to form a second insulator, a first conductor, and a third insulator;
A third insulating film and a fourth insulating film are sequentially formed so as to cover the first insulator, the oxide layer, the second insulator, the first conductor, and the third insulator. Membrane
By processing the third insulating film and the fourth insulating film,
A fourth insulator in contact with the second insulator, the first conductor, and the third insulator;
Forming a fifth insulator in contact with the fourth insulator;
Forming a first film containing a metal in contact with the first insulator, the oxide layer, and the fifth insulator;
Heat treatment in an atmosphere containing nitrogen,
Removing the first film;
Forming a sixth insulator on the first insulator, the oxide layer, and the fifth insulator, and forming an opening in the sixth insulator;
Forming a second conductor so as to fill the opening;
A method for manufacturing a semiconductor device. In claim 17,
The first film is
Formed by sputtering using one or more gases selected from argon, nitrogen, and oxygen;
A method for manufacturing a semiconductor device. In claim 17 or claim 18,
By performing the heat treatment, oxygen contained in a region where the oxide layer of the oxide layer and the first film are in contact with each other is extracted to the first film.
A method for manufacturing a semiconductor device. In claim 17,
Forming a second film covering at least the oxide, the first insulator, the third insulator, the fourth insulator, and the fifth insulator after the heat treatment; A method for manufacturing a semiconductor device. In claim 17,
The opening is formed such that at least a part of the fifth insulator, an upper surface of the oxide layer, and a side surface of the oxide layer are exposed.
A method for manufacturing a semiconductor device. In claim 17,
The method for manufacturing a semiconductor device, wherein the third insulating film and the fourth insulating film are processed by anisotropic etching using a dry etching method.

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