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WO2018207055A1 - Multilayer construction having electrically continuous conductor - Google Patents

Multilayer construction having electrically continuous conductor Download PDF

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Publication number
WO2018207055A1
WO2018207055A1 PCT/IB2018/053043 IB2018053043W WO2018207055A1 WO 2018207055 A1 WO2018207055 A1 WO 2018207055A1 IB 2018053043 W IB2018053043 W IB 2018053043W WO 2018207055 A1 WO2018207055 A1 WO 2018207055A1
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WO
WIPO (PCT)
Prior art keywords
electrode
major
substrate
multilayer construction
electrode portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2018/053043
Other languages
French (fr)
Inventor
Siang Sin Foo
Choong Meng HOW
Ravi Palaniswamy
Alejandro Aldrin II A. NARAG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Innovative Properties Co
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3M Innovative Properties Co
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Filing date
Publication date
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Publication of WO2018207055A1 publication Critical patent/WO2018207055A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections

Definitions

  • This disclosure relates generally to multilayer constructions having substrates and electrodes.
  • Printed circuit boards contain multiple layers of conductive metal sheets and non-conductive substrates. Electrically conductive material is provided within vias to electrically connect one or more of the conductive metal sheets which are separated by the substrate layers. Vias are conventionally manufactured by making holes (such as with a laser or by mechanical drilling) in the circuit board to create an electrical connection using an underlying seed layer (electro-less plating) and followed by an electrolytic plating process. As chip density increases, it becomes increasingly difficult to form holes sufficiently small for some circuit board and chip designs, and to adequately fill these holes with electrically conductive material.
  • a high density application is a light emitting semiconductor device (LESD).
  • the present invention includes a multilayer construction which includes a dielectric substrate and an electrically continuous electrode.
  • the dielectric substrate may define a first through via which defines a top opening at a major top surface of the substrate and a bottom opening at an opposing major bottom surface of the substrate.
  • the electrically continuous electrode includes three electrode portions.
  • the first electrode portion is disposed on the major top surface of the substrate and substantially covers the top opening of the first through via.
  • the second electrode portion has a major top surface and an opposing major bottom surface, the major top surface of the second electrode portion disposed on the major bottom surface of the substrate and substantially covers the bottom opening of the first through via.
  • the third electrode portion is disposed in and substantially fills the first through via and makes physical and electrical contact with the first and second electrode portions.
  • the bottom major surface of the second electrode portion has a curved concave surface portion substantially aligned with the first through via.
  • the electrically continuous electrode may be a unitary construction.
  • the electrically continuous electrode may include a discernible interface between the first and third electrode portions.
  • the discernible interface may be substantially planar, and may be within 0.5 ⁇ or within 0.25 ⁇ of the major top surface of the substrate.
  • the first through via defines a volume between the top and bottom openings of the first through via.
  • the third electrode portion may fill at least 50% of the volume, at least 70%, at least 80%, at least 90%, and up to 100% of the volume (entirely filling the volume).
  • the first electrode portion may cover at least 50%, by area, of the top opening of the first through via. That percentage may be at least 70%, at least 80%, at least 90%, at least 95%, and up to 100% (entirely covering the top opening).
  • the second electrode portion may cover at least 50%, by area, of the bottom opening of the first through via. That percentage may be at least 70%, at least 80%, at least 90%, at least 95%, and up to 100% (entirely covering the bottom opening).
  • the bottom major surface of the second electrode portion may also include substantially flat surface portions on each side of, and connected to, the curved concave surface portion.
  • the curved concave surface portion may define a maximum concave depth (d), wherein d > 1 ⁇ .
  • the depth (d) may also be > 2, 5, or 10 ⁇ .
  • the third electrode portion may physically contact a side wall of the first through via.
  • the third electrode portion and the side wall may define an elongated gap therebetween extending along at least a portion of a length of the side wall, or along its entire length.
  • the third electrode portion and a side wall of the first through via may define a gap therebetween extending from the side wall into the third electrode portion.
  • the second electrode portion may define first and second recesses in the bottom surface of the second electrode portion.
  • the substrate may comprise one or more of polyimide (PI), thermoplastic PI, aromatic polyamide, liquid crystal polymer (LCP), polycarbonate (PC), polyether ether ketone, polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), polycyclic olefin, polysulfone (PSU), polyethylene naphthalate (PEN), epoxy resin, FR4, and thermoplastic dielectric material.
  • the substrate may be dielectric and may be flexible or rigid.
  • the multilayer construction may also be flexible or rigid.
  • the first, second and third electrode portions may comprise copper.
  • the present invention also includes a light emitting semiconductor device (LESD) package.
  • This package includes the multilayer construction described above, with the first electrode portion being patterned to form spaced apart electrically conductive first and second pads. The first, but not the second, pad may be electrically connected to the third electrode portion.
  • the package also includes an LESD mounted on a major top surface of the multilayer construction. An electrically conductive first terminal of the LESD electrically is connected to the first pad, and an electrically conductive second terminal of the LESD is electrically connected to the second pad.
  • the third electrode portion may fill at least 80% of the first through via.
  • the third electrode portion may make direct physical contact with a side wall of the first through via.
  • the bottom major surface of the second electrode portion may comprise substantially flat surface portions on each side of the curved concave surface portion.
  • the dielectric substrate may define a second through via which defines a second top opening at a major top surface of the substrate and a second bottom opening at an opposing major bottom surface of the substrate.
  • the first electrode portion may cover the second through via; the third electrode portion may completely fill the second via and make physical and electrical contact with the first electrode layer; and the bottom major surface of the second electrode portion may comprise a second curved concave surface portion aligned with the second through via.
  • the present invention includes a multilayer construction for mounting a light emitting semiconductor device (LESD) which includes a dielectric substrate and a first electrode layer.
  • the dielectric substrate defines a first hollow via extending between the top and bottom major surfaces of the substrate, with the maximum lateral dimension of the first hollow via being in a range from about 40 to about 100 ⁇ .
  • the first electrode layer is disposed on the top major surface of the substrate and has an average thickness in a range from about 10 to about 30 ⁇ , or in the narrower range of from about 0.5 ⁇ to about 10 ⁇ .
  • a first portion of the first electrode layer may completely cover the first hollow via and have an electrically conductive top major surface exposed to air and a bottom major surface facing and directly exposed to the first hollow via.
  • the substrate may have an average thickness in a range from about 10 to about 50 ⁇ .
  • the present invention also includes a method of fabricating a multilayer construction, including the following steps:
  • the step of depositing the first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate may further include first depositing top and bottom electrode seed layers on the respective major top and bottom surfaces of the substrate, and then electroplating the first top and first bottom electrode layers on the respective top and bottom electrode seed layers.
  • the above method may also include the step of patterning the top electrode layer to form spaced apart electrically conductive first and second pads such that the first, but not the second, pad is electrically connected to the electrically conductive conducting portion.
  • the dielectric substrate and multilayer construction of the method above may be flexible or rigid.
  • FIG. 1 is a schematic side cross-sectional view of a multilayer construction according to one embodiment of the present invention.
  • FIGS. 2A and 2B are photomicrographs of a cross-section of a multilayer construction according to one embodiment of the present invention.
  • FIG. 3 is a schematic side cross-sectional view of a multilayer construction according to one embodiment of the present invention.
  • FIG. 4 is a schematic side cross-sectional view of a light emitting semiconductor device (LESD) package according to one embodiment of the present invention.
  • LESD light emitting semiconductor device
  • FIGS. 5A and 5B are schematic side cross-sectional views of the steps used to fabricate a multilayer construction according to one embodiment of the present invention.
  • Multilayer construction 100 includes dielectric substrate 110.
  • Substrate 110 may attach, support, and electrically isolate certain components of multilayer construction 100.
  • Substrate 110 has a major top surface 112 and an opposing major bottom surface 114.
  • Substrate 110 may be comprised of one or more of polyimide (PI), thermoplastic PI, aromatic polyamide, liquid crystal polymer (LCP), polycarbonate (PC), polyether ether ketone, polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), polycyclic olefin, polysulfone (PSU), polyethylene naphthalate (PEN), epoxy resin, FR4, and
  • Substrate 110 may be flexible or rigid, as may multilayer construction 100. Properties for which substrate 110 may be selected include, but are not limited to, processability, flame retardancy, glass transition temperature, decomposition temperature, coefficient of thermal expansion, thermal conductivity, electrical resistance, dielectric constant, strength, flexibility, and moisture absorption.
  • substrate 110 has a first through via 120 defining a top opening 124 at major top surface 112 of the substrate and a bottom opening 126 at opposing major bottom surface 114 of the substrate.
  • An electrically continuous electrode 70 comprises three portions. First electrode portion 130 of continuous electrode 70 has a major top surface 132 and an opposing major bottom surface 134. Major bottom surface 134 of first electrode portion 130 is disposed on major top surface 112 of substrate 110 and substantially covers top opening 124 of first through via 120.
  • a top electrode seed layer 109 may be applied to major top surface 112 of substrate 110 to facilitate application of first electrode portion 130.
  • Second electrode portion 140 of continuous electrode 70 has a major top surface 142 and an opposing major bottom surface 144.
  • Major top surface 142 of second electrode portion 140 is disposed on major bottom surface 114 of substrate 110 and substantially covers bottom opening 126 of first through via 120.
  • a bottom electrode seed layer 119 may be applied to major bottom surface 114 of substrate 110 to facilitate application of second electrode portion 140.
  • Third electrode portion 150 of continuous electrode portion 70 is disposed within and
  • First, second, and third electrode portions 130, 140, and 150 are preferably made of a conductive material, such as lead, tin, silver, copper, zinc, and indium, and alloys thereof. Properties for which the material of continuous electrode portion 70 may be selected include electrical conductivity, thermal conductivity, tensile strength, shear strength, toxicity, and melting point.
  • Bottom major surface 144 of second electrode portion 140 may have a curved concave surface portion 146 which is substantially aligned with first through via 120.
  • Electrode 70 may be of a unitary construction, meaning that there is no discernible interface within such construction between portions of the electrode. Alternatively, it is possible that interfaces between various portions of electrode 70 may be discernable, for example, as between first and third electrode portions 130 and 150 or second and third electrode portions 140 and 150. Regardless, electrode 70 is electrically continuous, meaning that the various portions of the electrode are sufficiently continuous so that the flow of electricity through the electrode between the portions is not significantly affected.
  • electrically continuous electrode 70 may include a discernible interface 152, which may be substantially planar, between first and third electrode portions 130 and 150. In one embodiment, discernible interface 152 is within 0.5 ⁇ of major top surface 112 of substrate 110.
  • Discernible interface 152 may also be within 0.25 ⁇ of major top surface 112 of substrate 110.
  • first through via 120 defines a volume between top and bottom openings 124 and 126 of the first through via, and third electrode portion 150 fills at least 50% of that volume. This percentage may be at least 70%, at least 80%, or at least 90%. This percentage may approach 100% where third electrode portion 150 completely fills first through via 120.
  • first electrode portion 130 covers at least 50%, by area, of top opening 124 of first through via 120. This percentage may be at least 70%, at least 80%, at least 90%, at least 95%, or the entire top opening 124 (equal to 100%), as shown in FIG. 1.
  • second electrode portion 140 covers at least 50%, by area, of bottom opening 126 of first through via 120. This percentage may be at least 70%, at least 80%, at least 90%, at least 95%, or the entire top opening 126 (equal to 100%), as shown in FIG. 1.
  • bottom major surface 144 of second electrode portion 140 further comprises two substantially flat surface portions 166 and 168 on each side of, and connected to, curved concave surface portion 146.
  • Curved concave surface portion 146 defines a maximum concave depth (d) that is equal to or greater than 1 ⁇ (thus d > 1 ⁇ ). Depth (d) may also be equal to or greater than 2, 5, or 10 ⁇ (d > 2 ⁇ , d > 5 ⁇ , or d > 10 ⁇ ).
  • third electrode portion 150 is disposed within and substantially fills first through via 120 and makes physical and electrical contact with first and second electrode portions 130 and 140.
  • third electrode portion 150 may be bounded on its sides by and make physical contact with at least one side wall 122 of first through via 120.
  • FIG. 2A A photo-micrograph of a cross-section of multilayer construction 100 taken through a plane substantially perpendicular to the major plane of substrate 110 (and the multilayer construction) is shown in FIG. 2A.
  • third electrode portion 150 and side wall 122 of first through via 120 define an elongated gap 123 therebetween extending along at least a portion of a length of the side wall.
  • Elongated gap 123 may also extend along an entire length of the side wall.
  • Third electrode portion 150 and side wall 122 of first through via 120 may also define a gap 125 therebetween extending from the side wall into the third electrode portion.
  • FIG. 2B A photo-micrograph of a cross-section of a multilayer construction according to another embodiment of the present invention is shown in FIG. 2B.
  • the multilayer construction described with respect to FIG. 1 may define a second through via 220 (similar to through via 120) extending between the top and bottom major surfaces of the substrate, with first electrode portion 130 covering the opening at the top of the second through via.
  • Electrode portion 250 may completely fill second through via 220 and makes physical and electrical contact with first and second electrode portions 130 and 140.
  • the bottom major surface of second electrode portion 140 comprises a second curved concave surface portion 246 aligned with second through via 220.
  • FIG. 3 shows a schematic cross-section of multilayer construction 100.
  • the bottom surface 144 of second electrode portion 140 defines first and second recesses 148 and 149. These recesses are co-axially aligned with and below third electrode portion 150, with the location of the recesses generally corresponding to the location of side wall 122 and the other side walls of the third electrode portion. If third electrode portion 150 is generally circular (as viewed from the bottom of multilayer structure 100), then the corresponding recess will also be generally circular. Because FIG. 3 shows multilayer construction 100 in cross-section, the generally circular peripheral recess appears as two recesses 148 and 149. This peripheral recess should be generally co-axial with curved concave surface portion 146.
  • side wall 122 is oriented at an angle A with respect to a plane substantially parallel to the multilayer construction.
  • angle A is preferably within the range of 25 to 90 degrees.
  • a light emitting semiconductor device (LESD) package 300 is shown in FIG. 4. It is comprised of multilayer construction 100, where first electrode portion 130 is patterned to form spaced apart electrically conductive first and second pads 310 and 320. First pad 310, but not second pad 320, is electrically connected to third electrode portion 150.
  • LESD 400 is mounted on a major top surface of multilayer construction 100. Electrically conductive first terminal 410 of LESD 400 is electrically connected to first pad 310, and electrically conductive second terminal 420 of the LESD is electrically connected to second pad 320.
  • a variety of materials may be used for the electrically conductive pads 310 and 320, including, but not limited to, copper, gold, nickel, and stainless steel. Properties for which the electrically conductive pads 310 and 320 may be selected include, but are not limited to, electrical conductivity and thermal conductivity.
  • Third electrode portion 150 may fill at least 70%, at least 80%, or at least 90%, and up to 100% of the volume of first through via 120. Third electrode portion 150 may make direct physical contact with side wall 122 of first through via 120. As similarly shown in FIG. 1, bottom major surface 144 of second electrode portion 140 further comprises two substantially flat surface portions 166 and 168 on each side of, and connected to, curved concave surface portion 146.
  • First through via 120 may have a maximum width (in the plane of the substrate) within the range of from about 40 to about 100 ⁇ .
  • First electrode portion 130 may have a thickness in the range from about 10 to about 30 ⁇ or within the narrower range from about 0.5 ⁇ to about 10 ⁇ .
  • the average thickness of substrate 110 is in a range from about 10 to about 50 ⁇ .
  • FIGS. 5A and 5B A method of fabricating a multilayer construction according to one embodiment of the present disclosure is shown in FIGS. 5A and 5B.
  • Step 1 a dielectric substrate 500 having opposing major top and bottom surfaces is provided.
  • Substrate 500 may be flexible or rigid, and the resultant multilayer construction may also be flexible or rigid.
  • a top electrode seed layer 509 may be deposited on the top major surface of dielectric substrate 500 and a bottom electrode seed layer 519 may be deposited on the bottom major surface of the substrate. This may be done by a variety of methods, including sputtering.
  • top electrode layer 510 is deposited on the top surface of dielectric substrate 500 (or onto top electrode seed layer 509 if present), and bottom electrode layer 520 is deposited on the bottom surface of the substrate (or onto bottom electrode seed layer 519 if present). Electrode layers 510 and 520 may be applied by known processes, such as electroplating.
  • top and bottom photoresist layers 515 and 525 are provided over electrode layers 510 and 520, respectively, on the sides opposite the substrate.
  • photoresist layers 515 and 525 are selectively exposed and then developed to remove the exposed portions of the photoresist and expose portions of top and bottom electrode layers 510 and 520, including exposing a first portion 521 of bottom electrode layer 520.
  • a protective liner 518 such as a laminate, is provided over the remaining portions of top photoresist layer 515.
  • first portion 521 of bottom electrode layer 520 (and bottom seed layer 519 if present) is removed to expose a portion 501 of the major bottom surface of substrate 500. This may be done by etching, such as copper etching if bottom electrode layer 520 comprises copper.
  • portion 502 of substrate 500 is removed in the area of exposed portion 501 of bottom electrode 520 thereby forming a through via 503 in substrate 500 extending between the opposing major top and bottom surfaces of the substrate.
  • Portion 502 of substrate 500 may be removed by known methods, such as chemical milling and/or strip resist.
  • Bottom photoresist layer 525 is also removed during this step.
  • protective liner 518 is removed.
  • Step 9 through via 503 is substantially filled with an electrically conductive material to form an electrically conductive connecting portion 504 between electrode layers 510 and 520.
  • additional conductive material may be deposited on both top and bottom electrode layers 510 and 520 to form additional electrode layers 530 and 540, respectively.
  • Top electrode layers 510 and 530 form a new thicker top electrode layer 550
  • bottom electrode layers 520 and 540 form a new thicker bottom electrode layer 560.
  • Thicker electrode layers 550 and 560 remain electrically connected by electrically conductive connecting portion 504 which extends between the two layers. All of these electrode layers and connecting portions may be made of the same conductive material, such as copper. This material may be applied by known methods, such as electroplating.
  • Step 10 the remaining portions of top photoresist layer 515 are removed. This may be done by known methods, such as by the use of strip resist.
  • Step 11 the thickness of thick bottom electrode layer 560 is reduced (and optionally the thickness of thick top electrode layer 550 is also reduced) by known methods, such as flash etching.
  • a protective liner 568 such as a laminate, is provided over the raised portions of top electrode layer 550. Also, a bottom photoresist layer 565 is provided over bottom electrode layer 560 on the side opposite substrate 500.
  • bottom photoresist layer 565 is selectively exposed and then developed to remove the exposed portions of the photoresist layer and expose portions of bottom electrode layer 560, including exposing a first portion 561 of the bottom electrode layer.
  • first portion 561 of bottom electrode layer 560 (and optional bottom seed layer 519) is removed to expose a portion 551 of the major bottom surface of substrate 500. This may be done by etching, such as copper etching if bottom electrode layer 560 comprises copper.
  • Step 15 protective liner 568 is removed and bottom photoresist layer 565 is also removed.
  • Step 16 a flash etch or similar process is applied to pattern the top electrode layer 550 to remove the remaining thin portions of the top electrode layer (and optional top seed layer 509) to form first and second spaced apart electrically conductive pads 601 and 602 such that the first, but not the second, pad is electrically connected to electrically conductive connecting portion 504.
  • the present invention also enables electroplating without undergoing a seed layer process (e.g., electro-less plating) and may allow for the creation of a larger volume of metal (e.g., copper) on vias for better thermal management for devices such as LESDs and RF MEMS filters. In some cases, reduces or eliminates the need to seed sidewalls of a via in order to fill the via with an electrically conductive material.
  • a seed layer process e.g., electro-less plating
  • metal e.g., copper
  • Embodiment 1 is a multilayer construction, comprising:
  • a dielectric substrate defining a first through via defining a top opening at a major top surface of the substrate and a bottom opening at an opposing major bottom surface of the substrate;
  • an electrically continuous electrode comprising:
  • a first electrode portion disposed on the major top surface of the substrate and substantially covering the top opening of the first through via
  • a second electrode portion having a major top surface and an opposing major bottom surface, the major top surface of the second electrode portion disposed on the major bottom surface of the substrate and substantially covering the bottom opening of the first through via;
  • a third electrode portion disposed in and substantially filling the first through via and making physical and electrical contact with the first and second electrode portions;
  • bottom major surface of the second electrode portion has a curved concave surface portion substantially aligned with the first through via.
  • Embodiment 2 is the multilayer construction of embodiment 1, wherein the electrically continuous electrode is a unitary construction.
  • Embodiment 3 is the multilayer construction of embodiment 1, wherein the electrically continuous electrode comprises a discernible interface between the first and third electrode portions.
  • Embodiment 4 is the multilayer construction of embodiment 3, wherein the discernible interface is substantially planar.
  • Embodiment 5 is the multilayer construction of embodiment 3, wherein the discernible interface is within 0.5 ⁇ of the major top surface of the substrate.
  • Embodiment 6 is the multilayer construction of embodiment 3, wherein the discernible interface is within 0.25 ⁇ of the major top surface of the substrate.
  • Embodiment 7 is the multilayer construction of embodiment 1, wherein the first through via defines a volume between the top and bottom openings of the first through via, the third electrode portion filling at least 50% of the volume.
  • Embodiment 8 is the multilayer construction of embodiment 7, the third electrode portion filling at least 70% of the volume.
  • Embodiment 9 is the multilayer construction of embodiment 7, the third electrode portion filling at least 80% of the volume.
  • Embodiment 10 is the multilayer construction of embodiment 7, the third electrode portion filling at least 90% of the volume .
  • Embodiment 11 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 50%, by area, of the top opening of the first through via.
  • Embodiment 12 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 70%, by area, of the top opening of the first through via.
  • Embodiment 13 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 80%, by area, of the top opening of the first through via.
  • Embodiment 14 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 90%, by area, of the top opening of the first through via.
  • Embodiment 15 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 95%, by area, of the top opening of the first through via.
  • Embodiment 16 is the multilayer construction of embodiment 1, wherein the first electrode portion covers, by area, the entire top opening of the first through via.
  • Embodiment is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 50%, by area, of the bottom opening of the first through via.
  • Embodiment 18 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 70%, by area, of the bottom opening of the first through via.
  • Embodiment 19 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 80%, by area, of the bottom opening of the first through via.
  • Embodiment 20 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 90%, by area, of the bottom opening of the first through via.
  • Embodiment 21 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 95%, by area, of the bottom opening of the first through via.
  • Embodiment 22 is the multilayer construction of embodiment 1, wherein the second electrode portion covers, by area, the entire bottom opening of the first through via.
  • Embodiment 23 is the multilayer construction of embodiment 1, wherein the bottom major surface of the second electrode portion further comprises substantially flat surface portions on each side of, and connected to, the curved concave surface portion.
  • Embodiment 24 is the multilayer construction of embodiment 1, wherein the curved concave surface portion defines a maximum concave depth (d), wherein d > 1 ⁇ .
  • Embodiment 25 is the multilayer construction of embodiment 24, wherein d > 2 ⁇ .
  • Embodiment 26 is the multilayer construction of embodiment 24, wherein d > 5 ⁇ .
  • Embodiment 27 is the multilayer construction of embodiment 24, wherein d > 10 ⁇ .
  • Embodiment 28 is the multilayer construction of embodiment 1, wherein the third electrode portion physically contacts a side wall of the first through via.
  • Embodiment 29 is the multilayer construction of embodiment 28, where the side wall defines an angle A with respect to a plane substantially parallel to the multilayer construction, where in 25° ⁇ A ⁇ 90°.
  • Embodiment 30 is the multilayer construction of embodiment 1, wherein in a cross-section of the third electrode portion in a plane substantially perpendicular to the multilayer construction, the third electrode portion and a side wall of the first through via define an elongated gap therebetween extending along at least a portion of a length of the side wall.
  • Embodiment 31 is the multilayer construction of embodiment 30, wherein the elongated gap extends substantially along an entire length of the side wall.
  • Embodiment 32 is the multilayer construction of embodiment 1, wherein in a cross-section of the third electrode portion in a plane substantially perpendicular to the multilayer construction, the third electrode portion and a side wall of the first through via define a gap therebetween extending from the side wall into the third electrode portion.
  • Embodiment 33 is the multilayer construction of embodiment 1, wherein in a cross-section of the second electrode portion and the first through via in a plane substantially perpendicular to the multilayer construction, the second electrode portion defines first and second recesses into the bottom surface of the second electrode portion.
  • Embodiment 34 is the multilayer construction of embodiment 1, wherein the substrate comprises one or more of polyimide (PI), thermoplastic PI, aromatic polyamide, liquid crystal polymer (LCP), polycarbonate (PC), polyether ether ketone, polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), polycyclic olefin, polysulfone (PSU), polyethylene naphthalate (PEN), epoxy resin, FR4, and thermoplastic dielectric material.
  • PI polyimide
  • LCP liquid crystal polymer
  • PC polycarbonate
  • PMMA polymethyl methacrylate
  • PSU polycyclic olefin
  • PSU polysulfone
  • PEN polyethylene naphthalate
  • epoxy resin FR4
  • thermoplastic dielectric material thermoplastic dielectric material
  • Embodiment 35 is the multilayer construction of embodiment 1, wherein the first, second and third electrode portions comprise copper.
  • Embodiment 36 is the multilayer construction of embodiment 1, wherein the dielectric substrate is flexible.
  • Embodiment 37 is the multilayer construction of embodiment 1, wherein the dielectric substrate is rigid.
  • Embodiment 38 is the multilayer construction of embodiment 1, wherein the multilayer construction is flexible.
  • Embodiment 39 is the multilayer construction of embodiment 1, wherein the multilayer construction is rigid.
  • Embodiment 40 is a light emitting semiconductor device (LESD) package, comprising:
  • the multilayer construction of claim 1 the first electrode portion patterned to form spaced apart electrically conductive first and second pads, the first, but not the second, pad electrically connected to the third electrode portion;
  • an LESD mounted on a major top surface of the multilayer construction, an electrically conductive first terminal of the LESD electrically connected to the first pad, and an electrically conductive second terminal of the LESD electrically connected to the second pad.
  • Embodiment 41 is the LESD package of embodiment 40, wherein the third electrode portion fills at least 80% of the first through via.
  • Embodiment 42 is the LESD package of embodiment 41, wherein the third electrode portion makes direct physical contact with a side wall of the first through via.
  • Embodiment 43 is the LESD package of embodiment 40, wherein the bottom major surface of the second electrode portion comprises substantially flat surface portions on each side of the curved concave surface portion.
  • Embodiment 44 is the LESD package of embodiment 40, wherein the dielectric substrate defines a second through via defining a second top opening at a major top surface of the substrate and a second bottom opening at an opposing major bottom surface of the substrate, wherein the first electrode portion covers the second through via, the third electrode portion completely fills the second through via and makes physical and electrical contact with the first electrode layer, and the bottom major surface of the second electrode portion comprises a second curved concave surface portion aligned with the second through via.
  • Embodiment 45 is a multilayer construction for mounting a light emitting semiconductor device (LESD), comprising:
  • a dielectric substrate defining a first hollow via extending between top and bottom major surfaces of the substrate, a maximum lateral dimension of the first hollow via being in a range from about 40 to about 100 ⁇ ;
  • a first electrode layer disposed on the top major surface of the substrate and having an average thickness in a range from about 10 to about 30 ⁇ , a first portion of the first electrode layer completely covering the first hollow via and having an electrically conductive top major surface exposed to air and a bottom major surface facing and directly exposed to the first hollow via.
  • Embodiment 46 is the multilayer construction of embodiment 45, wherein an average thickness of the substrate is in a range from about 10 to about 50 ⁇ .
  • Embodiment 47 is the multilayer construction of embodiment 45, wherein an average thickness of the first electrode layer is in a range from about 0.5 ⁇ to about 10 ⁇ .
  • Embodiment 48 is a method of fabricating a multilayer construction, comprising the steps of: providing a dielectric substrate having opposing major top and bottom surfaces;
  • first top and first bottom electrode layers depositing first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate
  • Embodiment 49 is the method of embodiment 48, wherein the step of depositing the first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate comprises first depositing top and bottom electrode seed layers on the respective major top and bottom surfaces of the substrate, and then electroplating the first top and first bottom electrode layers on the respective top and bottom electrode seed layers.
  • Embodiment 50 is the method of embodiment 48, wherein the dielectric substrate is flexible.
  • Embodiment 51 is the method of embodiment 48, wherein the dielectric substrate is rigid.
  • Embodiment 52 is the method of embodiment 48, wherein the multilayer construction is flexible.
  • Embodiment 53 is the method of embodiment 48, wherein the multilayer construction is rigid.
  • Embodiment 54 is the method of embodiment 48, further comprising the step of patterning the top electrode layer to form spaced apart electrically conductive first and second pads such that the first, but not the second, pad is electrically connected to the electrically conductive conducting portion.

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Abstract

A multilayer construction is disclosed that includes a dielectric substrate defining a through via having top and bottom openings at respective major top and bottom surfaces of the substrate. The multilayer construction also includes an electrically continuous electrode that includes first and second electrode portions disposed on the respective major top and bottom surfaces covering the respective top and bottom openings of the via, and a third electrode portion filling the via and making physical and electrical contact with the first and second electrode portions. The second electrode portion has a bottom major surface having a curved concave surface portion aligned with the through via.

Description

MULTILAYER CONSTRUCTION HAVING ELECTRICALLY CONTINUOUS CONDUCTOR
TECHNICAL FIELD
This disclosure relates generally to multilayer constructions having substrates and electrodes.
BACKGROUND
Printed circuit boards contain multiple layers of conductive metal sheets and non-conductive substrates. Electrically conductive material is provided within vias to electrically connect one or more of the conductive metal sheets which are separated by the substrate layers. Vias are conventionally manufactured by making holes (such as with a laser or by mechanical drilling) in the circuit board to create an electrical connection using an underlying seed layer (electro-less plating) and followed by an electrolytic plating process. As chip density increases, it becomes increasingly difficult to form holes sufficiently small for some circuit board and chip designs, and to adequately fill these holes with electrically conductive material. One example of a high density application is a light emitting semiconductor device (LESD).
SUMMARY
The present invention includes a multilayer construction which includes a dielectric substrate and an electrically continuous electrode. The dielectric substrate may define a first through via which defines a top opening at a major top surface of the substrate and a bottom opening at an opposing major bottom surface of the substrate. The electrically continuous electrode includes three electrode portions. The first electrode portion is disposed on the major top surface of the substrate and substantially covers the top opening of the first through via. The second electrode portion has a major top surface and an opposing major bottom surface, the major top surface of the second electrode portion disposed on the major bottom surface of the substrate and substantially covers the bottom opening of the first through via. The third electrode portion is disposed in and substantially fills the first through via and makes physical and electrical contact with the first and second electrode portions. The bottom major surface of the second electrode portion has a curved concave surface portion substantially aligned with the first through via.
In further aspects of the invention, the electrically continuous electrode may be a unitary construction. The electrically continuous electrode may include a discernible interface between the first and third electrode portions. The discernible interface may be substantially planar, and may be within 0.5 μπι or within 0.25 μπι of the major top surface of the substrate.
The first through via defines a volume between the top and bottom openings of the first through via. The third electrode portion may fill at least 50% of the volume, at least 70%, at least 80%, at least 90%, and up to 100% of the volume (entirely filling the volume).
The first electrode portion may cover at least 50%, by area, of the top opening of the first through via. That percentage may be at least 70%, at least 80%, at least 90%, at least 95%, and up to 100% (entirely covering the top opening). Similarly, the second electrode portion may cover at least 50%, by area, of the bottom opening of the first through via. That percentage may be at least 70%, at least 80%, at least 90%, at least 95%, and up to 100% (entirely covering the bottom opening).
The bottom major surface of the second electrode portion may also include substantially flat surface portions on each side of, and connected to, the curved concave surface portion. The curved concave surface portion may define a maximum concave depth (d), wherein d > 1 μπι. The depth (d) may also be > 2, 5, or 10 μπι.
The third electrode portion may physically contact a side wall of the first through via. When viewed as a cross-section in a plane substantially perpendicular to the major plane of the multilayer construction, the third electrode portion and the side wall may define an elongated gap therebetween extending along at least a portion of a length of the side wall, or along its entire length. Similarly, when viewed as a cross-section as described above, the third electrode portion and a side wall of the first through via may define a gap therebetween extending from the side wall into the third electrode portion. When viewed as the cross-section described above, the second electrode portion may define first and second recesses in the bottom surface of the second electrode portion.
With respect to the multilayer construction, the substrate may comprise one or more of polyimide (PI), thermoplastic PI, aromatic polyamide, liquid crystal polymer (LCP), polycarbonate (PC), polyether ether ketone, polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), polycyclic olefin, polysulfone (PSU), polyethylene naphthalate (PEN), epoxy resin, FR4, and thermoplastic dielectric material. The substrate may be dielectric and may be flexible or rigid. Similarly, the multilayer construction may also be flexible or rigid. The first, second and third electrode portions may comprise copper.
The present invention also includes a light emitting semiconductor device (LESD) package. This package includes the multilayer construction described above, with the first electrode portion being patterned to form spaced apart electrically conductive first and second pads. The first, but not the second, pad may be electrically connected to the third electrode portion. The package also includes an LESD mounted on a major top surface of the multilayer construction. An electrically conductive first terminal of the LESD electrically is connected to the first pad, and an electrically conductive second terminal of the LESD is electrically connected to the second pad.
With respect to this package, the third electrode portion may fill at least 80% of the first through via. The third electrode portion may make direct physical contact with a side wall of the first through via. And the bottom major surface of the second electrode portion may comprise substantially flat surface portions on each side of the curved concave surface portion.
With respect to this package, the dielectric substrate may define a second through via which defines a second top opening at a major top surface of the substrate and a second bottom opening at an opposing major bottom surface of the substrate. The first electrode portion may cover the second through via; the third electrode portion may completely fill the second via and make physical and electrical contact with the first electrode layer; and the bottom major surface of the second electrode portion may comprise a second curved concave surface portion aligned with the second through via.
The present invention includes a multilayer construction for mounting a light emitting semiconductor device (LESD) which includes a dielectric substrate and a first electrode layer. The dielectric substrate defines a first hollow via extending between the top and bottom major surfaces of the substrate, with the maximum lateral dimension of the first hollow via being in a range from about 40 to about 100 μπι. The first electrode layer is disposed on the top major surface of the substrate and has an average thickness in a range from about 10 to about 30 μπι, or in the narrower range of from about 0.5 μπι to about 10 μπι. A first portion of the first electrode layer may completely cover the first hollow via and have an electrically conductive top major surface exposed to air and a bottom major surface facing and directly exposed to the first hollow via. The substrate may have an average thickness in a range from about 10 to about 50 μπι.
The present invention also includes a method of fabricating a multilayer construction, including the following steps:
(1) providing a dielectric substrate having opposing major top and bottom surfaces;
(2) depositing first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate;
(3) removing a first portion of the first bottom electrode layer to expose a portion of the major bottom surface of the substrate;
(4) removing a portion of the substrate from the exposed portion of the major bottom surface of the substrate to expose a portion of the first top electrode and forming a via in the substrate extending between the opposing major top and bottom surfaces of the substrate;
(5) substantially filling the via with an electrically conductive material to form an electrically conductive connecting portion; and
(6) depositing second top and second bottom electrode layers on the respective first top and first bottom electrode layers to form, in combination, respective thicker top and bottom electrode layers, the electrically conductive connecting portion extending between and contacting the thicker top and bottom electrode layers.
The step of depositing the first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate may further include first depositing top and bottom electrode seed layers on the respective major top and bottom surfaces of the substrate, and then electroplating the first top and first bottom electrode layers on the respective top and bottom electrode seed layers.
The above method may also include the step of patterning the top electrode layer to form spaced apart electrically conductive first and second pads such that the first, but not the second, pad is electrically connected to the electrically conductive conducting portion.
The dielectric substrate and multilayer construction of the method above may be flexible or rigid.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic side cross-sectional view of a multilayer construction according to one embodiment of the present invention.
FIGS. 2A and 2B are photomicrographs of a cross-section of a multilayer construction according to one embodiment of the present invention.
FIG. 3 is a schematic side cross-sectional view of a multilayer construction according to one embodiment of the present invention.
FIG. 4 is a schematic side cross-sectional view of a light emitting semiconductor device (LESD) package according to one embodiment of the present invention.
FIGS. 5A and 5B are schematic side cross-sectional views of the steps used to fabricate a multilayer construction according to one embodiment of the present invention.
The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number. DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
A multilayer construction according to one embodiment of the present invention is shown in FIG. 1. Multilayer construction 100 includes dielectric substrate 110. Substrate 110 may attach, support, and electrically isolate certain components of multilayer construction 100. Substrate 110 has a major top surface 112 and an opposing major bottom surface 114. Substrate 110 may be comprised of one or more of polyimide (PI), thermoplastic PI, aromatic polyamide, liquid crystal polymer (LCP), polycarbonate (PC), polyether ether ketone, polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), polycyclic olefin, polysulfone (PSU), polyethylene naphthalate (PEN), epoxy resin, FR4, and
thermoplastic dielectric material. Substrate 110 may be flexible or rigid, as may multilayer construction 100. Properties for which substrate 110 may be selected include, but are not limited to, processability, flame retardancy, glass transition temperature, decomposition temperature, coefficient of thermal expansion, thermal conductivity, electrical resistance, dielectric constant, strength, flexibility, and moisture absorption.
As shown in FIG. 1, substrate 110 has a first through via 120 defining a top opening 124 at major top surface 112 of the substrate and a bottom opening 126 at opposing major bottom surface 114 of the substrate. An electrically continuous electrode 70 comprises three portions. First electrode portion 130 of continuous electrode 70 has a major top surface 132 and an opposing major bottom surface 134. Major bottom surface 134 of first electrode portion 130 is disposed on major top surface 112 of substrate 110 and substantially covers top opening 124 of first through via 120. Optionally, a top electrode seed layer 109 may be applied to major top surface 112 of substrate 110 to facilitate application of first electrode portion 130.
Second electrode portion 140 of continuous electrode 70 has a major top surface 142 and an opposing major bottom surface 144. Major top surface 142 of second electrode portion 140 is disposed on major bottom surface 114 of substrate 110 and substantially covers bottom opening 126 of first through via 120. Optionally, a bottom electrode seed layer 119 may be applied to major bottom surface 114 of substrate 110 to facilitate application of second electrode portion 140.
Third electrode portion 150 of continuous electrode portion 70 is disposed within and
substantially fills first through via 120 and makes physical and electrical contact with first and second electrode portions 130 and 140. First, second, and third electrode portions 130, 140, and 150 are preferably made of a conductive material, such as lead, tin, silver, copper, zinc, and indium, and alloys thereof. Properties for which the material of continuous electrode portion 70 may be selected include electrical conductivity, thermal conductivity, tensile strength, shear strength, toxicity, and melting point.
Bottom major surface 144 of second electrode portion 140 may have a curved concave surface portion 146 which is substantially aligned with first through via 120.
Electrically continuous electrode 70 may be of a unitary construction, meaning that there is no discernible interface within such construction between portions of the electrode. Alternatively, it is possible that interfaces between various portions of electrode 70 may be discernable, for example, as between first and third electrode portions 130 and 150 or second and third electrode portions 140 and 150. Regardless, electrode 70 is electrically continuous, meaning that the various portions of the electrode are sufficiently continuous so that the flow of electricity through the electrode between the portions is not significantly affected.
As shown in FIG. 1, electrically continuous electrode 70 may include a discernible interface 152, which may be substantially planar, between first and third electrode portions 130 and 150. In one embodiment, discernible interface 152 is within 0.5 μπι of major top surface 112 of substrate 110.
Discernible interface 152 may also be within 0.25 μπι of major top surface 112 of substrate 110.
In one embodiment, first through via 120 defines a volume between top and bottom openings 124 and 126 of the first through via, and third electrode portion 150 fills at least 50% of that volume. This percentage may be at least 70%, at least 80%, or at least 90%. This percentage may approach 100% where third electrode portion 150 completely fills first through via 120.
In one embodiment, first electrode portion 130 covers at least 50%, by area, of top opening 124 of first through via 120. This percentage may be at least 70%, at least 80%, at least 90%, at least 95%, or the entire top opening 124 (equal to 100%), as shown in FIG. 1. Similarly, in another embodiment, second electrode portion 140 covers at least 50%, by area, of bottom opening 126 of first through via 120. This percentage may be at least 70%, at least 80%, at least 90%, at least 95%, or the entire top opening 126 (equal to 100%), as shown in FIG. 1.
As shown in FIG. 1, bottom major surface 144 of second electrode portion 140 further comprises two substantially flat surface portions 166 and 168 on each side of, and connected to, curved concave surface portion 146. Curved concave surface portion 146 defines a maximum concave depth (d) that is equal to or greater than 1 μπι (thus d > 1 μπι). Depth (d) may also be equal to or greater than 2, 5, or 10 μπι (d > 2 μηι, d > 5 μηι, or d > 10 μπι). As discussed above, third electrode portion 150 is disposed within and substantially fills first through via 120 and makes physical and electrical contact with first and second electrode portions 130 and 140. In addition, third electrode portion 150 may be bounded on its sides by and make physical contact with at least one side wall 122 of first through via 120.
A photo-micrograph of a cross-section of multilayer construction 100 taken through a plane substantially perpendicular to the major plane of substrate 110 (and the multilayer construction) is shown in FIG. 2A. A shown there, third electrode portion 150 and side wall 122 of first through via 120 define an elongated gap 123 therebetween extending along at least a portion of a length of the side wall.
Elongated gap 123 may also extend along an entire length of the side wall. Third electrode portion 150 and side wall 122 of first through via 120 may also define a gap 125 therebetween extending from the side wall into the third electrode portion.
A photo-micrograph of a cross-section of a multilayer construction according to another embodiment of the present invention is shown in FIG. 2B. As shown there, the multilayer construction described with respect to FIG. 1 may define a second through via 220 (similar to through via 120) extending between the top and bottom major surfaces of the substrate, with first electrode portion 130 covering the opening at the top of the second through via. Electrode portion 250 may completely fill second through via 220 and makes physical and electrical contact with first and second electrode portions 130 and 140. The bottom major surface of second electrode portion 140 comprises a second curved concave surface portion 246 aligned with second through via 220.
FIG. 3 shows a schematic cross-section of multilayer construction 100. In one embodiment, the bottom surface 144 of second electrode portion 140 defines first and second recesses 148 and 149. These recesses are co-axially aligned with and below third electrode portion 150, with the location of the recesses generally corresponding to the location of side wall 122 and the other side walls of the third electrode portion. If third electrode portion 150 is generally circular (as viewed from the bottom of multilayer structure 100), then the corresponding recess will also be generally circular. Because FIG. 3 shows multilayer construction 100 in cross-section, the generally circular peripheral recess appears as two recesses 148 and 149. This peripheral recess should be generally co-axial with curved concave surface portion 146.
As further illustrated in FIG. 3, side wall 122 is oriented at an angle A with respect to a plane substantially parallel to the multilayer construction. In one embodiment, angle A is preferably within the range of 25 to 90 degrees.
A light emitting semiconductor device (LESD) package 300 according to one embodiment is shown in FIG. 4. It is comprised of multilayer construction 100, where first electrode portion 130 is patterned to form spaced apart electrically conductive first and second pads 310 and 320. First pad 310, but not second pad 320, is electrically connected to third electrode portion 150. LESD 400 is mounted on a major top surface of multilayer construction 100. Electrically conductive first terminal 410 of LESD 400 is electrically connected to first pad 310, and electrically conductive second terminal 420 of the LESD is electrically connected to second pad 320. A variety of materials may be used for the electrically conductive pads 310 and 320, including, but not limited to, copper, gold, nickel, and stainless steel. Properties for which the electrically conductive pads 310 and 320 may be selected include, but are not limited to, electrical conductivity and thermal conductivity.
Third electrode portion 150 may fill at least 70%, at least 80%, or at least 90%, and up to 100% of the volume of first through via 120. Third electrode portion 150 may make direct physical contact with side wall 122 of first through via 120. As similarly shown in FIG. 1, bottom major surface 144 of second electrode portion 140 further comprises two substantially flat surface portions 166 and 168 on each side of, and connected to, curved concave surface portion 146.
First through via 120 may have a maximum width (in the plane of the substrate) within the range of from about 40 to about 100 μπι. First electrode portion 130 may have a thickness in the range from about 10 to about 30 μπι or within the narrower range from about 0.5 μπι to about 10 μπι. The average thickness of substrate 110 is in a range from about 10 to about 50 μπι.
A method of fabricating a multilayer construction according to one embodiment of the present disclosure is shown in FIGS. 5A and 5B. With reference to FIG. 5A, in Step 1, a dielectric substrate 500 having opposing major top and bottom surfaces is provided. Substrate 500 may be flexible or rigid, and the resultant multilayer construction may also be flexible or rigid. Optionally, a top electrode seed layer 509 may be deposited on the top major surface of dielectric substrate 500 and a bottom electrode seed layer 519 may be deposited on the bottom major surface of the substrate. This may be done by a variety of methods, including sputtering.
In Step 2, top electrode layer 510 is deposited on the top surface of dielectric substrate 500 (or onto top electrode seed layer 509 if present), and bottom electrode layer 520 is deposited on the bottom surface of the substrate (or onto bottom electrode seed layer 519 if present). Electrode layers 510 and 520 may be applied by known processes, such as electroplating.
In Step 3, top and bottom photoresist layers 515 and 525 are provided over electrode layers 510 and 520, respectively, on the sides opposite the substrate.
In Step 4, photoresist layers 515 and 525 are selectively exposed and then developed to remove the exposed portions of the photoresist and expose portions of top and bottom electrode layers 510 and 520, including exposing a first portion 521 of bottom electrode layer 520.
In Step 5, a protective liner 518, such as a laminate, is provided over the remaining portions of top photoresist layer 515.
In Step 6, first portion 521 of bottom electrode layer 520 (and bottom seed layer 519 if present) is removed to expose a portion 501 of the major bottom surface of substrate 500. This may be done by etching, such as copper etching if bottom electrode layer 520 comprises copper.
In Step 7, portion 502 of substrate 500 is removed in the area of exposed portion 501 of bottom electrode 520 thereby forming a through via 503 in substrate 500 extending between the opposing major top and bottom surfaces of the substrate. Portion 502 of substrate 500 may be removed by known methods, such as chemical milling and/or strip resist. Bottom photoresist layer 525 is also removed during this step. In Step 8, protective liner 518 is removed.
In Step 9, through via 503 is substantially filled with an electrically conductive material to form an electrically conductive connecting portion 504 between electrode layers 510 and 520. During this step, additional conductive material may be deposited on both top and bottom electrode layers 510 and 520 to form additional electrode layers 530 and 540, respectively. Top electrode layers 510 and 530 form a new thicker top electrode layer 550, and bottom electrode layers 520 and 540 form a new thicker bottom electrode layer 560. Thicker electrode layers 550 and 560 remain electrically connected by electrically conductive connecting portion 504 which extends between the two layers. All of these electrode layers and connecting portions may be made of the same conductive material, such as copper. This material may be applied by known methods, such as electroplating.
With reference to FIG. 5B, in Step 10, the remaining portions of top photoresist layer 515 are removed. This may be done by known methods, such as by the use of strip resist.
In Step 11, the thickness of thick bottom electrode layer 560 is reduced (and optionally the thickness of thick top electrode layer 550 is also reduced) by known methods, such as flash etching.
In Step 12, a protective liner 568, such as a laminate, is provided over the raised portions of top electrode layer 550. Also, a bottom photoresist layer 565 is provided over bottom electrode layer 560 on the side opposite substrate 500.
In Step 13, bottom photoresist layer 565 is selectively exposed and then developed to remove the exposed portions of the photoresist layer and expose portions of bottom electrode layer 560, including exposing a first portion 561 of the bottom electrode layer.
In Step 14, first portion 561 of bottom electrode layer 560 (and optional bottom seed layer 519) is removed to expose a portion 551 of the major bottom surface of substrate 500. This may be done by etching, such as copper etching if bottom electrode layer 560 comprises copper.
In Step 15, protective liner 568 is removed and bottom photoresist layer 565 is also removed. In Step 16, a flash etch or similar process is applied to pattern the top electrode layer 550 to remove the remaining thin portions of the top electrode layer (and optional top seed layer 509) to form first and second spaced apart electrically conductive pads 601 and 602 such that the first, but not the second, pad is electrically connected to electrically conductive connecting portion 504.
The present invention also enables electroplating without undergoing a seed layer process (e.g., electro-less plating) and may allow for the creation of a larger volume of metal (e.g., copper) on vias for better thermal management for devices such as LESDs and RF MEMS filters. In some cases, reduces or eliminates the need to seed sidewalls of a via in order to fill the via with an electrically conductive material.
Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein. The use of numerical ranges by endpoints includes all numbers within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.
The following are embodiments of the present disclosure:
Embodiment 1 is a multilayer construction, comprising:
a dielectric substrate defining a first through via defining a top opening at a major top surface of the substrate and a bottom opening at an opposing major bottom surface of the substrate; and
an electrically continuous electrode comprising:
a first electrode portion disposed on the major top surface of the substrate and substantially covering the top opening of the first through via;
a second electrode portion having a major top surface and an opposing major bottom surface, the major top surface of the second electrode portion disposed on the major bottom surface of the substrate and substantially covering the bottom opening of the first through via; and
a third electrode portion disposed in and substantially filling the first through via and making physical and electrical contact with the first and second electrode portions;
wherein the bottom major surface of the second electrode portion has a curved concave surface portion substantially aligned with the first through via.
Embodiment 2 is the multilayer construction of embodiment 1, wherein the electrically continuous electrode is a unitary construction.
Embodiment 3 is the multilayer construction of embodiment 1, wherein the electrically continuous electrode comprises a discernible interface between the first and third electrode portions.
Embodiment 4 is the multilayer construction of embodiment 3, wherein the discernible interface is substantially planar.
Embodiment 5 is the multilayer construction of embodiment 3, wherein the discernible interface is within 0.5 μπι of the major top surface of the substrate.
Embodiment 6 is the multilayer construction of embodiment 3, wherein the discernible interface is within 0.25 μπι of the major top surface of the substrate.
Embodiment 7 is the multilayer construction of embodiment 1, wherein the first through via defines a volume between the top and bottom openings of the first through via, the third electrode portion filling at least 50% of the volume.
Embodiment 8 is the multilayer construction of embodiment 7, the third electrode portion filling at least 70% of the volume.
Embodiment 9 is the multilayer construction of embodiment 7, the third electrode portion filling at least 80% of the volume.
Embodiment 10 is the multilayer construction of embodiment 7, the third electrode portion filling at least 90% of the volume .
Embodiment 11 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 50%, by area, of the top opening of the first through via. Embodiment 12 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 70%, by area, of the top opening of the first through via.
Embodiment 13 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 80%, by area, of the top opening of the first through via.
Embodiment 14 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 90%, by area, of the top opening of the first through via.
Embodiment 15 is the multilayer construction of embodiment 1, wherein the first electrode portion covers at least 95%, by area, of the top opening of the first through via.
Embodiment 16 is the multilayer construction of embodiment 1, wherein the first electrode portion covers, by area, the entire top opening of the first through via.
Embodiment is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 50%, by area, of the bottom opening of the first through via.
Embodiment 18 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 70%, by area, of the bottom opening of the first through via.
Embodiment 19 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 80%, by area, of the bottom opening of the first through via.
Embodiment 20 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 90%, by area, of the bottom opening of the first through via.
Embodiment 21 is the multilayer construction of embodiment 1, wherein the second electrode portion covers at least 95%, by area, of the bottom opening of the first through via.
Embodiment 22 is the multilayer construction of embodiment 1, wherein the second electrode portion covers, by area, the entire bottom opening of the first through via.
Embodiment 23 is the multilayer construction of embodiment 1, wherein the bottom major surface of the second electrode portion further comprises substantially flat surface portions on each side of, and connected to, the curved concave surface portion.
Embodiment 24 is the multilayer construction of embodiment 1, wherein the curved concave surface portion defines a maximum concave depth (d), wherein d > 1 μπι.
Embodiment 25 is the multilayer construction of embodiment 24, wherein d > 2 μπι.
Embodiment 26 is the multilayer construction of embodiment 24, wherein d > 5 μπι.
Embodiment 27 is the multilayer construction of embodiment 24, wherein d > 10 μπι.
Embodiment 28 is the multilayer construction of embodiment 1, wherein the third electrode portion physically contacts a side wall of the first through via.
Embodiment 29 is the multilayer construction of embodiment 28, where the side wall defines an angle A with respect to a plane substantially parallel to the multilayer construction, where in 25° < A < 90°.
Embodiment 30 is the multilayer construction of embodiment 1, wherein in a cross-section of the third electrode portion in a plane substantially perpendicular to the multilayer construction, the third electrode portion and a side wall of the first through via define an elongated gap therebetween extending along at least a portion of a length of the side wall.
Embodiment 31 is the multilayer construction of embodiment 30, wherein the elongated gap extends substantially along an entire length of the side wall.
Embodiment 32 is the multilayer construction of embodiment 1, wherein in a cross-section of the third electrode portion in a plane substantially perpendicular to the multilayer construction, the third electrode portion and a side wall of the first through via define a gap therebetween extending from the side wall into the third electrode portion.
Embodiment 33 is the multilayer construction of embodiment 1, wherein in a cross-section of the second electrode portion and the first through via in a plane substantially perpendicular to the multilayer construction, the second electrode portion defines first and second recesses into the bottom surface of the second electrode portion.
Embodiment 34 is the multilayer construction of embodiment 1, wherein the substrate comprises one or more of polyimide (PI), thermoplastic PI, aromatic polyamide, liquid crystal polymer (LCP), polycarbonate (PC), polyether ether ketone, polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), polycyclic olefin, polysulfone (PSU), polyethylene naphthalate (PEN), epoxy resin, FR4, and thermoplastic dielectric material.
Embodiment 35 is the multilayer construction of embodiment 1, wherein the first, second and third electrode portions comprise copper.
Embodiment 36 is the multilayer construction of embodiment 1, wherein the dielectric substrate is flexible.
Embodiment 37 is the multilayer construction of embodiment 1, wherein the dielectric substrate is rigid.
Embodiment 38 is the multilayer construction of embodiment 1, wherein the multilayer construction is flexible.
Embodiment 39 is the multilayer construction of embodiment 1, wherein the multilayer construction is rigid.
Embodiment 40 is a light emitting semiconductor device (LESD) package, comprising:
the multilayer construction of claim 1, the first electrode portion patterned to form spaced apart electrically conductive first and second pads, the first, but not the second, pad electrically connected to the third electrode portion; and
an LESD mounted on a major top surface of the multilayer construction, an electrically conductive first terminal of the LESD electrically connected to the first pad, and an electrically conductive second terminal of the LESD electrically connected to the second pad.
Embodiment 41 is the LESD package of embodiment 40, wherein the third electrode portion fills at least 80% of the first through via.
Embodiment 42 is the LESD package of embodiment 41, wherein the third electrode portion makes direct physical contact with a side wall of the first through via. Embodiment 43 is the LESD package of embodiment 40, wherein the bottom major surface of the second electrode portion comprises substantially flat surface portions on each side of the curved concave surface portion.
Embodiment 44 is the LESD package of embodiment 40, wherein the dielectric substrate defines a second through via defining a second top opening at a major top surface of the substrate and a second bottom opening at an opposing major bottom surface of the substrate, wherein the first electrode portion covers the second through via, the third electrode portion completely fills the second through via and makes physical and electrical contact with the first electrode layer, and the bottom major surface of the second electrode portion comprises a second curved concave surface portion aligned with the second through via.
Embodiment 45 is a multilayer construction for mounting a light emitting semiconductor device (LESD), comprising:
a dielectric substrate defining a first hollow via extending between top and bottom major surfaces of the substrate, a maximum lateral dimension of the first hollow via being in a range from about 40 to about 100 μπι; and
a first electrode layer disposed on the top major surface of the substrate and having an average thickness in a range from about 10 to about 30 μπι, a first portion of the first electrode layer completely covering the first hollow via and having an electrically conductive top major surface exposed to air and a bottom major surface facing and directly exposed to the first hollow via.
Embodiment 46 is the multilayer construction of embodiment 45, wherein an average thickness of the substrate is in a range from about 10 to about 50 μπι.
Embodiment 47 is the multilayer construction of embodiment 45, wherein an average thickness of the first electrode layer is in a range from about 0.5 μπι to about 10 μπι.
Embodiment 48 is a method of fabricating a multilayer construction, comprising the steps of: providing a dielectric substrate having opposing major top and bottom surfaces;
depositing first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate;
removing a first portion of the first bottom electrode layer to expose an exposed portion of the major bottom surface of the substrate;
removing a portion of the substrate from the exposed portion of the major bottom surface of the substrate to expose an exposed portion of the first top electrode and forming a via in the substrate extending between the opposing major top and bottom surfaces of the substrate;
substantially filling the via with an electrically conductive material to form an electrically conductive connecting portion; and
depositing second top and second bottom electrode layers on the respective first top and first bottom electrode layers to form, in combination, respective thicker top and bottom electrode layers, the electrically conductive connecting portion extending between and contacting the thicker top and bottom electrode layers. Embodiment 49 is the method of embodiment 48, wherein the step of depositing the first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate comprises first depositing top and bottom electrode seed layers on the respective major top and bottom surfaces of the substrate, and then electroplating the first top and first bottom electrode layers on the respective top and bottom electrode seed layers.
Embodiment 50 is the method of embodiment 48, wherein the dielectric substrate is flexible.
Embodiment 51 is the method of embodiment 48, wherein the dielectric substrate is rigid.
Embodiment 52 is the method of embodiment 48, wherein the multilayer construction is flexible.
Embodiment 53 is the method of embodiment 48, wherein the multilayer construction is rigid.
Embodiment 54 is the method of embodiment 48, further comprising the step of patterning the top electrode layer to form spaced apart electrically conductive first and second pads such that the first, but not the second, pad is electrically connected to the electrically conductive conducting portion.
Various modifications and alterations of this invention will be apparent to those skilled in the art and it should be understood that this scope of this disclosure is not limited to the illustrative embodiments set forth herein. For example, the reader should assume that features of one disclosed embodiment may also be applied to all other disclosed embodiments unless otherwise indicated.

Claims

CLAIMS:
1. A multilayer construction, comprising:
a dielectric substrate defining a first through via defining a top opening at a major top surface of the substrate and a bottom opening at an opposing major bottom surface of the substrate; and
an electrically continuous electrode comprising:
a first electrode portion disposed on the major top surface of the substrate and substantially covering the top opening of the first through via;
a second electrode portion having a major top surface and an opposing major bottom surface, the major top surface of the second electrode portion disposed on the major bottom surface of the substrate and substantially covering the bottom opening of the first through via; and
a third electrode portion disposed in and substantially filling the first through via and making physical and electrical contact with the first and second electrode portions;
wherein the bottom major surface of the second electrode portion has a curved concave surface portion substantially aligned with the first through via.
2. The multilayer construction of claim 1, wherein the electrically continuous electrode comprises a discernible interface between the first and third electrode portions, and wherein the discernible interface is within 0.5 μπι of the major top surface of the substrate.
3. The multilayer construction of claim 1, wherein the first electrode portion covers, by area, the entire top opening of the first through via, and wherein the second electrode portion covers, by area, the entire bottom opening of the first through via.
4. The multilayer construction of claim 1, wherein the bottom major surface of the second portion further comprises substantially flat surface portions on each side of, and connected to, the curved concave surface portion, and wherein the curved concave surface portion defines a maximum concave depth (d), wherein d > 1 μπι.
5. A light emitting semiconductor device (LESD) package, comprising:
the multilayer construction of claim 1, the first electrode portion patterned to form spaced apart electrically conductive first and second pads, the first, but not the second, pad electrically connected to the third electrode portion; and
an LESD mounted on a major top surface of the multilayer construction, an electrically conductive first terminal of the LESD electrically connected to the first pad, and an electrically conductive second terminal of the LESD electrically connected to the second pad.
6. The LESD package of claim 5, wherein the third electrode portion fills at least 80% of the first through via, wherein the third electrode portion makes direct physical contact with a side wall of the first through via, and wherein the bottom major surface of the second electrode portion comprises substantially flat surface portions on each side of the curved concave surface portion.
7. The LESD package of claim 5, wherein the dielectric substrate defines a second through via defining a second top opening at a major top surface of the substrate and a second bottom opening at an opposing major bottom surface of the substrate, wherein the first electrode portion covers the second through via, the third electrode portion completely fills the second through via and makes physical and electrical contact with the first electrode layer, and the bottom major surface of the second electrode portion comprises a second curved concave surface portion aligned with the second through via.
8. A multilayer construction for mounting a light emitting semiconductor device (LESD), comprising: a dielectric substrate defining a first hollow via extending between top and bottom major surfaces of the substrate, a maximum lateral dimension of the first hollow via being in a range from about 40 to about 100 μπι; and
a first electrode layer disposed on the top major surface of the substrate and having an average thickness in a range from about 10 to about 30 μπι, a first portion of the first electrode layer completely covering the first hollow via and having an electrically conductive top major surface exposed to air and a bottom major surface facing and directly exposed to the first hollow via.
9. A method of fabricating a multilayer construction, comprising the steps of:
providing a dielectric substrate having opposing major top and bottom surfaces;
depositing first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate;
removing a first portion of the first bottom electrode layer to expose an exposed portion of the major bottom surface of the substrate;
removing a portion of the substrate from the exposed portion of the major bottom surface of the substrate to expose an exposed portion of the first top electrode and forming a via in the substrate extending between the opposing major top and bottom surfaces of the substrate;
substantially filling the via with an electrically conductive material to form an electrically conductive connecting portion; and
depositing second top and second bottom electrode layers on the respective first top and first bottom electrode layers to form, in combination, respective thicker top and bottom electrode layers, the electrically conductive connecting portion extending between and contacting the thicker top and bottom electrode layers.
10. The method of claim 9, wherein the step of depositing the first top and first bottom electrode layers on the respective major top and bottom surfaces of the substrate comprises first depositing top and bottom electrode seed layers on the respective major top and bottom surfaces of the substrate, and then electroplating the first top and first bottom electrode layers on the respective top and bottom electrode seed layers.
PCT/IB2018/053043 2017-05-10 2018-05-02 Multilayer construction having electrically continuous conductor Ceased WO2018207055A1 (en)

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