WO2018200482A1

WO2018200482A1 - Track and hold circuit

Info

Publication number: WO2018200482A1
Application number: PCT/US2018/029084
Authority: WO
Inventors: Susan Marya Schober; Robert C. Schober
Original assignee: Circuit Seed LLC
Current assignee: Circuit Seed LLC
Priority date: 2017-04-24
Filing date: 2018-04-24
Publication date: 2018-11-01
Anticipated expiration: 2019-10-24
Also published as: WO2018200482A4

Abstract

The present invention relates to an improvement to a track and hold circuit. A jitter-free track and hold function independent of signal amplitude is achieved by a circuit which fixes the sample voltage to the charge on a flying sampling capacitor and sets maintains that charge prior to isolation through applying application of the sample voltage to a utilization circuit. This may be done by adding an extra switch to the standard track and hold circuit and operating the switches in a timed sequence manner to provide the sample aperture based on the charge on the flying sampling capacitor common to the circuit.

Description

TITLE OF THE INVENTION

[0001] TRACK AND HOLD CIRCUIT

CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62/489,072 filed on April 24, 2017, the contents of which are incorporated herein by reference in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0003] N/A

NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT

[0004] N/A

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

[0005] This invention is related to a track and hold circuit, which is based on the realization that a jitter free track and hold function could be achieved by a circuit which fixes the sample voltage to the charge on a capacitor and sets that charge prior to applying the sample voltage to a utilization circuit.

[0006] The present invention is further based on the realization that a jitter free track and hold function could be achieved by a circuit that fixes its sampled input voltage as charge on a flying capacitor and maintains this charge while applying the sample voltage to a utilization circuit. Furthermore, using symmetrical transmission gate switches to initially disconnect and lastly reconnect the flying capacitor to a common mode analog ground, ideally located near half of the switch control logic power supply voltage, provides a precise sample aperture time which is independent of tracking voltage and without net switch charge injection onto the flying capacitor. Lastly, referencing this common mode flying capacitor terminal back to the same common mode analog ground during utilization nullifies parasitic alteration of the stored charge. Also, multiple capacitors may be employed for integer arithmetic in circuits such as ADCs and DACs. Replica differential configurations tend to cancel out leakage for long storage times with smaller capacitors and provide increased noise immunity. DESCRIPTION OF RELATED ART

[0007] In sampled data systems, it is essential to capture analog voltages at precisely defined instants in time and independent of voltage level and waveform shape (frequency content). Digital or analog processing of the stream sampled values is essential for computationally extracting information. As an example, if the goal is to quadratically separate composite signals as in QAM RF transmissions and the signal that has in band jitter, one quadrature signal will spill over into its quadrature component.

[0008] While a well-defined sampling clock can be logically operated within jitter specifications necessary for their host digital system, the analog switch turn-off time is a function of the analog voltage being sampled. This is because the sampling switch turns off at a threshold voltage difference between the analog voltage in the switch channelto the switch gate voltage, causing sampling switch opening at one time for higher analog voltages and a different time for lower analog voltages. The threshold difference between the finite slope of the turn-off switch control logic voltage signal and the analog voltage being sampled occurs at significantly different points in time.

[0009] An accuracy of a track and hold analog input signal capture circuit is limited by a combination of several error sources:

• Variation of the exact time that a sample clock edge cuts off its tracked input voltage signal in order to correctly capture the precise analog sampled voltage, in that the MOSFET switch turn-off depends on the threshold voltage difference between the logic signal and the analog value, causing the sampling cutoff time to be altered by the analog voltage level - the sampled voltage must be at a consistently exact time independent of the sampled analog voltage's magnitude;

• The switch turn-off causes charge transfer from logic control signals onto the holding capacitor(s) - the switch must not transfer a net charge from the logic signal into the sampled analog signal, causing a significant error;

• Holding capacitor leakage - causing sampled voltages to drift away from their exact sampled voltage value during the hold time window; • Logic and power supply noise coupling onto the holding capacitor through parasitic capacitance to unwanted signals - outside signals are capacitively coupled onto the holding capacitor's stored voltage;

• Holding capacitor parasitic capacitance when operated as a flying capacitor(s) in rearranging captured analog signal values - holding capacitor charge is transferred between the holding capacitor and the surrounding parasitic capacitance when the capacitors are rearranged for their use;

• Reconnect charge transfer from logic control signals back onto the holding capacitor(s) when the capacitor(s) are rearranged as flying capacitor(s) to manipulate the sampled value(s) - the MOSFET switches used to reconnect the holding capacitor(s) transfer charge from the logic control signals to the holding capacitor altering the held analog voltage.

[0010] There were several attempts made previously to address such problems. For example,

• "Bottom plate sampling" disconnects ground from one side of the sample & hold capacitor using a single MOSFET switch, in order to reference the logic turnoff threshold to a consistent voltage independent of analog signal voltage at switch turnoff;

• Adding an additional MOSFET switch as a cancellation capacitor, with a compliment logic signal at its gate, to reverse-couple the charge transfer error produced by the sample switch at the sample-clock transition time;

• Use large capacitors to mitigate leakage errors;

• Use larger capacitors to diminish charge coupling errors, but larger capacitors have proportionally larger parasitic coupling capacitance; and/or

• Use of larger capacitors to diminishes charge transfer errors from a ratio to switch charge errors over sampling capacitor stored charge that establishes the voltage error across the sampling capacitor(s).

[0011] Prior solution has a several limitations and/or shortcomings as listed below:

• Larger capacitors take up an excessive chip area;

• Lager capacitor limit speed;

• Power is increased from driving larger capacitors; • Special analog IC process extensions are required for high-K Metal -to-Metal capacitors required for higher value capacitance;

• IC process extensions are not available in nanoscale nodes for a couple of IC process generations (about 3 to 4 years) in time to their availability; and/or

• Yields are lower.

[0012] Accordingly, there exists a long felt needs for an improvement for a track and hold circuit.

BRIEF SUMMARY OF THE INVENTION

[0013] The present invention relates to a track and hold circuit.

[0014] An object of the present invention is to provide an improvement to a track and hold circuit.

[0015] Another object of the present invention is to provide a jitter-free track and hold function.

[0016] According to one aspect of the present invention, it provides a circuit which fixes the sample voltage to the charge on a capacitor and isolates that charge prior and during the application of the sample voltage to a utilization circuit.

[0017] According to another aspect of the present invention, it provides an improvement to a standard or existing track and hold circuit by adding an extra switch to the standard track and hold circuit and operating the switches in a timed sequence manner to provide the sample aperture based on the charge on the capacitor common to the circuit.

[0018] According to yet another aspect of the present invention, it provides a track and hold circuit having an input terminal, comprising: a first switch; a second switch; a floating capacitor having a first side and a second side, the first side of the capacitor is connected to the input terminal via the first switch; the second side of said capacitor is connected via the second switch to a common mode voltage source; and the first side of the capacitor is further connected to a utilization circuit; a controller connected to the first and second switches in a manner to supply a sample voltage to the utilization circuit by sequencing the closure of the first and second switches, wherein, at a first sequence, the first and second switches are closed such that an input voltage at the input terminal is tracked across the capacitor; at a second sequence, the first switch is closed and the second switch is opened, such that a charge on the capacitor is isolated; at a third sequence, both the first and second switches are opened, such that the input voltage at the input terminal is disconnected from the capacitor; at a fourth sequence, the first switch is opened and a utilization switch is closed, such that the voltage on the capacitor is supplied as the sample voltage to the utilization circuit for processing.

[0019] According to further aspect of the present invention, it provides a differential track and hold circuit having positive and negative input terminals, comprising: a first switch; a second switch; a first flying capacitor having a first side and a second side, the first side of the first flying capacitor is connected to the positive input terminal via the first switch; the second side of the first flying capacitor is connected via the second switch to a common mode voltage source; and the first side of the first flying capacitor is further connected to a utilization circuit; a third switch; a fourth switch; a second flying capacitor having a first side and a second side, the first side of the second flying capacitor is connected to the negative input terminal via the first switch; the second side of the second flying capacitor is connected via the second switch to the common mode voltage source; and the first side of the second flying capacitor is further connected to the utilization circuit; a controller connected to the first, second, third and fourth switches in a manner to supply a sample voltage to the utilization circuit by sequencing the closure of the first, second, third and fourth switches, wherein, at a first sequence, the first, second, third and fourth switches are closed such that input voltages at the positive and negative input terminals are tracked across the first and second flying capacitors; at a second sequence, the first and third switches are closed and the utilization switches are opened, such that charges on the first and second flying capacitors are isolated; at a third sequence, the first, second, third and fourth switches are opened, such that the input voltages at the positive and negative input terminals are disconnected from the first and second flying capacitors; at a fourth sequence, the first and third switches are opened and the utilization switches are closed, such that the voltages on the first and second flying capacitors are supplied as the sample voltage to the utilization circuit for processing.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0020] Fig. 1 is a schematic circuit diagram of a prior art track and hold circuit;

[0021] Fig. 2A is a diagram showing top plate sampling analog and logic waveform relationship of the circuit shown in Fig. 1;

[0022] Fig. 2B is a diagram of the signal and logic waveforms of the circuit of Fig. 1; [0023] Fig. 3A is a circuit diagram of a tack and hold circuit according to the principles of this invention;

[0024] Fig. 3B is a diagram of sample aperture time for Vcm based bottom plate sampling of the circuit shown in Fig. 3A;

[0025] Fig. 4 is a diagram of the signal and logic waveforms of the circuit of Fig. 3A;

[0026] Fig. 5 is a diagram of a differential track and hold circuit using two replica circuits of the type shown in Fig. 3A;

[0027] Fig. 6 is a timing diagram of the signal and logic waveforms of the circuit of Fig. 5;

[0028] Fig. 7 is a switch stage description of illustrative embodiments of Figs. 3A and 5;

[0029] Fig. 8 is a schematic circuit diagram of a control logic circuit; and

[0030] Fig. 9 is a schematic circuit diagram showing switch operation in a fundamental form in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0031] Traditional track and hold circuits comprise an analog sampling switch and a flying sampling capacitor characterized by such jitter, as is well known. In accordance with the present invention, an isolation switch is provided that connects the reference side of the flying sampling capacitor to the stable common mode voltage side of the flying sampling capacitor. A preferred embodiment of the present invention is based on the realization that a jitter free sample voltage can be realized by providing such an additional transmission gate switch (referenced to common mode or fixed voltage located near the midpoint of the switch logic control voltage) to a traditional track and hold circuit and by operating the switches in a manner to isolate the charge on a flying capacitor and to provide a sampled analog voltage determined by their isolated charge.

[0032] An analog switch opening is determined by the threshold voltage difference between the analog voltage and the switch controlling logic signal. As the analog voltage varies, the effective switch opening is varied with the switch threshold voltage difference, which is reflected in the switch opening time and seen as jitter in the aperture time. By using an aperture switch that is referenced to a fixed or common mode analog voltage, the opening voltage relation to the controlling signal is always the same, instead of being dependent on the sample voltage. After the aperture switch opening, the input voltage is disconnected, and the isolated capacitor voltage is applied to the utilization circuitry.

[0033] An isolation switch on the reference side of the flying sampling capacitor input always operates at a fixed analog voltage. This voltage is fixed and can be thought of as an analog virtual ground or common mode voltage that is used for the analog signals to swing about, thus the isolation switch is provided that connects the reference side of the flying sampling capacitor to the stable analog common mode voltage. This isolation switch is turned off before the sampling switch and defines the exact aperture time of the analog sample, freezing charge on the flying sampling capacitor. This fixes the voltage at the isolation switch to a DC voltage so that its threshold voltage variation effect is eliminated because the voltage is always virtual ground at the bottom plate of the flying sampling capacitor. The aperture time window is the speed that this switch can be turned off. Ground or any bottom plate DC voltage will work to fix this turn-off time variation. It is important to use a voltage that is relevant to the analog signal path to prevent ground, power supply or other coupled noise into the analog signal path.

[0034] The isolation switch creates a high impedance on one end of a flying sampling capacitor to prevent any charge movement form the flying sampling capacitor after the aperture-time switch is turned off. When the sample voltage on the flying capacitor is to be used, the flying sample capacitor may be connected to utilization circuit and then the isolated flying sampling capacitor can be effectively reconnected back to the same virtual ground which would cancel any parasitic capacitance on the common mode side of the flying sampling capacitor since this capacitor terminal is returned to the same common mode of fixed voltage. Maintaining high impedance on the common mode side of the isolated flying sampling capacitor maintains its charge and thus the voltage across the flying sampling capacitor, even though a low impedance on the output side of the flying sampling capacitor is used to drive its output voltage.

[0035] According to a preferred embodiment of the present invention, the circuit:

• generates an analog ground (V_cm) near the midpoint of the power supply voltage to provide a ground reference for bipolar analog signals to swing about V_cm which is normally generated by connecting a replica complementary pair of current field effect transistors (or CiFET) drain output to its common gate input, a preferred exemplary embodiment(s) of which is disclosed in PCT International Application No. PCT/US2016/044792 and US Patent Application No. 15/748,866, the contents of which are incorporated herein by reference in its entirety;

connects the reference "bottom-plate" of the flying sampling capacitor(s) to the common mode analog ground (V_cm) through an analog switch(s);

uses symmetric transmission gates for analog switches;

utilizes nominal semiconductor parameters, adjusts one of the transmission gate MOSFET design widths (typically a 15% wider P-channel) to equalize the capacitances of the gate-control-logic to analog-signal-channel— matching channel capacitance to the corresponding N-channel MOSFET transmission gate;

uses true-complement transmission gate control signals to switch both P and N channel transmission gates synchronously - true-complement logic signals use logic to align the complementary transmission gate drive logic signals, and include a cross-coupled inverter latch between the complementary gate drive logic signals to fine-align the complementary logic signals to lock them together essentially independent of IC process parameter variation, and the complementary gate clock signals must be properly buffer with about a 4: 1 strength steps so they are not overloaded;

while keeping at least one terminal of the flying sampling capacitor(s) open circuited

(high impedance) to maintain the sample stored charge and thus voltage across the flying sampling capacitor, rearranges the sampling capacitor(s) as needed (thus, treating the flying sampling capacitor as a battery or precise voltage source);

reconnects the flying sampling capacitor to V_cm terminal last using a charge-balanced transmission gate operated similar to the initial V_cm "bottom plate" capacitor switching operation.

maintains a high impedance on one terminal of the flying sampling capacitor(s) from the sample cutoff to the end of its holding application in order to preserve the sampled voltage(s); and

uses a replica differential configuration to cancel leakage and parametric drifting - replicas tend to drift the same way often offering differential cancellation of the drift errors. [0036] According to the preferred embodiment of the present invention, it provides, by first disconnecting the flying sampling capacitor's terminal connected to the mid-supply common- mode analog reference voltage (V_cm), the initial cutoff switch always operates with V_cm voltage in the channel, it causes the switch gate-to-channel switching voltage to be independent of the voltage on the other input end of the flying sampling capacitor(s).

[0037] According to the preferred embodiment of the present invention, it further provides, by using Vcm as the reference, consistent symmetric transmission gate switch operation.

[0038] According to the preferred embodiment of the present invention, it provides, by isolating charge on the flying sampling capacitor(s), charge is preserved from the beginning of the sample cutoff time up to the end of application time of the sampled voltage to enable treating the flying sampling capacitors as voltage sources during the holding process.

[0039] According to the preferred embodiment of the present invention, it provides, by using aligned complementary transmission gate switch logic signals, balanced charge transfer from gate to channel that is well matched to cancel from their opposite injection direction.

[0040] According to the preferred embodiment of the present invention, it provides, by reconnecting the V_cm voltage end of the flying sampling capacitor(s) last, their charge/voltage is maintained independent of parasitic capacitances.

[0041] According to the preferred embodiment of the present invention, it provides, by maintaining high impedance on at least one end of the flying sampling capacitor(s) during the hold time the charge and thus their voltage on these flying sampling capacitor(s) is preserved independent of capacitor value and tolerance yielding precision without precision parts.

[0042] Fig. 1 is a schematic diagram of a prior art track and hold circuit 10. The circuit comprises a switch SWi connected between an input voltage source and a utilization circuit 15 and to one side of a flying sampling capacitor 11. The second side of the flying sampling capacitor 11 is connected to common mode ground (or a fixed voltage) V_cmto form "top plate sampling."

[0043] Fig. 2 A is a diagram showing top plate sampling analog and logic waveform relationship of the circuit 10 shown in Fig. 1. As it can be seen, SWi turns off when its gate voltage reaches a threshold voltage below the analog voltage in its conduction channel. When this analog voltage is low, SWi turns off later. Fig. 2B is a timing diagram of the signal and logic waveforms of the operation of the circuit 10 of Fig. 1. The figure shows input voltages Vin High and Vin Low resulting in the sampling voltage error band which results in uncertainty causing jitter in the sample time.

[0044] Fig. 3A is a schematic circuit diagram of a track and hold circuit that is connected to a utilization circuit 25 in accordance with the preferred embodiment of the present invention. The circuit includes a second switch SWa2 connected between the second side of the flying sampling capacitor 21 and common mode ground. A control circuit 23 is connected to switches SWai and SWa2 responsive to a system command to operate the two switches as shown in the following Table 1. The control circuit 23 goes through a sequence of Tl, T2, T3, T4 and T5, then, return to Tl (and so on) for controlling the switches SWai and SWa2.

[0045]

Table 1

[0046] Fig. 3B shows consistent sample aperture time for Vcm based bottom plate sampling. Using a transmission gate switch for the added bottom plate switch SWa2 connected to Vcm and applying symmetrical gate control provided by the transmission driver logic circuit of Fig. 8, causes both transistors in this transmission gate to turn off together at their respective threshold voltages away from Vcm DC voltage to free the switch turn-OFF time from its channel voltage turn-OFF thresholds. The turn-OFF is referenced to the Vcm DC voltage instead of the varying incoming tracked voltage. [0047] Fig. 4 is a schematic diagram of the signal and logic waveforms of the operation of the circuit of Fig. 3A. The waveforms show that a jitter free voltage is applied to the utilization circuit at a voltage level determined by the isolated charge on flying sampling capacitor 21. The speed (the off time) of the first switch determines the aperture time for the circuit.

[0048] Fig. 5 is a schematic circuit diagram of a differential track and hold circuit in accordance with another preferred embodiment of the present invention. This circuit 30 comprises first and second track and hold circuits as shown in Fig. 3A. The circuit 30 is connected to a positive voltage input V+, a negative input V-, common mode ground V_cm, and a utilization circuit 35. The circuit 30 includes flying sampling capacitors Cbi and Cb2 and a control circuit 33 which are connected to control switches SWbi, SWb2, SWb3 and SWb4, responsive to a system command to operate the switches as shown in the following Table 2. The control circuit 33 goes through a sequence of Tl, T2, T3, T4 and T5, then, return to Tl (and so on) for controlling the switches SWbi, SW_b2, SW_B3 and SW_B4.

[0049]

[0050] Fig. 6 is a timing diagram of the waveform of the operation of the circuit of Fig. 5. It is seen from the figure that each side of the circuit operates as shown in Fig. 4 and provides the jitter free voltage determined by the difference in voltages of flying sampling capacitors Cbi and

[0051] Fig. 7 is a switch state diagram for the operation of circuits 20 and 30 of Figs. 3A and 5. A new sample voltage command occurs when the circuit is in a rest state as indicated in circle 100 of the figure. The tracking voltage is the input voltage. Switch SWa2 (or switches SWb2 and SWb4) is opened resulting in the termination of the wait period and the isolation and capture of the charge on flying sampling capacitor 21 (or flying sampling capacitors Cbi and Cb2) as indicated by circle 101. Switch SWai (or switches SWbi and SWb3) is then opened to disconnect and separate the input voltage as indicated as circle 103 and flying sampling capacitor 21 (or flying sampling capacitors Cbi and Cb2) is re-arranged and reconfigured as indicated by circle 105. Circle 106 indicates that the capacitor bottom plates are effectively reconnected to V_cm in the Utilization Circuit for computing. The stored charge and thus its capacitor voltage is utilized up to the return to tracking transition from the state 106 back to the state 100, when the hold voltage is terminated, as the circuit returns to the track new input voltage rest state indicated by circle 100.

[0052] The circuits of Figs. 3A and 5 exhibit parasitic capacitance as is well understood. The effects of such parasitics can be eliminated by reversing the switching sequence depicted in Fig. 7 at circle 105 and 106 so that Vcm is re-established on the reference plate of the flying sampling capacitor after the utilization 106 switches are closed.

[0053] There are also several dominant analog signal errors, that analog switches would encounter, and especially when the switches are operated for capturing and temporarily storing analog voltages as they are used for digitization or further processing. These errors are primarily caused by, for example:

1. the gate control logic voltage to sampling analog voltage defining the exact time for switch turn OFF point;

2. the logic transition coupling charge from the control logic signal onto analog signal capacitors; with

3. a charge transfer that is proportionally divided between the source and drain sides of the analog switch according to the impedance balance between the switch's terminal loads, (the lower impedance side of the switch receives the greater proportion of this turn-off charge transfer);

4. RC tracking and settling time errors in to the sampling capacitance;

5. leakage decay droop on the flying sampling capacitor(s);

6. parasitic capacitance loading; and

7. parasitic capacitance noise coupling from the power supply and other signals.

[0054] The present invention addresses the most significant and evasive first three causes listed above, namely 1, 2 and 3, while enabling the use of smaller flying sampling capacitors aid 4 and the others may usually be controlled by good engineering design and layout practices based on common general knowledge in the pertinent art, for instance, symmetrical layout around the V_cm midpoint analog ground diminishes 7. The size of the track & hold capacitance needs to be small in order to be fast and not consume large amounts of power and surface area, while being closely related to these overall error contributions. This sampling capacitance also has a lower limit related to desired accuracy which is limited by thermal noise at KT/C (Boltzmann constant (K) times Temperature in degrees Kelvin (T) divided by the storage capacitance (C)).

[0055] According to a preferred embodiment of the present invention, it is to use transmission gates, which are fabricated from complementary transistors, for all switches to cancel out control logic gate to analog channel charge transfer error by balancing the turn OFF charge transfers. Because the P- and N-channel gate control signals go in opposite directions, the change transfer tends to cancel, however, several secondary errors are introduced:

1. P- and N- channel transistors have different gate-to-channel capacitance;

2. P- and N- channel transistors are normally sized different for equalizing channel resistance;

3. Complementary logic signals have different delays and transition times that are IC process parameter dependent;

4. Individual P- and N-channel transistors turn OFF at their operating gate- to-channel voltage, making their individual turn OFF voltage to be a function of the sampled channel voltage; 5. This turn-OFF voltage variation causes the P and N-channel transistor timing to be a time dependent function of the AC input voltage;

6. Must always break before make all switch logic timing in order to not short out these flying sampling capacitor stored analog voltages;

7. The different P- and N-channel transistor turnoff times vary their charge transfer ratio; and

8. All these errors are significantly temperature and semiconductor parameter sensitive.

[0056] A relatively simple straight forward, but parametrically tracking transmission-gate control logic circuit 23 of Fig. 8 addresses most of the logic symmetry and relative timing issues. Its operational logic description is described from the input "Setup" pin 40 on the left to the output transmission-gate switches on the right.

[0057] The input "Setup" pin 40 on the left logic "1" places the target circuit in the initialization setup or tracking mode where an analog input voltage is being monitored. The logic circuit's critical timing occurs at the edge where its single logic input control pin is switched from Setup logic "1" to the opposite logic "0" state, defined as the Enable or Compute state.

[0058] The input inverter 41 on the left buffers the incoming logic signal with a similar pull-Up strength to pull-Down strength, roughly balancing these logic transition times. Although a P to N width of 2 is normally used for logic, a better balance may take a P to N ratio of 3 to 4 which defines a related logic common-Mode ratio. This cmRatio can be approximated by shorting an inverter output to its input while adjusting the width of the P-channel to cause the output voltage to rest near half of the power supply voltage using nominal (typical) IC parameters. This cmRatio is not a critical value but provides a good starting balance for the rest of the circuit where its analog operates about and is optimally defined as V_cm analog ground for bipolar analog signals to swing about. Since this V_cm is near ½ of the power supply Vdd, power and ground parasitics tend to cancel around V_cm.

[0059] In Fig. 8, the lower Setup logic channel is to the same as the upper Enable logic channel except their inputs are inverted. [0060] The "Break before make delays" are formed with a 2-input AND gate with its second input delayed with a non-inverting buffer. The relative sizing of these buffers can be set to provide the desired break before make logic separation delay.

[0061] The output of these NAND gates are buffered with both an inverter and non-inverted buffer to form a TRUE and COMPLEMENT logic state. These logic signals are complements that are not fine aligned due to the difference in time of their drive buffering.

[0062] These TRUE and COMPLMENT logic signals drive a cross-coupled RS latch that fights the mismatch before the midpoint voltage and aids after the midpoint to force an alignment at the midpoint crossover point to provide a symmetric output that tracks IC process parameter variations.

[0063] The same circuit 23 in Fig. 3A may be used for control circuit 33 in Fig. 5.

[0064] Additional inverter delays may be added to closely sequence two sets of transmission gates when needed to guarantee one set of transmission gates is opened before a following set of transmission gates. This would be the parallel set of transmission gates at the right that are operated at a buffer delay later than the transmission gates ETG1, ETG2, STG1 and STG2 shown in Fig. 8 for guaranteed close sequencing as used in disconnecting and isolating the initial sampled charge on the flying sampling capacitors C_Sm_P by SWa2 in Fig. 3A and the flying sampling capacitors Cbi and Cb2 by switches SW2, SWb4 in Fig. 5.

[0065] The input "Setup" pin 40 logic "1" places the target circuit in the initialization setup or tracking mode where an analog input voltage is being monitored. The logic circuit's critical timing occurs at the edge where its single logic input control pin is switched from Setup logic "1" to the opposite logic "0" state, defined as the Enable state.

[0066] On the right, there are two pair of dashed transmission-gate control signal lines to drive both the Su- & Su+ and En- & En+ switch gates, and delayed signal lines, dSu- & dSu+ and dEn- & dEn+. These transmission gates represent the various switches in the operational implementation. These dashed lines are buffered in accordance with the size of their loads. A buffer with a taper ratio of 4 is normally used as in common in logic design and must roughly take into account the wiring capacitance of the IC layout to maintain respectable logic speed.

[0067] Also, there is an example pair of load transmission gates between these dashed gate control signal lines followed by four dots to illustrate that more transmission gates can be driven by the same lines. These represent the complementary transmission gate switches that are driven to control various flying sampling capacitors in the track and hold circuit.

[0068] It is to be noted that the Output Buffers need to be sized to drive the multiplicity of transmission-gate switches when buffered with the standard taper ratio of around 3 to 4 optimally, as is normally used for a string of inverters. The goal is to provide

1. control flying sampling capacitor(s) connected alternately between an analog input and an amplifier in various configurations as appropriate for analog signal processing applications such as a sample/track and hold, offset correction/cancellation, integer arithmetic operations, switched capacitor filters, etc.

2. from switch control logic's capacitive charge transfer from the control logic signal onto their flying sampling capacitor when the switches are turned "OFF."

[0069] Fig. 9 is a schematic diagram of a circuit 50 for showing switch operation in the most fundamental form. Table 3 summarizes the operation of switches in the circuit 50.

[0070]

Table 3

[0071] The circuit 50 includes a flying sampling capacitor Cci, and a control circuit 53 which is connected to control switches SWci, SW_C2, SW_C3 and SW_C4, responsive to a system command to operate the switches as shown in Table 3. The control circuit 53 causes the circuit 50 to go through a sequence of Tl, T2, T3, T4, and T5, then return to Tl for another round of the sequence. At Tl of Table 3, switches SWci and SW_C2 are closed and switches SW_C3 and SW_C4 are opened to allow the flying sampling capacitor Cci to tracks the input voltage. Then, at T2, it opens SWci at a precise aperture time that is not a function of channel voltage, to isolate charge Q on the flying sampling capacitor Cci. At T3, it further opens the switch SW_C2 to disconnect the flying sampling capacitor Cci from the input voltage. At T4, switch SW_C3 is closed to reconfigure by connecting the top plate of the flying sampling capacitor Cci to low impedance (such as an op-amp output). At T5, the switch SWci reattaches the bottom plate of the flying sampling capacitor Cci to Van in high impedance such as a Van biased op-amp input.

[0072] The sequence of the process by the circuit 53 isolates and preserves the charge Q on the flying sampling capacitor Cci and thus its sampled voltage. By maintaining a high impedance on at least one end of the flying sampling capacitor Cci, also voltage or parasitic capacitance on the bottom (-) plate of the flying sampling capacitor Cci is returned to Van as the voltage across Vsmp is utilized, enacting a precision sample voltage.

[0073] Maintaining a high series impedance Z on the flying sampling capacitor Cci and returning one of the terminals of the flying sampling capacitor Cci to its sample cutoff voltage enables the sampled voltage to be applied as a precision voltage without precision parts while being independent of the parasitic capacitance of the flying sampling capacitor Cci. Also, using symmetrical P and N channel transmission gate switches dynamically cancels out charge transfer from gate control logic to the sampled analog voltage stored, while precisely defining the critical switch turn off time independent of channel voltage.

Claims

A track and hold circuit having an input terminal, compri a plurality of switches; a capacitor having a first side and a second side; a controller connected to the plurality of switches in a manner to supply a sample voltage to a utilization circuit by sequencing the operation of the plurality of switches, wherein, i. at a first sequence, the control circuit configures the plurality of switches to track an input voltage across the capacitor; ii. at a second sequence, the control circuit configures the plurality of switches to isolate a charge on the capacitor; iii. at a third sequence, the control circuit configures the plurality of switches to disconnect the input voltage from the capacitor; iv. at a fourth sequence, the control circuit configures the plurality of switches o supply the voltage held on the capacitor sample voltage to the utilization circuit for processing.

2. Ajitter free track and hold circuit comprising the circuit recited in claim 1.

3. A differential track and hold circuit having positive and negative input terminals, compri a. a first switch; b. a second switch; a first capacitor having a first side and a second side, the first side of the first capacitor is connected to the positive input terminal via the first switch; the second side of the first capacitor is connected via the second switch to a common mode voltage source; and the first side of the first capacitor is further connected to a utilization circuit; a third switch; a fourth switch; a second capacitor having a first side and a second side, the first side of the second capacitor is connected to the negative input terminal via the first switch; the second side of the second capacitor is connected via the second switch to the common mode voltage source; and the first side of the second capacitor is further connected to the utilization circuit; a controller connected to the first, second, third and fourth switches in a manner to supply a sample voltage to the utilization circuit by sequencing the closure of the first, second, third and fourth switches, wherein, i. at a first sequence, the first, second, third and fourth switches are closed such that input voltages at the positive and negative input terminals are tracked across the first and second capacitors; ii. at a second sequence, the first and third switches are closed and the second and fourth switches are opened, such that charges on the first and second capacitors are isolated; iii. at a third sequence, the first, second, third and fourth switches are opened, such that the input voltages at the positive and negative input terminals are disconnected from the first and second capacitors; iv. at a fourth sequence, the first and third switches are opened and the second and fourth switches are closed, such that the voltages on the first and second capacitors are supplied as the sample voltage to the utilization circuit for processing.

4. A track and hold circuit having an input terminal, comprising: a plurality of switches; a charge capacitor, having top plate and bottom plate; and a control circuit that controls the plurality of switches to carry out a process comprising: a. tracking an input voltage by connecting the top plate of the charge capacitor to the input terminal and the bottom plate of the charge capacitor to a common mode voltage source; b. isolating and capturing a sampled voltage on the charge capacitor by

disconnecting the bottom plate from the common voltage source; c. disconnecting the top plate of the charge capacitor from the input terminal to separate the input voltage; d. reconfiguring the capacitor by connecting the top plate of the charge capacitor to a low impedance; and e. rearranging and reconnecting the bottom plate of the charge capacitor to the common mode voltage source in high impedance to compute and sample a hold voltage on the sample capacitor.

5. A track and hold circuit comprising: a f rst switch; a second switch,

a capacitor having a first side and a second side, said first side is connected to an input terminal via said first switch, said second side of said capacitor is connected via said second switch to a common mode voltage source, said first side of said capacitor is connected to a utilization circuit; and

a controller connected to said first and second switches in a manner to supply a sample voltage to said utilization circuit to operate said first switch and said second switch in a sequence comprising the steps of Tl, T2, T3, T4 and T5 as follows:

6. A jitter-free track and hold circuit comprising: a capacitor having a first side and a second side; a first switch connected between an input terminal and said first side of said capacitor, said first side of said capacitor is connected to a utilization circuit; and a second switch connected between said second side of said capacitor and a common mode signal source; and a controller connected to said first and second switches, said controller being responsive to a system command to supply a sample voltage to said utilization circuit for operating said first switch and said second switch in a sequence comprising the steps of Tl, T2, T3, T4 and T5 as follows: