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WO2018139187A1 - Dispositif de capture d'images à semi-conducteurs, son procédé de commande et dispositif électronique - Google Patents

Dispositif de capture d'images à semi-conducteurs, son procédé de commande et dispositif électronique Download PDF

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Publication number
WO2018139187A1
WO2018139187A1 PCT/JP2018/000231 JP2018000231W WO2018139187A1 WO 2018139187 A1 WO2018139187 A1 WO 2018139187A1 JP 2018000231 W JP2018000231 W JP 2018000231W WO 2018139187 A1 WO2018139187 A1 WO 2018139187A1
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Prior art keywords
pixel
transfer
transistor
transfer transistor
solid
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English (en)
Japanese (ja)
Inventor
勇佑 松村
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
    • H04N25/623—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming by evacuation via the output or reset lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors

Definitions

  • the present technology relates to a solid-state imaging device, a driving method thereof, and an electronic device, and more particularly, to a solid-state imaging device capable of improving transfer characteristics, a driving method thereof, and an electronic device.
  • a technique in which an amplification transistor is used in a source ground connection instead of a source follower connection.
  • the voltage amplification gain of the amplification transistor can be greatly improved and the conversion efficiency can be increased as compared with the case where the amplification transistor is used with the source follower connection.
  • the amplification transistor when the amplification transistor is used with the source grounded, the gain is inverted amplification. For this reason, as the electric charge is accumulated in the FD (floating diffusion), the potential of the FD becomes lower, whereas the voltage read from the vertical signal line becomes higher.
  • Patent Document 1 discloses that a capacitor is connected to the FD, and a boost signal line connected to the capacitor is controlled to boost the potential of the FD only at the time of charge transfer. With this configuration, charge transfer from the PD to the FD can be assisted.
  • Patent Document 1 it is necessary to additionally arrange a capacitor and a boost signal line, which may reduce the degree of freedom of layout.
  • the present technology has been made in view of such a situation, and is intended to improve transfer characteristics while maintaining flexibility in layout.
  • a solid-state imaging device includes a pixel having a PD (photodiode) and a transfer transistor that transfers the charge of the PD, an FD (floating diffusion) that accumulates the charge from the transfer transistor and converts the charge into a voltage, and the FD
  • a grounded source amplification transistor that reads out the voltage of the pixel as a signal and a drive circuit that drives the pixel, and the drive circuit is disposed in the vicinity of the FD during charge transfer by the transfer transistor of the pixel.
  • An intermediate voltage is applied to a predetermined transistor electrically connected to the FD.
  • the FD is shared by a plurality of the pixels, and the drive circuit can apply the intermediate voltage to the transfer transistors of the non-readout pixels during charge transfer by the transfer transistors of the read pixels.
  • the drive circuit can apply the intermediate voltage to the transfer transistors of two or more non-readout pixels during charge transfer by the transfer transistor of one read pixel.
  • the drive circuit can apply the intermediate voltage to the transfer transistor of the readout pixel after charge transfer by the transfer transistor of the readout pixel.
  • the drive circuit may be configured to apply the intermediate voltage to a reset transistor that resets the charge accumulated in the FD during charge transfer by the transfer transistor of the pixel.
  • the intermediate voltage can be applied to a conversion efficiency switching transistor that switches the conversion efficiency of the FD during charge transfer by the transfer transistor of the pixel.
  • a driving method of the solid-state imaging device includes a pixel having a PD (photodiode) and a transfer transistor that transfers the charge of the PD, and an FD (floating diffusion) that accumulates the charge from the transfer transistor and converts it into a voltage.
  • a solid-state imaging device driving method comprising: a common-source amplification transistor that reads out the voltage of the FD as a signal; and a driving circuit that drives the pixel, wherein the driving circuit is a charge generated by the transfer transistor of the pixel.
  • An electronic device of the present technology includes a pixel having a PD (photodiode) and a transfer transistor that transfers the charge of the PD, an FD (floating diffusion) that accumulates the charge from the transfer transistor and converts the charge into a voltage, and the FD
  • a source-grounded amplification transistor that reads a voltage as a signal and a drive circuit that drives the pixel, and the drive circuit is disposed in the vicinity of the FD during charge transfer by the transfer transistor of the pixel;
  • a solid-state imaging device that applies an intermediate voltage to a predetermined transistor electrically connected to the FD is provided.
  • an intermediate voltage is applied to a predetermined transistor that is disposed in the vicinity of the FD and electrically connected to the FD.
  • 10 is a timing chart at the time of charge transfer in the second embodiment. 12 is a timing chart during charge transfer in the third embodiment. It is a top view which shows the layout of the pixel of 4th Embodiment. 10 is a timing chart during charge transfer in the fourth embodiment. It is a circuit diagram which shows the structural example of the pixel of 5th Embodiment. It is a top view which shows the layout of the pixel of 5th Embodiment. 10 is a timing chart during charge transfer in the fifth embodiment. It is a block diagram which shows the structural example of the electronic device to which this technique is applied. It is a figure which shows the usage example of an image sensor. It is a block diagram which shows an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.
  • FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a solid-state imaging device to which the present technology is applied.
  • the solid-state imaging device of FIG. 1 is configured as, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • CMOS Complementary Metal Oxide Semiconductor
  • 1 includes a pixel array section 12, a vertical drive circuit 13, a horizontal drive circuit 14, and an output circuit 15.
  • a plurality of pixels 21 are arranged in a matrix in the pixel array unit 12. Each pixel 21 is connected to the vertical drive circuit 13 for each row by a horizontal signal line 22 and connected to the horizontal drive circuit 14 for each column by a vertical signal line 23.
  • the vertical drive circuit 13 outputs a drive signal via the horizontal signal line 22 to drive the pixels 21 arranged in the pixel array unit 12 for each row.
  • the horizontal drive circuit 14 performs column processing for detecting a signal level by a CDS (Correlated Double Sampling) operation from a signal output from each pixel 21 of the pixel array unit 12 through the vertical signal line 23, and the pixel 21 performs photoelectric processing. An output signal corresponding to the charge generated by the conversion is output to the output circuit 15.
  • CDS Correlated Double Sampling
  • the output circuit 15 amplifies the output signal sequentially output from the horizontal drive circuit 14 to a voltage value of a predetermined level and outputs it to a subsequent image processing circuit or the like.
  • the solid-state imaging device 11 to which the present technology is applied includes a pixel 21 having a PD (photodiode) and a transfer transistor that transfers the charge of the PD, and an FD (floating diffusion) that accumulates the charge from the transfer transistor and converts it into a voltage. ), A grounded source amplification transistor that reads out the voltage of the FD as a signal, and a drive circuit that drives the pixel 21.
  • a PD photodiode
  • FD floating diffusion
  • the drive circuit is configured as a vertical drive circuit 13 and operates to apply an intermediate voltage to a predetermined transistor that is disposed in the vicinity of the FD and electrically connected to the FD during charge transfer by the transfer transistor of the pixel 21. .
  • FIG. 2 is a circuit diagram illustrating a configuration example of a pixel according to the first embodiment
  • FIG. 3 is a plan view illustrating a layout of the pixel.
  • a two-pixel sharing configuration is adopted in which one FD is shared by two pixels 21-1, 21-2.
  • the pixel 21-1 has a PD 41-1 and a transfer transistor 42-1
  • the pixel 21-2 has a PD 41-2 and a transfer transistor 42-2.
  • a connection point between the transfer transistors 42-1 and 42-2 constitutes the FD43.
  • the transfer transistor 42-1 is driven according to the transfer signal TG1 supplied from the vertical drive circuit 13 (FIG. 1) via the horizontal signal line 22T1, and is turned on at a timing when the transfer signal TG1 becomes a high level in a pulse shape.
  • the transfer transistor 42-1 is turned on, the charge generated in the PD 41-1 is transferred to the FD 43 via the transfer transistor 42-1.
  • the transfer transistor 42-2 is driven in accordance with the transfer signal TG2 supplied from the vertical drive circuit 13 via the horizontal signal line 22T2, and is turned on when the transfer signal TG2 becomes a high level in a pulse shape.
  • the transfer transistor 42-2 is turned on, the charge generated in the PD 41-2 is transferred to the FD 43 via the transfer transistor 42-2.
  • the FD 43 is connected to the gate electrode of the amplification transistor 44.
  • the amplification transistor 44 outputs a voltage having a level corresponding to the charge accumulated in the FD 43.
  • the selection transistor 45 is driven in accordance with the selection signal SEL supplied from the vertical drive circuit 13 via the horizontal signal line 22S, and is turned on at a timing when the selection signal SEL becomes a high level in a pulse shape.
  • the selection transistor 45 is turned on, the voltage output from the amplification transistor 44 can be output to the vertical signal line 23 via the selection transistor 45.
  • the source side of the amplification transistor 44 is grounded via a load transistor 46 that is an nMOS.
  • the amplification transistor 44 and the load transistor 46 operate as a common-source inverting amplifier, and a signal indicating a level corresponding to the charge accumulated in the FD 43 is output.
  • the reset transistor 47 is driven in accordance with the reset signal RST supplied from the vertical drive circuit 13 via the horizontal signal line 22R, and is turned on when the reset signal RST becomes a high level in a pulse shape.
  • the drain side of the reset transistor 47 is connected to the vertical signal line 23.
  • the reset transistor 47 is turned on, the charge accumulated in the FD 43 is transferred via the reset transistor 47.
  • the FD 43 is reset.
  • the transfer transistors 42-1 and 42-2 are arranged in the vicinity of the FD 43, and are electrically connected to the FD 43.
  • the transfer transistor 42-1 of the pixel 21-1 which is the pixel to be read (readout pixel), has a high level as the transfer signal TG1.
  • a voltage of (for example, about 3 V) is applied in a pulse shape.
  • the transfer transistor 42-1 is turned on, the charge generated in PD1 (PD41-1) is transferred to the FD 43 as shown in the lower part of FIG.
  • a high level voltage is applied in a pulse form as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 as the read pixel.
  • the transfer transistor 42-2 is turned on, although not shown, the charge generated in the PD2 (PD41-2) is transferred to the FD43.
  • PD1 (PD41-1) and PD2 (PD41-2) have a smaller amount of charge than in the case of high illuminance (FIG. 4). Accumulated.
  • a high level voltage is pulsed as a transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1 as the read pixel.
  • an intermediate voltage for example, about 1 V
  • an intermediate voltage that becomes an intermediate level between the high level and the low level as the transfer signal TG2 is applied to the transfer transistor 42-2 of the pixel 21-2 that is a pixel not to be read (non-read pixel). Is applied in pulses.
  • a high level voltage is applied in a pulse form as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 that is the read pixel.
  • an intermediate voltage is applied in the form of a pulse as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1, which is a non-read pixel.
  • the charge transfer can be assisted by feedthrough without the need to additionally arrange a capacitor or a boost signal line as in the configuration of Patent Document 1, so that the layout It is possible to improve transfer characteristics while maintaining the degree of freedom, and as a result, a high S / N ratio in the solid-state imaging device 11 can be realized.
  • the operation at the time of charge transfer under high illuminance and the operation at the time of charge transfer under low illuminance described above may be switched according to the charge amount of the PD, for example. Specifically, when the charge amount of the PD exceeds a predetermined amount, the operation at the time of charge transfer under high illuminance is performed, and when the charge amount of the PD does not exceed the predetermined amount, the charge under low illuminance Make sure that the transfer operation is performed.
  • the two-pixel sharing configuration has been described as an example, but the number of shared pixels is not limited to two.
  • FIG. 8 is a plan view showing the layout of the pixel according to the second embodiment.
  • a two-pixel sharing configuration is adopted in which one FD is shared by the four pixels 21-1 to 21-4.
  • the pixel 21-1 has a PD 41-1 and a transfer transistor 42-1
  • the pixel 21-2 has a PD 41-2 and a transfer transistor 42-2
  • the pixel 21-3 has a PD 41-3 and a transfer transistor 42-3
  • the pixel 21-4 has a PD 41-4 and a transfer transistor 42-4.
  • Each connection point of the transfer transistors 42-1 to 42-4 constitutes the FD43.
  • the transfer transistors 42-1 to 42-4 are arranged in the vicinity of the FD 43, and are electrically connected to the FD 43.
  • FIG. 9 shows a timing chart at the time of charge transfer under low illumination in this embodiment.
  • a high level voltage is applied in a pulse form as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1, which is the read pixel.
  • intermediate voltages are pulsed as transfer signals TG2, TG3, and TG4 to the transfer transistors 42-2, 42-3, and 42-4 of the pixels 21-2, 21-3, and 21-4 that are non-readout pixels. Applied in the form.
  • a high level voltage is applied in a pulse form as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 as the read pixel.
  • intermediate voltages are pulsed as transfer signals TG1, TG3, TG4 to the transfer transistors 42-1, 42-3, 42-4 of the pixels 21-1, 21-3, 21-4 which are non-readout pixels. Applied in the form.
  • a high-level voltage is applied in a pulse form to the transfer transistor of the readout pixel, and the other non-readout pixels are read out.
  • An intermediate voltage is applied in a pulsed manner to each transfer transistor.
  • the potential of the FD 43 is further increased by applying an intermediate voltage to the transfer transistors of two or more non-readout pixels during charge transfer by the transfer transistor of one read pixel.
  • the potential difference between the PD and the FD 43 of the readout pixel is further increased, and the transfer characteristics can be further improved.
  • FIG. 10 shows a timing chart at the time of charge transfer under low illuminance in the third embodiment.
  • a two-pixel sharing configuration is adopted in which one FD is shared by two pixels 21-1 and 21-2.
  • a high level voltage is applied as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1, which is the read pixel. Further, after charge transfer by the transfer transistor 42-1 of the pixel 21-1, an intermediate voltage is applied as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1. In the meantime, the intermediate voltage is applied in a pulse form as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 which is a non-read pixel.
  • a high level voltage is applied as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 that is the readout pixel.
  • an intermediate voltage is applied as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2.
  • an intermediate voltage is applied in the form of a pulse as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1, which is a non-read pixel.
  • the voltage applied to the transfer transistor can be lowered stepwise. As a result, it is possible to prevent the charge transferred from the PD of the readout pixel from the FD 43 from flowing back to the PD side.
  • the intermediate voltage is applied to the transfer transistor of the non-read pixel while the high level voltage and the intermediate voltage are applied to the transfer transistor of the read pixel. It is sufficient that an intermediate voltage is applied to the transfer transistor at least while a high level voltage is applied to the transfer transistor of the readout pixel.
  • present embodiment may be applied to the configuration of the second embodiment or other embodiments described later.
  • FIG. 11 is a plan view showing the layout of the pixel according to the fourth embodiment.
  • a two-pixel sharing configuration is adopted in which one FD is shared by two pixels 21-1, 21-2.
  • the pixel 21-1 has a PD 41-1 and a transfer transistor 42-1
  • the pixel 21-2 has a PD 41-2 and a transfer transistor 42-2.
  • a connection point between the transfer transistors 42-1 and 42-2 and the reset transistor 47 constitutes the FD43.
  • the transfer transistors 42-1 and 42-2 and the reset transistor 47 are arranged in the vicinity of the FD 43 and are electrically connected to the FD 43.
  • FIG. 12 shows a timing chart at the time of charge transfer under low illumination in this embodiment.
  • a high level voltage is applied in a pulse form as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1, which is the read pixel.
  • the intermediate voltage is applied in a pulse form as the transfer signal TG2 and the reset signal RST to the transfer transistor 42-2 and the reset transistor 47 of the pixel 21-2 which is a non-read pixel.
  • a high-level voltage is applied in a pulse form as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 that is the readout pixel.
  • the intermediate voltage is applied in a pulse form as the transfer signal TG1 and the reset signal RST to the transfer transistor 42-1 and the reset transistor 47 of the pixel 21-1, which is a non-read pixel.
  • the potential of the FD 43 is also boosted by applying an intermediate voltage to the reset transistor 47 during charge transfer by the transfer transistor of the readout pixel.
  • the potential difference between the PD and the FD 43 of the readout pixel becomes larger, and the transfer characteristics can be improved.
  • this embodiment may be applied to the configuration of the second embodiment, or may be applied to a configuration that does not share pixels.
  • FIG. 13 is a circuit diagram illustrating a configuration example of a pixel according to the fifth embodiment
  • FIG. 14 is a plan view illustrating a layout of the pixel.
  • the pixel 21-1 has a PD 41-1 and a transfer transistor 42-1
  • the pixel 21-2 has a PD 41-2 and a transfer transistor 42-2.
  • the connection point of the transfer transistors 42-1 and 42-2 and the conversion efficiency switching transistor 61 constitutes the FD43.
  • the conversion efficiency switching transistor 61 is driven in accordance with the switching signal FDG supplied from the vertical driving circuit 13 (FIG. 1) via the horizontal signal line 22F, and is turned on at a timing when the switching signal FDG is pulsed to a high level.
  • the conversion efficiency switching transistor 61 is turned on, the capacity of the FD 43 increases and the conversion efficiency is lowered.
  • the transfer transistors 42-1 and 42-2 and the conversion efficiency switching transistor 61 are arranged in the vicinity of the FD 43, and are electrically connected to the FD 43.
  • FIG. 15 shows a timing chart at the time of charge transfer under low illumination in this embodiment.
  • a high level voltage is applied in a pulse form as the transfer signal TG1 to the transfer transistor 42-1 of the pixel 21-1, which is the read pixel.
  • the intermediate voltage is applied in a pulse form as the transfer signal TG2 and the switching signal FDG to the transfer transistor 42-2 and the conversion efficiency switching transistor 61 of the pixel 21-2 which is a non-read pixel.
  • a high level voltage is applied in a pulse form as the transfer signal TG2 to the transfer transistor 42-2 of the pixel 21-2 as the read pixel.
  • the intermediate voltage is applied in a pulse form as the transfer signal TG1 and the switching signal FDG to the transfer transistor 42-1 and the conversion efficiency switching transistor 61 of the pixel 21-1, which is a non-read pixel.
  • the potential of the FD 43 is also boosted by applying an intermediate voltage to the conversion efficiency switching transistor 61 during charge transfer by the transfer transistor of the readout pixel.
  • the potential difference between the PD and the FD 43 of the readout pixel becomes larger, and the transfer characteristics can be improved.
  • this embodiment may be applied to the configuration of the second embodiment, or may be applied to a configuration that does not share pixels.
  • the solid-state imaging device 11 as described above is applied to various electronic devices such as an imaging system such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. be able to.
  • FIG. 16 is a block diagram illustrating a configuration example of an imaging apparatus that is an electronic apparatus to which the present technology is applied.
  • the imaging device 301 includes an optical system 302, a solid-state imaging device 303, and a DSP (Digital Signal Processor) 304, and a DSP 304, a display device 305, an operation system 306, and a memory via a bus 307. 308, the recording device 309, and the power supply system 310 are connected, and can capture still images and moving images.
  • a DSP Digital Signal Processor
  • the optical system 302 includes one or more lenses, guides image light (incident light) from a subject to the solid-state imaging device 303, and forms an image on a light receiving surface (sensor unit) of the solid-state imaging device 303.
  • the solid-state imaging device 303 As the solid-state imaging device 303, the solid-state imaging device 11 having the pixel 21 of any one of the above-described configuration examples is applied. In the solid-state imaging device 303, electrons are accumulated for a certain period according to an image formed on the light receiving surface via the optical system 302. Then, a signal corresponding to the electrons accumulated in the solid-state imaging device 303 is supplied to the DSP 304.
  • the DSP 304 performs various signal processing on the signal from the solid-state imaging device 303 to acquire an image, and temporarily stores the image data in the memory 308.
  • the image data stored in the memory 308 is recorded in the recording device 309 or supplied to the display device 305 to display an image.
  • the operation system 306 receives various operations by the user and supplies operation signals to each block of the imaging apparatus 301, and the power supply system 310 supplies power necessary for driving each block of the imaging apparatus 301.
  • the imaging device 301 configured as described above, by applying the solid-state imaging device 11 as described above as the solid-state imaging device 303, it is possible to improve the transfer characteristics while maintaining the degree of freedom of layout. Therefore, it is possible to realize a high S / N ratio.
  • the configuration of the solid-state imaging device according to the present technology can be employed in a backside illumination type CMOS image sensor or a frontside illumination type CMOS image sensor.
  • FIG. 17 is a diagram illustrating an example of using an image sensor to which the present technology is applied.
  • the image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
  • Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
  • Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
  • Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
  • Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports such as action cameras and wearable cameras for sports applications etc.
  • Equipment used for agriculture such as cameras for monitoring the condition of fields and crops
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.
  • FIG. 18 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp.
  • the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted.
  • the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image.
  • the vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light.
  • the imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
  • the vehicle interior information detection unit 12040 detects vehicle interior information.
  • a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
  • the microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010.
  • the microcomputer 12051 realizes an ADAS (Advanced Driver Assistance System) function including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintaining traveling, vehicle collision warning, or vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
  • the sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 19 is a diagram illustrating an example of an installation position of the imaging unit 12031.
  • the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100.
  • the imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100.
  • the forward images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 19 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100).
  • a predetermined speed for example, 0 km / h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
  • the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles.
  • the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining.
  • the audio image output unit 12052 When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to be superimposed and displayed.
  • voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the solid-state imaging device 11 of FIG. 1 can be applied to the imaging unit 12031.
  • a pixel having a PD (photodiode) and a transfer transistor for transferring the charge of the PD; FD (floating diffusion) that accumulates charges from the transfer transistor and converts them into a voltage; A common source amplification transistor that reads out the voltage of the FD as a signal; A drive circuit for driving the pixels, The driving circuit applies an intermediate voltage to a predetermined transistor that is disposed in the vicinity of the FD and electrically connected to the FD during charge transfer by the transfer transistor of the pixel.
  • the FD is shared by a plurality of the pixels
  • the driving circuit applies the intermediate voltage to the transfer transistors of two or more non-readout pixels during charge transfer by the transfer transistor of one read-out pixel.
  • the drive circuit applies the intermediate voltage to the transfer transistor of the readout pixel after charge transfer by the transfer transistor of the readout pixel.
  • a driving method of a solid-state imaging device comprising: a driving circuit that drives the pixels, The driving circuit includes a step of applying an intermediate voltage to a predetermined transistor that is disposed in the vicinity of the FD and electrically connected to the FD during charge transfer by the transfer transistor of the pixel. Method.
  • An electronic apparatus comprising: a solid-state imaging device that applies an intermediate voltage to a predetermined transistor that is disposed in the vicinity of the FD and is electrically connected to the FD during charge transfer by the transfer transistor of the pixel.
  • 11 solid-state imaging device 21, 211-1 to 21-4 pixels, 13 vertical drive circuit, 41-1 to 41-4 PD, 42-1 to 42-4 transfer transistor, 43 FD, 44 amplification transistor, 45 selection transistor , 46 load transistor, 47 reset transistor, 61 conversion efficiency switching transistor, 301 electronic device, 303 solid-state imaging device

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention concerne un dispositif de capture d'images à semi-conducteurs, son procédé de commande, et un dispositif électronique permettant d'améliorer les performances de transfert tout en maintenant le degré de liberté de disposition. Un dispositif de capture d'images à semi-conducteurs selon la présente invention comprend : des pixels comportant des PD et des transistors de transfert servant à transférer les charges sur les PD; des FD servant à accumuler les charges provenant des transistors de transfert et à convertir les charges en tensions; des transistors d'amplificateurs à source-mise à la terre servant à lire les tensions des FD en tant que signaux; et un circuit de commande destiné à commander les pixels. Lorsque la charge est transférée par le transistor de transfert d'un pixel, le circuit de commande applique une tension intermédiaire à un transistor prédéfini qui est disposé à proximité du FD et qui est connecté électriquement au FD. Cette technologie peut s'appliquer à des capteurs d'images à CMOS.
PCT/JP2018/000231 2017-01-24 2018-01-10 Dispositif de capture d'images à semi-conducteurs, son procédé de commande et dispositif électronique Ceased WO2018139187A1 (fr)

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JP2017010052A JP2018121142A (ja) 2017-01-24 2017-01-24 固体撮像装置およびその駆動方法、並びに電子機器
JP2017-010052 2017-01-24

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KR20230008299A (ko) 2021-07-06 2023-01-16 삼성전자주식회사 3개의 전압 레벨을 갖는 전송 게이트 신호를 사용하는 이미지 센서, 및 이의 동작 방법
JP2023034113A (ja) * 2021-08-30 2023-03-13 ソニーセミコンダクタソリューションズ株式会社 撮像素子及び撮像装置
JPWO2023074177A1 (fr) * 2021-10-27 2023-05-04
WO2024057810A1 (fr) * 2022-09-15 2024-03-21 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie, système d'imagerie et procédé de commande de dispositif d'imagerie

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JP2012010106A (ja) * 2010-06-24 2012-01-12 Canon Inc 固体撮像装置及び固体撮像装置の駆動方法
WO2012053127A1 (fr) * 2010-10-19 2012-04-26 パナソニック株式会社 Dispositif d'imagerie à semi-conducteurs, procédé d'entraînement de celui-ci, et dispositif d'imagerie
WO2013099723A1 (fr) * 2011-12-27 2013-07-04 ソニー株式会社 Élément de capture d'image, appareil de capture d'image, dispositif électronique et procédé de capture d'image
JP2014112580A (ja) * 2012-12-05 2014-06-19 Sony Corp 固体撮像素子および駆動方法

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JP2012010106A (ja) * 2010-06-24 2012-01-12 Canon Inc 固体撮像装置及び固体撮像装置の駆動方法
WO2012053127A1 (fr) * 2010-10-19 2012-04-26 パナソニック株式会社 Dispositif d'imagerie à semi-conducteurs, procédé d'entraînement de celui-ci, et dispositif d'imagerie
WO2013099723A1 (fr) * 2011-12-27 2013-07-04 ソニー株式会社 Élément de capture d'image, appareil de capture d'image, dispositif électronique et procédé de capture d'image
JP2014112580A (ja) * 2012-12-05 2014-06-19 Sony Corp 固体撮像素子および駆動方法

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