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WO2018125201A1 - Synthèse de polycarbosilanes et de derivitisation en matériau de remplissage sic haute densité - Google Patents

Synthèse de polycarbosilanes et de derivitisation en matériau de remplissage sic haute densité Download PDF

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Publication number
WO2018125201A1
WO2018125201A1 PCT/US2016/069465 US2016069465W WO2018125201A1 WO 2018125201 A1 WO2018125201 A1 WO 2018125201A1 US 2016069465 W US2016069465 W US 2016069465W WO 2018125201 A1 WO2018125201 A1 WO 2018125201A1
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Prior art keywords
dielectric film
monomer unit
carbosilane
hydrogen
linear
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Inventor
Tayseer MAHDI
James M. Blackwell
Jessica M. TORRES
Jeffery D. Bielefeld
John J. Plombon
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions

Definitions

  • Dielectric materials having a dielectric constant less than a dielectric constant of silicon dioxide are important to enabling new patterning schemes in lithographic processes.
  • Spin coating or spin-on deposition is a procedure used to deposit generally uniform thin films onto integrated circuit chips that are, for example, formed on a single wafer (e.g., a silicon wafer) that is then diced to create individual chips.
  • Spin coating or spin-on deposition may be used to deposit low-k dielectric materials into high aspect ratio trenches providing control over film thickness and gap fill.
  • Figure 1 shows a schematic of a homo-oligomer of similar carbosilane units.
  • Figure 2 shows a schematic of a co-oligomer of two dissimilar carbosilane units.
  • Figure 3 is a flow chart of a process to form a silicon carbide dielectric film on an integrated circuit substrate.
  • Figure 4 shows a cross-sectional side view of a portion of a integrated circuit substrate including a device layer, metallization to the device layer and a hard mask of a SiC dielectric material on the metallization.
  • Figure 5 shows a cross-sectional side view of an embodiment of a semiconductor device structure including a silicon carbide dielectric film.
  • Figure 6 shows a cross-sectional side view of another embodiment of a
  • semiconductor device structure including a silicon carbide dielectric film or films.
  • Figure 7 is an interposer implementing one or more embodiments.
  • Figure 8 illustrates an embodiment of a computing device.
  • a dielectric film on an integrated circuit substrate including cross-linked carbosilane units is described.
  • the cross-linked carbosilane units are selected from linear monomer units or at least one linear monomer unit and at least one heterocyclic monomer unit.
  • a linear monomer unit as used in here includes a C 2 to C 8 straight or branched chain alkenyl or alkynyl and a heterocyclic monomer unit includes a saturated or unsaturated moiety including an even-numbered ring structure of alternating silicon and carbon atoms (e.g., four to 10 ring members of silicon and carbon atoms).
  • An integrated circuit device including a dielectric film as, for example, an interlayer dielectric film and/or an etch- selective layer is also described.
  • a method of forming a dielectric film is further disclosed.
  • the method combines a first carbosilane unit with a second carbosilane unit.
  • the oligomer or polymer precursor produced by the combination is then deposited on a substrate such as through the use of a solvent.
  • the deposition is performed by a spin coating technique.
  • the deposited combination is then cross-linked to form a silicon carbide (SiC) dielectric film.
  • the dielectric film synthesis and processing methods provide silicon carbide films with a minimal amount of oxygen atoms (e.g., two percent or less oxygen atoms).
  • the film offers properties such as low shrinkage, high density, etch selectivity, gap fill and a dielectric constant less than a dielectric constant of silicon dioxide.
  • the low-k dielectric film can be used as an interlayer dielectric, as a spacer material or as a hard mask to enable patterning schemes in which, for example, silicon may be etched selectively relative to other materials such as silicon nitrid
  • a silicon carbide film is formed by a cross-linking of carbosilane units.
  • the carbosilane units are linear monomer units or linear monomer units and at least one heterocyclic monomer unit.
  • linear monomer units include a general formula:
  • Ri, R 2 , R and R4 are each independently selected of a hydrogen or a C 2 -C 4 straight or branched alkenyl or alkynyl, with the proviso that when one of Ri, R 2 , R and R4 is a hydrogen, no more than another one of Ri, R 2 , R and R 4 is a hydrogen.
  • independently selected in this context means that R 1 -R4 may be the same or different or some combination where, for example, two or three may be the same.
  • the proviso also provides that R 1 -R4 cannot each be a hydrogen.
  • Ri, R 2 , R 3 and R ⁇ are the same and are for example, vinyl
  • one of Ri, R 2 , R 3 and R4 is hydrogen while the each of the other of Ri, R 2 , R 3 and R4 are each vinyl, propenyl, butenyl, ethynyl or propynyl or are not each the same moiety but are individually selected from vinyl, propenyl, butenyl, ethynyl or propynyl.
  • two of Ri, R 2 , R 3 and R4 are hydrogen and the other two of Ri, R 2 , R 3 and R 4 are each vinyl, propynyl, butenyl, ethynyl, or propenyl or are not each the same moiety but are individually selected from vinyl, propenyl, butenyl, ethynyl or propynyl.
  • the unsaturated group e.g., a double bond, a triple bond
  • the unsaturated side chains represented by, for example, an alkenyl or alkynyl group promote cross-linking reactions that densify a silicon carbide film and minimize evaporation at elevated temperatures.
  • Strained organic rings e.g., C 3 -C 6 unsaturated rings
  • silylene groups e.g., SiH 2
  • Ri, R 2 , R 3 and R4 could also be incorporated on one or more of Ri, R 2 , R 3 and R4 to promote cross-linking reactions.
  • a carbosilane unit includes at least one heterocyclic monomer unit.
  • the heterocyclic monomer unit is an even numbered ring structure of alternating silicon and carbon atoms with optional side chains on the silicon atoms independently selected from a C2-C4 alkenyl or alkynyl such as the alkenyls and alkynyls identified above.
  • the at least one heterocyclic monomer unit is a saturated or unsaturated moiety of 4 to 10 ring members of silicon and carbon atoms.
  • the at least one heterocyclic monomer unit has a formula:
  • R 5 , R5, R7, R 8 , R9 and Rio are each independently selected of a hydrogen or a C 2 -C 4 straight or branched alkenyl or alkynyl (R 5 -R 10 may be the same or different). Examples include, but are not limited to, where each of R5-R10 are a hydrogen; where R 5 , R7 and R9 are each a hydrogen and R 6 , R 8 and Rio are each independently a C 2 -C 4 straight or branched alkenyl or alkynyl; and where each of R 5 -R 10 is a C 2 -C 4 straight or branched chain alkenyl or alkynyl.
  • the heterocyclic monomer unit is a saturated or unsaturated disilacyclobutane (C 2 Si 2 ) with optional side chains on the silicon atoms such as described.
  • each of R 5 -R 10 is individually selected from vinyl, propenyl, butenyl, ethynyl and propynyl.
  • one of R 5 -R 10 is a hydrogen
  • the other of R 5 -R 10 is independently selected from a straight or branched chain alkenyl or alkynyl such as vinyl, propenyl, butenyl, ethynyl and propynyl.
  • two of R 5 , R5, and R 7 are a hydrogen and the other of R 5 - R 10 is individually selected from a straight or branched alkenyl or alkynyl such as propenyl, butenyl, ethynyl or propynyl.
  • the carbosilane units are directly linked to form C-Si bonds or Si-Si bonds with no intermediates, such as oxygen there between.
  • the resulting carbosilane polymer contains minimal oxygen such as an oxygen content of two percent or less.
  • Figure 1 illustrates a cross-linking of two similar carbosilane units to form an oligomer (a homo-oligomer). The cross-linking is directly through the reactive functional groups (e.g., R 1 -R 10 ).
  • Figure 2 illustrates a cross-linking according to another embodiment involving two dissimilar carbosilane units (monomer units to form a co- oligomer).
  • a silicon to carbon ratio in the resulting polycarbosilane polymer may be varied.
  • Figure 3 presents a flow chart of a method of forming a SiC film.
  • the carbosilane units are combined to form an oligomer or polymer precursor or short chain polymer (block 310, Figure 3).
  • Polymer synthesis includes dehydrogenative coupling involving two silane molecules coupling to form Si-Si bonds eliminating hydrogen gas.
  • Hydrosilation is another process involving the insertion of a Si-H bond across unsaturated bonds such as alkynes, alkynes, carbonyls and a means to form Si-C bonds.
  • a combination of dehydrogenative coupling and hydrosilation may be used to produce a polymer with Si-C and Si-Si bonds.
  • a polymerization reaction employs a catalyst such as a homogenous catalyst including, but not limited to, rhodium (Rh), platinum (Pt), ruthenium (Ru), zirconium (Zr) and Lewis acids at relatively low catalyst loadings (e.g., 0.05-5 mol %).
  • a heterogeneous catalyst such as a transition metal or metals (e.g., Rh and/or Pt) supported on a substrate may also be used.
  • a heterogeneous catalyst allows purification of the catalyst from the polymer following the polymerization reaction as such catalysts are, for example, a solid that may be separated from a solution of the polymer by filtration.
  • Purification can be improved using metals scavengers, silica gel or alumina that lower metal contaminations to few parts per billion.
  • the polymerization of the carbosilane units produces a solution including oligomers of cross-linked carbosilane units (polymer precursors or short chain polymers) (block 320, Figure 3).
  • the oligomers and short chain polymers may be cross-linked further after being applied to a substrate.
  • oligomers and short chain polymers are combined with a solvent such as toluene to form a solution.
  • the solution is applied to a substrate by a spin coating process to define a film of a desired thickness (block 330, Figure 3).
  • the composition is subject to a cure process to drive off the solvent and further polymerize the oligomers and short chain polymers (block 340, Figure 3).
  • Representative cure processes include, but are not limited to, a rapid thermal anneal, a high pressure anneal, a reactive gas anneal (e.g., oxygen, ammonia, silane, hydrogen, hydrogen/nitrogen, ethylene, acetylene or ultraviolet (UV) radiation, electron beam radiation, and a remote or direct plasma).
  • a catalyst such as the homogeneous catalysts listed including, but not limited to, rhodium (Rh), platinum (Pt), ruthenium (Ru), zirconium (Zr) and Lewis acids may be incorporated into the silicon carbide film during the cure.
  • the following table presents representative cure conditions for representative cure processes to cure a SiC film:
  • Figure 4 shows a cross-sectional side view of a portion of a substrate having a device layer, metallization to the device layer and a dielectric film on the metallization including SiC as a hard mask.
  • Substrate 410 is, for example, a semiconductor substrate such as a bulk semiconductor substrate (e.g., bulk silicon substrate) or a silicon on insulator (SOI) substrate.
  • SOI silicon on insulator
  • device layer 415 of, for example, transistor devices (e.g., hundreds of thousands to millions of transistor devices) and possibly other devices (e.g., capacitors resistors, etc.).
  • dielectric layer 417 such as an initial interlayer dielectric (ILDO) of silicon dioxide or a material having a dielectric constant less than silicon dioxide (a low-k material).
  • ILDO initial interlayer dielectric
  • contacts to ones of devices in device layer 415 are, for example, a series of metal lines or traces (e.g., copper traces) between device contacts that form circuits and transmit power throughout a substrate area.
  • dielectric material 430 patterned to be disposed on lines or traces of metal layer 420.
  • hard mask 425 Disposed between openings in dielectric material 430 is hard mask 425 of, for example, a SiC film formed as described above.
  • dielectric material 430 is a material having etch characteristics different than hard mask 425 for a particular etchant.
  • a representative material is silicon nitride.
  • dielectric material 430 may be selectively etched relative to hard mask 425.
  • dielectric material 430 may be selectively removed relative to hard mask 425 to expose lines or traces of metal layer 420 to allow electrically conductive interconnects to be connected to the lines or traces.
  • SiC film such as a described herein as a mask in integrated circuit processing.
  • an SiC material deposited by spin coating may be used in multiple patterning techniques such as self-aligned double patterning to enhance feature density.
  • Figure 5 shows a cross-sectional schematic side view of an example semiconductor structure configured with a low-k interlayer dielectric in accordance with one embodiment of the present invention.
  • This example case includes a metal oxide semiconductor (MOS) transistor formed on substrate 500.
  • MOS metal oxide semiconductor
  • the transistor may be a planar configuration, or a non-planar configuration where the depicted side-view cross- section is taken parallel along a body or fin surrounded by dielectric material on the substrate.
  • any number of semiconductor devices may employ a low-k SiC dielectric or insulator material as described herein, and the disclosure is not intended to be limited to any particular type of integrated circuit.
  • a gate stack is formed over a channel region of the device, and includes gate dielectric layer 502, gate electrode 504, and optional hardmask 506. Spacers 510 are formed adjacent to the gate stack.
  • Gate dielectric 502 can be, for example, any suitable oxide such as silicon dioxide (Si0 2 ) or a high-k gate dielectric materials.
  • high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • the thickness of gate dielectric 502 should be sufficient to electrically isolate gate electrode 504 from the source and drain contacts.
  • high-k gate dielectric layer 502 may have a thickness in the range of 5 A to around 100 A thick (e.g., 10 A).
  • gate electrode 504 can be, for example, polysilicon, silicon nitride, silicon carbide, or a metal layer (e.g., tungsten, titanium nitride, tantalum, tantalum nitride) although other suitable gate electrode materials can be used as well.
  • Optional gate hard mask layer 506 can be used to provide certain benefits or uses during processing, such as protecting gate electrode 504 from subsequent etch and/or ion implantation processes.
  • Hard mask layer 506 may be formed using typical hard mask materials, such as such as silicon dioxide, silicon nitride, and/or other conventional insulator materials.
  • the gate stack can be formed as conventionally done or using any suitable custom techniques (e.g., conventional patterning process to etch away portions of the gate electrode and the gate dielectric layers to form the gate stack).
  • Each of gate dielectric 502 and gate electrode 504 may be formed, for example, using conventional deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), spin-on deposition (SOD), or physical vapor deposition (PVD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • SOD spin-on deposition
  • PVD physical vapor deposition
  • gate dielectric 502 and gate electrode 504 materials may be thermally grown.
  • any number of other suitable materials, geometries, and formation processes can be used to implement an embodiment of the present invention, so as to provide a
  • Spacers 510 may be formed, for example, using conventional materials such as silicon oxide, silicon nitride, or other suitable spacer materials.
  • the width of the spacers SIO may generally be chosen based on design requirements for the transistor being formed.
  • substrate 500 can be used to implement substrate 500, including bulk substrates, semiconductors-on-insulator substrates (XOI, where X is a semiconoductor material such as silicon, germanium, or germanium-enriched silicon), and multi-layered structures, including those substrates upon which fins or nanowires can be formed prior to a subsequent gate patterning process.
  • substrate 500 is a germanium or silicon or SiGe bulk substrate, or a germanium or silicon or SiGe on oxide substrate.
  • the example device also includes source/drain regions 512, which may be p-type or n-type.
  • source/drain regions 512 may be p-type or n-type.
  • the composition, doping, and geometry of source/drain regions 512 will vary depending on factors such as the composition of substrate 500, polarity of the device, the use of grading for lattice
  • source/drain regions 512 are implemented with doped silicon or silicon germanium. Liners and/or buffer layers may be provided as well, as sometimes done.
  • source/drain regions 512 are implemented with a raised configuration and include source/drain extensions 512A or so- called tip regions in relatively close proximity to the channel region so as to impart a larger hydrostatic stress on the channel.
  • Other embodiments may include tip regions implemented with a diffusion-based process where the tip regions generally do not induce a strain on the channel region.
  • the channel may be strained or unstrained, and the source/drain regions may or may not include tip regions formed in the area between the corresponding source/drain region and the channel region.
  • the claimed invention is not intended to be limited to any particular such structural features. Rather, any number of transistor structures and types can benefit from employing a low-k dielectric as described herein.
  • the device includes insulator layer 514 that has been deposited and then planarized down to hard mask 506.
  • Insulator layer 514 may be formed, for example, using low-k dielectric (insulator) materials as provided herein.
  • insulator layer 514 is some- times referred to as an interlayer dielectric (ILD), and provides electrical insulation between the source/drain and gate electrodes, as well as between neighboring devices.
  • ILD interlayer dielectric
  • hard mask 506 or spacers 510 are a low-k SiC dielectric material and insulator layer 514 is selected of another low-k dielectric material other than SiC.
  • the example embodiment of Figure 5 further includes contact resistance reducing metal 516, which in some embodiments include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum or nickel-aluminum, and/or other such resistance reducing metals or alloys.
  • Contact plug metal 518 which in some embodiments includes aluminum or tungsten, although any suitably conductive contact metal or alloy can be used, such as silver, nickel-platinum or nickel-aluminum or other alloys of nickel and aluminum, or titanium, using conventional deposition processes.
  • Metalization of the source/drain contacts can be carried out, for example, using a silicidation process (gener- ally, deposition of contact metal and subsequent annealing).
  • Figure 6 shows a cross-section side view of an example semiconductor structure configured with a low-k interlayer dielectric in accordance with another example
  • FIG. 6 is drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines.
  • This example semiconductor structure includes substrate 610 with multiple layers of dielectric (ILD 614A and ILD 614B) and inter-connect metal (metal (Ml) 618 A and via 618B) formed thereon, with various devices formed in the substrate and some of the layers (such as device 61 OA, device 61 OB and device 6 IOC), which can be, for example, transistors, diodes, capacitors, inductors or any other passive and/or active devices).
  • ILD 614A and ILD 614B inter-connect metal
  • Ml metal
  • FIG. 6 is drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines.
  • This example semiconductor structure includes substrate 610 with multiple layers of dielectric (ILD 614A and ILD 614B) and inter-connect metal (metal (Ml) 618 A and via 618B) formed thereon, with various devices formed
  • the dielectric material of ILD 614A and ILD 614B can be implemented with low-k SiC dielectric material as described herein and can be used, for example, to separate conductors from other conductors, or conductors from devices, or devices from devices, etc.
  • the semiconductor configurations that can utilize such dielectric materials as provided herein are effectively unlimited, and Figures 5-6 are merely provided as examples only and are not intended to limit the disclosure. Factors such as etch selectivity, desired electrical isolation, and/or distance between conductive features to be isolated can be considered in implementing a given configuration.
  • Interposer 700 is an intervening substrate used to bridge a first substrate 702 to second substrate 704.
  • First substrate 702 may be, for instance, an integrated circuit die.
  • Second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • interposer 700 may connect an integrated circuit die to ball grid array (BGA) 706 that can subsequently be connected to second substrate 704.
  • BGA ball grid array
  • first and second substrates 702/704 are attached to opposing sides of interposer 700.
  • first and second substrates 702/704 are attached to the same side of interposer 700.
  • three or more substrates are interconnected by way of interposer 700.
  • Interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 712.
  • Interposer 700 may further include embedded devices 714, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 700.
  • RF radio- frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 700.
  • Figure 8 illustrates computing device 800 in accordance with one embodiment.
  • Computing device 800 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a SoC die.
  • SoC system-on-a-chip
  • computing device 800 includes, but are not limited to, integrated circuit die 802 and at least one communication chip 808.
  • communication chip 808 is fabricated as part of integrated circuit die 802.
  • Integrated circuit die 802 may include CPU 804 as well as on-die memory 806, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).
  • eDRAM embedded DRAM
  • STTM or STTM-RAM spin-transfer torque memory
  • Computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.
  • volatile memory 810 e.g., DRAM
  • non-volatile memory 812 e.g., ROM or flash memory
  • graphics processing unit 814 GPU
  • digital signal processor 816 crypto processor 842 (a specialized processor that executes cryptographic algorithms within hardware)
  • chipset 820 antenna 822, display or a touchscreen display 824, touchscreen controller 826, battery 828 or other power source
  • a power amplifier not shown
  • global positioning system (GPS) device 844 global positioning system (GPS) device 844
  • compass 830 motion coprocessor or sensors 832 (that may include an accelerometer, a gyroscope, and a compass)
  • speaker 834 camera 836
  • user input devices 838 such as a keyboard, mouse, stylus, and touchpad
  • mass storage device 840 such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • Communications chip 808 enables wireless communications for the transfer of data to and from computing device 800.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • Communication chip 808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • Computing device 800 may include a plurality of communication chips 808. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second
  • communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • Processor 804 of computing device 800 includes dielectric material isolating or masking electrical conductors and devices such as low-k SiC materials formed in accordance with embodiments presented above.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • Communication chip 808 may also include dielectric material isolating or masking electrical conductors and devices such as low-k SiC materials formed in accordance with embodiments presented above.
  • computing device 800 may contain dielectric material isolating or masking electrical conductors and devices such as low-k SiC materials formed in accordance with implementations presented above.
  • computing device 800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • computing device 800 may be any other electronic device that processes data.
  • Example 1 is a dielectric film on a integrated circuit substrate including cross-linked carbosilane units selected from linear monomer units or at least one linear monomer unit and at least one heterocyclic monomer unit, wherein the linear monomer units include a C 2 to C 8 straight or branched alkenyl or alkynyl and the at least one heterocyclic monomer unit includes a saturated or unsaturated moiety including an even numbered ring structure of alternating silicon and carbon atoms.
  • Example 2 the linear monomer unit of the dielectric film of Example 1 includes a general formula:
  • Ri, R 2 , R 3 and R4 are each individually selected of a hydrogen or a C2-C4 straight or branched alkenyl or alkynyl, with the proviso that when one of Ri, R 2 , R 3 and R 4 is a hydrogen, no more than another of Ri, R 2 , R 3 and R4 is a hydrogen.
  • the at least one heterocyclic monomer unit of the dielectric film of Example 1 or 2 includes a general formula:
  • R 5 , 5 and R 7 are each individually selected of a hydrogen or a C 2 -C 4 straight or branched alkenyl or alkynyl.
  • the heterocyclic monomer unit of the dielectric film of Example 3 is saturated.
  • Example 5 an amount of oxygen atoms in the dielectric film of any of Examples 1- 4 is two percent or less.
  • Example 6 the monomer units of the dielectric film of any of Examples 1-4 are directly linked.
  • Example 7 the carbosilane units of the dielectric film of any of Examples 1-4 are different.
  • Example 8 is an integrated circuit including a dielectric film disposed on a substrate including a plurality of integrated circuit devices, the film included of cross-linked carbosilane units selected from linear monomer units or at least one linear monomer unit and at least one heterocyclic monomer unit, wherein the linear monomer units include a C 2 to C 8 straight or branched alkenyl or alkynyl and the at least one heterocyclic monomer unit includes a saturated or unsaturated moiety including an even numbered ring structure of alternating silicon and carbon atoms.
  • Example 9 the linear monomer unit of the device of Example 8 includes a general formula:
  • Ri, R 2 , R 3 and R4 are each individually selected of a hydrogen or a C2-C4 straight or branched alkenyl or alkynyl, with the proviso that when one of Ri, R 2 , R 3 and R 4 is a hydrogen, no more than another of Ri, R 2 , R 3 and R4 is a hydrogen.
  • the at least one heterocyclic monomer unit of the device of Example 8 includes a general formula:
  • R 5 , 5 and R 7 are each individually selected of a hydrogen or a C 2 -C 4 straight or branched alkenyl or alkynyl.
  • Example 11 the heterocyclic monomer unit of the device of Example 10 is saturated.
  • Example 12 an amount of oxygen atoms in the dielectric film of the device of Example 8 is two percent or less. In Example 13, the monomer units of the device of Example 8 are directly linked.
  • Example 14 the dielectric film of any of Examples 1-6 is a hard mask layer.
  • Example 15 is a method of forming a dielectric film including combining a first carbosilane unit with a second carbosilane unit wherein the first carbosilane unit and the second carbosilane unit are each selected from linear monomer units or one linear monomer unit and one heterocyclic monomer unit and the linear monomer unit includes a C 2 to C 8 straight or branched alkenyl or alkynyl and the one heterocyclic monomer unit includes a saturated or unsaturated moiety including an even numbered ring structure of alternating silicon and carbon atoms; and depositing the combination on a substrate; cross-linking the combination to form a dielectric film.
  • Example 16 combining a first carbosilane unit with a second carbosilane unit in the method of Example 15 includes stimulating an oligomerization of the first carbosilane unit with the second carbosilane unit with a catalyst.
  • Example 17 the catalyst of the device of Example 16 includes a transition metal catalyst.
  • the catalyst of the device of Example 17 includes a heterogenous transition metal catalyst.
  • Example 19 the catalyst of the device of Example 16 includes a Lewis acid.
  • Example 20 after combining and prior to depositing the combination on the substrate, the method of any of Examples 15-19 includes removing a portion of the catalyst from the combination.
  • cross-linking of the method of any of Examples 15-20 includes annealing the combination.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

L'invention concerne un film diélectrique, un dispositif comprenant un film diélectrique et un procédé de formation d'un film diélectrique sur un substrat de circuit intégré, le film diélectrique comprenant des unités de carbosilane réticulé choisies parmi des unités monomères linéaires ou au moins une unité monomère linéaire et au moins une unité monomère hétérocyclique, les unités monomères linéaires comprenant un alcényle ou un alcynyle linéaire ou ramifié en C2 à C8 et l'au moins une unité monomère hétérocyclique comprenant une fraction saturée ou insaturée comprenant un nombre pair de structure cyclique d'atomes de silicium et de carbone alternés.
PCT/US2016/069465 2016-12-30 2016-12-30 Synthèse de polycarbosilanes et de derivitisation en matériau de remplissage sic haute densité Ceased WO2018125201A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050182151A1 (en) * 1999-06-07 2005-08-18 Paul Apen Low dielectric constant polyorganosilicon materials generated from polycarbosilanes
US20120161295A1 (en) * 2010-12-23 2012-06-28 Michalak David J Cyclic carbosilane dielectric films
US20130320520A1 (en) * 2011-12-22 2013-12-05 David J. Michalak Chemically altered carbosilanes for pore sealing applications
US20140004358A1 (en) * 2012-06-28 2014-01-02 James M. Blackwell Low k carbosilane films
US20140038427A1 (en) * 2011-09-13 2014-02-06 Timothy W. Weidman Carbosilane Precursors For Low Temperature Film Deposition

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050182151A1 (en) * 1999-06-07 2005-08-18 Paul Apen Low dielectric constant polyorganosilicon materials generated from polycarbosilanes
US20120161295A1 (en) * 2010-12-23 2012-06-28 Michalak David J Cyclic carbosilane dielectric films
US20140038427A1 (en) * 2011-09-13 2014-02-06 Timothy W. Weidman Carbosilane Precursors For Low Temperature Film Deposition
US20130320520A1 (en) * 2011-12-22 2013-12-05 David J. Michalak Chemically altered carbosilanes for pore sealing applications
US20140004358A1 (en) * 2012-06-28 2014-01-02 James M. Blackwell Low k carbosilane films

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