WO2018125105A1

WO2018125105A1 - Templating of complex oxides for ferroelectric and magnetoelectric integration

Info

Publication number: WO2018125105A1
Application number: PCT/US2016/069023
Authority: WO
Inventors: Sasikanth Manipatruni; Chia-Ching Lin; Jasmeet S. Chawla; Dmitri E. Nikonov; Ian A. Young
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-12-28
Filing date: 2016-12-28
Publication date: 2018-07-05
Anticipated expiration: 2019-06-28

Abstract

An apparatus is provided which comprises: a multiferroic layer having an ordered crystalline structure; and a crystallinity templating layer adjacent to the multiferroic layer, wherein the crystallinity templating layer comprises a material which includes one of: MgO, MgAlO, c-Al₂O₃, InSnO, or Ag; and wherein the multiferroic layer comprises a material which includes one of: LuFe₂O₄, LuFeO₃, Lu₂O₃, h-LuFeO₃, Fe₂O₃, Fe₃O₄, BiFeO₃, Nd-BiFeO₃, layers of Pt and BiFeO₃, or layers of Pt and Nd-BiFeO₃.

Description

TEMPLATING OF COMPLEX OXIDES FOR FERROELECTRIC AND

MAGNETOELECTRIC INTEGRATION

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (i.e., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 micro- Ampere per bit

(μΑ/bit)) and voltage (e.g., greater than 0.7 volts (V)) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO). Ferroelectric and multiferroic materials can be used for building non-volatile logic. Ferroelectric and multiferroic materials are used for

ferroelectricity, ferro-magnetism, and/or multiferroic behavior. These materials require the use of crystalline and/or poly crystalline materials. However, developing consistent crystalline structures for these materials is a challenge.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates a magnetization response to applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates a magnetization response to applied magnetic field for a paramagnet. [0006] Fig. 1C illustrates a magnetization response to applied voltage field for a paramagnet connected to a magnetoelectric layer.

[0007] Fig. 2A illustrates a perpendicular magnetoelectric spin orbit logic (SOL), according to some embodiments of the disclosure.

[0008] Fig. IB illustrates a spin orbit material stack of an interconnect, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0010] Fig. 3 illustrates a material stack for multiferroic deposition on a backend of a semiconductor die, according to some embodiments of the disclosure.

[0011] Fig. 4 illustrates a cross-section of a templated multiferroic conductive via, according to some embodiments of the disclosure.

[0012] Fig. 5 illustrates a backend material stack for Bismuth Ferrite (BFO) with platinum (Pt) electrodes, according to some embodiments of the disclosure.

[0013] Fig. 6 illustrates a cross-section of a super lattice backend with a templating layer, according to some embodiments of the disclosure.

[0014] Figs. 7A-G illustrate cross-sections of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure.

[0015] Figs. 8A-G illustrate cross-sections of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure.

[0016] Figs. 9A-D illustrate cross-sections of ferroelectric and/or ferromagnetic interconnect or vias with various templating configurations, in accordance with some embodiments of the disclosure.

[0017] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments.

DETAILED DESCRIPTION

[0018] The Magnetoelectric (ME) effect has the ability to manipulate the magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications.

Compared to in-plane magnets, perpendicular magnets generally allow for easier lithography constraints on the magnetic dots with reduced aspect ratio requirements for shape.

Perpendicular magnets (e.g., with out-of-plane magnetization) exhibit higher retention since the magnetic energy barrier is proportional to anisotropy. Another benefit of perpendicular magnets is that they provide greater choice perpendicular anisotropy and super-lattices.

[0019] Various embodiments describe a perpendicular Magnetoelectric Spin Orbit

(MESO) Logic which is a combination of four optimum physical phenomena for spin-to- charge and charge-to-spin conversion. In some embodiments, spin-to-charge conversion is achieved via a layer with the inverse Rashba-Bychkov effect (or spin Hall effect) wherein a spin current injected from an input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus by the direction of magnetization. In some embodiments, charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet. In some embodiments, magnetic response of a perpendicular magnet is via applied exchange bias from magnetoelectric effect. In some embodiments, a templated magnetoelectric oxide provides perpendicular exchange bias to the perpendicular magnet due to partially compensated anti-ferromagnetism.

[0020] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on perpendicular nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoule (aJ)) because the current needs to be "on" for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate in the interconnect.

[0021] In some embodiments, ferroelectric and ferromagnetic devices positioned in the backend of a device processing stack are templated using a templating material such as MgO. Some embodiments describe templated ferroelectric materials with Lutetium and Scandium iron oxides in the backend of the semiconductor chip. Some embodiments describe templated ferroelectric materials with BFO (e.g., BiFeC ) and Nd, and La doped BiFeC in the backend of the semiconductor chip. The templating material of various embodiments improves crystallinity for improving ferroelectric properties (e.g., high enough value of saturated ferroelectric polarization P_s, and low value of coercive electric E_c). The templating material of various embodiments improves crystallinity for improving multiferroic properties (e.g., high enough values of saturated ferroelectric polarization P_s,

antiferromagnetic order parameter L, and uncompensated magnetization M_c). The templating material of various embodiments can be used for forming vias for integrating ferroelectric and/or multiferroic materials. The templating material of various embodiments is such that it allows the use of non-magnetic metal interconnects (e.g., Cu) to couple with the templated ferroelectric and/or multiferroic materials. Other technical effects will be evident from various embodiments and figures.

[0022] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0023] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0024] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0025] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0026] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0027] The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0028] Fig. 1A illustrates a magnetization hysteresis plot 100 for a perpendicular ferromagnet 101. Plot 100 shows the magnetization response to applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field 'FT while the y-axis is

magnetization 'm'. For ferromagnet (FM) 101, the relationship between 'FT and 'm' is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturation magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetizations, but rather depends on the history of applied magnetic fields. For example, the magnetization of perpendicular FM 101 in region 105 can be either in the +y direction or the -y direction. As such, changing the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.

[0029] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to applied magnetic field for paramagnet 121. A paramagnet as opposed to a ferromagnet exhibits magnetization when a magnetic field is applied to it.

Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0030] Fig. 1C illustrates a plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132. Here, the x-axis is voltage 'V applied across ME layer 132 and y-axis is magnetization 'm'. Ferroelectric polarization PFE is in ME layer 132 and is indicated by the arrow in the ME layer 132. In this example, magnetization is driven by exchange bias exerted by a ME effect from ME layer 132. When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +y direction by voltage +V_C) as shown by configuration 136. When negative voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the -y direction by voltage -V_c) as shown by configuration 134. Plot 130 shows that magnetization functions 133a and 133b have hysteresis. In some embodiments, by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. The hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.

[0031] Fig. 2A illustrates a perpendicular magnetoelectric spin orbit logic (SOL) 200 using templated multiferroic material, according to some embodiments of the disclosure. Fig. 2B illustrates a material stack at the input from an interconnect, according to some embodiments of the disclosure. Fig. 2C illustrates a perpendicular magnetoelectric material stack at the output to an interconnect, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0032] In some embodiments, SOL 200 comprises a first magnet 201 with perpendicular magnetic anisotropy (PMA), a stack of layers (e.g., layers 202, 203, and 204) adjacent to first magnet 201, interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) layer 206, and second magnet 207 with PMA. In some embodiments, ME layer 206 is adjacent to second magnet 207. In some embodiments, conductor 205 is coupled to at least a portion of the stack of layers (201, 202, 203, 204) and ME layer 206. For example, conductor 205 is coupled to layer 204 of the stack. In some embodiments, a contact (not shown) is provided on top of first magnet 201, where the contact is used to connect to a transistor or any source that provides charge current. In some embodiments, the contact is formed of non-magnetic metal (e.g., Cu, Ag, etc.). In some embodiments, a non-magnetic metal layer (e.g., Cu, Ag, etc.) is sandwiched between first magnet 201 and the stack of layers.

[0033] In some embodiments, the stack of layers is to provide an inverse Rashba-

Bychkov effect (or inverse spin Hall effect). In some embodiments, the stack of layers provides spin-to-charge conversion where a spin current J_s or is injected from first magnet 201 (also referred to as the input magnet) and charge current I_c is generated by the stack of layers. This charge current I_c is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I_c depends on the direction of magnetization of first magnet 201. In some embodiments, the charge current I_c charges the capacitor around ME layer 206 and switches its polarization. ME layer 206 exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207.

[0034] In this example, the length of first magnet is L_m, the width of conductor 205 is

Wc, and the length of conductor 205 from the interface of layer 204 to ME layer 206 is L_c. In some embodiments, conductor 205 is formed of a material which includes one or more of: Cu, Ag, Al, or Au. In some embodiments, a transistor (e.g., p-type transistor MPl) is coupled to first magnet 201. In this example, the source terminal of MPl is coupled to a supply Vdd, the gate terminal of MPl is coupled to a control voltage V_ci (e.g., a switching clock signal that switches between Vdd and ground levels), and the drain terminal of MPl is coupled to first magnet 201. The current Idrive from transistor MPl causes first magnet 201 to generate spin current the stack of layers (e.g., layers 202, 203, and 204).

[0035] In some embodiments, ME layer 206 forms a magnetoelectric capacitor to switch PMA FM magnets. For example, the conductor 205 forms one plate of the capacitor, PMA FM magnet 207 forms the other plate of the capacitor, and layer 206 is the magnetic- electric oxide that provides out-of-plane exchange bias to PMA FM magnet 207. In some embodiments, the magnetoelectric oxide comprises perpendicular exchange bias due to partially compensated anti-ferromagnetism.

[0036] The first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202, 203, and 204). The spin polarization is determined by the magnetization of first magnet 201. In some embodiments, the injection stack comprises i) an interface 203 with a high density 2D (two dimensional) electron gas and with high SOC formed between materials 202 and 204 such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt. In some

embodiments, a spacer (or template layer) is formed between first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0037] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (i.e., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device.

[0038] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

In some embodiments, the spin-orbit mechanism responsible for spin-to-charge current conversion is described by the inverse Rashba-Bychkov effect in a 2D electron gases.

Positive currents along the +y axis produce a spin injection current with transport direction along the +z direction and spins pointing to the +z direction.

[0039] The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

H_R = a_R(kxx). a

where a_Ris the Rashba coefficient, 'k' is the operator of momentum of electrons, x is a unit vector along the gradient of the potential at the surface, and σ is the operator of spin of electrons. This results in the generation of a charge current I_c in interconnect 205 proportional to the spin current (or J_s). The spin-orbit interaction by Ag and Bi interface layers (e.g., the Inverse Rashba-Bychkov Effect (IRBE)) produces a charge current I_c in the horizontal direction given as:

. _ ^_IRBEI_S

W_m

where w_m is width of the input magnet 201, and _IRYE is the IRYE constant (with units of length) proportional to a_R.

[0040] IRBE effect produces spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. The net conversion of the drive charge current Idrtve to magnetization dependent charge current is given as:

j _ _|_ }RBE^PId

c — W_m

where 'P' is the dimensionless spin polarization. For this estimate, the drive current Idrtve (Id) and the P signal charge current I_c = I_d = 100 μΑ is set. Estimating the resistance of the ISHE interface to be equal to R = 100 Ω, then the induced voltage is equal to V_ISHE = 10 mV.

[0041] The charge current I_c, carried by interconnect 205, produces a voltage on the capacitor of ME layer 206 comprising templated magnetoelectric material dielectric (such as BiFeC (BFO) or CrcC ) in contact with second magnet 207 (which serves as one of the plates of the capacitor). In some embodiments, templated magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures. As the charge accumulates on the magnetoelectric capacitor of ME layer 206, a strong magnetoelectric interaction causes the switching of magnetization in second magnet 207. For the following parameters of the magnetoelectric capacitor: thickness t_ME = Snm, dielectric constants = 500, area A = 60nm x 20nm. Then the capacitance is given as:

C =—2- « IfF

tME

[0042] Demonstrated values of the magnetoelectric coefficient is a_ME~10/c , where the speed of light is c. This translates to the effective magnetic field exerted on the nanomagnets, which is expressed as:

BME = a_MEE = ^aMEV,SHE ~0,06Γ

^ME

This is a strong field sufficient to switch magnetization.

[0043] The charge on the capacitor of ME layer 206 is Q =— x lO mV = 10 aC, and the time to fully charge it to the induced voltage is the induced voltage is td = 10 Q/I_d~l ps (with the account of decreased voltage difference as the capacitor charges). If the driving voltage is V_d = 100 mV, then the energy E_sw to switch is expressed as:

£_sw~100 m^x lOO μΑχΙ ps~10 a]

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t_sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t_sw~100 ps, for example. In some embodiments, a non-magnetic electrode (e.g., Cu) is formed and coupled to layer 204 to provide a connection to a supply (e.g., ground or Vdd). In some embodiments, the sideways section of conducting interconnect 205 is aligned with the interface between layer 202 and 204 to capture sideways IRBE current.

[0044] In some embodiments, materials for first and second magnets 201 and 207 have saturated magnetization M_s and effecting anisotropy field Hk. Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material (i.e., total magnetic flux density B substantially levels off). Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with Hk are materials with material properties that are highly directionally dependent. In some embodiments, a top contact is attached to magnet 201.

[0045] In some embodiments, materials for first and second magnets are paramagnets

201 and 207. Paramagnets are non-ferromagnetic elements with strong paramagnetism materials which have high number of unpaired spins but are not room temperature ferromagnets.

[0046] In some embodiments, first and second paramagnets 201 and 207 comprise a material which includes one or more of: Platinum (Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCb

(chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), Er203 (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd203), FeO and Fe203 (Iron oxide), Neodymium (Nd), Nd203

(Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), Srri203 (samarium oxide), Terbium (Tb), Tb203 (Terbium oxide), Thulium (Tm), T1T12O3 (Thulium oxide), and V2O3 (Vanadium oxide).

[0047] In some embodiments, the first and second paramagnets 201 and 207 comprise dopands which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, and Yb. The relaxation time of a paramagnet is enhanced (e.g., made shorter) by doping with materials with stronger dissipation elements to promote Spin-lattice relaxation time (Ti) and Spin-spin relaxation time (T2). Here, the term "Spin-lattice relaxation time (Ti)" generally refers to the mechanism by which the component of the magnetization vector along the direction of the static magnetic field reaches thermodynamic equilibrium with its surroundings. Here, the term "Spin-spin relaxation time (T₂)" generally refers to a spin-spin relaxation is the mechanism by which, the transverse component of the magnetization vector, exponentially decays towards its equilibrium value.

[0048] In some embodiments, first and second magnets 201 and 207 are free ferromagnets that are made from CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, first and second magnets 201 and 207 are free magnets that are formed from Heusler alloy (s). Heusler alloy is ferromagnetic metal alloy based on a Heusler phase. Heusler phase is intermetallic with certain composition and face-centered cubic (FCC) crystal structure. The ferromagnetic property of the Heusler alloy is a result of a double-exchange mechanism between neighboring magnetic ions.

[0049] In some embodiments, first and second magnets 201 and 207 are Heusler alloy lattices matched to Ag (i.e., the Heusler alloy is engineered to have a lattice constant close (e.g., within 3%) to that of Ag or to a rotated lattice). In some embodiments, the direction of the spin polarization is determined by the magnetization direction of first magnet 201. In some embodiments, the magnetization direction of second magnet 207 depends on the direction of the strain provided by ME layer 206, which in turn depends on the direction of an input charge current Icharge (IN).

[0050] In some embodiments, first and second magnets 201 and 207 include one or more of: Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them. In some embodiments, Heusler alloys that form first and second magnets 201 and 207 include one or more of: Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, PdJVInAl, PdJVInln, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, or MnGaRu.

[0051] In some embodiments, the thickness t_c of first and second magnets 201 and

207 may determine its magnetization direction. For example, when the thickness of a ferromagnetic layer is above a certain threshold (depending on the material of the magnet, e.g., approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane. Likewise, when the thickness of the ferromagnetic layer is below a certain threshold (depending on the material of the magnet), then the ferromagnetic layer exhibits magnetization direction which is perpendicular to the plane of the magnetic layer. Other factors may also determine the direction of magnetization. Here, first and second magnets 201 and 207 have out-of-plane magnetization (e.g., pointing in the +/- z-direction).

[0052] For example, factors such as surface anisotropy (depending on the adjacent layers or a multi-layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic) lattice, BCC (body centered cubic) lattice, or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.

[0053] In some embodiments, first and second magnets 201 and 207 are magnetized perpendicular to the plane of the chip having apparatus 200. In some embodiments, first and second magnets 201 and 207 with PMA are formed with multiple layers in a stack. The multiple thin layers can be layers of Cobalt and Platinum (i.e., Co/Pt), for example. Other examples of the multiple thin layers include: Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, MgO; Mn_xGa_y; Materials with Llo crystal symmetry; or materials with tetragonal crystal structure. In some embodiments, the perpendicular magnetic layer is formed of a single layer of one or more materials. In some embodiments, the single layer is formed of MnGa. In some embodiments, the perpendicular magnetic layer includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, YIG (Yttrium iron garnet), or a combination of them.

[0054] In some embodiments, the stack of layers comprises a first layer 202 comprising Ag, wherein first layer 202 is adjacent to first magnet 201; and a second layer 204 comprising a material or a hetero-structure which provided Rashba-Bychkov effect, wherein second layer 204 is adjacent to first layer 202 and to conductor 205. In some embodiments, layers 203 and 204 comprise two-dimensional materials (2D) with spin orbit interaction. In some embodiments, the 2D materials include one or more of: Mp, S, W, Se, Graphene, M0S2, \VSe2, WS2, or MoSe2. In some embodiments, the 2D materials include an absorbent which includes one or more of: Cu, Ag, Pt, Bi, Fr, or H absorbents.

[0055] In some embodiments, a third layer 203 is sandwiched between first layer 202 and second layer 204 as shown. The third layer 203 may be formed of special materials with the Rashba-Bychkov effect. In some embodiments, layer 203 comprises materials ROCI12, where 'R' includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where "Ch" is a chalcogenide includes one or more of: S, Se, or Te. In some embodiments, layer 202 and 204 are layers that form hetero-structure with Cu, Ag, Al, and/or Au. In some embodiments, the stack of layers comprises a material which includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0056] In some embodiments, ME layer 206 is formed of a material includes one or more of: CnC or multiferroic material. In some embodiments, ME layer 206 comprises Cr and O. In some embodiments, the multiferroic material comprises BiFeC . In some embodiments, ME layer 206 comprises magnetoelectric perovskites having output out-of- plane remnant magnetization. In some embodiments, the magnetoelectric perovskites comprise a material which includes one or more of: BFO, La-BFO, or Ce-BFO. In some embodiments, ME layer 206 comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity. In some embodiments, the magnetoelectric layer comprises a material which includes one or more of: CnO and B-CnC .

[0057] In various embodiments, the material that forms ME layer 206 is a templated material. For example, templated ferroelectric materials with Lutetium and scandium iron oxides are used for forming ME layer 206. In another example, templated ferroelectric materials with Nd doped BiFeCb or La doped BiFeC is used for forming ME layer 206. In some embodiments, templating material is part of the templated material. Figs. 3-6 illustrate various material stacks for templated multiferroic materials that can be used for ME layer 206. The same templated material stacks can also be used for forming interconnects and via of those materials, in accordance with some embodiments. Fabrication of various ferroelectric and/or multiferroic material based interconnect and vias are described with reference to Figs. 7-8.

[0058] Fig. 3 illustrates a cross-section of material stack 300 for multiferroic deposition on a backend, according to some embodiments of the disclosure. In some embodiments, material stack 300 comprises templating material 301 and multiferroic or ferroelectric material 302. In some embodiments, material stack 300 may be also include backend 303 of the wafer. In some embodiments, templating material 301

[0059] In some embodiments, templating material 301 comprises one or more of:

MgO, MgAlO, C-AI2O3, InSnO, or Ag. In some embodiments, multiferroic or ferroelectric material 302 comprises one or more of: LuFe204, LuFeC , LU2O3, h-LuFeCb (e.g., hexagonal LuFeC ), Fe203, Fe304, BiFeC (Bismuth Ferrite also referred to as BFO), Nd-BiFeC (e.g., Nd doped BFO material), layers of Pt and BiFe03, and layers of Pt and Nd-BiFe03. In some embodiments, when deposited at appropriate conditions, MgO forms a crystalline substrate due to high stability of its crystalline phase. This highly stable crystalline substrate templates

Lutetium based multiferroic material, in accordance with some embodiments.

[0060] In some embodiments, templated ferroelectric materials (i.e., 301 and 302 together) with Lutetium and Scandium iron oxides in the backend of a semiconductor chip may comprise the following templating forming order: MgO and LuFe204, MgO and

LuFe03, MgO and LU2O3, and MgO and h-LuFe03, where MgO is templating material 301 and the material paired with MgO is the to-be templated material 302.

[0061] Table 1 illustrates a relationship of deposited MgO and ferroelectric (FE) material deposited on top. In this case, MgO templates the FE material.

Table 1

[0062] In some embodiments, InSnO is a conductive oxide which is used for templating LuFeO class of FE materials because InSnO has a crystalline structure that matches the crystalline structure of LuFeO class of FE materials. In this example, InSnO is templating layer 301 and the to-be templated material 302 are one or more of: LuFe204, LuFe03, Fe304, LU2O3, h-LuFe03, or Nd-BFO. As such, in some embodiments, a conductive template is provided for the formation of conducting vias for FE and multiferroic materials inside a backend via.

[0063] In some embodiments, to template Nd doped BFO (Nd-BFO), MgO with 45 degree axial rotation is used. In this example, MgO with 45 degree axial rotation is templating layer 301 and Nd doped BFO is to-be templated material 302.

[0064] In some embodiments, templated ferroelectric materials (i.e., 301 and 302 together) with Lutetium and Scandium iron oxides in the backend of a semiconductor chip may comprise the following templating forming order: MgAlO and LuFe204, MgAlO and LuFe03, MgAlO and LU2O3, and MgAlO and h-LuFe03, where MgAlO is templating material 301 and the material paired with MgAlO is the to-be templated material 302. [0065] In some embodiments, templated ferroelectric materials (i.e., 301 and 302 together) with Lutetium and Scandium iron oxides in the backend of a semiconductor chip may comprise the following templating forming order: C-AI2O3 and LuFe204, C-AI2O3 and LuFeC , C-AI2O3 and LU2O3, and C-AI2O3 and h-LuFeC , where C-AI2O3 is templating material 301 and the material paired with C-AI2O3 is the to-be templated material 302.

[0066] In some embodiments, templated ferroelectric materials (i.e., 301 and 302 together) with Fe and Co oxides in the backend of a semiconductor chip may comprise the following templating forming order: MgO and Fe203, MgAlO and Fe203, C-AI2O3 and Fe203, MgO and Fe304, MgAlO and Fe304, and C-AI2O3 and Fe304.

[0067] In some embodiments, templated ferroelectric and multiferroic materials (i.e.,

301 and 302 together) with Nd doped BFO or La doped BFO may comprise the following templating forming order: MgO and BiFe03, MgAlO and BiFe03, C-AI2O3 and BiFe03, MgO and Nf-BiFe0₄, MgAlO and Nd-BiFe0₄, and C-AI2O3 and Nd-BiFe0₄.

[0068] In some embodiments, templated ferroelectric and multiferroic materials (i.e.,

301 and 302 together) with Nd doped BFO or La doped BFO with Pt insert may comprise the following templating forming order: MgO followed by Pt and BiFe03, MgAlO followed by Pt and BiFe0₃, C-AI2O3 followed by Pt and BiFe0₃, MgO followed by Pt and Nf-BiFe0₄, MgAlO followed by Pt and Nd-BiFe0₄, and C-AI2O3 followed by Pt and Nd-BiFe0₄.

[0069] In some embodiments, templating layer 301 is deposited using DC (direct current) deposition. For example, when templating layer 301 comprises MgO, DC deposition of Mg is followed by oxygen flow. In some embodiments, RF (radio frequency) deposition of MgO is performed at cryogenic low temperature followed by annealing. In some

embodiments, DC deposition Mg with oxygen flow is performed at cryogenic low temperature followed by annealing.

[0070] Fig. 4 illustrates cross-section 400 of a templated multiferroic conductive via, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0071] In some embodiments, multiferroic conductive via 402 can be formed by using conductive templating materials 401a on top and bottom of via 402. In some embodiments, the InSnO is a conductive oxide 401a which is used for templating LuFeO class of FE materials 402 because InSnO has a crystalline structure that matches the crystalline structure of LuFeO class of FE materials. The to-be templated material 402 can also be one of:

LuFe204, LuFe03, Fe304, LU2O3, h-LuFe03, or Nd-BFO, in accordance with some embodiments. As such, in some embodiments, a conductive template is provided for the formation of conducting vias for FE and multiferroic materials inside a backend via. In some embodiments, via 402 can be templated by one of top or bottom templating layers 401a (e.g., both 401a layers may not be needed to template in some cases).

[0072] Fig. 5 illustrates a cross-section of a backend material stack 500 for BFO with platinum (Pt) electrodes, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In some embodiments, material stack 500 comprises a stack of templating materials 501a and 501b which are used to template a ferroelectric and/or multiferroic material. In some embodiments, templating material 501a comprises one of MgO, MgAlO, and C-AI2O3. In some embodiments, templating material 501b comprises Pt. In some embodiments, the to-be templated material 502 is BFO (e.g., BiFeC ) or Nd doped BFO.

[0073] Fig. 6 illustrates cross-section 600 of super lattice backend with a templating layer, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0074] In some embodiments, templating layer 301 (e.g., one of MgO, MgAlO, c-

AI2O3, InSnO, or Ag) can be used to template a super lattice comprising layers 602a (e.g., LuFe20₄), 602b (e.g., LuFeOs), 602c (e.g., LuFe₂0₄), and 602d (e.g., Fe₃0₄). Any combination of FE and/or multiferroic materials discussed with reference to Fig. 3 can be used with the templating material 301 to form a super lattice of FE and/or multiferroic materials. These super lattice materials can be used in the backend of the die.

[0075] Figs. 7A-G illustrate cross-sections 700, 720, 730, 740, 750, 760, and 770, respectively, of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 7A-G having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0076] Although the fabrication processes with reference to Figs. 7A-G are shown in a particular order, the order of the actions can be modified. Thus, the illustrated

embodiments can be performed in a different order, and some actions/fabrication processes may be performed in parallel. Some of the fabrication processes listed in Figs. 2A-G are optional in accordance with certain embodiments. The numbering of the fabrication processes presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0077] Fig. 7A illustrates one example of a starting point. Here, the die cross-section

700 shows deposition of a layer of dielectric 701. In some embodiments, the dielectric is an oxide (e.g., SiC ) or a Si based substrate. In some embodiments, the process of fabricating the templated ferroelectric and/or multiferroic interconnect and vias can start at various points in the fabrication process as described with reference to various embodiments. Fig. 7B illustrates cross-section 720 of the die after deposition of ferroelectric and/or multiferroic layer 702a on layer 701. For example, a layer of LuFe204, LuFeCb, LU2O3, h-LuFeCb (e.g., hexagonal LuFeC ), Fe2Cb, Fe304, BiFeC (Bismuth Ferrite also referred to as BFO), Nd- BiFeCb (e.g., Nd doped BFO material), layers of Pt and BiFeCb, and layers of Pt and Nd- BiFeC is deposited on layer 701. This layer of ferroelectric and/or multiferroic 702a may initially have an unordered crystalline structure.

[0078] Here, the term unordered crystalline structure generally refers to a crystalline structure in which the electron wave diffraction is not defined by Bragg' s law. Unordered materials may exhibit high directional and angular isotropy without long range

spatial/directional periodicity. Unordered materials are characterized by a signature on a TEM (Transmission Electron Microscopy), STEM (Scanning Transmission Electron

Microscopy) or RHEED (Reflection High-Energy Electron Diffraction), XRD (X-ray Powder Diffraction) metrology.

[0079] Fig. 7C illustrates cross-section 730 of the die after deposition of a templating material 703 over ferroelectric and/or multiferroic layer 702a. Examples of templating material 703 include MgO, MgAlO, C-AI2O3, InSnO, and Ag. In some embodiments, after increasing temperature, e.g., to 298K, templating material 703 causes ferroelectric and/or multiferroic layer 702a to transform to ferroelectric and/or multiferroic layer 702b, where ferroelectric and/or multiferroic layer 702b has an ordered crystalline structure while ferroelectric and/or multiferroic layer 702a has an unordered crystalline structure. In some embodiments, ferroelectric and/or multiferroic layer 702a is Metal 0 (M0) layer. In other embodiments, ferroelectric and/or multiferroic layer 702a can be any metal layer of a process technology node.

[0080] Fig. 7D illustrates cross-section 740 of the die after templating material 703 is removed and dielectric layer 704 (e.g., layer of oxide) is deposited over ordered ferroelectric and/or multiferroic layer 702b. Here, the term "ordered" generally refers to material condition that shows electron wave diffraction as defined by Bragg' s law. Ordered material may be characterized by one of the space groups combined with a unit cell. Ordered material exhibit long range periodicity both in direction and displacement. In Metrology tools such as XRD and RHEED, an interferometric signature is evident for ordered materials.

[0081] In some embodiments, templating material 703 is a sacrificial layer which is removed after the crystalline structure of ferroelectric and/or multiferroic layer 702b is ordered to be ferroelectric and/or multiferroic layer 702a. In some embodiments, templating material 703 remains as is and further processing steps are performed above templating material 703.

[0082] In some embodiments, templating material 703 and ferroelectric and/or multiferroic layer 702a/b together form a pair of layers MgO and LuFe204, MgO and LuFe03, MgO and LU2O3, and MgO and h-LuFe03, MgAlO and LuFe204, MgAlO and LuFeOs, MgAlO and Lu₂0₃, and MgAlO and h-LuFe0₃, MgO followed by Pt and BiFeOs, MgAlO followed by Pt and BiFeOs, C-AI2O3 followed by Pt and BiFeOs, MgO followed by Pt and Nf-BiFe0₄, MgAlO followed by Pt and Nd-BiFe0₄, and C-AI2O3 followed by Pt and Nd-BiFe0₄.

[0083] In some embodiments, for the case of templating material 703 being MgO and ferroelectric and/or multiferroic layer 702a/b being Nd doped BFO a lattice of MgO is matched to a lattice of Co when rotated by 45°. In some embodiments, a crystalline axis of ferroelectric and/or multiferroic layer 702a/b is set by templating material 703.

[0084] Fig. 7E illustrates cross-section 750 of the die after trenches 705 are etched through dielectric layer 704. Any known suitable process of forming trenches 705 may be used. In this example, two trenches are etched (e.g., the left and right trenches) and each trench is a future location of a via to couple to ferroelectric and/or multiferroic layer 702b and a future location of another metal layer. In some embodiments, the other ferroelectric and/or multiferroic layer extends orthogonal to ferroelectric and/or multiferroic layer 702b. For example, ferroelectric and/or multiferroic layer 702b is metal layer 1 (Ml) and the other metal layer (later shown as 707) is metal layer 2 (M2).

[0085] Fig. 7F illustrates cross-section 760 of the die after templating material 706 is deposited along the outer walls of trenches 705. In some embodiments, templating material 706 is any of the materials discussed with reference to templating material 703. Any known method for depositing templating material 706 along the outer walls may be used. In this example, templating material 706 behaves as a liner which separates the via and interconnect ferroelectric and/or multiferroic from dielectric 704. [0086] Fig. 7G illustrates cross-section 770 of the die after ferroelectric and/or multiferroic 707 is deposited in trench 705. In some embodiments, material deposited for the via is different from the material deposited for the ferroelectric and/or multiferroic interconnect. In some embodiments, ferroelectric and/or multiferroic 707 is any of the materials discussed with reference to ferroelectric and/or multiferroic layer 702a/b. In some embodiments, after increasing temperature (e.g., to 298K), templating material 706 causes ferroelectric and/or multiferroic 707 to transform from unordered crystalline structure to ordered crystalline structure.

[0087] In some embodiments, damascene based processing method are used for creating templated interconnect 702b and 706. In some embodiments, subtractive processing methods are used for creating templating interconnect 702b and 706. In some embodiments, recess processing method are used to take advantage of the templated interconnect 702b and 706. In some embodiments, super-lattice stacks comprising of repeated patterns of template enhancing material (e.g., as those described with reference to Fig. 6) are used for ferroelectric and/or multiferroic 202b and ferroelectric and/or multiferroic 206.

[0088] Figs. 8A-G illustrate cross-sections 800, 820, 830, 840, 850, 860, and 870, respectively, of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 8A-G having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0089] Although the fabrication processes with reference to Figs. 8A-G are shown in a particular order, the order of the actions can be modified. Thus, the illustrated

embodiments can be performed in a different order, and some actions/fabrication processes may be performed in parallel. Some of the fabrication processes listed in Figs. 3A-G are optional in accordance with certain embodiments. The numbering of the fabrication processes presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0090] Figs. 8A-E are similar to Figs. 7A-E, and so they are not repeated again but a presented for completeness sake. In some embodiments, instead of forming liners of templating material along the edges of the trenches 705, ferroelectric and/or multiferroic 707 is deposited into trenches 705 as illustrated with reference Fig. 8F. In some embodiments, material deposited for the via is different from the material deposited for the ferroelectric and/or multiferroic interconnect. In some embodiments, ferroelectric and/or multiferroic 807 is any of the materials discussed with reference to ferroelectric and/or multiferroic layer 802a/b. In some embodiments, templating material layer 808 is deposited over ferroelectric and/or multiferroic 807 to transfer unordered metal 807 to ordered metal 809. In some embodiments, after the crystalline structure of ferroelectric and/or multiferroic 807 is ordered, templating layer 808 may be removed. In some embodiments, after the crystalline structure of ferroelectric and/or multiferroic 807 is ordered, templating layer 808 is not removed and further processing continues. In some embodiments, templating layer 808 is formed of any of the materials of templating material 703.

[0091] In some embodiments, damascene based processing method are used for creating templated interconnect 808. In some embodiments, subtractive processing methods are used for creating templating interconnect 808. In some embodiments, recess processing method are used to take advantage of the templated interconnect 808. In some embodiments, super-lattice stacks comprising of repeated patterns of template enhancing material (e.g., as those described with reference to Fig. 6) are used for ferroelectric and/or multiferroic 808.

[0092] Figs. 9A-D illustrate cross-sections 900, 920, and 930, respectively, of ferroelectric and/or ferromagnetic interconnect or vias with various templating

configurations, in accordance with some embodiments of the disclosure. Fig. 9D illustrates cross-section 940 after templating layer is removed, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 9A-D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0093] Cross-section 900 illustrates the case where templating material 901 is deposited on all four sides of interconnect ferroelectric and/or multiferroic 902. In some embodiments, templating material is any of the materials used for templating material 703. In some embodiments, ferroelectric and/or multiferroic 902 is any of the materials used for ferroelectric and/or multiferroic layer 702a/b. In some embodiments, the crystalline structure of templating material 901 is ordered while the crystalline structure of metal 902 is unordered. In some embodiments, the crystalline structure of templating material 901 is unordered while the crystalline structure of metal 902 is ordered. In some embodiments, when the combination of templating material 901 and metal 902 is heated (e.g., to about 298K), unordered crystalline structure metal 902 becomes ordered. As such, resistivity of metal 902 improves compared to its unordered crystalline state. [0094] Cross-section 920 illustrates the case where the templating material is deposited along three sides of metal 902. In some embodiments, when the combination of templating material 921 and ferroelectric and/or multiferroic 902 is heated to about 298K, unordered crystalline structure ferroelectric and/or multiferroic 902 becomes ordered.

[0095] Cross-section 930 illustrates the case where templating material 931 is deposited along one side of ferroelectric and/or multiferroic 902. In some embodiments, when the combination of templating material 931 and ferroelectric and/or multiferroic 902 is heated (e.g., to about 298K), unordered crystalline structure ferroelectric and/or multiferroic 902 becomes ordered. Cross-section 940 illustrates the case where templating material 931 is removed after chemical processing (e.g., etching process) leaving behind an ordered ferroelectric and/or multiferroic 902 with improved resistivity.

[0096] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0097] Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0098] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0099] In some embodiments, computing device 1600 includes first processor 1610 with templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments discussed. Other blocks of the computing device 1600 may also include templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[00100] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[00101] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[00102] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[00103] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[00104] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[00105] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[00106] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600. [00107] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00108] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00109] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00110] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00111] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00112] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00113] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00114] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00115] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00116] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00117] Example 1 is an apparatus which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a templated magnetoelectric layer adjacent to the second magnet, wherein the templated magnetoelectric layer has an ordered crystalline structure; and a conductor coupled to at least a portion of the stack of layers and the templated magnetoelectric layer.

[00118] Example 2 includes all features of example 1, wherein the templated magnetoelectric layer comprises a pair of materials including material A and material B, wherein material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, C-AI2O3, or InSnO; and wherein material B includes one or more of: Lu, Fe, O, Nd, Bi, Pt, LuFe204, LuFeCb, LU2O3, h-LuFeCb, Fe2Cb, Fe304, BiFeCb, Nd-BiFeCb, layers of Pt and BiFeCb, or layers of Pt and Nd-BiFe0₃.

[00119] Example 3 includes all features of example 3, wherein the templated magnetoelectric layer comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity.

[00120] Example 4 is according to any one of examples 1 to 3, wherein the stack of materials comprise two-dimensional materials (2D) with spin orbit interaction, wherein the 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, \VSe2, WS2, or MoSe2, and wherein the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.

[00121] Example 5 is according to any one of examples 1 to 3, wherein the first and second magnets are magnets comprise dopants which comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er. Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, Fe, O, FeO, Fe₂0₃, Nd, Nd20₃, K, KO2, Pr, Sm, SrmCb, Tb, Tb20₃, Tm, TircCb, V, or V20₃. \ [00122] Example 6 is according to any one of examples 1 to 3, wherein the first and second magnets comprise one or a combination of materials: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00123] Example 7 includes all features of example 6, wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Ga, Pd, Fe, Si, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, PdJVInAl, PdJVInln, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, and Mn₃X, where 'X' is one of Ga or Ge.

[00124] Example 8 is according to any one of examples 1 to 3, wherein the first and second magnets are formed of a stack of materials, wherein the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with Llo symmetry; or materials with tetragonal crystal structure.

[00125] Example 9 is according to any one of examples 1 to 3, wherein the first and second magnets are formed of a single layer of one or more materials, and wherein the single layer comprises Mn and Ga.

[00126] Example 10 is according to any one of examples 1 to 3, wherein the conductor is formed of a material which includes one of: Cu, Ag, Al, or Au.

[00127] Example 11 is according to any one of examples 1 to 3 comprises a layer sandwiched between the stack of layers and the first magnet.

[00128] Example 12 includes all features of example 11 wherein the layer comprises

Ag.

[00129] Example 13 is according to any one of claims 1 to 3 comprises a transistor coupled to the first paramagnet.

[00130] Example 14 is according to any one of claims 1 to 3, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a negative supply, and wherein the second paramagnet is coupled to ground.

[00131] Example 15 is according to any one of claims 1 to 3, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a positive supply, and wherein the second paramagnet is coupled to ground. [00132] Example 16 is according to any one of claims 1 to 3, wherein the stack of layers comprise materials ROCh2, where R is a material which includes one of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one of: S, Se, or Te.

[00133] Example 17 is an apparatus which comprises: a multiferroic layer having an ordered crystalline structure; and a crystallinity templating layer adjacent to the multiferroic layer.

[00134] Example 18 includes all features of example 17, wherein the: crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Bi, Nd, Pt, LuFe204, LuFe03, LU2O3, h-LuFe03, Fe203, Fe₃0₄, BiFe0₃, Nd-BiFe0₃, layers of Pt and BiFe0₃, or layers of Pt and Nd-BiFe0₃.

[00135] Example 19 includes all features of example 17, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.

[00136] Example 20 is according to any one of examples 17 to 19, wherein a crystalline axis of the multiferroic layer is aligned with the crystallinity of templating layer.

[00137] Example 21 is according to any one of examples 17 to 19, wherein the crystallinity templating layer is adjacent to: three sides of the multiferroic layer; four sides of the multiferroic layer; or one side of the multiferroic layer.

[00138] Example 22 is an integrated circuit die which comprises: an interlay er dielectric layer; and an interconnect formed within the interlay er dielectric layer, the interconnect comprising a crystalline multiferroic or ferroelectric.

[00139] Example 23 includes all features of example 22, wherein the: interlayer dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Fe, Bi, Fe, Pt, LuFe204, LuFe03, LU2O3, h-LuFe03, Fe₂0₃, Fe₃0₄, BiFe0₃, Nd-BiFe0₃, layers of Pt and BiFe0₃, or layers of Pt and Nd-BiFe0₃.

[00140] Example 24 is according to any one of examples 22 to 23, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.

[00141] Example 25 includes all features of example 23, wherein a crystalline axis of the multiferroic layer is aligned with the crystallinity of the interlayer dielectric layer.

[00142] Example 26 is a system which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 16, examples 17 to 21, or examples 22 to 25; and a wireless interface for allowing the processor to communicate with another device.

[00143] Example 27 is a method which comprises: forming a first magnet with perpendicular magnetic anisotropy (PMA); forming a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba- Bychkov effect; forming a second magnet with PMA; forming a templated magnetoelectric layer adjacent to the second magnet, wherein the templated magnetoelectric layer has an ordered crystalline structure; and forming a conductor coupled to at least a portion of the stack of layers and the templated magnetoelectric layer.

[00144] Example 28 includes all features of example 27, wherein the templated magnetoelectric layer comprises a pair of materials including material A and material B, wherein material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, c-AhCb, or InSnO; and wherein material B includes one or more of: Lu, Fe, O, Nd, Bi, Pt, LuFe204, LuFe0₃, LU2O3, h-LuFeCb, Fe₂0₃, Fe₃0₄, BiFe0₃, Nd-BiFe0₃, layers of Pt and BiFe0₃, or layers of Pt and Nd-BiFe0₃.

[00145] Example 29 includes all features of example 27, wherein the templated magnetoelectric layer comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity.

[00146] Example 30 is according to any one of examples 27 to 29, wherein forming the stack of materials comprises forming two-dimensional materials (2D) with spin orbit interaction, wherein the 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, \VSe2, WS2, or MoSe2, and wherein the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.

[00147] Example 31 is according to any one of examples 27 to 29, wherein the first and second magnets are magnets comprise dopants which comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er. Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, Fe, O, FeO, Fe₂0₃, Nd, Nd₂0₃, K, KO2, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

[00148] Example 32 is according to any one of examples 27 to 29, wherein the first and second magnets comprise one or a combination of materials: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00149] Example 33 includes all features of example 32, wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Ga, Pd, Fe, Si, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, PdJVInAl, PdJVInln, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, and Mn₃X, where 'X' is one of Ga or Ge.

[00150] Example 34 is according to any one of examples 27 to 29, wherein the first and second magnets are formed of a stack of materials, wherein the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with Llo symmetry; or materials with tetragonal crystal structure.

[00151] Example 35 is according to any one of examples 27 to 29, wherein forming the first and second magnets comprise forming a single layer of one or more materials, and wherein the single layer comprises Mn and Ga.

[00152] Example 36 is according to any one of examples 27 to 29, wherein the conductor is formed of a material which includes one of: Cu, Ag, Al, or Au.

[00153] Example 37 is according to any one of examples 27 to 29comprises forming a layer sandwiched between the stack of layers and the first magnet.

[00154] Example 38 includes all features of example 37, wherein the layer comprises

Ag.

[00155] Example 39 is according to any one of examples 27 to 29 comprises forming a transistor coupled to the first paramagnet.

[00156] Example 40 is according to any one of examples 27 to 29, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a negative supply, and wherein the second paramagnet is coupled to ground.

[00157] Example 41 is according to any one of examples 27 to 29, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a positive supply, and wherein the second paramagnet is coupled to ground.

[00158] Example 42 is according to any one of examples 27 to 29, wherein the stack of layers comprise materials ROCh2, where R is a material which includes one of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one of: S, Se, or Te.

[00159] Example 43 is a method which comprises: forming a multiferroic layer having an ordered crystalline structure; and forming a crystallinity templating layer adjacent to the multiferroic layer.

[00160] Example 44 includes all features of example 43, wherein the: crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Bi, Nd, Pt, LuFe204, LuFeC , LU2O3, h-LuFeC , Fe203, Fe₃0₄, BiFe0₃, Nd-BiFe0₃, layers of Pt and BiFeOs, or layers of Pt and Nd-BiFeCb.

[00161] Example 45 includes all features of example 44, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.

[00162] Example 46 is according to any one of claims 44 to 45, wherein forming the multiferroic layer comprises aligning a crystalline axis of the multiferroic layer with the crystallinity of templating layer.

[00163] Example 47 is according to any one of examples 44 to 45 comprises positioning the crystallinity templating layer along: three sides of the multiferroic layer; four sides of the multiferroic layer; or one side of the multiferroic layer.

[00164] Example 48 is a method which comprises: forming an interlay er dielectric layer; and forming an interconnect formed within the interlay er dielectric layer, the interconnect comprising a crystalline multiferroic or ferroelectric.

[00165] Example 49 includes all features of example 48, wherein the: interlayer dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Fe, Bi, Fe, Pt, LuFe204, LuFe03, LU2O3, h-LuFe03, Fe₂0₃, Fe₃0₄, BiFe0₃, Nd-BiFe0₃, layers of Pt and BiFe0₃, or layers of Pt and Nd-BiFe0₃.

[00166] Example 50 includes all features of example 49, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.

[00167] Example 51 is according to any one of examples 48 to 50, wherein forming the interconnect comprises aligning a crystalline axis of the multiferroic layer with the crystallinity of the interlayer dielectric layer.

[00168] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect;

a second magnet with PMA;

a templated magnetoelectric layer adjacent to the second magnet, wherein the templated magnetoelectric layer has an ordered crystalline structure; and

a conductor coupled to at least a portion of the stack of layers and the templated magnetoelectric layer.

2. The apparatus of claim 1, wherein the templated magnetoelectric layer comprises a pair of materials including material A and material B,

wherein material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, C-AI2O3, or InSnO; and

wherein material B includes one or more of: Lu, Fe, O, Nd, Bi, Pt, LuFe204, LuFe0₃, LU2O3, h-LuFe0₃, Fe₂0₃, Fe₃0₄, BiFe0₃, Nd-BiFe0₃, layers of Pt and BiFeC , or layers of Pt and Nd-BiFeCb.

3. The apparatus of claim 1, wherein the templated magnetoelectric layer comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity.

4. The apparatus according to any one of claims 1 to 3, wherein the stack of materials comprise two-dimensional materials (2D) with spin orbit interaction, wherein the 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, \VSe2, WS2, or MoSe2, and wherein the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.

5. The apparatus according to any one of claims 1 to 3, wherein the first and second magnets are magnets comprise dopants which comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er. Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, Fe, O, FeO, Fe₂0₃, Nd, Nd₂0₃, K, KO2, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

6. The apparatus according to any one of claims 1 to 3, wherein the first and second magnets comprise one or a combination of materials: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

7. The apparatus of claim 6, wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Ga, Pd, Fe, Si, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, and Mn₃X, where 'X' is one of Ga or Ge.

8. The apparatus according to any one of claims 1 to 3, wherein the first and second magnets are formed of a stack of materials, wherein the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with Llo symmetry; or materials with tetragonal crystal structure.

9. The apparatus according to any one of claims 1 to 3, wherein the first and second magnets are formed of a single layer of one or more materials, and wherein the single layer comprises Mn and Ga.

10. The apparatus according to any one of claims 1 to 3, wherein the conductor is formed of a material which includes one of: Cu, Ag, Al, or Au.

11. The apparatus according to any one of claims 1 to 3comprises a layer sandwiched between the stack of layers and the first magnet.

12. The apparatus of claim 12, wherein the layer comprises Ag.

13. The apparatus according to any one of claims 1 to 3 comprises a transistor coupled to the first paramagnet.

14. The apparatus according to any one of claims 1 to 3, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a negative supply, and wherein the second paramagnet is coupled to ground.

15. The apparatus according to any one of claims 1 to 3, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a positive supply, and wherein the second paramagnet is coupled to ground.

16. The apparatus according to any one of claims 1 to 3, wherein the stack of layers

comprise materials ROCh2, where R is a material which includes one of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one of: S, Se, or Te.

17. An apparatus comprising:

a multiferroic layer having an ordered crystalline structure; and

a crystallinity templating layer adjacent to the multiferroic layer.

18. The apparatus of claim 17, wherein the:

crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and

multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Bi, Nd, Pt, LuFe₂0₄, LuFe0₃, Lu₂0₃, h-LuFe0₃, Fe₂0₃, Fe₃0₄, BiFe0₃, Nd- BiFe0₃, layers of Pt and BiFe0₃, or layers of Pt and Nd-BiFe0₃.

19. The apparatus of claim 18, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.

20. The apparatus according to any one of claims 17 to 19, wherein a crystalline axis of the multiferroic layer is aligned with the crystallinity of templating layer.

21. The apparatus according to any one of claims 17 to 19, wherein the crystallinity

templating layer is adjacent to:

three sides of the multiferroic layer;

four sides of the multiferroic layer; or

one side of the multiferroic layer.

22. An integrated circuit die comprising: an interlay er dielectric layer; and

an interconnect formed within the interlay er dielectric layer, the interconnect comprising a crystalline multiferroic or ferroelectric.

23. The integrated circuit die of claim 22, wherein the:

interlay er dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and

multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Fe, Bi, Fe, Pt, LuFe₂0₄, LuFe0₃, Lu₂0₃, h-LuFe0₃, Fe₂0₃, Fe₃0₄, BiFe0₃, Nd- BiFe0₃, layers of Pt and BiFe0₃, or layers of Pt and Nd-BiFe0₃.

24. The integrated circuit die according to any one of claims 22 to 23, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.

25. The integrated circuit die of claim 23, wherein a crystalline axis of the multiferroic layer is aligned with the crystallinity of the interlay er dielectric layer.

26. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus claims 1 to 16, claims 17 to 21, or 22 to 25; and a wireless interface for allowing the processor to communicate with another device.