[go: up one dir, main page]

WO2018117402A1 - Method and apparatus for manufacturing epitaxial wafer - Google Patents

Method and apparatus for manufacturing epitaxial wafer Download PDF

Info

Publication number
WO2018117402A1
WO2018117402A1 PCT/KR2017/012416 KR2017012416W WO2018117402A1 WO 2018117402 A1 WO2018117402 A1 WO 2018117402A1 KR 2017012416 W KR2017012416 W KR 2017012416W WO 2018117402 A1 WO2018117402 A1 WO 2018117402A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
thickness
epitaxial
susceptor
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2017/012416
Other languages
French (fr)
Korean (ko)
Inventor
김인천
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Siltron Co Ltd
Original Assignee
SK Siltron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Siltron Co Ltd filed Critical SK Siltron Co Ltd
Publication of WO2018117402A1 publication Critical patent/WO2018117402A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68764—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68792—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the construction of the shaft
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

  • Embodiments relate to an epitaxial wafer fabrication method and apparatus.
  • Silicon wafers used as raw materials for semiconductor device manufacture generally include slicing to thinly cut single crystal silicon ingots into wafer forms, lapping to improve flatness while polishing to a desired wafer thickness, and wafers. It is manufactured in the form of a polished wafer through various process steps such as etching to remove an internal damage layer, polishing to improve surface mirroring and flatness. In addition, annealing may be further performed to adjust the density of defects, and may be manufactured in the form of an anneal wafer or in the form of an epitaxial wafer to be more suitable for forming a semiconductor device.
  • a gas such as a source gas and a dopant gas is supplied to the polysid wafer.
  • the above-mentioned gas is decomposed and reacted by a heater (not shown) of the epitaxial wafer manufacturing apparatus to deposit a silicon epitaxial layer (not shown) on the polysid wafer, thereby manufacturing a silicon epitaxial wafer.
  • a silicon epitaxial wafer is used for manufacturing high performance semiconductor devices.
  • silicon epitaxial wafers have a silicon epitaxial layer that is about a micrometer to several tens of microns thick.
  • the geometric shape such as the shape, thickness, flatness, etc. of the wafer greatly affects the yield of the semiconductor chip, and is thus strictly managed.
  • the semiconductor device manufacturing process becomes more dependent on the geometric shape of the wafer. That is, the flatness of the wafer has a great influence on the productivity and yield in the semiconductor manufacturing process due to the recent decrease in the line width and the increase in the degree of integration of semiconductor devices.
  • high flatness of the wafer is required due to the focusing problem of the exposure apparatus in a process such as photolithography.
  • the finer the circuit line width the lower the flatness on the wafer in the semiconductor process, resulting in distortion of the line, resulting in lowered device yield. Therefore, it is necessary to develop a high quality epitaxial wafer with excellent flatness.
  • the epitaxial layer is deposited on a polysid wafer having a poor flatness after the polishing process, the epitaxial wafer also has poor flatness, and its improvement is required.
  • Embodiments provide an epitaxial wafer fabrication method and apparatus having improved flatness.
  • an epitaxial wafer manufacturing method for forming an epitaxial layer on the wafer while the wafer is seated on a susceptor, the epitaxial layer having a matched thickness profile to offset the overall thickness variation of the wafer
  • A preset epi-process conditions of the respective thickness types of the wafer
  • B determining a thickness type of the wafer using the first thickness deviation in the center region and the second thickness variation in the edge region of the wafer seated on the susceptor
  • the epi process condition may further include a supply amount of the dopant gas.
  • the supply amount of the carrier gas may include a first supply amount of the carrier gas supplied over the wafer; Or it may include at least one of the second supply amount of the carrier gas supplied to the bottom of the wafer.
  • a center region of the wafer is defined as an area from the center of the wafer to a first point
  • an edge region of the wafer is defined as an area from a second point to a third point of the wafer.
  • the second point may be located farther from or the same as the first point than the first point
  • the third point may be located farther from the center than the second point.
  • each of the first and second points may be between 80 mm and 100 mm, and the third point may be between 140 mm and 148 mm.
  • the first thickness deviation is a value obtained by subtracting the second thickness at the first point from the first thickness at the center
  • the second thickness deviation is the third thickness at the second point. It may be a value obtained by subtracting the fourth thickness at the third point.
  • the step (b) may include obtaining the first and second thickness deviations; Obtaining a first comparison value by comparing the first thickness deviation with a first reference thickness value; Obtaining a second comparison value by comparing the second thickness deviation with a second reference thickness value; And determining a thickness type of the wafer using the first comparison value and the second comparison value.
  • the first reference thickness value may be 15 nm or 30 nm
  • the second reference thickness value may be '0'.
  • the relative ratio between the supply amount of the carrier gas, the supply amount of the source gas, the opening / closing degree of the gas supply valve, the rotational speed of the susceptor and the height of the susceptor is determined by the wafer.
  • Each of the thickness types may be set as different epi process conditions.
  • the wafer may be a wafer polished on both sides.
  • the controller may further control the supply amount of the dopant as the epi process condition.
  • the method and apparatus for manufacturing an epitaxial wafer according to the embodiment have a thickness profile capable of offsetting the overall thickness variation of the wafer by complexly adjusting each factor of the epitaxial conditions when the overall thickness of the wafer W is varied.
  • a thickness profile capable of offsetting the overall thickness variation of the wafer by complexly adjusting each factor of the epitaxial conditions when the overall thickness of the wafer W is varied.
  • FIG. 1 is a flowchart illustrating an epitaxial wafer manufacturing method according to an embodiment.
  • FIG. 2 is a view schematically showing a cross-sectional shape of the epitaxial wafer manufacturing apparatus according to the embodiment.
  • FIG. 3 is a plan view according to an exemplary embodiment of the gas supply valve illustrated in FIG. 2.
  • 4A to 4C are diagrams for describing a concept in which a thickness variation of a wafer is canceled by an epitaxial layer.
  • FIG. 5 is a flowchart for describing an exemplary embodiment of the 120th step illustrated in FIG. 1.
  • FIG. 6 shows a cross-sectional shape of the wafer for explaining the center region and the edge region of the wafer.
  • FIGS. 7A to 7D are diagrams showing first to fourth types of wafers when the first reference thickness value is 15 nm.
  • 8A to 8D are diagrams showing first to fourth types of wafers when the first reference thickness value is 30 nm.
  • FIG. 9A is a diagram for describing the GBIR
  • FIG. 9B is a diagram for explaining the SBIR.
  • 10A to 10C are diagrams for explaining an example of a process of manufacturing an epitaxial wafer in which the overall thickness variation is offset by the epitaxial layer to improve the overall thickness variation.
  • FIG. 11A shows the GBIR of the epitaxial wafer manufactured by the conventional method and the GBIR of the epitaxial wafer manufactured by the method according to the embodiment
  • FIG. 11B shows the SIBR of the epitaxial wafer manufactured by the conventional method.
  • the SBIR of the epitaxial wafer manufactured by the method by an example is shown.
  • FIG. 12A shows a histogram of GBIR of several epitaxial wafers manufactured by the conventional method and several epitaxial wafers manufactured by the method according to the embodiment
  • FIG. 12B shows several epitaxial wafers manufactured by the conventional method.
  • the histogram of the SBIR of the epitaxial wafers and the sheets of the epitaxial wafers produced by the method according to the embodiment is shown.
  • the epitaxial manufacturing method 100 and the apparatus 200 according to the embodiment will be described with reference to the accompanying drawings.
  • the epitaxial manufacturing apparatus 200 will be described using the Cartesian coordinate system (x-axis, y-axis, z-axis), but it can of course be explained by other coordinate systems.
  • FIG. 1 is a flowchart illustrating an epitaxial wafer manufacturing method 100 according to an embodiment.
  • FIG. 2 is a view schematically showing a cross-sectional shape of the epitaxial wafer manufacturing apparatus 200 according to the embodiment
  • FIG. 3 is a plan view according to an embodiment 240A of the gas supply valve 240 shown in FIG. 2. Indicates.
  • the epitaxial wafer manufacturing method 100 shown in FIG. 1 is described as being performed in the epitaxial wafer manufacturing apparatus 200 shown in FIG. 2, but the embodiment is not limited thereto. That is, the epitaxial wafer manufacturing method 100 illustrated in FIG. 1 may also be performed by an epitaxial wafer manufacturing apparatus having a configuration different from that of the epitaxial wafer manufacturing apparatus 200 illustrated in FIG. 2.
  • the epitaxial wafer manufacturing apparatus 200 illustrated in FIG. 2 includes a chamber 210, a chamber upper frame 212, a chamber lower frame 214, a gas supply unit 230, a gas supply valve 240, and a driving unit. 260, a storage 270, a controller 280, and a thickness type determiner 290.
  • the chamber 210 may be formed of quartz glass as a place where heat treatment is performed to form a film such as an epitaxial layer (hereinafter, referred to as an 'epitaxial layer') E on the surface of the wafer W.
  • the wafer W may be a polished wafer, but embodiments are not limited thereto.
  • the chamber 210 has a chamber upper frame 212 and a chamber lower frame 214, and a gas inlet IN and a gas outlet OUT may be disposed between the chambers 212 and 214.
  • a carrier gas, a source gas (or a source gas or a reactive gas) required for growing the epi layer E on the wafer W in the chamber 210 is provided through the gas inlet IN.
  • An epitaxial layer E may be formed in the wafer W by being introduced into the 210, and a gas that contributes to the reaction after the epitaxial layer E is formed may be discharged through the gas outlet OUT.
  • the gas inlet IN and the gas outlet OUT are formed to face each other, and the source gas introduced through the gas inlet IN may flow along the surface of the wafer W in a laminar flow state.
  • the chamber 210 may include a susceptor 220, a lift arm 250, a support base 252, a drive shaft (or support shaft) 254, and a support pin 256. Can be.
  • the wafer W may be loaded or unloaded into the chamber 210 or out of the chamber 210 one by one by a conveying unit (not shown). It is not limited by longevity.
  • the susceptor 220 provides a space in which the wafer W is to be loaded and supports the wafer W while forming the epitaxial layer on the wafer (or substrate) W.
  • the susceptor 220 may be made of a graphite material covered with silicon carbide, and may have a disk planar shape. In addition, the susceptor 220 may have various cross-sectional shapes. After being seated on the susceptor 220, the wafer W may be rapidly heat treated and the epi layer E may be grown on the main surface of the wafer W. FIG.
  • the support part supporting part 252 is a part serving to support the susceptor 220, and the material may be quartz, silicon, or silicon carbide, and may be implemented by coating silicon or silicon carbide with quartz.
  • the lift arm 250 is disposed between the drive shaft 254 and the support pin 256, and may extend from the drive shaft 254 in a radial shape to be connected to the support pin 256.
  • the lift arm 250 serves to raise and lower the support pin 256 when the drive shaft 254 moves up and down.
  • the support pin 256 extends in a vertical direction from the tip of the lift arm 250, is disposed through the susceptor 220, and the lift arm 250 to be lifted together when the lift arm 250 moves.
  • the susceptor 220 may have a through hole (not shown) into which the support pin 256 is inserted.
  • the drive shaft 254 is connected to the support base 252 to support the susceptor 220, and is connected to the lift arm 250 to support the support pin 256.
  • the drive shaft 254 may rotate or move up and down by the driving unit 260. That is, the driving shaft 254 may be determined by the driving unit 260 its lifting and rotation speed.
  • the drive shaft 254 is rotated by the driver 260, the susceptor 220 rotates together with the support part supporter 252 so that the wafer W may rotate.
  • the wafer W may be rotated at high speed so that the thickness of the epi layer E is formed uniformly.
  • the driving unit 260 serves to elevate the support pin 256 through the lift arm 250, and serves to elevate the susceptor 220 through the support base 252.
  • the driver 260 may adjust at least one of lifting and lowering speeds of the driving shaft 254. For example, when the driving shaft 254 is lifted and lowered by the driving unit 260, the height of the susceptor 220 may be raised or lowered.
  • the gas supply unit 230 supplies a carrier gas, a source gas, and a dopant gas to the gas supply valve 240.
  • the gas supply unit 240 supplies the supply amount of the carrier gas, the supply amount of the source gas, and the supply amount of the dopant gas supplied to the gas supply valve 240. Each can be adjusted.
  • the gas supply valve (Accuset) (or AMV: Automated Metering Valve) 240 may transfer the carrier gas, the source gas, and the dopant gas supplied from the gas supply unit 230 to the inside of the chamber 210 through the gas inlet IN. It is injected and serves to supply the wafer (W). In this case, the opening / closing degree of the gas supply valve 240 may be adjusted in response to the second control signal C2 generated from the controller 280.
  • the gas supply valve 240A may include a central injection nozzle and an edge injection nozzle.
  • the central injection nozzle injects gas toward the center portion IN of the wafer W, and the edge injection nozzle injects gas toward the edges OUT1 and OUT2 of the wafer W.
  • This nozzle configuration method is also referred to as multiport injector (MPI).
  • the temperature of the wafer W is maintained at about 1100 ° C. to 1200 ° C., for example, and the carbon is subjected to heat treatment for about 10 minutes in a hydrogen (H 2) atmosphere. Eliminate system impurities and natural oxide films.
  • a source gas such as Trichlorosilane (SiHCl 3) or SiH 2 Cl 2 and a carrier gas such as hydrogen (H 2) are supplied into the chamber 210.
  • a dopant gas such as B2H6 or PH3 may be supplied to the chamber 210 together with the carrier gas and the source gas.
  • the carrier gas, the source gas and the dopant gas may be supplied in the arrow direction 310 inside the chamber 210, as well as the carrier gas may be supplied in the arrow direction 320.
  • the gas may be decomposed and reacted by a heater (not shown) of the epitaxial wafer manufacturing apparatus 200 to deposit the epitaxial layer E on the wafer W, thereby manufacturing the epitaxial wafer EP.
  • an epitaxial wafer manufacturing method 100 is as follows.
  • Epi process conditions of the epi layer E having a matched thickness profile are set in advance for each thickness type of the wafer W so as to offset the overall thickness variation of the wafer W (step 110).
  • the epi process conditions of the epi layer set differently for each thickness type of the wafer W may be stored in the storage unit 270.
  • the wafer W on which the epitaxial layer E is to be formed is sliced into a predetermined silicon ingot and cut into thin wafers, and the cut wafer is wrapped to form both surfaces.
  • double side polishing DSP
  • it may be prepared by applying a process such as etching, polishing, and the like.
  • the wafer W may be washed with an alkaline aqueous solution such as ammonia and hydrogen peroxide mixed solution and / or an acid aqueous solution such as hydrofluoric acid, and then mounted on the susceptor 220.
  • an alkaline aqueous solution such as ammonia and hydrogen peroxide mixed solution and / or an acid aqueous solution such as hydrofluoric acid
  • the wafer W may be a silicon wafer, for example, may have a diameter of 300 mm, but the embodiment is not limited by the material or the diameter of the wafer W.
  • FIGS. 4A to 4C are diagrams for explaining a concept in which the thickness variation of the wafer W is canceled by the epi layer E.
  • the horizontal axis represents the y-axis direction (that is, the radial direction of the wafer W).
  • the vertical axis represents the position in the z-axis direction (eg, normalized THK of the wafer).
  • FIG. 4A shows the thickness profile of the wafer W
  • FIG. 4B shows the thickness profile of the epi layer E that can offset the thickness variation of the wafer W
  • FIG. 4C shows the thickness of the wafer W.
  • the deviation represents the thickness profile of the epitaxial wafer EW offset by the epi layer E.
  • the center area (CA) of the wafer W has a flat thickness and there is no thickness variation
  • the edge area (EA) of the wafer W is It is assumed that there is a thickness deviation bent upwards.
  • the epi layer E having the thickness profile illustrated in FIG. 4B is formed on the wafer W
  • the overall thickness variation of the text wafer EW ' may be eliminated. This is because the entire thickness variation of the wafer W is canceled out by the epi layer E.
  • the epi layer E as illustrated in FIG. 4B may be implemented by epi process conditions.
  • the epi process conditions for forming the epi layer E having a matched thickness file so as to offset the thickness variation of the wafer W include the supply amount of the carrier gas, the supply amount of the source gas, and the gas supply valve. It may include at least one of the opening and closing degree of the 240, 240A, the rotational speed of the susceptor 220 or the height of the susceptor 220.
  • the rotational speed of the susceptor 220 may mean the rotational speed of the wafer (W).
  • the supply amount of the carrier gas may include at least one of the first and second supply amounts.
  • the first supply amount may mean a supply amount of a carrier gas supplied onto the wafer W, as indicated by an arrow 310 in FIG. 2.
  • the second supply amount may mean, for example, a supply amount of a carrier gas supplied below the wafer W, as indicated by an arrow 320 in FIG. 2.
  • the epi process conditions may further include a supply amount of the dopant gas, but the embodiment is not limited thereto.
  • the dopant gas may be supplied together with the source gas in the chamber 210 as indicated by arrow 310 in FIG. 2.
  • the epi process conditions different for each thickness type of the wafer W include a supply amount of a carrier gas, a supply amount of a source gas, an opening / closing degree of the gas supply valves 240 and 240A, and the susceptor 220. It may mean a relative ratio between the rotational speed of) and the height of the susceptor 220.
  • a supply amount of a carrier gas e.g., a gas supplied to the substrate.
  • a supply amount of a source gas e.g., a supply amount of a source gas
  • an opening / closing degree of the gas supply valves 240 and 240A e.g., a relative ratio between the rotational speed of
  • step 120 the first thickness deviation ⁇ T1 in the center region CA of the wafer W seated on the susceptor 220 and the second thickness in the edge region EA.
  • the thickness ⁇ T2 is used to determine the thickness type of the wafer W as a target for forming the epi layer E (step 120).
  • step 120 may be performed by the thickness type determiner 290 illustrated in FIG. 2. That is, the thickness type determiner 290 may determine the thickness type of the wafer W seated on the susceptor 220, and output the determined thickness type to the controller 280.
  • FIG. 5 is a flowchart for describing an embodiment 120A of the 120th step illustrated in FIG. 1.
  • FIG. 6 shows a cross-sectional shape of the wafer W for explaining the center area CA and the edge area EA of the wafer W. As shown in FIG.
  • step 120A shown in FIG. 5 the center area CA and the edge area EA of the wafer W will be described with reference to FIG. 6.
  • the center area CA of the wafer W may be defined as an area from the center PO of the wafer W to the first point ⁇ P1.
  • the edge area EA of the wafer W may be defined as an area from the second point ⁇ P2 to the third point ⁇ P3 of the wafer W.
  • the second point ⁇ P2 may be located farther from the center P0 than the first point ⁇ P1 or may be the same as the first point ⁇ P1, and the third point ⁇ P3 may be the second point ⁇ It may be located far from the center P0 than P2).
  • the first point P1 is 80 mm to 100 mm, for example, 90 mm
  • P2 may be 80 mm to 100 mm, for example, 100 mm
  • the third point P3 may be 140 mm to 148 mm, for example, 144 mm, but the embodiment is not limited thereto.
  • the first thickness deviation ⁇ T1 is a value obtained by subtracting the second thickness T2 at the first point P1 from the first thickness T1 at the center P0, and the second thickness deviation ⁇ T2.
  • the column may be a value obtained by subtracting the fourth thickness T4 at the third point P3 from the third thickness T3 at the second point P2, but the embodiment is not limited thereto.
  • step 121 the first thickness deviation ⁇ T1 and the second thickness deviation ⁇ T2 of the wafer W seated on the susceptor 220 are obtained (step 121).
  • a first comparison value is obtained by comparing the first thickness deviation ⁇ T1 with the first reference thickness value RT1, and the second thickness deviation ⁇ T2 is compared with the second reference thickness value RT2.
  • the second comparison value may be obtained, and the thickness type of the wafer W may be determined using the first comparison value and the second comparison value (steps 122 to 128).
  • the first thickness deviation ⁇ T1 is smaller than the first reference thickness value RT1 (step 122). If it is determined that the first thickness deviation ⁇ T1 is smaller than the first reference thickness value RT1, it is determined whether the second thickness deviation ⁇ T2 is greater than the second reference thickness value RT2 (step 123). . However, if it is determined that the first thickness deviation ⁇ T1 is not smaller than the first reference thickness value RT1, it is determined whether the second thickness deviation ⁇ T2 is greater than the second reference thickness value RT2 (step 124). ).
  • the first reference thickness value RT1 may be 15 nm or 30 nm
  • the second reference thickness value RT2 may be '0', but embodiments are not limited thereto.
  • the thickness type of (W) is determined as the first type TP1 (step 125).
  • the susceptor 220 is determined.
  • the thickness type of the seated wafer W is determined as the second type TP2 (step 126).
  • the first thickness deviation ⁇ T1 when the first thickness deviation ⁇ T1 is not smaller than the first reference thickness value RT1 and the second thickness deviation ⁇ T2 is larger than the second reference thickness value RT2, the first thickness deviation ⁇ T1 may be seated on the susceptor 220.
  • the thickness type of the wafer W is determined as the third type TP3 (step 127).
  • the thickness type of the wafer W thus obtained is determined as the fourth type TP4 (step 128).
  • step 124 when the first thickness deviation ⁇ T1 is equal to the first reference thickness value RT1, the process proceeds to step 124.
  • the embodiment is not limited thereto. That is, according to another embodiment, when it is determined in step 122 that the first thickness deviation ⁇ T1 is equal to the first reference thickness value RT1, the process may proceed to step 123 instead of step 124.
  • step 126 when the second thickness deviation ⁇ T2 is equal to the second reference thickness value RT2 in step 123, the process proceeds to step 126, but the embodiment is not limited thereto. That is, according to another embodiment, when it is determined in step 123 that the second thickness deviation ⁇ T2 is equal to the second reference thickness value RT2, the process may proceed to step 125 instead of step 126.
  • step 124 when the second thickness deviation ⁇ T2 is equal to the second reference thickness value RT2 in step 124, the process proceeds to step 128, but the embodiment is not limited thereto. That is, according to another embodiment, when it is determined in step 124 that the second thickness deviation ⁇ T2 is equal to the second reference thickness value RT2, the process may proceed to step 127 instead of step 128.
  • Step 120A illustrated in FIG. 5 may be performed by the thickness type determiner 290 illustrated in FIG. 3.
  • an epitaxial layer may be formed on the wafer W under epi process conditions corresponding to the thickness type determined in the 120 or 120A) step among the preset epi process conditions (step 130). .
  • the controller 280 reads an epi process condition corresponding to the thickness type of the wafer W determined by the thickness type determiner 290 from the storage unit 270, and reads the epi process.
  • the units 230, 240, and 260 may be controlled by generating the first to third control signals C1 to C3 based on the condition. That is, the controller 280 may control the gas supply unit 230 by generating the first control signal C1 to adjust the supply amount of the carrier gas, the supply amount of the source gas, and the supply amount of the dopant gas.
  • the controller 280 may generate a second control signal C2 to adjust the opening / closing degree of the gas supply valve 240.
  • controller 280 generates a third control signal C3 to control the raising and lowering speed of the driving shaft 254 through the driving unit 260 to thereby rotate the susceptor 220 or the susceptor 220. At least one of the height can be adjusted.
  • each of the first point P1 and the second point P2 is equal to 90 mm
  • the third The epitaxial process for each thickness type of the wafer W assuming that the point P3 is 148 mm, the first reference thickness value RT1 is 15 nm or 30 nm, and the second reference thickness value RT2 is 0 nm.
  • FIGS. 7A to 7D are diagrams showing the first to fourth types TP1 to TP4 of the wafer W when the first reference thickness value RT1 is 15 nm, and the horizontal axis in each drawing represents the wafer W.
  • FIG. Indicates the position in the radial direction, and the vertical axis indicates the thickness of the wafer W, respectively.
  • the first thickness deviation ⁇ T1 is smaller than 15 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is smaller than 0 nm, which is the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 210 is determined as the first type TP1.
  • the first thickness deviation ⁇ T1 is smaller than 15 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is 0, the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 210 is determined as the second type TP2.
  • the first thickness deviation ⁇ T1 is not smaller than 15 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 220 is determined as the third type TP3.
  • the first thickness deviation ⁇ T1 is not smaller than 15 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 220 is determined as the fourth type TP4.
  • FIGS. 8A to 8D are diagrams showing the first to fourth types TP1 to TP4 of the wafer W when the first reference thickness value RT1 is 30 nm, and the horizontal axis in each drawing represents the wafer W.
  • FIG. Indicates the position in the radial direction, and the vertical axis indicates the thickness of the wafer W, respectively.
  • the first thickness deviation ⁇ T1 is smaller than 30 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is smaller than 0 nm, which is the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 210 is determined as the first type TP1.
  • the first thickness deviation ⁇ T1 is smaller than 30 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is 0, the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 210 is determined as the second type TP2.
  • the first thickness deviation ⁇ T1 is not smaller than 30 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 220 is determined as the third type TP3.
  • the first thickness deviation ⁇ T1 is not smaller than 30 nm, which is the first reference thickness value RT1
  • the second thickness deviation ⁇ T2 is the second reference thickness value RT2.
  • the thickness type of the wafer W seated on the susceptor 220 is determined as the fourth type TP4.
  • the epitaxial layer E may be formed on the wafer W by varying the epi process conditions as shown in Table 1 according to the determined thickness type. ) Can be formed.
  • H represents hydrogen (H2) which is a carrier gas
  • H2 Main represents the 1st supply amount of hydrogen (H2) which is carrier gas
  • H2 slit shows the 2nd of hydrogen (H2) which is carrier gas.
  • 'TCS' indicates the source gas
  • 'Accuset (In / Out)' indicates the opening / closing degree of the gas supply valves 240 and 240A
  • HT indicates the height of the susceptor 220
  • RPM represents the rotation speed of the susceptor 220, respectively.
  • Table 1 described above is an epi process condition preset in step 110 for each thickness type TP1 to TP4 of the wafer W, and the relative ratio between the factors of the epi process condition is the thickness type of the wafer W (TP1 to TP4). You can see the difference by).
  • Table 1 may be stored in the form of a look up table (LUT) in the storage unit 270 illustrated in FIG. 3.
  • the relative ratio of each factor in the epi process condition is determined. 40%, H2 Slit 30%, TCS 10%, Accuset (In / Out) 10%, HT 7% and RPM 3%.
  • the thickness type of the wafer W is determined as the second type (TP2)
  • the relative ratio of each factor in the epi-process conditions shows that, among 100%, H2 Main accounts for 42% and H2 Slit accounts for 31%.
  • TCS accounted for 6%
  • Accuset (In / Out) accounted for 10%
  • HT accounted for 10%
  • RPM accounted for 1%.
  • the thickness type of the wafer W is determined as the third type (TP3)
  • TP3 the third type
  • H2 Main occupies 42% and H2 Slit 30% among 100%.
  • TCS accounted for 8%
  • Accuset (In / Out) accounted for 10%
  • HT accounted for 7%
  • RPM accounted for 3%.
  • the thickness type of the wafer W is determined as the fourth type (TP4)
  • TP4 the fourth type
  • H2 Main occupies 42% and H2 Slit is 31%.
  • TCS accounted for 6%
  • Accuset (In / Out) accounted for 10%
  • HT accounted for 10%
  • RPM accounted for 1%.
  • the thickness variation of the wafer W may be offset by the epi layer E.
  • FIG. For example, the thickness of the edge area EA of the wafer W shown in FIGS. 7A, 7C, 8A, or 8C decreases from the second point P2 to the third point P3.
  • the thickness variation of the wafer W is offset by the epi layer E, The thickness variation in the edge area EA of the epitaxial wafer EW finally manufactured may be minimized.
  • the epitaxial wafer manufacturing method 100 and the apparatus 200 according to the embodiment classify a plurality of wafers for forming an epitaxial layer by thickness type, and then place an epitaxial layer on the wafer W having the largest thickness type.
  • the epi layer may be preferentially formed on the wafer W having a large thickness type, such as by changing the epi process condition to form an epi layer on the wafer W having a large thickness type.
  • the embodiment is not limited thereto.
  • GBIR Global Backside Ideal Range
  • SBIR Site Backside Ideal Range
  • FIG. 9A is a diagram for describing the GBIR
  • FIG. 9B is a diagram for explaining the SBIR.
  • GBIR is a difference value between the maximum thickness Tmax and the minimum thickness Tmin of the wafer W with respect to an ideal backside reference plane 400, and a unit is ⁇ m / Wafer (or , Nm / Wafer, or simply ⁇ m or nm) and may be expressed as in Equation 1 below.
  • SBIR is a difference value between the maximum thickness STmax and the minimum thickness STmin of the wafer site WS with respect to the ideal backside reference plane 410, and the unit is ⁇ m / Wafer ( Or nm / Wafer, or simply ⁇ m or nm) and may be expressed as Equation 2 below.
  • the wafer site WS may mean each piece when the wafer W is divided into, for example, small pieces in a long direction.
  • 10A to 10C illustrate an example of a process of manufacturing an epitaxial wafer in which the overall thickness variation of the wafer W is offset by the epi layer E, thereby improving the overall thickness variation.
  • FIG. 10A shows a three-dimensional map of the wafer W
  • FIG. 10B shows a three-dimensional map of the epi layer E having a thickness profile capable of offsetting the thickness variation of the wafer W
  • FIG. 10C shows a three-dimensional map of the epitaxial wafer EW in which the thickness variation of the wafer W is offset by the epi layer E.
  • FIG. 10A shows a three-dimensional map of the wafer W
  • FIG. 10B shows a three-dimensional map of the epi layer E having a thickness profile capable of offsetting the thickness variation of the wafer W
  • FIG. 10C shows a three-dimensional map of the epitaxial wafer EW in which the thickness variation of the wafer W is offset by the epi layer E.
  • FIG. 10A shows a three-dimensional map of the wafer W
  • FIG. 10B shows a three-dimensional map of the epi layer E having a thickness profile capable of offsetting the thickness variation of the wafer W
  • FIG. 10C shows a three-dimensional map of the epit
  • E is formed on the wafer W shown in Fig. 10A, an epitaxial wafer EW with improved GBIR to 89.4 nm and SBIR to 35.2 nm can be manufactured as shown in Fig. 10C.
  • the epitaxial wafer manufacturing method C2 according to the embodiment which considers the thickness variation of the wafer W and the conventional epitaxial wafer manufacturing method C1 which does not consider the thickness variation of the wafer W is manufactured.
  • the flatness of the epitaxial wafer will be described with reference to the accompanying drawings as follows.
  • FIG. 11A shows the GBIR of the epitaxial wafer manufactured by the conventional method and the GBIR of the epitaxial wafer manufactured by the method according to the embodiment
  • FIG. 11B shows the SIBR of the epitaxial wafer manufactured by the conventional method.
  • the SBIR of the epitaxial wafer manufactured by the method by an example is shown.
  • the GBIR (C1) of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the thickness variation of the wafer W as in the prior art As can be seen that the GBIR (C2) of the plurality of epitaxial wafers having the epitaxial layer (E) having a thickness profile capable of canceling the thickness variation of the wafer (W) on the wafer (W) is relatively small. .
  • an embodiment is compared with SBIR C1 of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the flatness of the wafer W as in the prior art.
  • SBIR (C2) of the plurality of epitaxial wafers formed on the wafer (W) having an epitaxial layer (E) having a thickness profile that can offset the thickness variation of the wafer (W) is relatively small.
  • Each dot shown in FIG. 11B may represent the maximum SBIR of each epitaxial wafer.
  • FIG. 12A shows a histogram of GBIR of several epitaxial wafers manufactured by the conventional method and several epitaxial wafers manufactured by the method according to the embodiment
  • FIG. 12B shows several epitaxial wafers manufactured by the conventional method.
  • the histogram of the SBIR of the epitaxial wafers and the sheets of the epitaxial wafers produced by the method according to the embodiment is shown.
  • Example C2 has more epitaxial wafers with lower GIBR than conventional C1.
  • the frequency number of the SBIR C1 of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the flatness of the wafer W as before and
  • the embodiment (C2) has a lot of epitaxial wafers having a lower SIBR than the conventional (C1).
  • the epitaxial wafer manufacturing method 100 and the apparatus 200 when there is a variation in the overall thickness of the wafer W, the factors of the epi process conditions (H2 Main, H2 Slit, TCS, Since the epitaxial layer E can be formed on the wafer W, which has a thickness profile capable of canceling the overall thickness variation of the wafer W by adjusting Accuset (In / Out), HT, and RPM), The GBIR and SBIR of the finally produced epitaxial wafer (EW) can be improved and the yield can be improved.
  • An epitaxial wafer manufacturing method and apparatus may be used to manufacture a wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

According to an embodiment, an epitaxial wafer manufacturing method of forming an epitaxial layer on a wafer in a state in which the wafer is loaded on a susceptor comprises the steps of: pre-setting, for each thickness type of the wafers, epitaxial process conditions of the epitaxial layer having a thickness profile matched so as to offset the total thickness deviation of the wafer; determining the thickness type of the wafer by using a first thickness deviation in a center region of the wafer loaded on the susceptor and a second thickness deviation in an edge region thereof; and forming the epitaxial layer on the wafer according to the epitaxial process condition, which corresponds to the determined thickness type, among the preset epitaxial process conditions, wherein the epitaxial process conditions include at least one from the amount of a carrier gas supplied, the amount of a source gas supplied, the degree of opening/closing a gas supply valve, and the rotational speed of the susceptor or the height of the susceptor.

Description

에피텍셜 웨이퍼 제조 방법 및 장치Epitaxial Wafer Manufacturing Method and Apparatus

실시 예는 에피텍셜 웨이퍼 제조 방법 및 장치에 관한 것이다.Embodiments relate to an epitaxial wafer fabrication method and apparatus.

반도체 소자 제조의 원료로 사용되는 실리콘 웨이퍼는 일반적으로, 단결정 실리콘 잉곳(ingot)을 웨이퍼 형태로 얇게 절단하는 슬라이싱(slicing), 원하는 웨이퍼의 두께로 연마하면서 평탄도를 개선하는 래핑(lapping), 웨이퍼 내부의 손상(damage)층 제거를 위한 식각(etching), 표면 경면화 및 평탄도를 향상시키기 위한 폴리싱(polishing) 등의 여러 공정 단계를 거쳐 폴리시드 웨이퍼(polished wafer) 형태로 제조된다. 그리고, 결함 밀도 조정을 위해 열처리를 더 실시하여 어닐드 웨이퍼(annealed wafer) 형태로 제조되거나 반도체 소자 형성에 보다 적합하도록 에피텍셜 웨이퍼 형태로 제조되기도 한다.Silicon wafers used as raw materials for semiconductor device manufacture generally include slicing to thinly cut single crystal silicon ingots into wafer forms, lapping to improve flatness while polishing to a desired wafer thickness, and wafers. It is manufactured in the form of a polished wafer through various process steps such as etching to remove an internal damage layer, polishing to improve surface mirroring and flatness. In addition, annealing may be further performed to adjust the density of defects, and may be manufactured in the form of an anneal wafer or in the form of an epitaxial wafer to be more suitable for forming a semiconductor device.

일반적인 실리콘 에피텍셜 웨이퍼 제조 방법에 의하면, 서셉터(미도시) 상에 기판인 실리콘 폴리시드 웨이퍼(미도시)를 로딩한 후, 소스 가스 및 도펀트 가스 등의 가스를 폴리시드 웨이퍼에 공급한다. 에피텍셜 웨이퍼 제조 장치의 히터(미도시)에 의해 전술한 가스가 분해되고 반응하여 폴리시드 웨이퍼에 실리콘 에피텍셜층(미도시)이 증착됨으로써 실리콘 에피텍셜 웨이퍼가 제조될 수 있다.According to the general silicon epitaxial wafer manufacturing method, after loading a silicon polysid wafer (not shown) which is a substrate on a susceptor (not shown), a gas such as a source gas and a dopant gas is supplied to the polysid wafer. The above-mentioned gas is decomposed and reacted by a heater (not shown) of the epitaxial wafer manufacturing apparatus to deposit a silicon epitaxial layer (not shown) on the polysid wafer, thereby manufacturing a silicon epitaxial wafer.

이러한 제조 방법에 의해 실리콘 폴리시드 웨이퍼에 임의의 막 두께나 저항률을 가지는 실리콘 에피텍셜층을 형성할 수 있으므로, 실리콘 에피텍셜 웨이퍼는 고성능 반도체 소자 제조에 사용되고 있다. 보통 이러한 실리콘 에피텍셜 웨이퍼는 대략 ㎛에서 수십 ㎛ 정도 두께의 실리콘 에피텍셜층을 갖는다.Since a silicon epitaxial layer having an arbitrary film thickness and resistivity can be formed on a silicon polished wafer by such a manufacturing method, a silicon epitaxial wafer is used for manufacturing high performance semiconductor devices. Usually such silicon epitaxial wafers have a silicon epitaxial layer that is about a micrometer to several tens of microns thick.

한편, 반도체 소자 제조 공정에서 웨이퍼의 형상이나 두께, 평탄도 등과 같은 기하학적인 모양은 반도체 칩의 수율에 크게 영향을 미치므로 엄격하게 관리되고 있다. 특히, 반도체 소자의 고집적화가 진행되어 감에 따라 반도체 소자 제조 공정은 웨이퍼의 기하학적인 모양에 대한 의존도가 더욱 커지게 되었다. 즉, 최근 반도체 소자의 선폭 감소와 집적도의 증가로 인해 웨이퍼의 평탄도는 반도체 제조 공정에서의 생산성과 수율에 커다란 영향을 미친다. 특히 포토리소그라피 등의 공정에서 노광 장치의 초점(focusing) 문제로 인해 웨이퍼의 고평탄도가 요구된다. 회로 선폭이 미세하면 미세해질수록, 반도체 공정 상에서 웨이퍼 상의 평탄도 불량에 의해 선의 왜곡현상이 일어나 소자의 수율 저하를 발생시킨다. 따라서, 평탄도가 우수한 고품위 에피텍셜 웨이퍼의 개발이 필요하다.On the other hand, in the semiconductor device manufacturing process, the geometric shape such as the shape, thickness, flatness, etc. of the wafer greatly affects the yield of the semiconductor chip, and is thus strictly managed. In particular, as the integration of semiconductor devices proceeds, the semiconductor device manufacturing process becomes more dependent on the geometric shape of the wafer. That is, the flatness of the wafer has a great influence on the productivity and yield in the semiconductor manufacturing process due to the recent decrease in the line width and the increase in the degree of integration of semiconductor devices. In particular, high flatness of the wafer is required due to the focusing problem of the exposure apparatus in a process such as photolithography. The finer the circuit line width, the lower the flatness on the wafer in the semiconductor process, resulting in distortion of the line, resulting in lowered device yield. Therefore, it is necessary to develop a high quality epitaxial wafer with excellent flatness.

그러나, 일반적인 실리콘 폴리시드 웨이퍼 제조 방법에 의하면, 폴리싱 공정 후의 나쁜 평탄도를 갖는 폴리시드 웨이퍼에 에피텍셜층을 증착하기 때문에, 에피텍셜 웨이퍼 역시 열악한 평탄도를 가지므로 이의 개선이 요구되고 있다.However, according to the general method of manufacturing a silicon polysid wafer, since the epitaxial layer is deposited on a polysid wafer having a poor flatness after the polishing process, the epitaxial wafer also has poor flatness, and its improvement is required.

실시 예는 개선된 평탄도를 갖는 에피텍셜 웨이퍼 제조 방법 및 장치를 제공한다.Embodiments provide an epitaxial wafer fabrication method and apparatus having improved flatness.

일 실시 예에 의하면, 서셉터에 웨이퍼가 안착된 상태에서 상기 웨이퍼에 에피층을 형성하는 에피텍셜 웨이퍼 제조 방법은, 상기 웨이퍼의 전체 두께 편차를 상쇄시킬 수 있도록 매칭된 두께 프로파일을 갖는 상기 에피층의 에피 공정 조건을 상기 웨이퍼의 두께 타입 별로 미리 설정하는 (a) 단계; 상기 서셉터에 안착된 상기 웨이퍼의 센터 영역에서의 제1 두께 편차와 에지 영역에서의 제2 두께 편차를 이용하여, 상기 웨이퍼의 두께 타입을 결정하는 (b) 단계; 및 미리 설정된 상기 에피 공정 조건 중에서, 상기 결정된 두께 타입에 해당하는 에피 공정조건으로 상기 웨이퍼에 상기 에피층을 형성하는 (c) 단계를 포함하고, 상기 에피 공정 조건은 캐리어 가스의 공급량, 소스 가스의 공급량, 가스 공급 밸브의 개/폐 정도, 상기 서셉터의 회전 속도 또는 상기 서셉터의 높이 중 적어도 하나를 포함할 수 있다. 상기 에피 공정 조건은 도펀트 가스의 공급량을 더 포함할 수 있다.According to one embodiment, an epitaxial wafer manufacturing method for forming an epitaxial layer on the wafer while the wafer is seated on a susceptor, the epitaxial layer having a matched thickness profile to offset the overall thickness variation of the wafer (A) preset epi-process conditions of the respective thickness types of the wafer; (B) determining a thickness type of the wafer using the first thickness deviation in the center region and the second thickness variation in the edge region of the wafer seated on the susceptor; And (c) forming the epitaxial layer on the wafer at an epitaxial process condition corresponding to the determined thickness type among the preset epitaxial process conditions, wherein the epitaxial process condition includes a supply amount of a carrier gas, It may include at least one of the supply amount, the opening / closing degree of the gas supply valve, the rotational speed of the susceptor or the height of the susceptor. The epi process condition may further include a supply amount of the dopant gas.

예를 들어, 상기 캐리어 가스의 공급량은 상기 웨이퍼의 위로 공급되는 캐리어 가스의 제1 공급량; 또는 상기 웨이퍼의 아래로 공급되는 캐리어 가스의 제2 공급량 중 적어도 하나를 포함할 수 있다.For example, the supply amount of the carrier gas may include a first supply amount of the carrier gas supplied over the wafer; Or it may include at least one of the second supply amount of the carrier gas supplied to the bottom of the wafer.

예를 들어, 상기 웨이퍼의 센터 영역은 상기 웨이퍼의 중심으로부터 제1 지점까지의 영역으로 정의되고, 상기 웨이퍼의 에지 영역은 상기 웨이퍼의 제2 지점으로부터 제3 지점까지의 영역으로 정의되며, 상기 제2 지점은 상기 제1 지점보다 상기 중심으로부터 멀리 위치하거나 제1 지점과 동일할 수 있고, 상기 제3 지점은 상기 제2 지점보다 상기 중심으로부터 멀리 위치할 수 있다.For example, a center region of the wafer is defined as an area from the center of the wafer to a first point, and an edge region of the wafer is defined as an area from a second point to a third point of the wafer. The second point may be located farther from or the same as the first point than the first point, and the third point may be located farther from the center than the second point.

예를 들어, 상기 제1 및 제2 지점 각각은 80 ㎜ 내지 100 ㎜이고, 상기 제3 지점은 140 ㎜ 내지 148 ㎜일 수 있다. For example, each of the first and second points may be between 80 mm and 100 mm, and the third point may be between 140 mm and 148 mm.

예를 들어, 상기 제1 두께 편차는 상기 중심에서의 제1 두께로부터 상기 제1 지점에서의 제2 두께를 감산한 값이고, 상기 제2 두께 편차는 상기 제2 지점에서의 제3 두께로부터 상기 제3 지점에서의 제4 두께를 감산한 값일 수 있다.For example, the first thickness deviation is a value obtained by subtracting the second thickness at the first point from the first thickness at the center, and the second thickness deviation is the third thickness at the second point. It may be a value obtained by subtracting the fourth thickness at the third point.

예를 들어, 상기 (b) 단계는 상기 제1 및 제2 두께 편차를 구하는 단계; 상기 제1 두께 편차를 제1 기준 두께값과 비교하여 제1 비교값을 구하는 단계; 상기 제2 두께 편차를 제2 기준 두께값과 비교하여 제2 비교값을 구하는 단계; 및 상기 제1 비교값과 상기 제2 비교값을 이용하여 상기 웨이퍼의 두께 타입을 결정하는 단계를 포함할 수 있다.For example, the step (b) may include obtaining the first and second thickness deviations; Obtaining a first comparison value by comparing the first thickness deviation with a first reference thickness value; Obtaining a second comparison value by comparing the second thickness deviation with a second reference thickness value; And determining a thickness type of the wafer using the first comparison value and the second comparison value.

예를 들어, 상기 제1 기준 두께값은 15 ㎚ 혹은 30 ㎚이고, 상기 제2 기준 두께값은 '0'일 수 있다.For example, the first reference thickness value may be 15 nm or 30 nm, and the second reference thickness value may be '0'.

예를 들어, 상기 (a) 단계에서 상기 캐리어 가스의 공급량, 상기 소스 가스의 공급량, 상기 가스 공급 밸브의 개/폐 정도, 상기 서셉터의 회전 속도 및 상기 서셉터의 높이 간의 상대적인 비율이 상기 웨이퍼의 두께 타입 별로 서로 다른 상기 에피 공정 조건으로서 설정될 수 있다.For example, in the step (a), the relative ratio between the supply amount of the carrier gas, the supply amount of the source gas, the opening / closing degree of the gas supply valve, the rotational speed of the susceptor and the height of the susceptor is determined by the wafer. Each of the thickness types may be set as different epi process conditions.

예를 들어, 상기 웨이퍼는 양면 연마된 웨이퍼일 수 있다.For example, the wafer may be a wafer polished on both sides.

다른 실시 예에 의하면, 웨이퍼에 에피층을 형성하는 에피텍셜 웨이퍼 제조 장치는, 캐리어 가스와 소스 가스를 공급하는 가스 공급부; 상기 웨이퍼가 안착되는 서셉터; 상기 서셉터를 지지하는 구동축; 상기 구동축의 승강과 회전 속도를 조절하는 구동부; 상기 가스 공급부로부터 공급되는 상기 캐리어 가스 및 상기 소스 가스를 상기 웨이퍼로 공급하는 가스 공급 밸브; 상기 웨이퍼의 전체 두께 편차를 상쇄시킬 수 있도록 매칭된 두께 프로파일을 갖는 상기 에피층의 에피 공정 조건을 상기 웨이퍼의 두께 타입 별로 저장한 저장부; 상기 서셉터에 안착된 상기 웨이퍼의 두께 타입을 결정하는 두께 타입 결정부; 및 상기 두께 타입 결정부에서 결정된 두께 타입에 상응하는 에피 공정 조건을 상기 저장부로부터 독출하고, 독출된 상기 에피 공정 조건에 해당하는 캐리어 가스의 공급량, 상기 소스 가스의 공급량, 상기 가스 공급 밸브의 개/폐 정도, 상기 서셉터의 회전 속도 또는 상기 서셉터의 높이 중 적어도 하나를 조정하기 위해, 상기 가스 공급부, 상기 가스 공급 밸브 또는 상기 구동부 중 적어도 하나를 제어하는 제어부를 포함할 수 있다.According to another embodiment, an epitaxial wafer manufacturing apparatus for forming an epitaxial layer on a wafer includes a gas supply unit supplying a carrier gas and a source gas; A susceptor on which the wafer is seated; A drive shaft supporting the susceptor; A drive unit which adjusts the lifting speed and the rotation speed of the drive shaft; A gas supply valve supplying the carrier gas and the source gas supplied from the gas supply part to the wafer; A storage unit storing epi process conditions of the epi layer having a matched thickness profile for each thickness type of the wafer so as to cancel the overall thickness variation of the wafer; A thickness type determination unit determining a thickness type of the wafer seated on the susceptor; And reading an epi process condition corresponding to the thickness type determined by the thickness type determining unit from the storage unit, and supplying the carrier gas corresponding to the read epi process condition, supplying the source gas, opening the gas supply valve. And a control unit for controlling at least one of the gas supply unit, the gas supply valve, or the driving unit to adjust at least one of the degree of closure, the rotation speed of the susceptor, and the height of the susceptor.

예를 들어, 상기 제어부는 상기 에피 공정 조건으로서 도펀트의 공급량을 더 제어할 수 있다.For example, the controller may further control the supply amount of the dopant as the epi process condition.

실시 예에 따른 에피텍셜 웨이퍼 제조 방법 및 장치는 웨이퍼(W)의 전체 두께에 편차가 있을 경우, 에피 공정 조건의 각 인자를 복합적으로 조절하여 웨이퍼의 전체 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층을 웨이퍼에 형성함으로써, 개선된 GBIR 및 개선된 SBIR을 갖는 에피텍셜 웨이퍼를 제조하여 수율을 향상시킬 수 있다.The method and apparatus for manufacturing an epitaxial wafer according to the embodiment have a thickness profile capable of offsetting the overall thickness variation of the wafer by complexly adjusting each factor of the epitaxial conditions when the overall thickness of the wafer W is varied. By forming the epi layer on the wafer, an epitaxial wafer with improved GBIR and improved SBIR can be produced to improve yield.

도 1은 실시 예에 의한 에피텍셜 웨이퍼 제조 방법을 설명하기 위한 플로우차트이다.1 is a flowchart illustrating an epitaxial wafer manufacturing method according to an embodiment.

도 2는 실시 예에 의한 에피텍셜 웨이퍼 제조 장치의 단면 형상을 개략적으로 나타내는 도면이다.2 is a view schematically showing a cross-sectional shape of the epitaxial wafer manufacturing apparatus according to the embodiment.

도 3은 도 2에 도시된 가스 공급 밸브의 일 실시 예에 의한 평면도를 나타낸다.3 is a plan view according to an exemplary embodiment of the gas supply valve illustrated in FIG. 2.

도 4a 내지 도 4c는 웨이퍼의 두께 편차가 에피층에 의해 상쇄되는 개념을 설명하기 위한 도면이다.4A to 4C are diagrams for describing a concept in which a thickness variation of a wafer is canceled by an epitaxial layer.

도 5는 도 1에 도시된 제120 단계의 일 실시 예를 설명하기 위한 플로우차트이다.FIG. 5 is a flowchart for describing an exemplary embodiment of the 120th step illustrated in FIG. 1.

도 6은 웨이퍼의 센터 영역과 에지 영역을 설명하기 위한 웨이퍼의 단면 형상을 나타낸다.6 shows a cross-sectional shape of the wafer for explaining the center region and the edge region of the wafer.

도 7a 내지 도 7d는 제1 기준 두께값이 15 ㎚인 경우, 웨이퍼의 제1 내지 제4 타입을 나타내는 도면이다.7A to 7D are diagrams showing first to fourth types of wafers when the first reference thickness value is 15 nm.

도 8a 내지 도 8d는 제1 기준 두께값이 30 ㎚인 경우, 웨이퍼의 제1 내지 제4 타입을 나타내는 도면이다.8A to 8D are diagrams showing first to fourth types of wafers when the first reference thickness value is 30 nm.

도 9a는 GBIR을 설명하기 위한 도면이고, 도 9b는 SBIR을 설명하기 위한 도면이다.FIG. 9A is a diagram for describing the GBIR, and FIG. 9B is a diagram for explaining the SBIR.

도 10a 내지 도 10c는 웨이퍼의 전체 두께 편차가 에피층에 의해 상쇄되어 전체 두께 편차가 개선된 에피텍셜 웨이퍼가 제조되는 과정의 일 례를 설명하기 위한 도면을 나타낸다.10A to 10C are diagrams for explaining an example of a process of manufacturing an epitaxial wafer in which the overall thickness variation is offset by the epitaxial layer to improve the overall thickness variation.

도 11a는 기존의 방법에 의해 제조된 에피텍셜 웨이퍼의 GBIR과 실시 예에 의한 방법에 의해 제조된 에피텍셜 웨이퍼의 GBIR을 나타내고, 도 11b는 기존의 방법에 의해 제조된 에피텍셜 웨이퍼의 SIBR과 실시 예에 의한 방법에 의해 제조된 에피텍셜 웨이퍼의 SBIR을 나타낸다.11A shows the GBIR of the epitaxial wafer manufactured by the conventional method and the GBIR of the epitaxial wafer manufactured by the method according to the embodiment, and FIG. 11B shows the SIBR of the epitaxial wafer manufactured by the conventional method. The SBIR of the epitaxial wafer manufactured by the method by an example is shown.

도 12a는 기존의 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼와 실시 예에 의한 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼의 GBIR의 히스토그램을 나타내고, 도 12b는 기존의 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼와 실시 예에 의한 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼의 SBIR의 히스토그램을 나타낸다.12A shows a histogram of GBIR of several epitaxial wafers manufactured by the conventional method and several epitaxial wafers manufactured by the method according to the embodiment, and FIG. 12B shows several epitaxial wafers manufactured by the conventional method. The histogram of the SBIR of the epitaxial wafers and the sheets of the epitaxial wafers produced by the method according to the embodiment is shown.

이하, 본 발명을 구체적으로 설명하기 위해 실시 예를 들어 설명하고, 발명에 대한 이해를 돕기 위해 첨부도면을 참조하여 상세하게 설명하기로 한다. 그러나, 본 발명에 따른 실시 예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시 예들에 한정되는 것으로 해석되지 않아야 한다. 본 발명의 실시 예들은 당 업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되는 것이다.Hereinafter, the present invention will be described in detail with reference to the following examples, and the present invention will be described in detail with reference to the accompanying drawings. However, embodiments according to the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art.

이하, 실시 예에 의한 에피텍셜 제조 방법(100) 및 장치(200)를 첨부된 도면을 참조하여 다음과 같이 설명한다. 편의상, 데카르트 좌표계(x축, y축, z축)를 이용하여 에피텍셜 제조 장치(200)를 설명하지만, 다른 좌표계에 의해서도 이를 설명할 수 있음은 물론이다.Hereinafter, the epitaxial manufacturing method 100 and the apparatus 200 according to the embodiment will be described with reference to the accompanying drawings. For convenience, the epitaxial manufacturing apparatus 200 will be described using the Cartesian coordinate system (x-axis, y-axis, z-axis), but it can of course be explained by other coordinate systems.

도 1은 실시 예에 의한 에피텍셜 웨이퍼 제조 방법(100)을 설명하기 위한 플로우차트이다.1 is a flowchart illustrating an epitaxial wafer manufacturing method 100 according to an embodiment.

도 2는 실시 예에 의한 에피텍셜 웨이퍼 제조 장치(200)의 단면 형상을 개략적으로 나타내는 도면이고, 도 3은 도 2에 도시된 가스 공급 밸브(240)의 일 실시 예(240A)에 의한 평면도를 나타낸다.FIG. 2 is a view schematically showing a cross-sectional shape of the epitaxial wafer manufacturing apparatus 200 according to the embodiment, and FIG. 3 is a plan view according to an embodiment 240A of the gas supply valve 240 shown in FIG. 2. Indicates.

이해를 돕기 위해, 도 1에 도시된 에피텍셜 웨이퍼 제조 방법(100)은 도 2에 도시된 에피텍셜 웨이퍼 제조 장치(200)에서 수행되는 것으로 설명하지만, 실시 예는 이에 국한되지 않는다. 즉, 도 1에 도시된 에피텍셜 웨이퍼 제조 방법(100)은 도 2에 도시된 에피텍셜 웨이퍼 제조 장치(200)와 다른 구성을 갖는 에피텍셜 웨이퍼 제조 장치에 의해서도 수행될 수 있음은 물론이다.For ease of understanding, the epitaxial wafer manufacturing method 100 shown in FIG. 1 is described as being performed in the epitaxial wafer manufacturing apparatus 200 shown in FIG. 2, but the embodiment is not limited thereto. That is, the epitaxial wafer manufacturing method 100 illustrated in FIG. 1 may also be performed by an epitaxial wafer manufacturing apparatus having a configuration different from that of the epitaxial wafer manufacturing apparatus 200 illustrated in FIG. 2.

도 1에 도시된 에피텍셜 웨이퍼 제조 방법(100)을 설명하기에 앞서, 도 2에 도시된 에피텍셜 웨이퍼 제조 장치(200)에 대해 개략적으로 살펴보면 다음과 같다.Prior to describing the epitaxial wafer manufacturing method 100 illustrated in FIG. 1, the epitaxial wafer manufacturing apparatus 200 illustrated in FIG. 2 will be described below.

도 2에 도시된 에피텍셜 웨이퍼 제조 장치(200)는 챔버(chamber)(210), 챔버 상부 프레임(212), 챔버 하부 프레임(214), 가스 공급부(230), 가스 공급 밸브(240), 구동부(260), 저장부(270), 제어부(280) 및 두께 타입 결정부(290)를 포함할 수 있다.The epitaxial wafer manufacturing apparatus 200 illustrated in FIG. 2 includes a chamber 210, a chamber upper frame 212, a chamber lower frame 214, a gas supply unit 230, a gas supply valve 240, and a driving unit. 260, a storage 270, a controller 280, and a thickness type determiner 290.

챔버(210)는 웨이퍼(W)의 표면에 에피텍셜(epitaxial)층(이하, '에피층')(E)과 같은 막을 형성하기 위해 열처리가 수행되는 장소로서 석영 유리로 구현될 수 있다. 예를 들어, 웨이퍼(W)는 폴리시드(polished) 웨이퍼일 수 있으나, 실시 예는 이에 국한되지 않는다. 챔버(210)는 챔버 상부 프레임(212)과 챔버 하부 프레임(214)을 가지며, 이들(212, 214) 사이에 가스 유입구(IN) 및 가스 배출구(OUT)가 배치될 수 있다. 챔버(210) 내부에서 웨이퍼(W)에 에피층(E)을 성장시키기 위해 필요한 캐리어(carrier) 가스, 소스(source) 가스(또는, 원료 가스 또는 반응 가스)가 가스 유입구(IN)를 통해 챔버(210)의 내부로 도입되어 웨이퍼(W)에 에피층(E)이 형성될 수 있고, 에피층(E)을 형성한 이후에 반응에 기여한 가스는 가스 배출구(OUT)를 통해 배출될 수 있다. 이를 위해, 가스 유입구(IN)와 가스 배출구(OUT)는 서로 대향하여 형성되며, 가스 유입구(IN)를 통해 유입된 소스가스가 웨이퍼(W)의 표면을 따라 층류 상태로 흐를 수 있다.The chamber 210 may be formed of quartz glass as a place where heat treatment is performed to form a film such as an epitaxial layer (hereinafter, referred to as an 'epitaxial layer') E on the surface of the wafer W. For example, the wafer W may be a polished wafer, but embodiments are not limited thereto. The chamber 210 has a chamber upper frame 212 and a chamber lower frame 214, and a gas inlet IN and a gas outlet OUT may be disposed between the chambers 212 and 214. A carrier gas, a source gas (or a source gas or a reactive gas) required for growing the epi layer E on the wafer W in the chamber 210 is provided through the gas inlet IN. An epitaxial layer E may be formed in the wafer W by being introduced into the 210, and a gas that contributes to the reaction after the epitaxial layer E is formed may be discharged through the gas outlet OUT. . To this end, the gas inlet IN and the gas outlet OUT are formed to face each other, and the source gas introduced through the gas inlet IN may flow along the surface of the wafer W in a laminar flow state.

챔버(210)는 서셉터(susceptor)(220), 리프트 아암(lift arm)(250), 지지부 받침부(252), 구동축(또는, 지지축)(254) 및 지지핀(256)을 포함할 수 있다.The chamber 210 may include a susceptor 220, a lift arm 250, a support base 252, a drive shaft (or support shaft) 254, and a support pin 256. Can be.

반송부(미도시)에 의해 웨이퍼(W)가 한 장씩 챔버(210)의 내부로 또는 챔버(210) 외부로 매엽식으로 반입되거나 반출될 수 있으며, 실시 예는 이러한 웨이퍼(W)가 운반되는 장 수 등에 의해 국한되지 않는다.The wafer W may be loaded or unloaded into the chamber 210 or out of the chamber 210 one by one by a conveying unit (not shown). It is not limited by longevity.

서셉터(220)는 웨이퍼(또는, 기판)(W)에 에피층을 형성하는 동안, 웨이퍼(W)가 안착(loading)될 공간을 제공하며, 웨이퍼(W)를 지지하는 역할을 한다. 서셉터(220)는 탄화 실리콘으로 커버되는 그래파이트(graphite) 재료로 이루어질 수 있으며, 원반 평면 형상을 가질 수 있다. 또한, 서셉터(220)는 다양한 단면 형상을 가질 수 있다. 서셉터(220)에 안착된 후, 웨이퍼(W)는 급속 열처리될 수도 있고 에피층(E)이 웨이퍼(W)의 주면 위에 성장될 수도 있다.The susceptor 220 provides a space in which the wafer W is to be loaded and supports the wafer W while forming the epitaxial layer on the wafer (or substrate) W. The susceptor 220 may be made of a graphite material covered with silicon carbide, and may have a disk planar shape. In addition, the susceptor 220 may have various cross-sectional shapes. After being seated on the susceptor 220, the wafer W may be rapidly heat treated and the epi layer E may be grown on the main surface of the wafer W. FIG.

지지부 받침부(252)는 서셉터(220)를 받치는 역할을 하는 부분으로서, 재질은 석영, 실리콘, 또는 탄화 규소일 수 있으며, 석영에 실리콘이나 탄화 규소의 피막을 입혀 구현될 수 있다.The support part supporting part 252 is a part serving to support the susceptor 220, and the material may be quartz, silicon, or silicon carbide, and may be implemented by coating silicon or silicon carbide with quartz.

리프트 아암(250)은 구동축(254)과 지지핀(256) 사이에 배치되며, 방사선 모양으로 구동축(254)으로부터 연장되어 지지핀(256)과 연결될 수 있다. 리프트 아암(250)은 구동축(254)이 승강 운동을 할 때, 지지핀(256)을 승강시키는 역할을 한다.The lift arm 250 is disposed between the drive shaft 254 and the support pin 256, and may extend from the drive shaft 254 in a radial shape to be connected to the support pin 256. The lift arm 250 serves to raise and lower the support pin 256 when the drive shaft 254 moves up and down.

지지핀(256)은 리프트 아암(250)의 선단으로부터 수직 방향으로 연장되고, 서셉터(220)를 관통하여 배치되며, 리프트 아암(250)이 승강운동을 할 때 함께 승강되도록 리프트 아암(250)과 연결된다. 이를 위해, 서셉터(220)는 지지핀(256)이 삽입되는 관통공(미도시)을 가질 수 있다.The support pin 256 extends in a vertical direction from the tip of the lift arm 250, is disposed through the susceptor 220, and the lift arm 250 to be lifted together when the lift arm 250 moves. Connected with To this end, the susceptor 220 may have a through hole (not shown) into which the support pin 256 is inserted.

구동축(254)은 지지부 받침부(252)와 연결되어 서셉터(220)를 지지하는 역할을 하고, 리프트 아암(250)과 연결되어 지지핀(256)을 지지하는 역할을 한다. 구동부(260)에 의해 구동축(254)은 회전 운동을 하거나 승강 운동을 할 수 있다. 즉, 구동축(254)은 구동부(260)에 의해 그의 승강 및 회전 속도가 결정될 수 있다. 구동부(260)에 의해 구동축(254)이 회전할 때, 지지부 받침부(252)와 함께 서셉터(220)가 회전함으로써 웨이퍼(W)가 회전할 수 있다. 예를 들어, 웨이퍼(W) 위에 에피층(E)을 형성할 때 에피층(E)의 두께가 균일하게 형성되도록 하기 위해, 웨이퍼(W)는 고속으로 회전될 수 있다.The drive shaft 254 is connected to the support base 252 to support the susceptor 220, and is connected to the lift arm 250 to support the support pin 256. The drive shaft 254 may rotate or move up and down by the driving unit 260. That is, the driving shaft 254 may be determined by the driving unit 260 its lifting and rotation speed. When the drive shaft 254 is rotated by the driver 260, the susceptor 220 rotates together with the support part supporter 252 so that the wafer W may rotate. For example, when forming the epi layer E on the wafer W, the wafer W may be rotated at high speed so that the thickness of the epi layer E is formed uniformly.

또한, 구동부(260)는 리프트 아암(250)을 통해 지지핀(256)을 승강시키는 역할을 하고, 지지부 받침부(252)를 통해 서셉터(220)를 승강시키는 역할을 한다. 제어부(280)로부터 발생된 제3 제어 신호(C3)에 응답하여, 구동부(260)는 구동축(254)의 승강 또는 회전 속도 중 적어도 하나를 조절할 수 있다. 예를 들어, 구동부(260)에 의해 구동축(254)이 승강할 때, 서셉터(220)의 높이가 올라가거나 내려갈 수 있다.In addition, the driving unit 260 serves to elevate the support pin 256 through the lift arm 250, and serves to elevate the susceptor 220 through the support base 252. In response to the third control signal C3 generated from the controller 280, the driver 260 may adjust at least one of lifting and lowering speeds of the driving shaft 254. For example, when the driving shaft 254 is lifted and lowered by the driving unit 260, the height of the susceptor 220 may be raised or lowered.

가스 공급부(230)는 캐리어 가스, 소스 가스 및 도펀트 가스를 가스 공급 밸브(240)로 공급하는 역할을 한다. 이때, 제어부(280)로부터 발생된 제1 제어 신호(C1)에 응답하여, 가스 공급부(240)는 가스 공급 밸브(240)로 공급되는 캐리어 가스의 공급량, 소스 가스의 공급량 및 도펀트 가스의 공급량을 각각 조절할 수 있다.The gas supply unit 230 supplies a carrier gas, a source gas, and a dopant gas to the gas supply valve 240. At this time, in response to the first control signal C1 generated from the controller 280, the gas supply unit 240 supplies the supply amount of the carrier gas, the supply amount of the source gas, and the supply amount of the dopant gas supplied to the gas supply valve 240. Each can be adjusted.

가스 공급 밸브(Accuset)(또는, AMV:Automated Metering Valve)(240)는 가스 공급부(230)로부터 공급되는 캐리어 가스, 소스 가스 및 도펀트 가스를 가스 유입구(IN)를 통해 챔버(210)의 내부로 주입하여 웨이퍼(W)로 공급하는 역할을 한다. 이때, 제어부(280)로부터 발생된 제2 제어 신호(C2)에 응답하여, 가스 공급 밸브(240)의 개/폐 정도가 조정될 수 있다.The gas supply valve (Accuset) (or AMV: Automated Metering Valve) 240 may transfer the carrier gas, the source gas, and the dopant gas supplied from the gas supply unit 230 to the inside of the chamber 210 through the gas inlet IN. It is injected and serves to supply the wafer (W). In this case, the opening / closing degree of the gas supply valve 240 may be adjusted in response to the second control signal C2 generated from the controller 280.

도 3을 참조하면, 가스 공급 밸브(240A)는 중앙 분사 노즐과 가장 자리 분사 노즐을 포함할 수 있다. 중앙 분사 노즐은 웨이퍼(W)의 중심부(IN)를 향해 가스를 분사하고, 가장 자리 분사 노즐은 웨이퍼(W)의 가장 자리(OUT1, OUT2)를 향해 가스를 분사한다. 이러한 노즐 구성 방식을 MPI(multiport injector)라고도 칭한다.Referring to FIG. 3, the gas supply valve 240A may include a central injection nozzle and an edge injection nozzle. The central injection nozzle injects gas toward the center portion IN of the wafer W, and the edge injection nozzle injects gas toward the edges OUT1 and OUT2 of the wafer W. This nozzle configuration method is also referred to as multiport injector (MPI).

전술한 구성을 갖는 에피텍셜 웨이퍼 제조 장치(200)에 의해 에피텍셜 웨이퍼를 제조하는 과정에 대해 간략히 살펴보면 다음과 같다.The process of manufacturing the epitaxial wafer by the epitaxial wafer manufacturing apparatus 200 having the above-described configuration will be briefly described as follows.

서셉터(220) 상에 웨이퍼(W)를 안착시킨 후, 웨이퍼(W)의 온도를 예를 들어 1100 ℃ 내지 1200℃ 정도로 유지하고, 수소(H2) 분위기 중에서 약 10분 정도의 열처리에 의해 탄소계 불순물이나 자연 산화막 등을 제거한다.After the wafer W is seated on the susceptor 220, the temperature of the wafer W is maintained at about 1100 ° C. to 1200 ° C., for example, and the carbon is subjected to heat treatment for about 10 minutes in a hydrogen (H 2) atmosphere. Eliminate system impurities and natural oxide films.

이후, TCS(Trichlorosilane, SiHCl3) 또는 SiH2Cl2와 같은 소스 가스와 수소(H2)와 같은 캐리어 가스를 챔버(210) 내로 공급한다. 에피층(E)을 도전성 있게 증착하고자 할 경우, B2H6나 PH3와 같은 도펀트 가스가 캐리어 가스 및 소스 가스와 함께 챔버(210)로 공급할 수 있다.Thereafter, a source gas such as Trichlorosilane (SiHCl 3) or SiH 2 Cl 2 and a carrier gas such as hydrogen (H 2) are supplied into the chamber 210. When the epitaxial layer E is to be conductively deposited, a dopant gas such as B2H6 or PH3 may be supplied to the chamber 210 together with the carrier gas and the source gas.

캐리어 가스, 소스 가스 및 도펀트 가스는 챔버(210) 내부에서 화살표 방향(310)으로 공급되며, 뿐만 아니라 캐리어 가스는 화살표 방향(320)으로도 공급될 수 있다. 에피텍셜 웨이퍼 제조 장치(200)의 히터(미도시)에 의해 이러한 가스가 분해되고 반응하여 웨이퍼(W)에 에피텍셜층(E)이 증착되어 에피텍셜 웨이퍼(EP)가 제조될 수 있다.The carrier gas, the source gas and the dopant gas may be supplied in the arrow direction 310 inside the chamber 210, as well as the carrier gas may be supplied in the arrow direction 320. The gas may be decomposed and reacted by a heater (not shown) of the epitaxial wafer manufacturing apparatus 200 to deposit the epitaxial layer E on the wafer W, thereby manufacturing the epitaxial wafer EP.

도 1 내지 도 3을 참조하여, 실시 예에 의한 에피텍셜 웨이퍼 제조 방법(100)을 살펴보면 다음과 같다.Referring to FIGS. 1 to 3, an epitaxial wafer manufacturing method 100 according to an embodiment is as follows.

웨이퍼(W)의 전체 두께 편차를 상쇄시킬 수 있도록 매칭된 두께 프로파일을 갖는 에피층(E)의 에피 공정 조건을 웨이퍼(W)의 두께 타입별로 미리 설정한다(제110 단계). 예를 들어, 웨이퍼(W)의 두께 타입별로 서로 달리 설정된 에피층의 에피 공정 조건은 저장부(270)에 저장될 수 있다.Epi process conditions of the epi layer E having a matched thickness profile are set in advance for each thickness type of the wafer W so as to offset the overall thickness variation of the wafer W (step 110). For example, the epi process conditions of the epi layer set differently for each thickness type of the wafer W may be stored in the storage unit 270.

도 1에 도시된 에피텍셜 웨이퍼 제조 방법(100)에서 에피층(E)이 형성될 웨이퍼(W)란, 소정의 실리콘 잉곳을 슬라이싱하여 웨이퍼 형태로 얇게 절단하고, 절단된 웨이퍼를 래핑하여 양면을 연마(DSP:Double Side Polishing)한 후, 식각, 폴리싱 등의 공정을 적용함으로써 준비될 수 있다. 이후, 웨이퍼(W)는 최종 폴리싱(FP:Final Polishing)된 후, 암모니아 및 과산화수소 혼합액 등의 알칼리 수용액 및/또는 불소산 등의 산 수용액으로 세척된 후 서셉터(220)에 안착될 수 있다.In the epitaxial wafer manufacturing method 100 shown in FIG. 1, the wafer W on which the epitaxial layer E is to be formed is sliced into a predetermined silicon ingot and cut into thin wafers, and the cut wafer is wrapped to form both surfaces. After double side polishing (DSP), it may be prepared by applying a process such as etching, polishing, and the like. Subsequently, after the final polishing (FP: Final Polishing), the wafer W may be washed with an alkaline aqueous solution such as ammonia and hydrogen peroxide mixed solution and / or an acid aqueous solution such as hydrofluoric acid, and then mounted on the susceptor 220.

또한, 웨이퍼(W)는 실리콘 웨이퍼일 수 있으며, 예를 들어 300 ㎜의 구경을 가질 수 있지만, 실시 예는 웨이퍼(W)의 재질이나 구경에 의해 국한되지 않는다.In addition, the wafer W may be a silicon wafer, for example, may have a diameter of 300 mm, but the embodiment is not limited by the material or the diameter of the wafer W.

도 4a 내지 도 4c는 웨이퍼(W)의 두께 편차가 에피층(E)에 의해 상쇄되는 개념을 설명하기 위한 도면으로서, 각 도면에서 횡축은 y축 방향(즉, 웨이퍼(W)의 반경 방향)으로의 위치를 나타내고, 종축은 z축 방향으로의 위치(예를 들어, 웨이퍼의 정규화된 두께(Normalized THK))를 나타낸다.4A to 4C are diagrams for explaining a concept in which the thickness variation of the wafer W is canceled by the epi layer E. In each drawing, the horizontal axis represents the y-axis direction (that is, the radial direction of the wafer W). The vertical axis represents the position in the z-axis direction (eg, normalized THK of the wafer).

구체적으로 도 4a는 웨이퍼(W)의 두께 프로파일을 나타내고, 도 4b는 웨이퍼(W)의 두께 편차를 상쇄시킬 수 있는 에피층(E)의 두께 프로파일을 나타내고, 도 4c는 웨이퍼(W)의 두께 편차가 에피층(E)에 의해 상쇄된 에피텍셜 웨이퍼(EW)의 두께 프로파일을 나타낸다.Specifically, FIG. 4A shows the thickness profile of the wafer W, FIG. 4B shows the thickness profile of the epi layer E that can offset the thickness variation of the wafer W, and FIG. 4C shows the thickness of the wafer W. FIG. The deviation represents the thickness profile of the epitaxial wafer EW offset by the epi layer E. FIG.

예를 들어, 도 4a에 예시된 바와 같이 웨이퍼(W)의 센터 영역(CA:Center Area)은 두께가 플랫(flat)하여 두께 편차가 없고 웨이퍼(W)의 에지 영역(EA:Edge Area)은 상부로 휘어진 두께 편차를 갖는다고 가정한다. 이 경우, 도 4b에 예시된 두께 프로파일을 갖는 에피층(E)을 웨이퍼(W)에 형성할 경우, 도 4c에 예시된 바와 같이 에피층(E)이 형성된 웨이퍼(W)(즉, '에피텍셜 웨이퍼(EW)'라 한다)의 전체 두께 편차는 없어질 수 있다. 이는 에피층(E)에 의해 웨이퍼(W)의 전체 두께 편차가 상쇄되기 때문이다. 예를 들어, 도 4b에 예시된 바와 같은 에피층(E)은 에피 공정 조건에 의해 구현될 수 있다.For example, as illustrated in FIG. 4A, the center area (CA) of the wafer W has a flat thickness and there is no thickness variation, and the edge area (EA) of the wafer W is It is assumed that there is a thickness deviation bent upwards. In this case, when the epi layer E having the thickness profile illustrated in FIG. 4B is formed on the wafer W, the wafer W on which the epi layer E is formed as shown in FIG. The overall thickness variation of the text wafer EW 'may be eliminated. This is because the entire thickness variation of the wafer W is canceled out by the epi layer E. FIG. For example, the epi layer E as illustrated in FIG. 4B may be implemented by epi process conditions.

전술한 바와 같이, 웨이퍼(W)의 두께 편차를 상쇄시킬 수 있도록 매칭된 두께 파일을 갖는 에피층(E)을 형성하기 위한 에피 공정 조건은, 캐리어 가스의 공급량, 소스 가스의 공급량, 가스 공급 밸브(240, 240A)의 개/폐 정도, 서셉터(220)의 회전 속도 또는 서셉터(220)의 높이 중 적어도 하나를 포함할 수 있다. 여기서, 서셉터(220)가 회전할 때 웨이퍼(W)도 회전하므로, 서셉터(220)의 회전 속도는 웨이퍼(W)의 회전 속도를 의미할 수도 있다.As described above, the epi process conditions for forming the epi layer E having a matched thickness file so as to offset the thickness variation of the wafer W include the supply amount of the carrier gas, the supply amount of the source gas, and the gas supply valve. It may include at least one of the opening and closing degree of the 240, 240A, the rotational speed of the susceptor 220 or the height of the susceptor 220. Here, since the wafer W also rotates when the susceptor 220 rotates, the rotational speed of the susceptor 220 may mean the rotational speed of the wafer (W).

캐리어 가스의 공급량은 제1 또는 제2 공급량 중 적어도 하나를 포함할 수 있다. 제1 공급량이란, 예를 들어 도 2에 화살표(310)로 표시한 바와 같이 웨이퍼(W)의 위로 공급되는 캐리어 가스의 공급량을 의미할 수 있다. 또한, 제2 공급량이란, 예를 들어, 도 2에 화살표(320)로 표시한 바와 같이 웨이퍼(W)의 아래로 공급되는 캐리어 가스의 공급량을 의미할 수 있다.The supply amount of the carrier gas may include at least one of the first and second supply amounts. For example, the first supply amount may mean a supply amount of a carrier gas supplied onto the wafer W, as indicated by an arrow 310 in FIG. 2. In addition, the second supply amount may mean, for example, a supply amount of a carrier gas supplied below the wafer W, as indicated by an arrow 320 in FIG. 2.

또한, 에피 공정 조건은 도펀트 가스의 공급량을 더 포함할 수 있지만, 실시 예는 이에 국한되지 않는다. 도펀트 가스는 소스 가스와 함께 도 2에 화살표(310)로 표시한 바와 같이 챔버(210) 내에서 공급될 수 있다.In addition, the epi process conditions may further include a supply amount of the dopant gas, but the embodiment is not limited thereto. The dopant gas may be supplied together with the source gas in the chamber 210 as indicated by arrow 310 in FIG. 2.

또한, 실시 예에 의하면, 웨이퍼(W)의 두께 타입별로 서로 다른 에피 공정 조건이란, 캐리어 가스의 공급량, 소스 가스의 공급량, 가스 공급 밸브(240, 240A)의 개/폐 정도, 서셉터(220)의 회전 속도 및 서셉터(220)의 높이 간의 상대적인 비율을 의미할 수 있다. 이러한 일 례는 후술되는 표 1에 보여진다.In addition, according to the embodiment, the epi process conditions different for each thickness type of the wafer W include a supply amount of a carrier gas, a supply amount of a source gas, an opening / closing degree of the gas supply valves 240 and 240A, and the susceptor 220. It may mean a relative ratio between the rotational speed of) and the height of the susceptor 220. One such example is shown in Table 1 below.

다시 도 1을 참조하면, 제110 단계 후에, 서셉터(220)에 안착된 웨이퍼(W)의 센터 영역(CA)에서의 제1 두께 편차(ΔT1)와 에지 영역(EA)에서의 제2 두께 편차(ΔT2)를 이용하여, 에피층(E)을 형성하기 위한 대상이 되는 웨이퍼(W)의 두께 타입을 결정한다(제120 단계). 예를 들어, 제120 단계는 도 2에 도시된 두께 타입 결정부(290)에서 수행될 수 있다. 즉, 두께 타입 결정부(290)는 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 결정하고, 결정된 두께 타입을 제어부(280)로 출력할 수 있다.Referring back to FIG. 1, after step 110, the first thickness deviation ΔT1 in the center region CA of the wafer W seated on the susceptor 220 and the second thickness in the edge region EA. The thickness ΔT2 is used to determine the thickness type of the wafer W as a target for forming the epi layer E (step 120). For example, step 120 may be performed by the thickness type determiner 290 illustrated in FIG. 2. That is, the thickness type determiner 290 may determine the thickness type of the wafer W seated on the susceptor 220, and output the determined thickness type to the controller 280.

도 5는 도 1에 도시된 제120 단계의 일 실시 예(120A)를 설명하기 위한 플로우차트이다.FIG. 5 is a flowchart for describing an embodiment 120A of the 120th step illustrated in FIG. 1.

도 6은 웨이퍼(W)의 센터 영역(CA)과 에지 영역(EA)을 설명하기 위한 웨이퍼(W)의 단면 형상을 나타낸다.6 shows a cross-sectional shape of the wafer W for explaining the center area CA and the edge area EA of the wafer W. As shown in FIG.

도 5에 도시된 제120A 단계를 설명하기에 앞서, 도 6을 참조하여 웨이퍼(W)의 센터 영역(CA)과 에지 영역(EA)에 대해 살펴보면 다음과 같다.Before describing step 120A shown in FIG. 5, the center area CA and the edge area EA of the wafer W will be described with reference to FIG. 6.

웨이퍼(W)의 센터 영역(CA)이란, 웨이퍼(W)의 중심(PO)으로부터 제1 지점(±P1)까지의 영역으로 정의될 수 있다. 또한, 웨이퍼(W)의 에지 영역(EA)이란, 웨이퍼(W)의 제2 지점(±P2)으로부터 제3 지점(±P3)까지의 영역으로 정의될 수 있다. 제2 지점(±P2)은 제1 지점(±P1) 보다 중심(P0)으로부터 멀리 위치하거나 제1 지점(±P1)과 동일할 수 있고, 제3 지점(±P3)은 제2 지점(±P2)보다 중심(P0)으로부터 멀리 위치할 수 있다.The center area CA of the wafer W may be defined as an area from the center PO of the wafer W to the first point ± P1. In addition, the edge area EA of the wafer W may be defined as an area from the second point ± P2 to the third point ± P3 of the wafer W. The second point ± P2 may be located farther from the center P0 than the first point ± P1 or may be the same as the first point ± P1, and the third point ± P3 may be the second point ± It may be located far from the center P0 than P2).

만일, 웨이퍼(W)가 300 ㎜의 직경을 갖는 양면 연마(DSP:Double Side Polishing)된 웨이퍼일 경우, 제1 지점(P1)은 80 ㎜ 내지 100 ㎜ 예를 들어, 90 ㎜이고, 제2 지점(P2)은 80 ㎜ 내지 100 ㎜ 예를 들어, 100 ㎜이고, 제3 지점(P3)은 140 ㎜ 내지 148 ㎜ 예를 들어, 144 ㎜일 수 있으나, 실시 예는 이에 국한되지 않는다.If the wafer W is a double side polished wafer having a diameter of 300 mm, the first point P1 is 80 mm to 100 mm, for example, 90 mm, and the second point. P2 may be 80 mm to 100 mm, for example, 100 mm, and the third point P3 may be 140 mm to 148 mm, for example, 144 mm, but the embodiment is not limited thereto.

또한, 제1 두께 편차(ΔT1)란 중심(P0)에서의 제1 두께(T1)로부터 제1 지점(P1)에서의 제2 두께(T2)를 감산한 값이고, 제2 두께 편차(ΔT2)란 제2 지점(P2)에서의 제3 두께(T3)로부터 제3 지점(P3)에서의 제4 두께(T4)를 감산한 값일 수 있으나, 실시 예는 이에 국한되지 않는다.The first thickness deviation ΔT1 is a value obtained by subtracting the second thickness T2 at the first point P1 from the first thickness T1 at the center P0, and the second thickness deviation ΔT2. The column may be a value obtained by subtracting the fourth thickness T4 at the third point P3 from the third thickness T3 at the second point P2, but the embodiment is not limited thereto.

다시, 도 5를 참조하면, 제110 단계 후에, 서셉터(220)에 안착된 웨이퍼(W)의 제1 두께 편차(ΔT1) 및 제2 두께 편차(ΔT2)를 구한다(제121 단계).Referring back to FIG. 5, after step 110, the first thickness deviation ΔT1 and the second thickness deviation ΔT2 of the wafer W seated on the susceptor 220 are obtained (step 121).

제121 단계 후에, 제1 두께 편차(ΔT1)를 제1 기준 두께값(RT1)과 비교하여 제1 비교값을 구하고, 제2 두께 편차(ΔT2)를 제2 기준 두께값(RT2)과 비교하여 제2 비교값을 구하고, 제1 비교값과 제2 비교값을 이용하여 웨이퍼(W)의 두께 타입을 결정할 수 있다(제122 내지 제128 단계).After operation 121, a first comparison value is obtained by comparing the first thickness deviation ΔT1 with the first reference thickness value RT1, and the second thickness deviation ΔT2 is compared with the second reference thickness value RT2. The second comparison value may be obtained, and the thickness type of the wafer W may be determined using the first comparison value and the second comparison value (steps 122 to 128).

예를 들어, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작은가를 판단한다(제122 단계). 만일, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작은 것으로 판단되면, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)보다 큰가를 판단한다(제123 단계). 그러나, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작지 않은 것으로 판단되면, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)보다 큰가를 판단한다(제124 단계). 예를 들어, 제1 기준 두께값(RT1)은 15 ㎚ 혹은 30 ㎚이고, 제2 기준 두께값(RT2)은 '0'일 수 있으나, 실시 예는 이에 국한되지 않는다.For example, it is determined whether the first thickness deviation ΔT1 is smaller than the first reference thickness value RT1 (step 122). If it is determined that the first thickness deviation ΔT1 is smaller than the first reference thickness value RT1, it is determined whether the second thickness deviation ΔT2 is greater than the second reference thickness value RT2 (step 123). . However, if it is determined that the first thickness deviation ΔT1 is not smaller than the first reference thickness value RT1, it is determined whether the second thickness deviation ΔT2 is greater than the second reference thickness value RT2 (step 124). ). For example, the first reference thickness value RT1 may be 15 nm or 30 nm, and the second reference thickness value RT2 may be '0', but embodiments are not limited thereto.

만일, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)보다 큰 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제1 타입(TP1)으로서 결정한다(제125 단계).If the first thickness deviation ΔT1 is smaller than the first reference thickness value RT1, and the second thickness deviation ΔT2 is greater than the second reference thickness value RT2, the wafer seated on the susceptor 220. The thickness type of (W) is determined as the first type TP1 (step 125).

또한, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)보다 크지 않은 것으로 판단되면, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제2 타입(TP2)으로서 결정한다(제126 단계).In addition, when it is determined that the first thickness deviation ΔT1 is smaller than the first reference thickness value RT1 and the second thickness deviation ΔT2 is not larger than the second reference thickness value RT2, the susceptor 220 is determined. The thickness type of the seated wafer W is determined as the second type TP2 (step 126).

또한, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작지 않고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)보다 큰 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제3 타입(TP3)으로서 결정한다(제127 단계).In addition, when the first thickness deviation ΔT1 is not smaller than the first reference thickness value RT1 and the second thickness deviation ΔT2 is larger than the second reference thickness value RT2, the first thickness deviation ΔT1 may be seated on the susceptor 220. The thickness type of the wafer W is determined as the third type TP3 (step 127).

또한, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)보다 작지 않고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)보다 크지 않은 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제4 타입(TP4)으로서 결정한다(제128 단계).In addition, when the first thickness deviation ΔT1 is not smaller than the first reference thickness value RT1 and the second thickness deviation ΔT2 is not greater than the second reference thickness value RT2, it is seated on the susceptor 220. The thickness type of the wafer W thus obtained is determined as the fourth type TP4 (step 128).

도 5의 경우, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)과 동일할 경우 제124 단계로 진행하는 것으로 예시되어 있으나, 실시 예는 이에 국한되지 않는다. 즉, 다른 실시 예에 의하면, 제122 단계에서 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)과 동일하다고 판단될 경우 제124 단계 대신에 제123 단계로 진행할 수도 있다.In FIG. 5, when the first thickness deviation ΔT1 is equal to the first reference thickness value RT1, the process proceeds to step 124. However, the embodiment is not limited thereto. That is, according to another embodiment, when it is determined in step 122 that the first thickness deviation ΔT1 is equal to the first reference thickness value RT1, the process may proceed to step 123 instead of step 124.

이와 비슷하게, 제123 단계에서 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)과 동일할 경우 제126 단계로 진행하는 것으로 예시되어 있으나, 실시 예는 이에 국한되지 않는다. 즉, 다른 실시 예에 의하면, 제123 단계에서 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)과 동일하다고 판단될 경우 제126 단계 대신에 제125 단계로 진행할 수 있다.Similarly, when the second thickness deviation ΔT2 is equal to the second reference thickness value RT2 in step 123, the process proceeds to step 126, but the embodiment is not limited thereto. That is, according to another embodiment, when it is determined in step 123 that the second thickness deviation ΔT2 is equal to the second reference thickness value RT2, the process may proceed to step 125 instead of step 126.

또한, 제124 단계에서 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)과 동일할 경우 제128 단계로 진행하는 것으로 예시되어 있으나, 실시 예는 이에 국한되지 않는다. 즉, 다른 실시 예에 의하면, 제124 단계에서 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)과 동일하다고 판단될 경우 제128 단계 대신에 제127 단계로 진행할 수도 있다.In addition, when the second thickness deviation ΔT2 is equal to the second reference thickness value RT2 in step 124, the process proceeds to step 128, but the embodiment is not limited thereto. That is, according to another embodiment, when it is determined in step 124 that the second thickness deviation ΔT2 is equal to the second reference thickness value RT2, the process may proceed to step 127 instead of step 128.

도 5에 도시된 제120A 단계는 도 3에 도시된 두께 타입 결정부(290)에서 수행될 수 있다.Step 120A illustrated in FIG. 5 may be performed by the thickness type determiner 290 illustrated in FIG. 3.

제120 또는 제120A 단계 후에, 미리 설정된 에피 공정 조건 중에서, 제120 또는 제120A) 단계에서 결정된 두께 타입에 해당하는 에피 공정 조건에서 웨이퍼(W)에 에피층을 형성할 수 있다(제130 단계).After the 120 or 120A step, an epitaxial layer may be formed on the wafer W under epi process conditions corresponding to the thickness type determined in the 120 or 120A) step among the preset epi process conditions (step 130). .

제130 단계가 수행될 수 있도록, 제어부(280)는 두께 타입 결정부(290)에서 결정된 웨이퍼(W)의 두께 타입에 상응하는 에피 공정 조건을 저장부(270)로부터 독출하고, 독출된 에피 공정 조건에 의거하여 제1 내지 제3 제어 신호(C1 내지 C3)를 발생하여 각 부(230, 240, 260)를 제어할 수 있다. 즉, 제어부(280)는 제1 제어 신호(C1)를 발생하여 가스 공급부(230)를 제어함으로써, 캐리어 가스의 공급량, 소스 가스의 공급량 및 도펀트 가스의 공급량을 조절할 수 있다. 또한, 제어부(280)는 제2 제어 신호(C2)를 발생하여 가스 공급 밸브(240)의 개/폐 정도를 조정할 수 있다. 또한, 제어부(280)는 제3 제어 신호(C3)를 발생하여 구동부(260)를 통해 구동축(254)의 승강과 회전 속도를 제어함으로써, 서셉터(220)의 회전 속도 또는 서셉터(220)의 높이 중 적어도 하나를 조정할 수 있다.In order to perform step 130, the controller 280 reads an epi process condition corresponding to the thickness type of the wafer W determined by the thickness type determiner 290 from the storage unit 270, and reads the epi process. The units 230, 240, and 260 may be controlled by generating the first to third control signals C1 to C3 based on the condition. That is, the controller 280 may control the gas supply unit 230 by generating the first control signal C1 to adjust the supply amount of the carrier gas, the supply amount of the source gas, and the supply amount of the dopant gas. In addition, the controller 280 may generate a second control signal C2 to adjust the opening / closing degree of the gas supply valve 240. In addition, the controller 280 generates a third control signal C3 to control the raising and lowering speed of the driving shaft 254 through the driving unit 260 to thereby rotate the susceptor 220 or the susceptor 220. At least one of the height can be adjusted.

이하, 전술한 실시 예에 의한 에피텍셜 웨이퍼 제조 방법(100) 및 장치(200)의 이해를 돕기 위해, 제1 지점(P1)과 제2 지점(P2) 각각은 동일하게 90 ㎜이고, 제3 지점(P3)은 148 ㎜이고, 제1 기준 두께값(RT1)이 15 ㎚ 또는 30 ㎚이고, 제2 기준 두께값(RT2)이 0 ㎚라고 가정하면서, 웨이퍼(W)의 두께 타입별로 에피 공정 조건을 달리하여 웨이퍼(W)에 에피층(E)을 형성하는 례에 대해 첨부된 도면을 참조하여 다음과 같이 살펴본다.Hereinafter, to facilitate understanding of the epitaxial wafer manufacturing method 100 and the apparatus 200 according to the above-described embodiment, each of the first point P1 and the second point P2 is equal to 90 mm, and the third The epitaxial process for each thickness type of the wafer W, assuming that the point P3 is 148 mm, the first reference thickness value RT1 is 15 nm or 30 nm, and the second reference thickness value RT2 is 0 nm. An example of forming the epitaxial layer E on the wafer W under different conditions will be described as follows with reference to the accompanying drawings.

도 7a 내지 도 7d는 제1 기준 두께값(RT1)이 15 ㎚인 경우, 웨이퍼(W)의 제1 내지 제4 타입(TP1 내지 TP4)을 나타내는 도면으로서, 각 도면에서 횡축은 웨이퍼(W)의 반경 방향으로의 위치를 나타내고 종축은 웨이퍼(W)의 두께를 각각 나타낸다.7A to 7D are diagrams showing the first to fourth types TP1 to TP4 of the wafer W when the first reference thickness value RT1 is 15 nm, and the horizontal axis in each drawing represents the wafer W. FIG. Indicates the position in the radial direction, and the vertical axis indicates the thickness of the wafer W, respectively.

도 7a에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 15 ㎚보다 작고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 클 때, 서셉터(210)에 안착된 웨이퍼(W)의 두께 타입을 제1 타입(TP1)으로서 결정한다.As shown in FIG. 7A, the first thickness deviation ΔT1 is smaller than 15 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is smaller than 0 nm, which is the second reference thickness value RT2. When large, the thickness type of the wafer W seated on the susceptor 210 is determined as the first type TP1.

또는, 도 7b에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 15 ㎚보다 작고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 크지 않을 때, 서셉터(210)에 안착된 웨이퍼(W)의 두께 타입을 제2 타입(TP2)으로서 결정한다.Alternatively, as shown in FIG. 7B, the first thickness deviation ΔT1 is smaller than 15 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is 0, the second reference thickness value RT2. When not larger than nm, the thickness type of the wafer W seated on the susceptor 210 is determined as the second type TP2.

또는, 도 7c에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 15 ㎚보다 작지 않고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 큰 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제3 타입(TP3)으로서 결정한다.Alternatively, as shown in FIG. 7C, the first thickness deviation ΔT1 is not smaller than 15 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is the second reference thickness value RT2. When larger than 0 nm, the thickness type of the wafer W seated on the susceptor 220 is determined as the third type TP3.

또한, 도 7d에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 15 ㎚보다 작지 않고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 크지 않은 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제4 타입(TP4)으로서 결정한다.In addition, as shown in FIG. 7D, the first thickness deviation ΔT1 is not smaller than 15 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is the second reference thickness value RT2. When not larger than 0 nm, the thickness type of the wafer W seated on the susceptor 220 is determined as the fourth type TP4.

도 8a 내지 도 8d는 제1 기준 두께값(RT1)이 30 ㎚인 경우, 웨이퍼(W)의 제1 내지 제4 타입(TP1 내지 TP4)을 나타내는 도면으로서, 각 도면에서 횡축은 웨이퍼(W)의 반경 방향으로의 위치를 나타내고 종축은 웨이퍼(W)의 두께를 각각 나타낸다.8A to 8D are diagrams showing the first to fourth types TP1 to TP4 of the wafer W when the first reference thickness value RT1 is 30 nm, and the horizontal axis in each drawing represents the wafer W. FIG. Indicates the position in the radial direction, and the vertical axis indicates the thickness of the wafer W, respectively.

도 8a에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 30 ㎚보다 작고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 클 때, 서셉터(210)에 안착된 웨이퍼(W)의 두께 타입을 제1 타입(TP1)으로서 결정한다.As shown in FIG. 8A, the first thickness deviation ΔT1 is smaller than 30 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is smaller than 0 nm, which is the second reference thickness value RT2. When large, the thickness type of the wafer W seated on the susceptor 210 is determined as the first type TP1.

또는, 도 8b에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 30 ㎚보다 작고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 크지 않을 때, 서셉터(210)에 안착된 웨이퍼(W)의 두께 타입을 제2 타입(TP2)으로서 결정한다.Alternatively, as shown in FIG. 8B, the first thickness deviation ΔT1 is smaller than 30 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is 0, the second reference thickness value RT2. When not larger than nm, the thickness type of the wafer W seated on the susceptor 210 is determined as the second type TP2.

또는, 도 8c에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 30 ㎚보다 작지 않고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 큰 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제3 타입(TP3)으로서 결정한다.Alternatively, as shown in FIG. 8C, the first thickness deviation ΔT1 is not smaller than 30 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is the second reference thickness value RT2. When larger than 0 nm, the thickness type of the wafer W seated on the susceptor 220 is determined as the third type TP3.

또한, 도 8d에 도시된 바와 같이, 제1 두께 편차(ΔT1)가 제1 기준 두께값(RT1)인 30 ㎚보다 작지 않고, 제2 두께 편차(ΔT2)가 제2 기준 두께값(RT2)인 0 ㎚보다 크지 않은 경우, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입을 제4 타입(TP4)으로서 결정한다.In addition, as shown in FIG. 8D, the first thickness deviation ΔT1 is not smaller than 30 nm, which is the first reference thickness value RT1, and the second thickness deviation ΔT2 is the second reference thickness value RT2. When not larger than 0 nm, the thickness type of the wafer W seated on the susceptor 220 is determined as the fourth type TP4.

전술한 바와 같이, 서셉터(220)에 안착된 웨이퍼(W)의 두께 타입이 결정될 경우, 결정된 두께 타입에 따라 다음 표 1에서와 같이 에피 공정 조건을 달리하여 웨이퍼(W)에 에피층(E)을 형성할 수 있다.As described above, when the thickness type of the wafer W seated on the susceptor 220 is determined, the epitaxial layer E may be formed on the wafer W by varying the epi process conditions as shown in Table 1 according to the determined thickness type. ) Can be formed.

구분division H2 Main(slm)H2 Main (slm) H2 slit(slm)H2 slit (slm) TCS(sccm)TCS (sccm) Accuset(In/Out)Accuset (In / Out) HT(㎜)HT (mm) RPMRPM TP1TP1 40%40% 30%30% 10%10% 10%10% 7%7% 3%3% TP2TP2 42%42% 31%31% 6%6% 10%10% 10%10% 1%One% TP3TP3 42%42% 30%30% 8%8% 10%10% 7%7% 3%3% TP4TP4 42%42% 31%31% 6%6% 10%10% 10%10% 1%One%

여기서, 'H'는 캐리어 가스인 수소(H2)를 나타내고, 'H2 Main'은 캐리어 가스인 수소(H2)의 제1 공급량을 나타내고, 'H2 slit'은 캐리어 가스인 수소(H2)의 제2 공급량을 나타내고, 'TCS'는 소스 가스를 나타내고, 'Accuset(In/Out)'는 가스 공급 밸브(240, 240A)의 개/폐 정도를 나타내고, HT는 서셉터(220)의 높이를 나타내고, RPM은 서셉터(220)의 회전 속도를 각각 나타낸다.Here, "H" represents hydrogen (H2) which is a carrier gas, "H2 Main" represents the 1st supply amount of hydrogen (H2) which is carrier gas, and "H2 slit" shows the 2nd of hydrogen (H2) which is carrier gas. 'TCS' indicates the source gas, 'Accuset (In / Out)' indicates the opening / closing degree of the gas supply valves 240 and 240A, HT indicates the height of the susceptor 220, RPM represents the rotation speed of the susceptor 220, respectively.

전술한 표 1은 웨이퍼(W)의 두께 타입(TP1 내지 TP4)별로 제110 단계에서 미리 설정된 에피 공정 조건으로서, 에피 공정 조건의 인자들 간의 상대적 비율이 웨이퍼(W)의 두께 타입(TP1 내지 TP4)별로 다름을 알 수 있다. 예를 들어, 표 1은 도 3에 도시된 저장부(270)에 룩업테이블(LUT:Look Up Table)의 형태로 저장될 수 있다.Table 1 described above is an epi process condition preset in step 110 for each thickness type TP1 to TP4 of the wafer W, and the relative ratio between the factors of the epi process condition is the thickness type of the wafer W (TP1 to TP4). You can see the difference by). For example, Table 1 may be stored in the form of a look up table (LUT) in the storage unit 270 illustrated in FIG. 3.

표 1을 참조하면, 제120 또는 제120A 단계에서 웨이퍼(W)의 두께 타입이 제1 타입(TP1)으로 결정될 때, 에피 공정 조건에서 각 인자의 상대적 비율을 살펴보면, 100% 중에서, H2 Main이 40%를 차지하고, H2 Slit이 30%를 차지하고, TCS가 10%를 차지하고, Accuset(In/Out)가 10%를 차지하고, HT가 7%를 차지하고 RPM이 3%를 차지한다.Referring to Table 1, when the thickness type of the wafer W is determined as the first type TP1 in the 120 or 120A step, the relative ratio of each factor in the epi process condition is determined. 40%, H2 Slit 30%, TCS 10%, Accuset (In / Out) 10%, HT 7% and RPM 3%.

그러나, 웨이퍼(W)의 두께 타입이 제2 타입(TP2)으로 결정될 때, 에피 공정 조건에서 각 인자의 상대적 비율을 살펴보면, 100% 중에서, H2 Main이 42%를 차지하고, H2 Slit이 31%를 차지하고, TCS가 6%를 차지하고, Accuset(In/Out)가 10%를 차지하고, HT가 10%를 차지하고 RPM이 1%를 차지한다.However, when the thickness type of the wafer W is determined as the second type (TP2), the relative ratio of each factor in the epi-process conditions shows that, among 100%, H2 Main accounts for 42% and H2 Slit accounts for 31%. TCS accounted for 6%, Accuset (In / Out) accounted for 10%, HT accounted for 10%, and RPM accounted for 1%.

그러나, 웨이퍼(W)의 두께 타입이 제3 타입(TP3)으로 결정될 때, 에피 공정 조건에서 각 인자의 상대적 비율을 살펴보면, 100% 중에서, H2 Main이 42%를 차지하고, H2 Slit이 30%를 차지하고, TCS가 8%를 차지하고, Accuset(In/Out)가 10%를 차지하고, HT가 7%를 차지하고 RPM이 3%를 차지한다.However, when the thickness type of the wafer W is determined as the third type (TP3), when looking at the relative ratio of each factor in the epi process conditions, H2 Main occupies 42% and H2 Slit 30% among 100%. TCS accounted for 8%, Accuset (In / Out) accounted for 10%, HT accounted for 7%, and RPM accounted for 3%.

그러나, 웨이퍼(W)의 두께 타입이 제4 타입(TP4)으로 결정될 때, 에피 공정 조건에서 각 인자의 상대적 비율을 살펴보면, 100% 중에서, H2 Main이 42%를 차지하고, H2 Slit이 31%를 차지하고, TCS가 6%를 차지하고, Accuset(In/Out)가 10%를 차지하고, HT가 10%를 차지하고 RPM이 1%를 차지한다.However, when the thickness type of the wafer W is determined as the fourth type (TP4), when looking at the relative ratio of each factor in the epi process condition, among the 100%, H2 Main occupies 42% and H2 Slit is 31%. TCS accounted for 6%, Accuset (In / Out) accounted for 10%, HT accounted for 10%, and RPM accounted for 1%.

전술한 표 1에서와 같이, 웨이퍼(W)의 두께 타입에 따라 에피 공정 조건의 각 인자가 사용되는 정도가 달라짐을 알 수 있다.As shown in Table 1, it can be seen that the degree of use of each factor of the epi-process conditions varies depending on the thickness type of the wafer W.

웨이퍼(W)의 두께 편차는 에피층(E)에 의해 상쇄될 수 있다. 예를 들어, 도 7a, 도 7c, 도 8a 또는 도 8c에 도시된 웨이퍼(W)의 에지 영역(EA)의 두께는 제2 지점(P2)으로부터 제3 지점(P3)으로 갈수록 감소한다. 이때, 에피층(E)의 두께가 제2 지점(P2)으로부터 제3 지점(P3)으로 갈수록 증가하도록 형성될 경우, 웨이퍼(W)의 두께 편차는 에피층(E)에 의해 상쇄되기 때문에, 최종적으로 제조되는 에피텍셜 웨이퍼(EW)의 에지 영역(EA)에서의 두께 편차는 최소화될 수 있다.The thickness variation of the wafer W may be offset by the epi layer E. FIG. For example, the thickness of the edge area EA of the wafer W shown in FIGS. 7A, 7C, 8A, or 8C decreases from the second point P2 to the third point P3. At this time, when the thickness of the epi layer E is formed to increase from the second point P2 to the third point P3, the thickness variation of the wafer W is offset by the epi layer E, The thickness variation in the edge area EA of the epitaxial wafer EW finally manufactured may be minimized.

또한, 실시 예에 의한 에피텍셜 웨이퍼 제조 방법(100) 및 장치(200)는 에피층을 형성하기 위한 복수의 웨이퍼를 두께 타입별로 분류한 후, 가장 많은 두께 타입을 갖는 웨이퍼(W)에 에피층을 형성한 후, 에피 공정 조건을 변경하여 차상위로 많은 두께 타입을 갖는 웨이퍼(W)에 에피층을 형성하는 등, 두께 타입이 많은 웨이퍼(W)에 우선적으로 에피층(E)을 형성할 수 있으나, 실시 예는 이에 국한되지 않는다.In addition, the epitaxial wafer manufacturing method 100 and the apparatus 200 according to the embodiment classify a plurality of wafers for forming an epitaxial layer by thickness type, and then place an epitaxial layer on the wafer W having the largest thickness type. After forming the film, the epi layer may be preferentially formed on the wafer W having a large thickness type, such as by changing the epi process condition to form an epi layer on the wafer W having a large thickness type. However, the embodiment is not limited thereto.

일반적으로 웨이퍼(W)나 에피텍셜 웨이퍼(EW)의 두께 편차 즉, 평탄한 정도를 평가하는 척도로서 GBIR(Global Backside Ideal Range) 또는 SBIR(Site Backside Ideal Range)가 있다.In general, there is a Global Backside Ideal Range (GBIR) or a Site Backside Ideal Range (SBIR) as a measure for evaluating the thickness variation, that is, the flatness of the wafer W or the epitaxial wafer EW.

도 9a는 GBIR을 설명하기 위한 도면이고, 도 9b는 SBIR을 설명하기 위한 도면이다.FIG. 9A is a diagram for describing the GBIR, and FIG. 9B is a diagram for explaining the SBIR.

도 9a를 참조하면, GBIR이란, 기준면(ideal backside reference plane)(400)을 기준으로 웨이퍼(W)의 최대 두께(Tmax)와 최소 두께(Tmin) 간의 차이값으로서, 단위는 ㎛/Wafer(또는, ㎚/Wafer, 또는 간략히 ㎛ 또는 ㎚)일 수 있으며 다음 수학식 1과 같이 표현될 수 있다.Referring to FIG. 9A, GBIR is a difference value between the maximum thickness Tmax and the minimum thickness Tmin of the wafer W with respect to an ideal backside reference plane 400, and a unit is μm / Wafer (or , Nm / Wafer, or simply μm or nm) and may be expressed as in Equation 1 below.

Figure PCTKR2017012416-appb-M000001
Figure PCTKR2017012416-appb-M000001

도 9b를 참조하면, SBIR이란, 기준면(ideal backside reference plane)(410)을 기준으로 웨이퍼 사이트(WS)의 최대 두께(STmax)와 최소 두께(STmin) 간의 차이값으로서, 단위는 ㎛/Wafer(또는, ㎚/Wafer, 또는 간략히 ㎛ 또는 ㎚)일 수 있으며 다음 수학식 2와 같이 표현될 수 있다.Referring to FIG. 9B, SBIR is a difference value between the maximum thickness STmax and the minimum thickness STmin of the wafer site WS with respect to the ideal backside reference plane 410, and the unit is μm / Wafer ( Or nm / Wafer, or simply μm or nm) and may be expressed as Equation 2 below.

Figure PCTKR2017012416-appb-M000002
Figure PCTKR2017012416-appb-M000002

여기서, 웨이퍼 사이트(WS)란, 각 웨이퍼(W)를 예를 들어 장방향의 작은 조각들로 구분할 때, 각 조각을 의미할 수 있다.Here, the wafer site WS may mean each piece when the wafer W is divided into, for example, small pieces in a long direction.

도 10a 내지 도 10c는 웨이퍼(W)의 전체 두께 편차가 에피층(E)에 의해 상쇄되어 전체 두께 편차가 개선된 에피텍셜 웨이퍼가 제조되는 과정의 일 례를 설명하기 위한 도면을 나타낸다.10A to 10C illustrate an example of a process of manufacturing an epitaxial wafer in which the overall thickness variation of the wafer W is offset by the epi layer E, thereby improving the overall thickness variation.

구체적으로 도 10a는 웨이퍼(W)의 3차원 맵(Map)을 나타내고, 도 10b는 웨이퍼(W)의 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층(E)의 3차원 맵을 나타내고, 도 10c는 웨이퍼(W)의 두께 편차가 에피층(E)에 의해 상쇄된 에피텍셜 웨이퍼(EW)의 3차원 맵을 나타낸다.Specifically, FIG. 10A shows a three-dimensional map of the wafer W, FIG. 10B shows a three-dimensional map of the epi layer E having a thickness profile capable of offsetting the thickness variation of the wafer W, FIG. 10C shows a three-dimensional map of the epitaxial wafer EW in which the thickness variation of the wafer W is offset by the epi layer E. FIG.

도 10a에 도시된 웨이퍼(W)가 94.6 ㎚의 GBIR을 갖고, 51.3 ㎚의 SBIR를 가질 때, 실시 예에 의한 에피텍셜 제조 방법(100)에 의해 도 10b에 도시된 바와 같이 형태의 에피층(E)을 도 10a에 도시된 웨이퍼(W)에 형성하면, 도 10c에 도시된 바와 같이 GBIR이 89.4 ㎚로 개선되고 SBIR이 35.2 ㎚로 개선된 에피텍셜 웨이퍼(EW)가 제조될 수 있다.When the wafer W shown in FIG. 10A has a GBIR of 94.6 nm and an SBIR of 51.3 nm, an epitaxial layer having a shape as shown in FIG. 10B by the epitaxial manufacturing method 100 according to the embodiment. If E) is formed on the wafer W shown in Fig. 10A, an epitaxial wafer EW with improved GBIR to 89.4 nm and SBIR to 35.2 nm can be manufactured as shown in Fig. 10C.

이하, 웨이퍼(W)의 두께 편차를 고려하지 않는 기존의 에피텍셜 웨이퍼 제조 방법(C1)과 웨이퍼(W)의 두께 편차를 고려하는 실시 예에 의한 에피텍셜 웨이퍼 제조 방법(C2)에 의해 제조된 에피텍셜 웨이퍼의 평탄도를 다음과 같이 첨부된 도면을 참조하여 비교 설명한다.Hereinafter, the epitaxial wafer manufacturing method C2 according to the embodiment which considers the thickness variation of the wafer W and the conventional epitaxial wafer manufacturing method C1 which does not consider the thickness variation of the wafer W is manufactured. The flatness of the epitaxial wafer will be described with reference to the accompanying drawings as follows.

도 11a는 기존의 방법에 의해 제조된 에피텍셜 웨이퍼의 GBIR과 실시 예에 의한 방법에 의해 제조된 에피텍셜 웨이퍼의 GBIR을 나타내고, 도 11b는 기존의 방법에 의해 제조된 에피텍셜 웨이퍼의 SIBR과 실시 예에 의한 방법에 의해 제조된 에피텍셜 웨이퍼의 SBIR을 나타낸다.11A shows the GBIR of the epitaxial wafer manufactured by the conventional method and the GBIR of the epitaxial wafer manufactured by the method according to the embodiment, and FIG. 11B shows the SIBR of the epitaxial wafer manufactured by the conventional method. The SBIR of the epitaxial wafer manufactured by the method by an example is shown.

도 11a를 참조하면, 기존에서와 같이 웨이퍼(W)의 두께 편차를 고려하지 않고 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 GBIR(C1)과 비교할 때, 실시 예에서와 같이 웨이퍼(W)의 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 GBIR(C2)이 상대적으로 작음을 알 수 있다.Referring to FIG. 11A, when compared with the GBIR (C1) of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the thickness variation of the wafer W as in the prior art, As can be seen that the GBIR (C2) of the plurality of epitaxial wafers having the epitaxial layer (E) having a thickness profile capable of canceling the thickness variation of the wafer (W) on the wafer (W) is relatively small. .

도 11b를 참조하면, 기존에서와 같이 웨이퍼(W)의 평탄도를 고려하지 않고 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 SBIR(C1)과 비교할 때, 실시 예에서와 같이 웨이퍼(W)의 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 SBIR(C2)이 상대적으로 작음을 알 수 있다. 도 11b에 도시된 각 점은 각 에피텍셜 웨이퍼의 최대 SBIR을 나타낼 수 있다.Referring to FIG. 11B, an embodiment is compared with SBIR C1 of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the flatness of the wafer W as in the prior art. As can be seen that the SBIR (C2) of the plurality of epitaxial wafers formed on the wafer (W) having an epitaxial layer (E) having a thickness profile that can offset the thickness variation of the wafer (W) is relatively small. . Each dot shown in FIG. 11B may represent the maximum SBIR of each epitaxial wafer.

도 12a는 기존의 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼와 실시 예에 의한 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼의 GBIR의 히스토그램을 나타내고, 도 12b는 기존의 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼와 실시 예에 의한 방법에 의해 제조된 여러 장의 에피텍셜 웨이퍼의 SBIR의 히스토그램을 나타낸다.12A shows a histogram of GBIR of several epitaxial wafers manufactured by the conventional method and several epitaxial wafers manufactured by the method according to the embodiment, and FIG. 12B shows several epitaxial wafers manufactured by the conventional method. The histogram of the SBIR of the epitaxial wafers and the sheets of the epitaxial wafers produced by the method according to the embodiment is shown.

도 12a를 참조하면, 기존에서와 같이 웨이퍼(W)의 평탄도를 고려하지 않고 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 GBIR(C1)의 빈도 수와, 실시 예에서와 같이 웨이퍼(W)의 평탄도를 고려하여 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 GBIR(C2)의 빈도 수를 비교할 때, 실시 예(C2)가 기존(C1)보다 낮은 GIBR을 갖는 에피텍셜 웨이퍼가 많음을 알 수 있다.Referring to FIG. 12A, the frequency number of the GBIR C1 of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the flatness of the wafer W as before, and As in the example, the frequency of GBIR (C2) of several epitaxial wafers having an epitaxial layer E formed on the wafer W having a thickness profile that can offset the thickness variation in consideration of the flatness of the wafer W. When comparing the numbers, it can be seen that Example C2 has more epitaxial wafers with lower GIBR than conventional C1.

도 12b를 참조하면, 기존에서와 같이 웨이퍼(W)의 평탄도를 고려하지 않고 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 SBIR(C1)의 빈도 수와, 실시 예에서와 같이 웨이퍼(W)의 평탄도를 고려하여 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층(E)을 웨이퍼(W)에 형성한 여러 장의 에피텍셜 웨이퍼의 SBIR(C2)의 빈도 수를 비교할 때, 실시 예(C2)가 기존(C1)보다 낮은 SIBR을 갖는 에피텍셜 웨이퍼가 많음을 알 수 있다.Referring to FIG. 12B, the frequency number of the SBIR C1 of several epitaxial wafers in which the epi layer E is formed on the wafer W without considering the flatness of the wafer W as before, and As in the example, the frequency of SBIR (C2) of several epitaxial wafers in which the epitaxial layer E having a thickness profile capable of canceling the thickness variation in consideration of the flatness of the wafer W is formed on the wafer W. When comparing the numbers, it can be seen that the embodiment (C2) has a lot of epitaxial wafers having a lower SIBR than the conventional (C1).

전술한 실시 예에 의한 에피텍셜 웨이퍼 제조 방법(100) 및 장치(200)에 의하면, 웨이퍼(W)의 전체 두께에 편차가 있을 경우, 에피 공정 조건의 각 인자(H2 Main, H2 Slit, TCS, Accuset(In/Out), HT, RPM)를 복합적으로 조절하여 웨이퍼(W)의 전체 두께 편차를 상쇄시킬 수 있는 두께 프로파일을 갖는 에피층(E)을 웨이퍼(W)에 형성할 수 있기 때문에, 최종적으로 제조되는 에픽텍셜 웨이퍼(EW)의 GBIR 및 SBIR이 개선될 수 있으며 수율도 개선될 수 있다.According to the epitaxial wafer manufacturing method 100 and the apparatus 200 according to the above-described embodiment, when there is a variation in the overall thickness of the wafer W, the factors of the epi process conditions (H2 Main, H2 Slit, TCS, Since the epitaxial layer E can be formed on the wafer W, which has a thickness profile capable of canceling the overall thickness variation of the wafer W by adjusting Accuset (In / Out), HT, and RPM), The GBIR and SBIR of the finally produced epitaxial wafer (EW) can be improved and the yield can be improved.

이상에서 실시 예를 중심으로 설명하였으나 이는 단지 예시일 뿐 본 발명을 한정하는 것이 아니며, 본 발명이 속하는 분야의 통상의 지식을 가진 자라면 본 실시 예의 본질적인 특성을 벗어나지 않는 범위에서 이상에 예시되지 않은 여러 가지의 변형과 응용이 가능함을 알 수 있을 것이다. 예를 들어, 실시 예에 구체적으로 나타난 각 구성 요소는 변형하여 실시할 수 있는 것이다. 그리고 이러한 변형과 응용에 관계된 차이점들은 첨부된 청구 범위에서 규정하는 본 발명의 범위에 포함되는 것으로 해석되어야 할 것이다.Although the above description has been made with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not illustrated above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

발명의 실시를 위한 형태는 전술한 "발명의 실시를 위한 최선의 형태"에서 충분히 설명되었다.Embodiments for carrying out the invention have been described fully in the foregoing "Best Modes for Carrying Out the Invention".

실시 예에 의한 에피텍셜 웨이퍼 제조 방법 및 장치는 웨이퍼를 제조하는 데 이용될 수 있다.An epitaxial wafer manufacturing method and apparatus according to the embodiment may be used to manufacture a wafer.

Claims (12)

서셉터에 웨이퍼가 안착된 상태에서 상기 웨이퍼에 에피층을 형성하는 에피텍셜 웨이퍼 제조 방법에 있어서,In the epitaxial wafer manufacturing method of forming an epitaxial layer on the wafer while the wafer is seated on a susceptor, (a) 상기 웨이퍼의 전체 두께 편차를 상쇄시킬 수 있도록 매칭된 두께 프로파일을 갖는 상기 에피층의 에피 공정 조건을 상기 웨이퍼의 두께 타입 별로 미리 설정하는 단계;(a) presetting epi process conditions of the epi layer having a matched thickness profile for each thickness type of the wafer so as to offset the overall thickness variation of the wafer; (b) 상기 서셉터에 안착된 상기 웨이퍼의 센터 영역에서의 제1 두께 편차와 에지 영역에서의 제2 두께 편차를 이용하여, 상기 웨이퍼의 두께 타입을 결정하는 단계; 및(b) determining a thickness type of the wafer using a first thickness deviation in a center region of the wafer seated on the susceptor and a second thickness deviation in an edge region; And (c) 미리 설정된 상기 에피 공정 조건 중에서, 상기 결정된 두께 타입에 해당하는 에피 공정조건으로 상기 웨이퍼에 상기 에피층을 형성하는 단계를 포함하고,(c) forming the epitaxial layer on the wafer under epitaxial conditions corresponding to the determined thickness type among the preset epitaxial conditions, 상기 에피 공정 조건은 캐리어 가스의 공급량, 소스 가스의 공급량, 가스 공급 밸브의 개/폐 정도, 상기 서셉터의 회전 속도 또는 상기 서셉터의 높이 중 적어도 하나를 포함하는 에피텍셜 웨이퍼 제조 방법.And the epi process conditions include at least one of a supply amount of a carrier gas, a supply amount of a source gas, an opening / closing degree of a gas supply valve, a rotation speed of the susceptor, or a height of the susceptor. 제1 항에 있어서, 상기 캐리어 가스의 공급량은The method of claim 1, wherein the supply amount of the carrier gas 상기 웨이퍼의 위로 공급되는 캐리어 가스의 제1 공급량; 또는A first supply amount of carrier gas supplied over the wafer; or 상기 웨이퍼의 아래로 공급되는 캐리어 가스의 제2 공급량 중 적어도 하나를 포함하는 에피텍셜 웨이퍼 제조 방법.And at least one of a second supply amount of carrier gas supplied down the wafer. 제1 항에 있어서, 상기 웨이퍼의 센터 영역은 상기 웨이퍼의 중심으로부터 제1 지점까지의 영역으로 정의되고,The method of claim 1, wherein the center area of the wafer is defined as an area from the center of the wafer to a first point, 상기 웨이퍼의 에지 영역은 상기 웨이퍼의 제2 지점으로부터 제3 지점까지의 영역으로 정의되며,An edge region of the wafer is defined as an area from a second point to a third point of the wafer, 상기 제2 지점은 상기 제1 지점보다 상기 중심으로부터 멀리 위치하거나 제1 지점과 동일할 수 있고, 상기 제3 지점은 상기 제2 지점보다 상기 중심으로부터 멀리 위치하는 에피텍셜 웨이퍼 제조 방법.Wherein the second point may be located farther from or the same as the first point than the first point, and the third point is located farther from the center than the second point. 제3 항에 있어서, 상기 제1 및 제2 지점 각각은 80 ㎜ 내지 100 ㎜이고, 상기 제3 지점은 140 ㎜ 내지 148 ㎜인 에피텍셜 웨이퍼 제조 방법.The method of claim 3, wherein each of the first and second points is between 80 mm and 100 mm and the third point is between 140 mm and 148 mm. 제3 항에 있어서, 상기 제1 두께 편차는 상기 중심에서의 제1 두께로부터 상기 제1 지점에서의 제2 두께를 감산한 값이고,The method of claim 3, wherein the first thickness deviation is a value obtained by subtracting a second thickness at the first point from the first thickness at the center, 상기 제2 두께 편차는 상기 제2 지점에서의 제3 두께로부터 상기 제3 지점에서의 제4 두께를 감산한 값인 에피텍셜 웨이퍼 제조 방법.And the second thickness deviation is a value obtained by subtracting the fourth thickness at the third point from the third thickness at the second point. 제5 항에 있어서, 상기 (b) 단계는The method of claim 5, wherein step (b) 상기 제1 및 제2 두께 편차를 구하는 단계;Obtaining the first and second thickness deviations; 상기 제1 두께 편차를 제1 기준 두께값과 비교하여 제1 비교값을 구하는 단계;Obtaining a first comparison value by comparing the first thickness deviation with a first reference thickness value; 상기 제2 두께 편차를 제2 기준 두께값과 비교하여 제2 비교값을 구하는 단계; 및Obtaining a second comparison value by comparing the second thickness deviation with a second reference thickness value; And 상기 제1 비교값과 상기 제2 비교값을 이용하여 상기 웨이퍼의 두께 타입을 결정하는 단계를 포함하는 에피텍셜 웨이퍼 제조 방법.Determining a thickness type of the wafer using the first comparison value and the second comparison value. 제6 항에 있어서, 상기 제1 기준 두께값은 15 ㎚ 혹은 30 ㎚이고, 상기 제2 기준 두께값은 '0'인 에피텍셜 웨이퍼 제조 방법.The method of claim 6, wherein the first reference thickness value is 15 nm or 30 nm, and the second reference thickness value is '0'. 제1 항에 있어서, 상기 (a) 단계에서The method of claim 1, wherein in step (a) 상기 캐리어 가스의 공급량, 상기 소스 가스의 공급량, 상기 가스 공급 밸브의 개/폐 정도, 상기 서셉터의 회전 속도 및 상기 서셉터의 높이 간의 상대적인 비율이 상기 웨이퍼의 두께 타입 별로 서로 다른 상기 에피 공정 조건으로서 설정되는 에피텍셜 웨이퍼 제조 방법.The epi process conditions in which a relative ratio between the supply amount of the carrier gas, the supply amount of the source gas, the opening / closing degree of the gas supply valve, the rotational speed of the susceptor, and the height of the susceptor are different for each thickness type of the wafer An epitaxial wafer manufacturing method set as. 제4 항에 있어서, 상기 웨이퍼는 양면 연마된 웨이퍼인 에피텍셜 웨이퍼 제조 방법.The method of claim 4, wherein the wafer is a double side polished wafer. 제1 항에 있어서, 상기 에피 공정 조건은 도펀트 가스의 공급량을 더 포함하는 에피텍셜 웨이퍼 제조 방법.The epitaxial wafer manufacturing method of claim 1, wherein the epitaxial processing condition further includes a supply amount of a dopant gas. 웨이퍼에 에피층을 형성하는 에피텍셜 웨이퍼 제조 장치에 있어서,In the epitaxial wafer manufacturing apparatus which forms an epitaxial layer in a wafer, 캐리어 가스와 소스 가스를 공급하는 가스 공급부;A gas supply unit supplying a carrier gas and a source gas; 상기 웨이퍼가 안착되는 서셉터;A susceptor on which the wafer is seated; 상기 서셉터를 지지하는 구동축;A drive shaft supporting the susceptor; 상기 구동축의 승강과 회전 속도를 조절하는 구동부;A drive unit which adjusts the lifting speed and the rotation speed of the drive shaft; 상기 가스 공급부로부터 공급되는 상기 캐리어 가스 및 상기 소스 가스를 상기 웨이퍼로 공급하는 가스 공급 밸브;A gas supply valve supplying the carrier gas and the source gas supplied from the gas supply part to the wafer; 상기 웨이퍼의 전체 두께 편차를 상쇄시킬 수 있도록 매칭된 두께 프로파일을 갖는 상기 에피층의 에피 공정 조건을 상기 웨이퍼의 두께 타입 별로 저장한 저장부;A storage unit storing epi process conditions of the epi layer having a matched thickness profile for each thickness type of the wafer so as to cancel the overall thickness variation of the wafer; 상기 서셉터에 안착된 상기 웨이퍼의 두께 타입을 결정하는 두께 타입 결정부; 및A thickness type determination unit determining a thickness type of the wafer seated on the susceptor; And 상기 두께 타입 결정부에서 결정된 두께 타입에 상응하는 에피 공정 조건을 상기 저장부로부터 독출하고, 독출된 상기 에피 공정 조건에 해당하는 캐리어 가스의 공급량, 상기 소스 가스의 공급량, 상기 가스 공급 밸브의 개/폐 정도, 상기 서셉터의 회전 속도 또는 상기 서셉터의 높이 중 적어도 하나를 조정하기 위해, 상기 가스 공급부, 상기 가스 공급 밸브 또는 상기 구동부 중 적어도 하나를 제어하는 제어부를 포함하는 에피텍셜 웨이퍼 제조 장치.The epi process condition corresponding to the thickness type determined by the thickness type determination unit is read out from the storage unit, and the supply amount of the carrier gas corresponding to the read epi process condition, the supply amount of the source gas, and opening / opening of the gas supply valve And a control unit controlling at least one of the gas supply unit, the gas supply valve, and the driving unit to adjust at least one of a degree of closure, a rotation speed of the susceptor, and a height of the susceptor. 제11 항에 있어서, 상기 제어부는 상기 에피 공정 조건으로서 도펀트의 공급량을 더 제어하는 에피텍셜 웨이퍼 제조 장치.The epitaxial wafer manufacturing apparatus of claim 11, wherein the control unit further controls a supply amount of a dopant as the epi process condition.
PCT/KR2017/012416 2016-12-23 2017-11-03 Method and apparatus for manufacturing epitaxial wafer Ceased WO2018117402A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2016-0178206 2016-12-23
KR1020160178206A KR20180074273A (en) 2016-12-23 2016-12-23 Method and apparatus for manufacturing epitaxial wafer

Publications (1)

Publication Number Publication Date
WO2018117402A1 true WO2018117402A1 (en) 2018-06-28

Family

ID=62626707

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2017/012416 Ceased WO2018117402A1 (en) 2016-12-23 2017-11-03 Method and apparatus for manufacturing epitaxial wafer

Country Status (3)

Country Link
KR (1) KR20180074273A (en)
TW (1) TW201837989A (en)
WO (1) WO2018117402A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3978647A1 (en) 2020-09-30 2022-04-06 Siltronic AG Method and device for depositing an epitaxial layer on a substrate wafer of semiconductor material

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3996130B1 (en) * 2020-11-09 2023-03-08 Siltronic AG Method for depositing an epitaxial layer on a substrate wafer
US12482662B2 (en) 2022-02-21 2025-11-25 Globalwafers Co., Ltd. Systems and methods for producing epitaxial wafers
CN114783860A (en) * 2022-03-07 2022-07-22 上海华虹宏力半导体制造有限公司 Method for adjusting epitaxial growth uniformity

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070006179A (en) * 2005-07-07 2007-01-11 삼성전자주식회사 Film Forming Apparatus for Semiconductor Manufacturing
KR20090092223A (en) * 2008-02-26 2009-08-31 실트로닉 아게 Controlled edge thickness in a silicon wafer
US20100015402A1 (en) * 2008-07-16 2010-01-21 Siltronic Ag Method for depositing a layer on a semiconductor wafer by means of cvd and chamber for carrying out the method
KR20130081805A (en) * 2012-01-10 2013-07-18 주식회사 엘지실트론 Insert for injecting react gas and vapor deposition apparatus including the same
JP2014036153A (en) * 2012-08-09 2014-02-24 Sumco Corp Method of manufacturing epitaxial silicon wafer and epitaxial silicon wafer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070006179A (en) * 2005-07-07 2007-01-11 삼성전자주식회사 Film Forming Apparatus for Semiconductor Manufacturing
KR20090092223A (en) * 2008-02-26 2009-08-31 실트로닉 아게 Controlled edge thickness in a silicon wafer
US20100015402A1 (en) * 2008-07-16 2010-01-21 Siltronic Ag Method for depositing a layer on a semiconductor wafer by means of cvd and chamber for carrying out the method
KR20130081805A (en) * 2012-01-10 2013-07-18 주식회사 엘지실트론 Insert for injecting react gas and vapor deposition apparatus including the same
JP2014036153A (en) * 2012-08-09 2014-02-24 Sumco Corp Method of manufacturing epitaxial silicon wafer and epitaxial silicon wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3978647A1 (en) 2020-09-30 2022-04-06 Siltronic AG Method and device for depositing an epitaxial layer on a substrate wafer of semiconductor material

Also Published As

Publication number Publication date
TW201837989A (en) 2018-10-16
KR20180074273A (en) 2018-07-03

Similar Documents

Publication Publication Date Title
US8268708B2 (en) Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
US7935614B2 (en) Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
US8372298B2 (en) Method for producing epitaxially coated silicon wafers
US7922813B2 (en) Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
KR100935141B1 (en) Heat treatment apparatus, manufacturing method of semiconductor device, manufacturing method of substrate, manufacturing method of SIOM substrate, support part and substrate support
EP0953659B1 (en) Apparatus for thin film growth
WO2018117402A1 (en) Method and apparatus for manufacturing epitaxial wafer
KR100975717B1 (en) Meteorological Growth System and Meteorological Growth Method
KR20110049764A (en) Silicon Wafer Manufacturing Method
US7659207B2 (en) Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafer
WO2016148385A1 (en) Lift pin and method for manufacturing same
KR101559977B1 (en) Silicon epitaxial wafer and method for manufacturing the same
EP1953808B1 (en) Method for manufacturing epitaxial wafer
US20080308036A1 (en) Vapor-phase growth apparatus and vapor-phase growth method
KR101921979B1 (en) Method and apparatus for manufacturing epitaxial wafer
CN118866664A (en) A method for preparing a silicon epitaxial wafer crack prevention sheet for MOS
WO2014062000A1 (en) Susceptor for epitaxial growing and method for epitaxial growing
KR100431089B1 (en) Semiconductor wafer comprising a thin epitaxial silicon layer and method for producing same
JP3488804B2 (en) CVD apparatus and susceptor for CVD apparatus
KR100900895B1 (en) Epitaxial Wafer Manufacturing Method
JP2001302395A (en) Manufacturing method of high flatness epitaxial wafer
KR20230016383A (en) Boat for vertical haet treatment and heat treatment method of silicon wafer using same
CN118814262A (en) Epitaxial growth method, epitaxial growth equipment, and epitaxial wafer
JPH08279470A (en) Manufacturing for epitaxial wafer
CN116072524A (en) Method for improving slip line of silicon epitaxial wafer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17883768

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17883768

Country of ref document: EP

Kind code of ref document: A1