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WO2018195761A1 - Transistor basé sur un matériau bidimensionnel et son procédé de préparation, et dispositif de réseau de transistors - Google Patents

Transistor basé sur un matériau bidimensionnel et son procédé de préparation, et dispositif de réseau de transistors Download PDF

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Publication number
WO2018195761A1
WO2018195761A1 PCT/CN2017/081821 CN2017081821W WO2018195761A1 WO 2018195761 A1 WO2018195761 A1 WO 2018195761A1 CN 2017081821 W CN2017081821 W CN 2017081821W WO 2018195761 A1 WO2018195761 A1 WO 2018195761A1
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Prior art keywords
layer
dimensional material
graphene
material layer
drain
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Chinese (zh)
Inventor
赵冲
徐慧龙
张臣雄
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201780083547.4A priority Critical patent/CN110178221B/zh
Priority to PCT/CN2017/081821 priority patent/WO2018195761A1/fr
Publication of WO2018195761A1 publication Critical patent/WO2018195761A1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

Definitions

  • the present invention relates to the field of field effect transistor technology, and in particular to a transistor based on two-dimensional materials, a method for fabricating the same, and a transistor array device.
  • the graphene transistor When the graphene transistor is used as a radio frequency device, its two main indicators are the cutoff frequency f T and the maximum resonance frequency f max , both of which are affected by the contact resistance of the graphene transistor and the mobility of the graphene material. Impact. Among them, the contact resistance refers to the contact resistance between the metal source drain electrode and the graphene. When the contact resistance is large, both f T and f max are small, and the device performance is poor.
  • the carrier mobility refers to the average drift velocity of carriers (electrons and holes) under the action of a unit electric field. The greater the mobility, the same electric field conditions, the downloading of carriers through the channel between the source and the drain. The shorter the time, the higher the cutoff frequency f T , ie, f T is proportional to the carrier mobility of the material, and the high mobility is also helpful for increasing f max .
  • multilayer graphene is applied to the transistor structure by increasing the number of graphene layers because the density of the multilayer graphene at the Fermi level is higher than that of the single-layer graphene. It will become larger, which is equivalent to increasing the passage of carriers in the metal into the graphene, thereby reducing the contact resistance.
  • studies have also shown that the mobility of graphene decreases as the number of layers increases. Therefore, there is a contradiction in the use of multilayer graphene: on the one hand, a transistor having a smaller contact resistance can be obtained by increasing the number of layers of graphene. On the other hand, the graphene thickens and its mobility decreases.
  • the first aspect of the embodiments of the present invention provides a transistor based on a two-dimensional material to solve the prior art multilayer graphene-based transistor, which has a reduced carrier mobility and reduced transconductance. Poor performance of the device.
  • the first aspect of the embodiments of the present invention provides a transistor based on a two-dimensional material, including:
  • a source and a drain respectively disposed at two ends of the substrate, a channel between the source and the drain, and a first two-dimensional material layer disposed in a middle portion of the channel;
  • a second two-dimensional material layer disposed in a channel region on a side of the first two-dimensional material layer and connected to the source, disposed on the other side of the first two-dimensional material layer and opposite to the drain a third two-dimensional material layer in the extremely connected channel region, the first two-dimensional material layer, the second two-dimensional material layer, and the third two-dimensional material layer being an integral film of the same material;
  • the thickness of the second two-dimensional material layer and the third two-dimensional material layer are both greater than the thickness of the first two-dimensional material layer.
  • first two-dimensional material layer, the second two-dimensional material layer, and the two-dimensional material in the third two-dimensional material layer include graphene, black phosphorus, molybdenum disulfide, and tungsten disulfide One.
  • the thickness of the first two-dimensional material layer is 1-5 layers of graphene, or 1 - the thickness of 5 layers of molybdenum disulfide or the thickness of 1-5 layers of tungsten disulfide.
  • the second two-dimensional material layer and the third two-dimensional material layer is graphene, or molybdenum disulfide, or tungsten disulfide
  • the second two-dimensional material layer, the third The thickness of the two-dimensional material layer is 5-20 layers of graphene, or 5-20 The thickness of the layer of molybdenum disulfide or the thickness of 5-20 layers of tungsten disulfide.
  • the thickness of the first two-dimensional material layer is a thickness of 1-20 layers of black phosphorus.
  • the thickness of the second two-dimensional material layer and the third two-dimensional material layer is 10-30.
  • the thickness of the layer of black phosphorus is 10-30.
  • the first two-dimensional material layer is obtained by chemical vapor deposition extension growth based on the second two-dimensional material layer and the third two-dimensional material layer.
  • the material of the insulating substrate includes at least one of Si, SiO 2 , SOI, and SiC.
  • the material of the source and the drain are both selected from a simple substance of metal, or a laminated structure of different metals, or a metal carbide.
  • the metal element includes one of platinum, copper, nickel, and gold
  • the stacked structure of the different metals includes a stacked titanium layer/gold layer, a chromium layer/gold layer, a titanium layer/nickel layer, or a chromium layer/ A nickel layer comprising molybdenum carbide, or tantalum carbide, or tungsten carbide.
  • the material of the gate dielectric layer includes at least one of aluminum oxide, tantalum oxide, and antimony trioxide; and the material of the gate electrode includes one of gold, palladium, and tungsten.
  • the two-dimensional material-based transistor provided by the first aspect of the present invention has a structure in which the second and third two-dimensional material layers are in contact with the metal electrode, and the two-dimensional material is in contact with the metal electrode. It can ensure that each layer of two-dimensional material is connected to the metal electrode, so that the contact resistance is reduced; on the other hand, the first two-dimensional material layer in the middle of the channel is thinner than the two-dimensional material layer in the contact, thereby ensuring high
  • the mobility also ensures the modulation of the gate-to-channel, which ultimately results in excellent overall transistor performance.
  • an embodiment of the present invention further provides a method for fabricating a transistor based on a two-dimensional material, including the following steps:
  • a position defining a gate is exposed on the first graphene layer, and then a gate dielectric layer is deposited, and a gate is prepared on the gate dielectric layer to obtain a graphene-based transistor.
  • the material of the metal substrate includes one of copper, nickel, platinum, and alloys thereof.
  • the material of the metal substrate is a copper-nickel alloy, and the copper-nickel alloy has a mass content of copper of 50%-85%.
  • the etching method includes reactive ion etching, or oxygen plasma etching, or wet etching.
  • the photoresist comprises a positive or negative glue, and the positive glue comprises polymethyl methacrylate.
  • the manner of exposure includes electron beam exposure or optical exposure.
  • the method of disposing a layer of graphene on a metal substrate comprises transferring the desired graphene onto the metal substrate or depositing and depositing directly on the metal substrate to obtain the graphene.
  • the material of the insulating substrate includes at least one of Si, SiO 2 , SOI, and SiC.
  • the embodiment of the invention further provides a method for preparing a transistor based on a two-dimensional material, comprising the following steps:
  • first two-dimensional material layer Forming a first two-dimensional material layer, a second two-dimensional material layer, and a third two-dimensional material layer on the insulating substrate by a method of chemical vapor deposition, wherein the first two-dimensional material layer is formed in the second Between the two-dimensional material layer and the third two-dimensional material layer, the thickness of the second two-dimensional material layer and the third two-dimensional material layer is greater than the thickness of the first two-dimensional material layer;
  • the source and the drain Between the drains is a channel, and in the channel, the second two-dimensional material layer, the first two-dimensional material layer and the third two-dimensional material are sequentially disposed between the source and the drain Layer, three are a monolithic film of the same material;
  • the two-dimensional material It is one of black phosphorus, molybdenum disulfide, and tungsten disulfide.
  • the material of the insulating substrate includes at least one of Si, SiO 2 , SOI, and SiC.
  • the preparation method provided by the second aspect of the embodiment of the invention has simple process and is suitable for industrial production.
  • the present invention provides a transistor array device comprising the array structure formed by the two-dimensional material-based transistor of the first aspect of the present invention.
  • FIG. 1 is a schematic structural diagram of a transistor based on a two-dimensional material according to an embodiment of the present invention
  • FIG. 2 is a flow chart of a process for preparing a transistor based on a two-dimensional material according to an embodiment of the present invention.
  • an embodiment of the present invention provides a transistor based on a two-dimensional material, comprising: an insulating substrate 10; a source 11 and a drain 12 respectively disposed at two ends of the substrate 10, the source Between 11 and the drain 12 is a channel 13 in the middle of which is disposed a first two-dimensional material layer 131; on the side of the first two-dimensional material layer 131 and connected to the source 11 a second two-dimensional material layer 132 in the channel region, a third two-dimensional material layer 133 disposed in a channel region on the other side of the first two-dimensional material layer 131 and connected to the drain electrode 12,
  • the first two-dimensional material layer 131, the second two-dimensional material layer 132, and the third two-dimensional material layer 133 are an integral film layer; and includes a first two-dimensional material layer 131 disposed on the first two-dimensional material layer 131.
  • a gate dielectric layer 14 and a gate electrode 15 disposed on the gate dielectric layer 14; the second two-dimensional material layer 132 and
  • the two-dimensional material may be one of graphene, black phosphorus, molybdenum disulfide, and tungsten disulfide.
  • the first two-dimensional material layer 131 is a graphene layer, and the graphene layer has a thickness of 1-5 layers, and further may be 2-3 layers.
  • the first two-dimensional material layer selects a smaller number of layers of graphene to ensure good mobility.
  • the second two-dimensional material layer 132 and the third two-dimensional material layer 133 are both graphene layers.
  • the graphene layer has a thickness of 5-20 layers, and further The thickness is 10-20 layers.
  • the first two-dimensional material layer 131 is a molybdenum disulfide layer, and the molybdenum disulfide layer has a thickness of 1-5 layers, and further may be 2-3 layers.
  • the second two-dimensional material layer 132 and the third two-dimensional material layer 133 are both molybdenum disulfide layers.
  • the molybdenum disulfide layer has a thickness of 5-20 layers. Further, the thickness is 10-20 layers.
  • the first two-dimensional material layer 131 is a tungsten disulfide layer, and the tungsten disulfide layer has a thickness of 1-5 layers, and further may be 2-3 layers.
  • the second two-dimensional material layer 132 and the third two-dimensional material layer 133 are both a tungsten disulfide layer.
  • the tungsten disulfide layer has a thickness of 5-20 layers. Further, the thickness is 10-20 layers.
  • the first two-dimensional material layer 131 is a black phosphorus layer, and the black phosphorus layer has a thickness of 1-20 layers, and further may be 5-15 layers.
  • the second two-dimensional material layer 132 and the third two-dimensional material layer 133 are all black phosphorus layers.
  • the black phosphorus layer has a thickness of 10-30 layers, and further The thickness is 15-20 layers.
  • the first two-dimensional material layer 131, the second two-dimensional material layer 132, and the third two-dimensional material layer 133 are mutually bonded to form an integral film layer, thereby enabling Ensures efficient carrier transfer between source and drain, ultimately improving transistor performance.
  • the two-dimensional material is graphene
  • the first two-dimensional material layer 131 is obtained by chemical vapor deposition extension growth based on the second two-dimensional material layer 132 and the third two-dimensional material layer 133.
  • the source 11 and the second two-dimensional material layer 132, the drain 12 and the third two-dimensional material layer 133 are all in edge contact, so that sufficient two-dimensional materials can be ensured.
  • Conductive channels allow carriers to flow from the electrodes, effectively reducing contact resistance.
  • the thickness of the second two-dimensional material layer 132 and the third two-dimensional material layer 133 may be equal or not equal.
  • the material of the insulating substrate 10 includes at least one of Si, SiO 2 , SOI, and SiC.
  • the materials of the source electrode 11 and the drain electrode 12 are each selected from a metal simple substance or a laminated structure of different metals or a metal carbide.
  • the metal element includes one of platinum, copper, nickel, and gold
  • the stacked structure of the different metals includes a stacked titanium layer/gold layer, a chromium layer/gold layer, a titanium layer/nickel layer, or A chromium layer/nickel layer comprising molybdenum carbide, or tantalum carbide, or tungsten carbide.
  • the material of the gate dielectric layer 14 includes at least one of aluminum oxide, tantalum oxide, and antimony trioxide; and the material of the gate electrode 15 includes one of gold, palladium, and tungsten.
  • the two-dimensional material-based transistor provided in the above structure has a thicker second and third two-dimensional material layers in contact with the metal electrode, and the two-dimensional material is in contact with the metal electrode, thereby ensuring Each layer of two-dimensional material is connected to the metal electrode to reduce the contact resistance; on the other hand, the first two-dimensional material layer in the middle of the channel is thinner than the two-dimensional material layer at the contact, thereby ensuring high migration.
  • the rate ensures the modulation of the gate to the channel, which ultimately makes the overall performance of the transistor excellent.
  • the embodiment of the present invention further provides the method for preparing the above-mentioned two-dimensional material-based transistor, comprising the following steps:
  • the metal substrate 1 may be made of one of copper, nickel, platinum, and alloys thereof.
  • the metal substrate The material of 1 is made of copper-nickel alloy, and the copper content of the copper-nickel alloy is 50%-85%.
  • the increase in copper content is more It is advantageous to grow thinner graphene on the substrate, and the increase in nickel content is more conducive to the growth of thicker graphene on the substrate.
  • a two-dimensional material 2 is disposed on the metal substrate 1, and the two-dimensional material 2 may be prepared on another substrate and then transferred to a metal substrate. 1 can also be directly grown on the metal substrate 1 by chemical vapor deposition; the two-dimensional material 2 can be specifically graphene, the graphene can be set to 5-20 layers, and further can be 10-20 layers.
  • the exposure may be by electron beam exposure or optical exposure.
  • a photoresist is used to protect a region not to be etched, the photoresist includes a positive adhesive or a negative adhesive, and the positive adhesive includes polymethyl methacrylate, and the etching method includes Reactive ion etching or oxygen plasma etching.
  • the two-dimensional material layer 3 controlling the experimental conditions such that the number of layers of the grown two-dimensional material is smaller than the number of layers of the two-dimensional material 2, and when the two-dimensional material 3 is graphene, the thickness of the two-dimensional material layer 3 is 1-
  • the thickness of the 5-layer graphene may further be 2-3 layers.
  • the material of the insulating substrate 10 includes at least one of Si, SiO 2 , SOI, and SiC.
  • the method of transferring may be a hot press transfer method or a PMMA based method.
  • the exposure may be electron beam exposure or optical exposure, and electron beam exposure may be preferred, since the lengths of the remaining second two-dimensional material layer 132 and the third two-dimensional material layer 133 are below several tens of nanometers, and the first two-dimensional The length of the material layer 131 is not required, and the etching method may be reactive ion etching or oxygen plasma etching.
  • the source 11 and the drain are respectively defined at the outer side edges of the second two-dimensional material layer 132 and the third two-dimensional material layer 133 by photoresist exposure development.
  • the position of the pole 12 is then deposited to obtain the source 11 and the drain 12; between the source 11 and the drain 12 is a channel 13, in the channel 13, the source 11 and the drain 12
  • the second two-dimensional material layer 132, the first two-dimensional material layer 131 and the third two-dimensional material layer 133 are disposed in sequence; in the embodiment of the invention, the source 11 and the drain
  • the material of 12 is selected from the group consisting of a simple metal or a laminated structure of different metals or a metal carbide.
  • the metal element includes one of platinum, copper, nickel, and gold
  • the stacked structure of the different metals includes a stacked titanium layer/gold layer, a chromium layer/gold layer, a titanium layer/nickel layer, or A chromium layer/nickel layer comprising molybdenum carbide, or tantalum carbide, or tungsten carbide.
  • the exposure may be electron beam exposure
  • the method of depositing the source 11 and the drain 12 may be electron beam evaporation, the source 11 and the second two-dimensional material layer 132, the drain 12 and the third two-dimensional material.
  • the connection type of layer 133 is edge contact.
  • the material of the gate dielectric layer 14 is a high-k dielectric material
  • k is a dielectric constant
  • the high-k dielectric material can be prepared by, for example, atomic layer deposition (ALD) deposition, high-k dielectric material.
  • ALD atomic layer deposition
  • it may be at least one of alumina (Al 2 O 3 ), cerium oxide (HfO 2 ), and antimony trioxide (Y 2 O 3 ).
  • a gate electrode 15 is formed on the gate dielectric layer 14 to obtain a transistor based on a two-dimensional material.
  • the gate 15 may have a thickness of 20-80 nm, and the material may be gold, palladium, or tungsten, or other suitable metal electrode materials.
  • the gate electrode 15 can be deposited by electron beam evaporation, thermal evaporation or vacuum deposition.
  • the embodiment of the invention further provides a method for preparing the above-mentioned molybdenum disulfide-based transistor, comprising the following steps:
  • the insulating substrate material comprises at least one of Si, SiO 2 , SOI, SiC;
  • the molybdenum disulfide has a thickness of 5-20 layers, and may further be 10-20 layers; the molybdenum disulfide outside the predetermined area has a thickness of 1-5 layers, and further may be 2-3 layers;
  • Embodiments of the present invention also provide a method for fabricating the above-described tungsten disulfide-based transistor, comprising the following steps:
  • the insulating substrate material comprises at least one of Si, SiO 2 , SOI, SiC;
  • S50 growing tungsten disulfide on the insulating substrate by a method of chemical vapor deposition, wherein a thickness of the tungsten disulfide in the predetermined region is greater than a thickness of the tungsten disulfide outside the predetermined region;
  • the thickness of the tungsten disulfide is 5-20 layers, and further may be 10-20 layers;
  • the thickness of the tungsten disulfide outside the predetermined area is 1-5 layers, and further may be 2-3 layers;
  • the selection of the photoresist, the etching, the exposure mode, the source and drain, the gate dielectric layer, the gate, etc. involved in the preparation process of the graphene-based transistor is also applicable to the disulfide-based Preparation of transistors of molybdenum and tungsten disulfide.
  • the preparation method based on the two-dimensional material provided by the above embodiments of the present invention has a simple process and is suitable for industrial production.
  • an embodiment of the present invention further provides a transistor array device including an array structure formed by the above-described two-dimensional material-based transistor according to an embodiment of the present invention.
  • the transistor array device may be a radio frequency device having a high cutoff frequency and a maximum resonant frequency.
  • a method for preparing a graphene-based transistor includes the following steps:
  • the thickness of the graphene is 5-10 layers;
  • the gas source for growing graphene is methane, and the carrier gas used is argon gas.
  • 60sccm methane, 15sccm hydrogen and 300sccm argon gas were introduced into the CVD system.
  • the system was low pressure, the pressure was 100Pa, and the growth temperature was 1100 °C.
  • the graphene had covered the surface of the copper/nickel substrate, and then the graphene had covered the surface of the copper/nickel substrate.
  • the CVD system is slowly cooled to a normal temperature, and the cooling rate is 3 ° C / min (the thickness of the graphene can be controlled by the cooling rate, and the faster the temperature is, the thinner the graphene is);
  • the pole and the drain; the metal of the source and the drain are Ti/Au stacked, the thickness of Ti/Au is 10 nm/90 nm, the lower layer is titanium (Ti), and the upper layer is gold (Au).
  • the second graphene layer, the first graphene layer and the third graphene are sequentially disposed between the source and the drain a layer, a source and a second graphene layer, a drain and a third graphene layer are connected to each other in an edge contact;
  • a method for preparing a graphene-based transistor includes the following steps:
  • the number of layers of graphene is 1-2 layers, the gas source for growing graphene is methane, the carrier gas used is argon gas, 10sccm methane and 2sccm hydrogen are introduced into the CVD system, the system is low pressure, the growth temperature At 1050 ° C, after 30 minutes, the graphene has covered the surface of the copper substrate, and then the CVD system is cooled to normal temperature;
  • the pole and the drain; the metal of the source and the drain are Ti/Au stacked, the thickness of Ti/Au is 10 nm/90 nm, the lower layer is titanium (Ti), and the upper layer is gold (Au).
  • the second graphene layer, the first graphene layer and the third graphene are sequentially disposed between the source and the drain a layer, a source and a second graphene layer, a drain and a third graphene layer are connected to each other in an edge contact;
  • a method of making a transistor based on MoS 2 comprising the steps of:
  • the metal Mo is deposited on the surface of the SiO 2 by magnetron sputtering, and the deposited thickness is 0.5 nm;
  • the MoS 2 is grown on the above-mentioned SiO 2 /Si substrate with metal Mo by chemical vapor deposition.
  • the growth conditions were as follows: the gas introduced was H 2 S, so that the pressure in the chamber was 10000 Pa, the growth temperature was 800 ° C, and the growth time was 3 hours. After the growth is completed, the MoS 2 in the predetermined region is about 10 layers, and the other portions of the MoS 2 are about 3 layers.
  • the metal of the source and the drain are Ti/Au stacked, the thickness of Ti/Au is 5 nm/90 nm, the lower layer is titanium (Ti), and the upper layer is gold (Au).
  • a channel is formed between the source and the drain, and the second MoS2 layer, the first MoS 2 layer and the third MoS 2 layer are sequentially disposed between the source and the drain.
  • the connection type between the source and the second MoS 2 , the drain and the third MoS 2 layer are edge contacts;
  • the S90, the preparation of gold metal gate layer on the gate dielectric layer is hafnium oxide, based on the obtained transistor MoS 2.
  • a process for preparing 2-based WS transistor comprising the steps of:
  • the growth conditions were as follows: the gas to be introduced was 200 sccm of argon gas, the pressure was normal pressure, and the raw materials used were WO 3 and S powder, and the growth temperature was 825 °C.
  • the WO 3 and S molecules are carried by Ar to the surface of the substrate, and WS 2 is formed on the substrate, the growth time is 3 hours, and the WS 2 grown in the predetermined region is about 10 layers, and the rest of the WS 2 is about 2 layer.
  • the metal of the source and the drain are Ti/Au stacked, the thickness of Ti/Au is 5 nm/90 nm, the lower layer is titanium (Ti), and the upper layer is gold (Au).
  • a channel is formed between the source and the drain, and the second WS 2 layer, the first WS 2 layer and the third WS 2 are sequentially disposed between the source and the drain.
  • the layer, the source and the connection type of the second WS 2 , the drain and the third WS 2 layer are both edge contacts;
  • the S90, the preparation of gold metal gate layer on the gate dielectric layer is hafnium oxide, to obtain the transistor based on WS 2.

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Abstract

L'invention concerne un transistor basé sur un matériau bidimensionnel, comprenant un substrat isolant (10), et une électrode de source (11) ainsi qu'une électrode de drain (12) étant disposées au niveau de deux extrémités du substrat isolant (10), un canal (13) étant disposé entre l'électrode de source (11) et l'électrode de drain (12), et la partie centrale du canal (13) est pourvue d'une première couche de matériau bidimensionnel (131); d'une deuxième couche de matériau bidimensionnel (132) dans une zone de canal disposée sur un côté de la première couche de matériau bidimensionnel (131) et connectée à l'électrode de source (11), et une troisième couche de matériau bidimensionnel (133) dans une zone de canal disposée sur l'autre côté de la première couche de matériau bidimensionnel (131) et connectée à l'électrode de drain (12), les trois couches de matériau bidimensionnel étant une couche de film intégrale du même matériau; et une couche diélectrique de grille (14) ainsi qu'une électrode de grille (15) disposées sur la première couche de matériau bidimensionnel (131). L'épaisseur de la deuxième couche de matériau bidimensionnel (132) et l'épaisseur de la troisième couche de matériau bidimensionnel (133) sont toutes deux supérieures à l'épaisseur de la première couche de matériau bidimensionnel (131). Dans la structure de transistor, les deuxième et troisième couches de matériau bidimensionnel en contact avec les électrodes de source et de drain sont plus épaisses, de telle sorte que la résistance de contact peut être réduite, tandis que la première couche de matériau bidimensionnel dans la partie centrale du canal est plus mince que les zones de contact, assurant ainsi un taux de migration élevé et la modulation de la grille sur le canal en même temps. L'invention concerne en outre un procédé de préparation d'un transistor basé sur un matériau bidimensionnel et son application.
PCT/CN2017/081821 2017-04-25 2017-04-25 Transistor basé sur un matériau bidimensionnel et son procédé de préparation, et dispositif de réseau de transistors Ceased WO2018195761A1 (fr)

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CN201780083547.4A CN110178221B (zh) 2017-04-25 2017-04-25 一种基于二维材料的晶体管及其制备方法和晶体管阵列器件
PCT/CN2017/081821 WO2018195761A1 (fr) 2017-04-25 2017-04-25 Transistor basé sur un matériau bidimensionnel et son procédé de préparation, et dispositif de réseau de transistors

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CN111969058B (zh) * 2020-07-30 2022-07-01 电子科技大学中山学院 一种二硫化钼场效应晶体管及其制备方法和应用
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