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WO2018176565A1 - 一种液晶显示面板及装置 - Google Patents

一种液晶显示面板及装置 Download PDF

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Publication number
WO2018176565A1
WO2018176565A1 PCT/CN2017/082812 CN2017082812W WO2018176565A1 WO 2018176565 A1 WO2018176565 A1 WO 2018176565A1 CN 2017082812 W CN2017082812 W CN 2017082812W WO 2018176565 A1 WO2018176565 A1 WO 2018176565A1
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WO
WIPO (PCT)
Prior art keywords
liquid crystal
crystal display
common line
voltage
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/082812
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English (en)
French (fr)
Inventor
姜祥卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/546,945 priority Critical patent/US10438552B2/en
Priority to EP17903277.6A priority patent/EP3608711A4/en
Priority to JP2019554353A priority patent/JP6830551B2/ja
Publication of WO2018176565A1 publication Critical patent/WO2018176565A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel and device.
  • the size of the pixel is smaller and smaller, and the pixel aperture ratio is also smaller, thereby affecting the display brightness.
  • the conventional display panel includes a main pixel portion 101 and a sub-pixel portion 102, and three thin film transistors T1-T3, and the gates of T1-T3 are connected to the scan line 12, T1 and T2.
  • the sources are all connected to the data line 11, and the source of T3 is connected to the common line 13 through the shallow holes.
  • the internal resistance of T3 is much smaller than the internal resistance of T2, and the size of T3 is smaller than the size of T2.
  • the internal resistance of T3 and the resistance accuracy of deep and shallow holes are difficult to control. That is, the internal resistance of T3 and the resistance of the deep and shallow holes are likely to fluctuate, resulting in uneven voltage of the sub-pixel portion 102, which tends to cause uneven alignment during light alignment, and reduces display effects.
  • An object of the present invention is to provide a liquid crystal display panel and device capable of improving display performance.
  • the present invention provides a liquid crystal display panel, including:
  • the first common line is for providing a common voltage
  • the second common line is for performing a liquid crystal display panel
  • the main pixel portion has a first thin film transistor and a first pixel electrode
  • the first thin film transistor has a first gate, a first source, a first drain, the first gate and the scan a line connection, the first source is connected to the data line, and the first drain is connected to the first pixel electrode;
  • the sub-pixel portion has a second thin film transistor, a third thin film transistor, and a second pixel electrode, and the second thin film transistor has a second gate, a second source, and a second drain, and the third thin film transistor
  • the third gate, the third source, and the third drain are both connected to the scan line, and the second source is connected to the data line.
  • the second drain is connected to the third drain, the third drain is connected to the second pixel electrode, and the third source is connected to the second common line.
  • the voltage input by the second common line is equal to the voltage input by the data line, and the voltage input by the second common line is The voltage input to the first common line is not equal.
  • the second common line and the data line are both grounded.
  • the voltage input by the second common line is equal to the voltage input by the first common line.
  • the voltage of the sub-pixel portion is as follows:
  • Vsub R2/(R2+R3+R4 )* VCom2
  • VCom2 is a voltage input to the second common line
  • R1-R3 respectively represent internal resistances of the first thin film transistor, the second thin film transistor, and the second thin film transistor
  • R4 represents a resistance of the deep and shallow holes
  • Vsub" represents The voltage of the sub-pixel portion is described.
  • the invention provides a liquid crystal display panel comprising:
  • the first common line is for providing a common voltage
  • the second common line is for performing a liquid crystal display panel
  • the main pixel portion has a first thin film transistor and a first pixel electrode
  • the first thin film transistor has a first gate, a first source, and a first drain, a first gate is connected to the scan line, the first source is connected to the data line, and the first drain is connected to the first pixel electrode;
  • the sub-pixel portion has a second thin film transistor, a third thin film transistor, and a second pixel electrode, and the second thin film transistor has a second gate, a second source, and a second drain, and the third thin film transistor
  • the third gate, the third source, and the third drain are both connected to the scan line, and the second source is connected to the data line.
  • the second drain is connected to the third drain, the third drain is connected to the second pixel electrode, and the third source is connected to the second common line.
  • the voltage input by the second common line is equal to the voltage input by the data line, and the voltage input by the second common line is The voltage input to the first common line is not equal.
  • the second common line and the data line are both grounded.
  • the voltage of the sub-pixel portion is obtained according to the voltage input to the second common line.
  • the voltage input by the second common line is equal to the voltage input by the first common line.
  • the present invention further provides a liquid crystal display device comprising: a backlight module and a liquid crystal display panel, the liquid crystal display panel comprising: a data line, a scan line, a first common line, a second common line, a main pixel portion, and a sub-pixel portion;
  • the first common line is used to provide a common voltage
  • the second common line is used to make the voltage of the sub-pixel portion equal to a fixed value when the liquid crystal display panel is aligned, and the voltage of the main pixel portion The voltages of the sub-pixel portions are not equal.
  • the main pixel portion has a first thin film transistor and a first pixel electrode
  • the first thin film transistor has a first gate, a first source, and a first drain, a first gate is connected to the scan line, the first source is connected to the data line, and the first drain is connected to the first pixel electrode;
  • the sub-pixel portion has a second thin film transistor, a third thin film transistor, and a second pixel electrode, and the second thin film transistor has a second gate, a second source, and a second drain, and the third thin film transistor
  • the third gate, the third source, and the third drain are both connected to the scan line, and the second source is connected to the data line.
  • the second drain is connected to the third drain, the third drain is connected to the second pixel electrode, and the third source is connected to the second common line.
  • the voltage input by the second common line is equal to the voltage input by the data line, and the voltage input by the second common line is The voltage input to the first common line is not equal.
  • the second common line and the data line are both grounded.
  • the voltage of the sub-pixel portion is obtained according to the voltage input to the second common line.
  • the voltage input by the second common line is equal to the voltage input by the first common line.
  • the liquid crystal display panel and device of the present invention increase the voltage of the sub-pixel portion during the alignment process by adding an additional common line, thereby avoiding voltage unevenness of the sub-pixel portion, thereby making the alignment more uniform and improving the display effect. .
  • FIG. 1 is a schematic structural view of a conventional liquid crystal display panel.
  • FIG. 2 is an equivalent circuit diagram of a conventional liquid crystal display panel.
  • FIG. 3 is a schematic structural view of a liquid crystal display panel of the present invention.
  • FIG. 2 is an equivalent circuit diagram of a conventional liquid crystal display panel.
  • the electrical principle of the conventional liquid crystal display panel is specifically as follows: when the scanning line 12 is turned on, T2 and T3 are turned on, and the internal resistance and the deep and shallow hole resistance constitute a voltage dividing circuit.
  • Equation 1 the voltage of the sub-pixel portion 102 is as shown in Equation 1:
  • R1-R3 represent the internal resistance of T1-T3
  • R4 represents the internal resistance of the deep and shallow holes
  • Vsub represents the voltage of the sub-pixel portion 102
  • Vmain represents the voltage of the main pixel portion 101.
  • the voltage VCom of the common line 13 is an alternating voltage, such as an amplitude of 12 V.
  • the data line 11 is grounded, and the voltage of the data line is Vd.
  • the voltage Vsub' of the sub-pixel portion 102 is as shown in Formula 2:
  • the process is limited by various processes such as film formation, exposure, etching, etc., so that different regions R3 and R4 of the display panel are different, thereby causing a difference in the voltage of the sub-pixel portion 102, that is, the display panel is The alignment voltages of the sub-pixel portions in different regions are different, resulting in poor alignment.
  • FIG. 3 is a schematic structural diagram of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel of the present invention includes a data line 11, a scan line 12, a first common line 21, and a second common line 22; the liquid crystal display panel further includes a main pixel portion 201 and a sub-pixel portion 202.
  • the data line 11 is for inputting a data signal
  • the scan line 12 is for inputting a scan signal.
  • the first common line 21 is for providing a common voltage VCom1
  • the second common line 22 is for making the voltage of the sub-pixel portion 202 equal to a fixed value when the liquid crystal display panel is aligned, even if the sub-pixel portion The voltage remains constant.
  • the first common line 21 and the second common line 22 can be obtained by patterning the same metal layer.
  • the voltage of the main pixel portion 201 is not equal to the voltage of the sub-pixel portion 202.
  • the main pixel portion 201 has a first thin film transistor T1 and a first pixel electrode 203, and the first thin film transistor T1 has a first gate, a first source, and a first drain.
  • a gate is connected to the scan line 12
  • the first source is connected to the data line 11
  • the first drain is connected to the first pixel electrode 203.
  • the sub-pixel portion 202 has a second thin film transistor T2, a third thin film transistor T3, and a second pixel electrode 204.
  • the second thin film transistor T2 has a second gate, a second source, and a second drain.
  • the third thin film transistor T3 has a third gate, a third source, and a third drain. The second gate and the third gate are both connected to the scan line 12, the second source is connected to the data line 11, and the second drain is connected to the third drain.
  • the third drain is connected to the second pixel electrode 204, and the third source is connected to the second common line 22.
  • the third source is connected to the second common line 22 through the shallow holes.
  • the first common line 21 inputs an alternating voltage whose amplitude is 12V.
  • the voltage input by the second common line 22 is equal to the voltage input by the data line 11, and the voltage input by the second common line 22 is not equal to the voltage input by the first common line 12.
  • the second common line 22 and the data line 11 are both grounded.
  • the voltage Vsub" of the sub-pixel portion 202 is as shown in Formula 3:
  • Vsub R2/(R2+R3+R4)* VCom2 Equation 3
  • VCom2 is the voltage input to the second common line 22
  • R1-R3 respectively represent the internal resistance of T1-T3
  • R4 represents the resistance of the deep and shallow holes
  • Vsub" represents the voltage of the sub-pixel portion 102 at this time.
  • the voltage of the sub-pixel portion 202 is obtained according to the voltage input from the second common line 22.
  • the voltage of Vsub" is equal to the ground voltage, that is, the voltage of the sub-pixel portion 202 is fixed, so that the voltage difference of each sub-pixel portion is uniform, and is no longer subjected to the internal resistance of the TFT and the shallow hole.
  • the influence of the internal resistance is such that the alignment voltages of the sub-pixel portions in the entire liquid crystal display panel are the same, and the alignment failure is eliminated.
  • the voltage input by the second common line 22 is equal to the voltage input by the first common line 21, that is, VCom2 is equal to VCom1.
  • the first common line 21 and the second common line 22 may be electrically connected during panel display or testing.
  • the liquid crystal display panel of the present invention avoids the influence of the process process on the resistance of the T3 and the resistance of the deep and shallow holes by adding an additional common line, so that the voltage of the sub-pixel portion in the alignment is the same, that is, the sub-pixel portion is in the alignment process.
  • the voltage in the middle is kept constant, and the voltage of the sub-pixel portion is prevented from being uneven, so that the alignment is more uniform and the display effect is improved.
  • the present invention further provides a liquid crystal display device comprising a backlight module and a liquid crystal display panel, as shown in FIG. 3, the liquid crystal display panel includes a data line 11, a scan line 12, a first common line 21 and a second common line 22;
  • the liquid crystal display panel further includes a main pixel portion 201 and a sub-pixel portion 202.
  • the data line 11 is for inputting a data signal
  • the scan line 12 is for inputting a scan signal.
  • the first common line 21 is for providing a common voltage VCom1
  • the second common line 22 is for making the voltage of the sub-pixel portion 202 equal to a fixed value when the liquid crystal display panel is aligned, even if the sub-pixel portion The voltage remains constant.
  • the first common line 21 and the second common line 22 can be obtained by patterning the same metal layer.
  • the voltage of the main pixel portion 201 is not equal to the voltage of the sub-pixel portion 202.
  • the main pixel portion 201 has a first thin film transistor T1 and a first pixel electrode 203, and the first thin film transistor T1 has a first gate, a first source, and a first drain.
  • a gate is connected to the scan line 12
  • the first source is connected to the data line 11
  • the first drain is connected to the first pixel electrode 203.
  • the sub-pixel portion 202 has a second thin film transistor T2, a third thin film transistor T3, and a second pixel electrode 204.
  • the second thin film transistor T2 has a second gate, a second source, and a second drain.
  • the third thin film transistor T3 has a third gate, a third source, and a third drain. The second gate and the third gate are both connected to the scan line 12, the second source is connected to the data line 11, and the second drain is connected to the third drain.
  • the third drain is connected to the second pixel electrode 204, and the third source is connected to the second common line 22.
  • the third source is connected to the second common line 22 through the shallow holes.
  • the first common line 21 inputs an alternating voltage whose amplitude is 12V.
  • the voltage input by the second common line 22 is equal to the voltage input by the data line 11, and the voltage input by the second common line 22 is not equal to the voltage input by the first common line 12.
  • the second common line 22 and the data line 11 are both grounded.
  • the voltage Vsub" of the sub-pixel portion 202 is as shown in Formula 3:
  • Vsub R2/(R2+R3+R4)* VCom2 Equation 3
  • VCom2 is the voltage input to the second common line 22
  • R1-R3 respectively represent the internal resistance of T1-T3
  • R4 represents the resistance of the deep and shallow holes
  • Vsub" represents the voltage of the sub-pixel portion 102 at this time.
  • the voltage of the sub-pixel portion 202 is obtained according to the voltage input from the second common line 22.
  • the voltage of Vsub" is equal to the ground voltage, that is, the voltage of the sub-pixel portion 202 is fixed, so that the voltage difference of each sub-pixel portion is uniform, and is no longer subjected to the internal resistance of the TFT and the shallow hole.
  • the influence of the internal resistance is such that the alignment voltages of the sub-pixel portions in the entire liquid crystal display panel are the same, and the alignment failure is eliminated.
  • the voltage input by the second common line 22 is equal to the voltage input by the first common line 21, that is, VCom2 is equal to VCom1.
  • the first common line 21 and the second common line 22 may be electrically connected during panel display or testing.
  • the liquid crystal display device of the present invention avoids the influence of the process process on the resistance of the T3 and the resistance of the deep and shallow holes by adding an additional common line, so that the voltage of the sub-pixel portion in the alignment direction is the same, that is, the sub-pixel portion is in the alignment process.
  • the voltage in the middle is kept constant, and the voltage of the sub-pixel portion is prevented from being uneven, so that the alignment is more uniform and the display effect is improved.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种液晶显示面板及装置，其包括：数据线（11）、扫描线（12）、第一公共线（21）、第二公共线（22）、主像素部（101，201）以及子像素部（102，202）；第一公共线（21）用于提供公共电压，第二公共线（22）用于在对液晶显示面板进行配向时，使子像素部（102，202）的电压等于固定值，主像素部（101，201）的电压与子像素部（102，202）的电压不等。

Description

一种液晶显示面板及装置 技术领域
本发明涉及显示器技术领域，特别是涉及一种液晶显示面板及装置。
 背景技术
随着液晶显示面板精细度的提高，像素的尺寸越来越小，像素开口率也随之变小，从而影响显示亮度。
为了提高显示亮度，如图1所示，现有的显示面板包括主像素部101和子像素部102，以及三个薄膜晶体管T1-T3，T1-T3的栅极与扫描线12连接，T1和T2的源极都与数据线11连接，T3的源极通过深浅孔与公共线13连接。其中T3的内电阻远小于T2的内电阻，T3的尺寸要比较T2的尺寸小。通过T2、T3两个TFT内电阻的分压作用，使得子像素部102的电位比主像素部101电位低，实现了8个显示畴，从而提升视角。
但是在实际制程过程中，受成膜厚度、曝光、蚀刻等多方面的影响，使得T3的内电阻以及深浅孔的电阻精度不易控制。也即T3的内电阻及深浅孔的电阻容易出现波动，导致子像素部102的电压不均匀，光配向时容易导致配向不均，降低了显示效果。
因此，有必要提供一种液晶显示面板及装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶显示面板及装置，能够提高显示效果。
 技术解决方案
为解决上述技术问题，本发明提供一种液晶显示面板，其包括：
数据线、扫描线、第一公共线、第二公共线、主像素部以及子像素部；所述第一公共线用于提供公共电压，所述第二公共线用于在对液晶显示面板进行配向时，使所述子像素部的电压等于固定值，所述主像素部的电压与所述子像素部的电压不等；所述子像素部的电压根据所述第二公共线输入的电压获得的；
其中所述主像素部，具有第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线连接，所述第一源极与所述数据线连接，所述第一漏极与所述第一像素电极连接；
所述子像素部，具有第二薄膜晶体管、第三薄膜晶体管以及第二像素电极，所述第二薄膜晶体管具有第二栅极、第二源极、第二漏极，所述第三薄膜晶体管具有第三栅极、第三源极、第三漏极，所述第二栅极、所述第三栅极都与所述扫描线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极连接，所述第三源极与所述第二公共线连接。
在本发明的液晶显示面板中，当对液晶显示面板进行配向时，所述第二公共线输入的电压与所述数据线输入的电压相等，且所述第二公共线输入的电压与所述第一公共线输入的电压不等。
在本发明的液晶显示面板中，所述第二公共线和所述数据线都接地。
在本发明的液晶显示面板中，当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线输入的电压与所述第一公共线输入的电压相等。
在本发明的液晶显示面板中，所述子像素部的电压如下所示：
Vsub”=R2/(R2+R3+R4 )* VCom2
其中，VCom2为所述第二公共线输入的电压，R1-R3分别表示所述第一薄膜晶体管、第二薄膜晶体管以及第二薄膜晶体管的内电阻，R4表示深浅孔的电阻，Vsub”表示所述子像素部的电压。
本发明提供一种液晶显示面板，其包括：
数据线、扫描线、第一公共线、第二公共线、主像素部以及子像素部；所述第一公共线用于提供公共电压，所述第二公共线用于在对液晶显示面板进行配向时，使所述子像素部的电压等于固定值，所述主像素部的电压与所述子像素部的电压不等。
在本发明的液晶显示面板中，所述主像素部，具有第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线连接，所述第一源极与所述数据线连接，所述第一漏极与所述第一像素电极连接；
所述子像素部，具有第二薄膜晶体管、第三薄膜晶体管以及第二像素电极，所述第二薄膜晶体管具有第二栅极、第二源极、第二漏极，所述第三薄膜晶体管具有第三栅极、第三源极、第三漏极，所述第二栅极、所述第三栅极都与所述扫描线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极连接，所述第三源极与所述第二公共线连接。
在本发明的液晶显示面板中，当对液晶显示面板进行配向时，所述第二公共线输入的电压与所述数据线输入的电压相等，且所述第二公共线输入的电压与所述第一公共线输入的电压不等。
在本发明的液晶显示面板中，所述第二公共线和所述数据线都接地。
在本发明的液晶显示面板中，所述子像素部的电压根据所述第二公共线输入的电压获得的。
在本发明的液晶显示面板中，当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线输入的电压与所述第一公共线输入的电压相等。
本发明还提供一种液晶显示装置，其包括：背光模块以及液晶显示面板，该液晶显示面板包括：数据线、扫描线、第一公共线、第二公共线、主像素部以及子像素部；所述第一公共线用于提供公共电压，所述第二公共线用于在对液晶显示面板进行配向时，使所述子像素部的电压等于固定值，所述主像素部的电压与所述子像素部的电压不等。
在本发明的液晶显示装置中，所述主像素部，具有第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线连接，所述第一源极与所述数据线连接，所述第一漏极与所述第一像素电极连接；
所述子像素部，具有第二薄膜晶体管、第三薄膜晶体管和第二像素电极，所述第二薄膜晶体管具有第二栅极、第二源极、第二漏极，所述第三薄膜晶体管具有第三栅极、第三源极、第三漏极，所述第二栅极、所述第三栅极都与所述扫描线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极连接，所述第三源极与所述第二公共线连接。
在本发明的液晶显示装置中，当对液晶显示面板进行配向时，所述第二公共线输入的电压与所述数据线输入的电压相等，且所述第二公共线输入的电压与所述第一公共线输入的电压不等。
在本发明的液晶显示装置中，所述第二公共线和所述数据线都接地。
在本发明的液晶显示装置中，所述子像素部的电压根据所述第二公共线输入的电压获得的。
在本发明的液晶显示装置中，当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线输入的电压与所述第一公共线输入的电压相等。
 有益效果
本发明的液晶显示面板及装置，通过增加额外的公共线，以使得子像素部在配向过程中的电压保持恒定，从而避免了子像素部的电压不均匀，使得配向更加均匀，提高了显示效果。
 附图说明
图1为现有的液晶显示面板的结构示意图。
图2为现有的液晶显示面板的等效电路图。
图3为本发明的液晶显示面板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为现有的液晶显示面板的等效电路图。
如图2所示，现有的液晶显示面板的电性原理具体如下：当扫描线12打开时，T2、T3导通，其内部电阻与深浅孔电阻构成分压电路。
在显示过程中，子像素部102的电压如公式1所示：
Vsub=(R3+R4)/(R2+R2+R4 )*Vmain 公式1
其中，R1-R3分别表示T1-T3的内电阻，R4表示深浅孔的内电阻，Vsub表示子像素部102的电压，Vmain表示主像素部101的电压。
在HVA光配向时，公共线13的电压VCom为交流电压，比如幅值为12 V。数据线11接地，数据线的电压为Vd，此时子像素部102的电压Vsub’如公式2所示：
Vsub’=R2/(R2+R3+R4 )* VCom 公式2
但是实际制程过程中，受成膜、曝光、蚀刻等多方面的工艺的限制，使得显示面板的不同区域R3、R4存在差异、从而导致子像素部102的电压存在差异，也即使得显示面板的不同区域的子像素部的配向电压不同，导致配向不良。
请参照图3，图3为本发明的液晶显示面板的结构示意图。
如图3所示，本发明的液晶显示面板包括数据线11、扫描线12、第一公共线21以及第二公共线22；所述液晶显示面板还包括主像素部201和子像素部202。
数据线11用于输入数据信号，扫描线12用于输入扫描信号。所述第一公共线21用于提供公共电压VCom1，所述第二公共线22用于在对液晶显示面板进行配向时，使所述子像素部202的电压等于固定值，也即使子像素部的电压保持恒定。第一公共线21和第二公共线22可以通过对同一金属层进行图案化处理得到。其中所述主像素部201的电压与所述子像素部202的电压不等。
在一实施方式中，该主像素部201具有第一薄膜晶体管T1和第一像素电极203，所述第一薄膜晶体管T1具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线12连接，所述第一源极与所述数据线11连接，所述第一漏极与所述第一像素电极203连接。
该子像素部202具有第二薄膜晶体管T2、第三薄膜晶体管T3和第二像素电极204。所述第二薄膜晶体管T2具有第二栅极、第二源极、第二漏极。所述第三薄膜晶体管T3具有第三栅极、第三源极、第三漏极。所述第二栅极、所述第三栅极都与所述扫描线12连接，所述第二源极与所述数据线11连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极204连接，所述第三源极与所述第二公共线22连接。其中第三源极通过深浅孔与第二公共线22连接。
当对液晶显示面板进行配向时，第一公共线21输入交流电压，该电压的幅值为12V。所述第二公共线22输入的电压与所述数据线11输入的电压相等，且所述第二公共线22输入的电压与所述第一公共线12输入的电压不等。其中所述第二公共线22和所述数据线11都接地。
此时子像素部202的电压Vsub”如公式3所示：
Vsub”=R2/(R2+R3+R4 )* VCom2 公式3
其中，VCom2为所述第二公共线22输入的电压，R1-R3分别表示T1-T3的内电阻，R4表示深浅孔的电阻，Vsub”表示此时子像素部102的电压。也即所述子像素部202的电压根据所述第二公共线22输入的电压获得的。
由于第二公共线22接地，使得Vsub”的电压等于接地电压，也即使得子像素部202的电压固定，从而使得各子像素部的电压差一致，不再受到TFT的内电阻和深浅孔的内电阻的影响，从而使整个液晶显示面板内子像素部的配向电压相同，消除配向不良的情形。
当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线22输入的电压与所述第一公共线21输入的电压相等，也即VCom2等于VCom1。具体地可以在面板显示或者测试过程中，第一公共线21与第二公共线22电性连接。
本发明的液晶显示面板，通过增加额外的公共线，避免制程工艺对T3内电阻及深浅孔的电阻的影响，从而使得子像素部在配向时的电压相同，也即使得子像素部在配向过程中的电压保持恒定，避免子像素部的电压不均匀的情况，使得配向更加均匀，提高了显示效果。
本发明还提供一种液晶显示装置，其包括背光模块和液晶显示面板，如图3所示，该液晶显示面板包括数据线11、扫描线12、第一公共线21以及第二公共线22；所述液晶显示面板还包括主像素部201和子像素部202。
数据线11用于输入数据信号，扫描线12用于输入扫描信号。所述第一公共线21用于提供公共电压VCom1，所述第二公共线22用于在对液晶显示面板进行配向时，使所述子像素部202的电压等于固定值，也即使子像素部的电压保持恒定。第一公共线21和第二公共线22可以通过对同一金属层进行图案化处理得到。所述主像素部201的电压与所述子像素部202的电压不等。
在一实施方式中，该主像素部201具有第一薄膜晶体管T1和第一像素电极203，所述第一薄膜晶体管T1具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线12连接，所述第一源极与所述数据线11连接，所述第一漏极与所述第一像素电极203连接。
该子像素部202具有第二薄膜晶体管T2、第三薄膜晶体管T3和第二像素电极204。所述第二薄膜晶体管T2具有第二栅极、第二源极、第二漏极。所述第三薄膜晶体管T3具有第三栅极、第三源极、第三漏极。所述第二栅极、所述第三栅极都与所述扫描线12连接，所述第二源极与所述数据线11连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极204连接，所述第三源极与所述第二公共线22连接。其中第三源极通过深浅孔与第二公共线22连接。
当对液晶显示面板进行配向时，第一公共线21输入交流电压，该电压的幅值为12V。所述第二公共线22输入的电压与所述数据线11输入的电压相等，且所述第二公共线22输入的电压与所述第一公共线12输入的电压不等。其中所述第二公共线22和所述数据线11都接地。
此时子像素部202的电压Vsub”如公式3所示：
Vsub”=R2/(R2+R3+R4 )* VCom2 公式3
其中，VCom2为所述第二公共线22输入的电压，R1-R3分别表示T1-T3的内电阻，R4表示深浅孔的电阻，Vsub”表示此时子像素部102的电压。也即所述子像素部202的电压根据所述第二公共线22输入的电压获得的。
由于第二公共线22接地，使得Vsub”的电压等于接地电压，也即使得子像素部202的电压固定，从而使得各子像素部的电压差一致，不再受到TFT的内电阻和深浅孔的内电阻的影响，从而使整个液晶显示面板内子像素部的配向电压相同，消除配向不良的情形。
当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线22输入的电压与所述第一公共线21输入的电压相等，也即VCom2等于VCom1。具体地可以在面板显示或者测试过程中，第一公共线21与第二公共线22电性连接。
本发明的液晶显示装置，通过增加额外的公共线，避免制程工艺对T3内电阻及深浅孔的电阻的影响，从而使得子像素部在配向时的电压相同，也即使得子像素部在配向过程中的电压保持恒定，避免子像素部的电压不均匀的情况，使得配向更加均匀，提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种液晶显示面板，其包括：数据线、扫描线、第一公共线、第二公共线、主像素部以及子像素部；所述第一公共线用于提供公共电压，所述第二公共线用于在对液晶显示面板进行配向时，使所述子像素部的电压等于固定值，所述主像素部的电压与所述子像素部的电压不等；所述子像素部的电压根据所述第二公共线输入的电压获得的；
    其中所述主像素部，具有第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线连接，所述第一源极与所述数据线连接，所述第一漏极与所述第一像素电极连接；
    所述子像素部，具有第二薄膜晶体管、第三薄膜晶体管以及第二像素电极，所述第二薄膜晶体管具有第二栅极、第二源极、第二漏极，所述第三薄膜晶体管具有第三栅极、第三源极、第三漏极，所述第二栅极、所述第三栅极都与所述扫描线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极连接，所述第三源极与所述第二公共线连接。
  2. 根据权利要求1所述的液晶显示面板，其中：
    当对液晶显示面板进行配向时，所述第二公共线输入的电压与所述数据线输入的电压相等，且所述第二公共线输入的电压与所述第一公共线输入的电压不等。
  3. 根据权利要求2所述的液晶显示面板，其中所述第二公共线和所述数据线都接地。
  4. 根据权利要求1所述的液晶显示面板，其中当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线输入的电压与所述第一公共线输入的电压相等。
  5. 根据权利要求1所述的液晶显示面板，其中所述子像素部的电压如下所示：
    Vsub”=R2/(R2+R3+R4 )* VCom2
    其中，VCom2为所述第二公共线输入的电压，R1-R3分别表示所述第一薄膜晶体管、第二薄膜晶体管以及第二薄膜晶体管的内电阻，R4表示深浅孔的电阻，Vsub”表示所述子像素部的电压。
  6. 一种液晶显示面板，其包括：数据线、扫描线、第一公共线、第二公共线、主像素部以及子像素部；所述第一公共线用于提供公共电压，所述第二公共线用于在对液晶显示面板进行配向时，使所述子像素部的电压等于固定值，所述主像素部的电压与所述子像素部的电压不等。
  7. 根据权利要求6所述的液晶显示面板，其中：
    所述主像素部，具有第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线连接，所述第一源极与所述数据线连接，所述第一漏极与所述第一像素电极连接；
    所述子像素部，具有第二薄膜晶体管、第三薄膜晶体管以及第二像素电极，所述第二薄膜晶体管具有第二栅极、第二源极、第二漏极，所述第三薄膜晶体管具有第三栅极、第三源极、第三漏极，所述第二栅极、所述第三栅极都与所述扫描线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极连接，所述第三源极与所述第二公共线连接。
  8. 根据权利要求6所述的液晶显示面板，其中：
    当对液晶显示面板进行配向时，所述第二公共线输入的电压与所述数据线输入的电压相等，且所述第二公共线输入的电压与所述第一公共线输入的电压不等。
  9. 根据权利要求8所述的液晶显示面板，其中所述第二公共线和所述数据线都接地。
  10. 根据权利要求6所述的液晶显示面板，其中所述子像素部的电压根据所述第二公共线输入的电压获得的。
  11. 根据权利要求6所述的液晶显示面板，其中当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线输入的电压与所述第一公共线输入的电压相等。
  12. 一种液晶显示装置，其包括：
    背光模块，以及
    液晶显示面板，其包括：数据线、扫描线、第一公共线、第二公共线、主像素部以及子像素部；所述第一公共线用于提供公共电压，所述第二公共线用于在对液晶显示面板进行配向时，使所述子像素部的电压等于固定值，所述主像素部的电压与所述子像素部的电压不等。
  13. 根据权利要求12所述的液晶显示装置，其中：
    所述主像素部，具有第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管具有第一栅极、第一源极、第一漏极，所述第一栅极与所述扫描线连接，所述第一源极与所述数据线连接，所述第一漏极与所述第一像素电极连接；
    所述子像素部，具有第二薄膜晶体管、第三薄膜晶体管以及第二像素电极，所述第二薄膜晶体管具有第二栅极、第二源极、第二漏极，所述第三薄膜晶体管具有第三栅极、第三源极、第三漏极，所述第二栅极、所述第三栅极都与所述扫描线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第三漏极连接，所述第三漏极与所述第二像素电极连接，所述第三源极与所述第二公共线连接。
  14. 根据权利要求12所述的液晶显示装置，其中当对液晶显示面板进行配向时，所述第二公共线输入的电压与所述数据线输入的电压相等，且所述第二公共线输入的电压与所述第一公共线输入的电压不等。
  15. 根据权利要求14所述的液晶显示装置，其中所述第二公共线和所述数据线都接地。
  16. 根据权利要求12所述的液晶显示装置，其中所述子像素部的电压根据所述第二公共线输入的电压获得的。
  17. 根据权利要求12所述的液晶显示装置，其中当液晶显示面板进行显示或者对液晶显示面板进行测试时，所述第二公共线输入的电压与所述第一公共线输入的电压相等。
PCT/CN2017/082812 2017-04-01 2017-05-03 一种液晶显示面板及装置 Ceased WO2018176565A1 (zh)

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