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WO2018163896A1 - Dispositif d'imagerie à semi-conducteurs et système de caméra qui utilise celui-ci - Google Patents

Dispositif d'imagerie à semi-conducteurs et système de caméra qui utilise celui-ci Download PDF

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Publication number
WO2018163896A1
WO2018163896A1 PCT/JP2018/007107 JP2018007107W WO2018163896A1 WO 2018163896 A1 WO2018163896 A1 WO 2018163896A1 JP 2018007107 W JP2018007107 W JP 2018007107W WO 2018163896 A1 WO2018163896 A1 WO 2018163896A1
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Prior art keywords
comparator
imaging device
solid
state imaging
conversion
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English (en)
Japanese (ja)
Inventor
阿部　豊
西村　佳壽子
洋 藤中
範彦 角谷
陽介 東
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to US16/491,123 priority Critical patent/US10931908B2/en
Priority to JP2019504487A priority patent/JP7303103B2/ja
Publication of WO2018163896A1 publication Critical patent/WO2018163896A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45237—Complementary long tailed pairs having parallel inputs and being supplied in series
    • H03F3/45242—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors

Definitions

  • the present disclosure relates to a solid-state imaging device and a camera system using the same.
  • MOS-type image sensors in which peripheral circuits can be mixed in the same chip are mainly column AD conversion systems that simultaneously AD-convert pixel output signals for each column in an image sensor having a large number of pixels.
  • the solid-state imaging device has further increased in frame rate, and the digital output data has also increased in bit rate.
  • the upper bit side and the lower bit side AD conversion circuits having a configuration that adopts different AD conversion methods have been proposed.
  • Patent Document 1 discloses a column AD conversion circuit that digitally converts upper bits by a successive approximation AD conversion method and digitally converts lower bits by a single slope AD conversion method.
  • SAR + SS type AD conversion in which the upper bit AD conversion is performed by successive approximation AD conversion (hereinafter referred to as SAR conversion) and the lower bit AD conversion is performed by single slope AD conversion (hereinafter referred to as SS conversion).
  • SAR conversion successive approximation AD conversion
  • SS conversion single slope AD conversion
  • Patent Document 1 does not affect the final digital value by performing SS conversion in a wider range than the narrowed range even if noise is mixed during SAR conversion.
  • noise is mixed during conversion, there is a problem that a conversion error occurs in the final digital value.
  • Patent Document 1 it is necessary to reduce the operation band to a low speed in order to suppress the mixing of noise in SS conversion, and the operation speed of SAR conversion does not increase and the total AD conversion time becomes long. There is another problem.
  • an object of the present disclosure is to provide a solid-state imaging device that realizes high-speed SAR conversion and performs high-quality and high-frame-rate reading while suppressing noise contamination in SS conversion.
  • a solid-state imaging device has a photoelectric conversion unit that converts an optical signal into an electric signal, and includes a plurality of pixel cells arranged in the X direction and the Y direction, A plurality of vertical signal lines connected to the pixel cells and arranged in the X direction for transmitting the electrical signals as analog signals, and an X direction connected to the plurality of vertical signal lines and converting the analog signals to digital signals.
  • the first AD converter circuit uses the first comparator to narrow down the range including the potential of the analog signal by binary search, and based on the result of binary search, Top
  • the second AD converter circuit performs a first AD conversion to generate a first digital signal that is a portion, and the second AD converter circuit compares the magnitude relationship between the narrowed analog signal and the RAMP signal. By measuring the time until the output is inverted, the second AD conversion for generating the second digital signal which is the remaining lower side portion of the digital signal is performed.
  • a camera system includes the solid-state imaging device described above.
  • high-speed AD conversion can be realized while noise is suppressed, and high-frame-rate and high-quality imaging can be performed.
  • FIG. 1 is a diagram illustrating a configuration example of the solid-state imaging device according to the first embodiment.
  • FIG. 2 is a diagram illustrating a configuration example of the pixel cell according to the first embodiment.
  • FIG. 3 is an example illustrating a configuration example of the AD conversion unit according to the first embodiment.
  • FIG. 4 is an operation timing chart of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is an operation timing chart of the solid-state imaging device according to the first embodiment.
  • FIG. 6 is an operation timing chart of the solid-state imaging device according to the first embodiment.
  • FIG. 7A is a diagram illustrating a configuration example of the first comparator according to the first embodiment.
  • FIG. 7B is a diagram illustrating another configuration example of the first comparator according to the first embodiment.
  • FIG. 7C is a diagram illustrating a configuration example of the second comparator according to the first embodiment.
  • FIG. 7D is a diagram illustrating another configuration example of the second comparator according to the first embodiment.
  • FIG. 8A is a diagram showing another configuration example of the pixel cell according to Embodiment 1.
  • FIG. 8B is a cross-sectional view showing another configuration example of the pixel cell according to Embodiment 1.
  • FIG. 9 is a diagram illustrating a configuration example of an AD conversion unit according to the second embodiment.
  • FIG. 10 is a diagram illustrating a configuration example of the AD conversion unit according to the second embodiment.
  • FIG. 11 is a diagram illustrating a configuration example of the solid-state imaging device according to the third embodiment.
  • FIG. 12 is a diagram illustrating a configuration example of an AD conversion unit according to the third embodiment.
  • FIG. 13 is a diagram illustrating a configuration example of an AD conversion unit according to the third embodiment.
  • FIG. 14 is a diagram illustrating a configuration example of a buffer circuit according to the third embodiment.
  • FIG. 15 is a diagram illustrating a configuration example of a camera system according to the fourth embodiment.
  • FIG. 1 is a diagram illustrating an overall configuration of the solid-state imaging device according to the first embodiment.
  • the solid-state imaging device of the figure includes a pixel array unit 1, a vertical scanning circuit 2, a current source unit 3, an AD unit 4, a memory unit 5, and an output selection circuit 6.
  • the pixel array unit 1 includes a plurality of pixel cells (unit cells) 10 each having a photoelectric conversion unit that converts an optical signal into an electrical signal.
  • the plurality of pixel cells 10 are arranged in an array (that is, two-dimensionally) in the X direction and the Y direction.
  • a common vertical signal line 11 is connected to the pixel cells 10 belonging to the same column.
  • the pixel cells 10 belonging to the same row are connected to a common transfer signal line 12, reset signal line 13, and selection signal line 15.
  • the vertical scanning circuit 2 sequentially scans the pixel array unit 1 in units of rows by using the transfer signal line 12, the reset signal line 13, and the selection signal line 15.
  • the current source unit 3 has a plurality of current sources 30 arranged in the X direction. Each current source 30 forms a source follower circuit that is paired with the readout transistor in the pixel cell 10 selected by scanning.
  • the AD (Analog Digital) unit 4 includes a plurality of AD conversion units 40 arranged in the X direction.
  • the memory unit 5 includes a plurality of memory circuits 50 arranged in the X direction.
  • the output selection circuit 6 selects the memory circuit 50 and outputs a digital signal for each pixel cell 10.
  • FIG. 2 is a diagram illustrating a configuration example of the pixel cell 10 according to the first embodiment.
  • a pixel cell 10 shown in FIG. 2 includes a photodiode 100, an FD unit 101, a transfer transistor (transfer Tr) 102, a reset transistor (reset Tr) 103, a read transistor (read Tr) 104, and a selection transistor (selection). Tr) 105.
  • the photodiode 100 is a photoelectric conversion element (also referred to as a photoelectric conversion unit, a light receiving unit, or a pixel) that converts an optical signal into an electric signal.
  • a photoelectric conversion element also referred to as a photoelectric conversion unit, a light receiving unit, or a pixel
  • the FD unit 101 is transferred with the signal charge generated by the photodiode 100 and temporarily holds it as an electric signal.
  • the transfer transistor 102 is provided between the photodiode 100 and the FD unit 101, and transfers signal charges from the photodiode 100 to the FD unit 101.
  • the reset transistor 103 is connected to the FD unit 101 and resets the FD unit 101.
  • the gate of the read transistor 104 is connected to the FD unit 101, and outputs a potential corresponding to the potential of the FD unit 101.
  • the selection transistor 105 is provided between the readout transistor 104 and the vertical signal line 11, selects the output of the readout transistor 104, and outputs a potential signal from the pixel cell 10 to the vertical signal line 11.
  • the gate of the transfer transistor 102 is connected to the transfer signal line 12, the gate of the reset transistor 103 is connected to the reset signal line 13, and the gate of the selection transistor 105 is connected to the selection signal line 15.
  • the vertical scanning circuit 2 is connected to the transfer signal line 12, the reset signal line 13, and the selection signal line 15, and the pixel cell 10 generates and outputs an electric signal corresponding to the optical signal for each row. Take control.
  • the current source unit 3 has a current source 30 provided for each column.
  • the current source 30 is connected to the vertical signal line 11 of each column, and forms a source follower circuit together with the read transistor 104 of each pixel cell of the corresponding column.
  • the potential of the FD unit 101 is read out to the vertical signal line 11 by the formed source follower circuit.
  • the AD unit 4 includes an AD conversion unit 40 provided for each vertical signal line 11.
  • the AD conversion unit 40 is connected to the vertical signal line 11 and converts an analog signal read out to the vertical signal line 11 into a digital value.
  • the memory circuit 50 temporarily holds the digital signal converted by the AD conversion unit 40.
  • the output selection circuit 6 sequentially selects and outputs the digital signals held in the memory circuit 50 for each predetermined column unit.
  • FIG. 3 is a diagram illustrating a configuration example of the AD conversion unit 40 according to the present embodiment.
  • the third includes a first switch 401, a first AD conversion circuit 41, and a second AD conversion circuit 42.
  • the first AD converter circuit 41 includes a capacitor group 400, a first signal line S1 having a first potential V1, a second signal line S2 having a second potential V2, and a first comparator 404.
  • the capacitor group 400 includes a plurality of capacitors 400_0 to N (N is an integer of 2 or more).
  • the switch group 408 includes a plurality of switches 408_1 to N provided corresponding to the plurality of capacitors 400_1 to N.
  • the plurality of capacitors 400_0 to 400_N have weighted capacitance values, and in this embodiment, 2 0 ⁇ C, 2 0 ⁇ C, 2 1 ⁇ C,..., 2 N ⁇ C, (N is Although it is a binary weight type capacitance value such as an integer of 2 or more, it is not necessarily limited to this.
  • the first switch 401 is disposed between the vertical signal line 11 and the first node n1, and is turned on to transmit an analog signal output from the vertical signal line 11 to the first node n1,
  • the capacitor group 400 holds the total charge amount by being turned off.
  • the first comparator 404 is connected to the first node n1, compares the magnitude relationship between the potential Vsh of the first node n1 and the reference potential Vref of the reference signal line 414, and compares the result with the first control circuit. It outputs to 406.
  • the second switches 408_1 to 408_N select and supply either the first potential V1 or the second potential V2 to the corresponding capacitors 400_1 to 400_N according to the output of the first control circuit 406.
  • the first control circuit 406 controls the second switches 408_1 to 408_N according to the output of the first comparator 404 so that the range including the potential Vsh of the first node n1 is narrowed down by binary search. And a first digital signal corresponding to the result of the binary search is generated.
  • the first digital signal is an upper portion of the digital signal obtained by converting the analog signal of the vertical signal line 11.
  • the second comparator 405 is connected to the first node n1, compares the magnitude Vsh between the potential Vsh of the first node n1 and the ramp signal of the RAMP signal 413, and the result is sent to the second control circuit 407. Output.
  • the second control circuit 407 measures the time until the magnitude relationship between the potential Vsh of the first node n1 and the potential of the RAMP signal is switched, and generates a second digital signal corresponding to the measured time.
  • the second digital signal is the remaining lower side portion of the digital signal obtained by converting the analog signal of the vertical signal line 11.
  • the output selection circuit 6 selectively reads and outputs the first digital signal and the second digital signal generated by each AD converter 40.
  • FIG. 5 and FIG. 6 are operation timing charts of the solid-state imaging device of FIG. However, N in FIG.
  • ⁇ RS indicates a pulse signal for commonly controlling reset transistors in a predetermined row.
  • ⁇ TX indicates a pulse signal for commonly controlling transfer transistors in a predetermined row.
  • ⁇ SEL indicates a pulse signal for commonly controlling the selection transistors in a predetermined row.
  • V pix indicates the potential of the vertical signal line 11 connected to a predetermined pixel cell.
  • ⁇ SH indicates a pulse signal for commonly controlling the first switch 401.
  • V sh indicates the potential of the first node n1 of the AD conversion unit 40 in a predetermined column.
  • V ramp indicates the potential of the RAMP signal line 413.
  • V ref indicates the potential of the reference signal line 414.
  • V 1 (V1 in the figure) represents the first potential.
  • V 2 (V2 in the figure) represents the second potential.
  • ⁇ SW2_1 to ⁇ SW2_4 represent pulse signals for controlling a plurality of second switches in a predetermined column.
  • Second switch 408_1 ⁇ 408_4 is the time when the pulse signal ⁇ SW2_1 ⁇ ⁇ SW2_4 the "L" level to control the respectively supplied to the capacitor 400_1 ⁇ 400_4 to the corresponding second potential V 2, the "H" level first supplying a potential V 1 to the corresponding capacitor 400_1 ⁇ 400_4.
  • the first AD conversion is performed between time t4 and time t5, and details thereof are shown in FIG.
  • the first comparator 404 compares V ref and V sh . If V sh is higher, the first control circuit 406 returns ⁇ SW2_1 to the “L” level, and if lower, the “H” level. Operate to maintain. Here, since towards the V sh is high, FaiSW2_1 returns to "L" level and the signal supplied to the capacitor 400_1 be returned to the second potential V 2, V sh is returned to V rst.
  • V sh increases by (V 1 ⁇ V 2 ) / 2 2 .
  • V ref and V sh are compared. If V sh is high, the first control circuit 406 returns ⁇ SW2_2 to the “L” level, and if low, operates to maintain the “H” level.
  • V sh since V sh is higher, ⁇ SW2_2 returns to the “L” level, the signal supplied to the capacitor 400_2 also returns to V 2 , and V sh returns to V rst .
  • V sh increases by (V 1 ⁇ V 2 ) / 2 3 .
  • V ref and V sh are compared. If V sh is high, the first control circuit 406 returns to the ⁇ SW2_3 “L” level, and if low, operates to maintain the “H” level.
  • V sh is lower, ⁇ SW2_3 maintains the “H” level, the signal supplied to the capacitor 400_3 is also maintained at the first potential V 1 , and V sh is also V rst + (V 1 ⁇ V 2 ) / 2 3 is maintained.
  • V sh increases by (V 1 ⁇ V 2 ) / 2 4 .
  • V ref and V sh are compared, and if V sh is high, the first control circuit 406 returns ⁇ SW2_4 to the “L” level, and if low, operates to maintain the “H” level.
  • V sh since V sh is higher, ⁇ SW2_2 returns to the “L” level, the signal supplied to the capacitor 400_4 also returns to V 2 , and V sh also changes to V rst + (V 1 ⁇ V 2 ) / 2 3 .
  • V ramp starts sweeping at time t6, and the second control circuit 407 measures time T d until time t7 (t7 is not shown) when the magnitude relationship between Vsh and V ramp is switched. and it outputs a second digital signal D2_rst corresponding to T d.
  • the sweep of V ramp stops at time t8.
  • the first AD conversion is performed between time t11 and time t12. The details are shown in FIG.
  • SW2_1 to SW2_4 are reset to “L” level between time t8 and time t9.
  • the first comparator 404 compares V ref and V sh . If V sh is higher, the first control circuit 406 returns ⁇ SW2_1 to the “L” level, and if lower, the “H” level. Operate to maintain. Here, since towards the V sh is high, FaiSW2_1 returns to "L" level and the signal supplied to the capacitor 400_1 be returned to the second potential V 2, V sh is returned to V sig.
  • V sh increases by (V 2 ⁇ V 1 ) / 2 2 .
  • V ref and V sh are compared, and if V sh is high, the first control circuit 406 returns ⁇ SW2_2 to the “L” level, and if low, operates to maintain the “H” level.
  • V sh is lower, ⁇ SW2_2 maintains the “H” level, the signal supplied to the capacitor 400_2 is also maintained at V 1 , and V sh is also V sig + (V 1 ⁇ V 2 ) / 2. 2 is maintained.
  • V sh increases by (V 1 ⁇ V 2 ) / 2 3 .
  • V ref and V sh are compared. If V sh is high, the first control circuit 406 returns to the ⁇ SW2_3 “L” level, and if low, operates to maintain the “H” level.
  • V sh since V sh is higher, ⁇ SW2_3 returns to the L ′′ level, the signal supplied to the capacitor 400_1 also returns to V 2 , and V sh returns to V rst + (V 1 ⁇ V 2 ) / 2 2 . .
  • V sh increases by (V 1 ⁇ V 2 ) / 2 4 .
  • V ref and V sh are compared. If V sh is high, the first control circuit 406 returns ⁇ SW2_4 to the “L” level, and if low, operates to maintain the “H” level.
  • V sh is lower, ⁇ SW2_4 maintains the “H” level, the signal supplied to the capacitor 400_4 also maintains V 1 , and V sh is also V rst + (V 1 ⁇ V 2 ) / 2. 2 + (V 1 ⁇ V 2 ) / 2 4 is maintained.
  • V ramp starts sweeping at time t13, and the second control circuit 407 measures time Tu until time t14 (t14 is not shown) when the magnitude relationship between V sh and V ramp is switched.
  • a second digital signal D2_sig corresponding to Tu is output. The sweep of V ramp stops at time t15.
  • the first comparator 404 is used for the first AD conversion for acquiring the first digital signal by the binary search.
  • the noise of the first comparator 404 superimposes noise on the first digital signal.
  • the noise is also added to the potential of the first node n1.
  • the noise is canceled at the time of AD conversion of 2 and does not affect the finally obtained digital conversion value.
  • the operation speed of the first comparator 404 is slow, the time required for the first AD conversion becomes long.
  • the first comparator 404 is excellent in high speed, for example, as shown in FIG. 7A.
  • a latch type comparison circuit or a chopper type comparison circuit as shown in FIG. 7B, high-speed digital conversion can be performed without affecting the AD conversion accuracy.
  • the noise of the second comparator 405 superimposes noise on the second digital signal, which causes an AD conversion error.
  • the conversion time required for the second AD conversion depends on the clock frequency for performing time measurement, and the time required for the second AD conversion is long even if the operation speed of the second comparator is low. Must not. Therefore, by using a differential amplification type comparison circuit such as shown in FIG. 7C or FIG. 7D that is excellent in low noise for the second comparator 405, the AD converter speed is not affected. Accurate digital conversion is possible.
  • the upper bit side is subjected to successive approximation AD conversion
  • the lower bit side is subjected to single slope AD conversion.
  • the comparator used for successive approximation AD conversion is different from the comparator used for single slope AD conversion.
  • the pixel cell 10 includes a plurality of pixels (that is, a plurality of photodiodes 100), and further includes any one or all of the FD portion 101, the reset transistor 103, the readout transistor 104, and the selection transistor 105.
  • a structure shared by two pixel cells, a so-called multi-pixel one-cell structure can be used. That is, in the pixel cell 10 of FIG.
  • one reset transistor 103, one readout transistor 104, and one selection transistor 105 are provided corresponding to one pixel (that is, the photodiode 100), but in a plurality of adjacent pixel cells. If the reset transistor 103, the readout transistor 104, and the selection transistor 105 are shared, the number of transistors per pixel can be substantially reduced.
  • a pixel has a structure in which a pixel is formed on the surface of a semiconductor substrate, that is, on the same side as a surface on which a gate terminal and a wiring of a transistor are formed, and the pixel is on the back surface of the semiconductor substrate, that is, a transistor.
  • a so-called back-illuminated image sensor (back-illuminated solid-state imaging device) structure formed on the back surface side with respect to the surface on which the gate terminal and the wiring are formed can also be used.
  • an image sensor structure using a photoelectric conversion film (a photoelectric conversion film using an organic material as an example) can be used.
  • FIG. 8B is a cross-sectional view showing another configuration example of the pixel cell according to Embodiment 1.
  • the pixel cell in FIG. 8B includes a semiconductor substrate 801, a gate electrode 802, a contact plug 803, a wiring layer 807, a photoelectric conversion film 110, a color filter 812, and an on-chip lens 813.
  • the FD portion 101 is provided in the semiconductor substrate 801 and is electrically connected to the pixel electrode 808 via the contact plug 803.
  • the photoelectric conversion layer 809 When the photoelectric conversion layer 809 is irradiated with light and a bias potential is applied between the transparent electrode 810 and the pixel electrode 808, an electric field is generated, and one of positive and negative charges generated by the photoelectric conversion is a pixel.
  • the collected charges collected by the electrode 808 are accumulated in the FD unit 101. Reading out the charges accumulated in the FD unit 101 is basically the same as the photodiode type in FIG.
  • FIG. 8B shows an example of a pixel circuit without a transfer transistor, a transfer transistor can also be used.
  • V ref is a reference potential, but it can also be a potential output from the pixel cell when there is no light irradiation.
  • D1_rst is ⁇ 0, 0, 0, 0 ⁇
  • V sh at time t28 is also V rst , so the operation from time t21 to time t28 is performed. May be omitted.
  • the solid-state imaging device has a photoelectric conversion unit that converts an optical signal into an electrical signal, and includes a plurality of pixel cells 10 arranged in the X direction and the Y direction, and a plurality of pixel cells 10.
  • a plurality of vertical signal lines 11 connected to the pixel cell 10 and arranged in the X direction for transmitting electrical signals as analog signals, and connected to the plurality of vertical signal lines 11 in the X direction for converting analog signals into digital signals.
  • a plurality of AD converters 40 arranged, and the AD converter 40 includes a first AD converter circuit 41 having a first comparator 404 and a second AD converter having a second comparator 405.
  • the first AD converter circuit 41 uses the first comparator 404 to narrow the range including the potential of the analog signal by a binary search, and based on the result of the binary search, signal
  • the second AD converter circuit 42 performs a first AD conversion for generating a first digital signal that is a higher-order part, and the second AD converter circuit 42 compares the magnitude relationship between the narrowed analog signal and the RAMP signal. By measuring the time until the output of 405 is inverted, the second AD conversion for generating the second digital signal which is the remaining lower side portion of the digital signal is performed.
  • the first comparator 404 is faster than the second comparator 405, and the second comparator 405 may be more resistant to noise mixing than the first comparator 404.
  • the first AD converter circuit 41 narrows down the range including the potential of the analog signal by the binary search based on the output of the first comparator 404, and the first digital circuit based on the result of the binary search.
  • the second AD converter circuit 42 includes a first control circuit 406 that performs control to generate a signal, and measures the time until the output of the second comparator 405 is inverted.
  • a second control circuit 407 that performs control to generate two digital signals may be provided.
  • the first AD converter circuit 41 includes a plurality of capacitors 400_1 to 400_N coupled to the first node n1, and a first switch 401 disposed between the vertical signal line 11 and the first node n1. Are connected to the first signal line S1 having the first potential V1, the second signal line S2 having the second potential V2, and the plurality of capacitors 400_1 to 400_N.
  • Second comparator 405 , A ramp signal line 413 connected to the second comparator 450 and a second control circuit 407 connected to the output of the second comparator 405, and the plurality of capacitors 400_1 to 400_N include A potential corresponding to an analog signal may be held via one switch 401.
  • the individual imaging apparatus may perform the second AD conversion after performing the first AD conversion.
  • first comparator 404 and the second comparator 405 may have different configurations.
  • the first comparator 404 may be a latch-type comparison circuit.
  • the first comparator 404 may be a chopper type comparison circuit.
  • the second comparator 405 may be a differential amplification type comparison circuit.
  • the photoelectric conversion unit may have a photoelectric conversion film.
  • Embodiment 2 A solid-state imaging device according to Embodiment 2 will be described with reference to FIGS. 9 and 10.
  • FIG. 9 is a diagram illustrating a configuration example of the solid-state imaging device according to the second embodiment.
  • the solid-state imaging device of FIG. 9 is different from the solid-state imaging device of FIG. 1 in that an AD conversion unit 140 is provided instead of the AD conversion unit 40 in the AD unit 4.
  • an AD conversion unit 140 is provided instead of the AD conversion unit 40 in the AD unit 4.
  • FIG. 10 is a diagram illustrating a configuration example of the AD conversion unit 140 according to the present embodiment.
  • the AD conversion unit 140 of FIG. 10 is different from the AD conversion unit 40 of FIG. 3 in that a third switch 409 is added.
  • the third switch 409 is inserted between the first node n1 and the second comparator 405, and propagates the potential of the first node n1 to the second comparator 405 when in the on state. At this time, the second comparator 405 and the first node n1 are disconnected.
  • the second comparator compares the magnitude relationship between the potential of the first node n1 and the potential of the RAMP signal at least when the third switch is in the ON state, and outputs the result to the second control circuit.
  • the operation of the solid-state imaging device according to the present embodiment is substantially the same as FIGS. 4, 5 and 6 shown as the operation timing charts of the solid-state imaging device of the first embodiment, but in FIG.
  • the third switch 409 is turned off.
  • the wiring load for connection to the second comparator 405 is disconnected.
  • the column circuit of the solid-state imaging device is generally on the order of several ⁇ m, the wiring is often long and the wiring load is often large.
  • the time required for the first AD conversion can be shortened, higher-speed AD conversion can be realized, and high image quality and a high frame rate can be realized.
  • the pixel cell 10 in FIG. 9 may not have a one-pixel one-cell structure, but may have a multi-pixel one-cell structure.
  • the solid-state imaging device of FIG. 9 can be a back-illuminated solid-state imaging device.
  • the pixel cell 10 in FIG. 9 may use the structure of an image sensor using a photoelectric conversion film (a photoelectric conversion film using an organic material as an example) shown in FIGS. 8A and 8B.
  • a photoelectric conversion film a photoelectric conversion film using an organic material as an example
  • the first AD converter circuit 41 includes the plurality of capacitors 400_1 to 400_N coupled to the first node n1, the vertical signal line 11, and the first signal line.
  • a first switch 401 disposed between the nodes n1, a first signal line S1 having a first potential, a second signal line S2 having a second potential, and a plurality of capacitors 400_1 to 400_N.
  • a plurality of second switches 408_1 to 408_N that are connected to select the first signal line S1 or the second signal line S2 and connect to the capacitors 400_1 to 400_N, and a first node connected to the first node n1.
  • the second AD converter circuit 42 includes a second comparator 405 connected to the first node n1 via the third switch 409, a ramp signal line 413 connected to the second comparator, And a second control circuit 407 connected to the output of the comparator 405, and the first node n 1 holds a potential corresponding to the analog signal through the first switch 401.
  • the wiring load parasitic on the first node n1 is reduced, and the first node n1 due to the operation of the second switch is reduced.
  • the potential change becomes faster. That is, the first AD conversion can be made faster.
  • the third switch 409 may electrically disconnect the first node n1 and the second comparator 405 during the first AD conversion.
  • Embodiment 3 A solid-state imaging device according to Embodiment 3 will be described with reference to FIGS. 11 and 12.
  • FIG. 11 is a diagram illustrating a configuration example of the solid-state imaging device according to the third embodiment.
  • the solid-state imaging device of FIG. 11 is different from the solid-state imaging device of FIG. 1 in that an AD conversion unit 240 is provided instead of the AD conversion unit 40 in the AD unit 4.
  • AD conversion unit 240 is provided instead of the AD conversion unit 40 in the AD unit 4.
  • FIG. 12 is a diagram illustrating a configuration example of the AD conversion unit 240 according to the third embodiment.
  • the AD converter 240 in FIG. 12 is different from the AD converter 40 in FIG. 3 in that a buffer circuit 411 is added.
  • the buffer circuit 411 is inserted between the first node n1 and the first comparator 404 and the second comparator 405, and buffers the analog signal held in the first node n1 for the first. To the second comparator 404 and the second comparator 405.
  • the first comparator 404 is connected to the buffer circuit 411, compares the magnitude relationship between the output of the buffer circuit 411 and the reference potential, and outputs the result to the first control circuit 406.
  • the second comparator 405 is connected to the buffer circuit 411, compares the potential of the signal output from the buffer circuit 411 and the potential of the RAMP signal, and outputs the result to the second control circuit 407. .
  • the second control circuit 407 measures the time until the magnitude relationship between the potential of the signal output from the buffer circuit 411 and the potential of the RAMP signal is switched, and generates a second digital signal corresponding to the measured time. .
  • the operation of the solid-state imaging device according to the present embodiment is the same as that of FIGS. 4, 5, and 6 shown as the operation timing chart of the solid-state imaging device of the first embodiment.
  • the buffer circuit 411 is arranged between the first comparator 404 and the second comparator 405, the capacitive load parasitic on the first node n1 is significantly reduced.
  • the capacitive load parasitic on the first node n1 not only increases the time required for the first AD conversion, but also causes an error in the ratio of the capacitance at the time of switching the capacitance during the first AD conversion. This is a factor that hinders the improvement of accuracy.
  • the capacitive load parasitic on the first node n1 is reduced, so that the error of the capacitance ratio at the time of capacitance switching can be reduced, and the AD conversion can be highly accurate.
  • this embodiment can reduce an error during the first AD conversion, can realize a high-precision AD conversion, and can realize an image sensor with a high image quality and a high frame rate.
  • a third switch 409 is provided between the buffer circuit 411 and the second comparator 405, and the third switch 409 is controlled to be turned off during the first AD conversion. Also good.
  • the buffer circuit 411 may be configured by a source follower circuit as shown in FIG.
  • the solid-state imaging device includes the buffer circuit 411 between the first node n1 and the second comparator 405.
  • the wiring load of the second comparator from the first node n1 is reduced by the presence of the buffer circuit 411 during the first AD conversion, the wiring load parasitic on the first node n1 is small.
  • the first AD conversion can be made faster.
  • a buffer circuit 411 may be provided between the first node n1 and the third switch 409.
  • the buffer circuit 411 may be a source follower circuit.
  • FIG. 15 shows an example of the configuration of a camera system including a solid-state imaging device according to the fourth embodiment.
  • This camera system includes an optical system 231, a solid-state imaging device 232, and a system controller 234.
  • the optical system 231 includes one or more lenses.
  • the solid-state imaging device 232 is the solid-state imaging device according to any one of the first to third embodiments described above.
  • the signal processing unit 233 performs signal processing on the data taken by the solid-state imaging device 232 and outputs it as an image or data.
  • the system controller 234 controls the solid-state imaging device 232 and the signal processing unit 233.
  • the camera system according to the present embodiment uses the solid-state imaging device according to any one of the above-described embodiments (Embodiments 1 to 3), thereby realizing high-speed AD conversion while suppressing noise, and achieving a high frame Capable of rate and high image quality. Therefore, high-speed and high-accuracy sensor imaging can be performed, and as a result, a camera system with good image characteristics can be provided.
  • the camera system according to the fourth embodiment includes any one of the solid-state imaging devices described in the first to third embodiments.
  • high-speed AD conversion can be realized while suppressing noise, and high frame rate and high image quality imaging can be performed.
  • the present disclosure can be suitably used for a solid-state imaging device and a camera.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Analogue/Digital Conversion (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention concerne un dispositif d'imagerie à semi-conducteurs comportant un premier circuit de conversion analogique-numérique (41) et un deuxième circuit de conversion analogique-numérique (42) dans chaque rangée. Le premier circuit de conversion analogique-numérique utilise un premier comparateur (404) pour rétrécir, au moyen d'une recherche binaire, la plage dans laquelle la tension d'un signal analogique est incluse, et effectue une première conversion analogique-numérique pour générer un premier signal numérique, c'est-à-dire une partie d'ordre élevé d'un signal numérique, en fonction du résultat de la recherche binaire. Le deuxième circuit de conversion analogique-numérique (42) effectue une deuxième conversion analogique-numérique pour générer un deuxième signal numérique, c'est-à-dire la partie d'ordre faible restante du signal numérique, en mesurant le temps jusqu'à l'émission en sortie d'un deuxième comparateur (405) pour comparer la relation d'amplitude entre un signal RAMP et les inversions de signaux analogiques réduits.
PCT/JP2018/007107 2017-03-08 2018-02-27 Dispositif d'imagerie à semi-conducteurs et système de caméra qui utilise celui-ci Ceased WO2018163896A1 (fr)

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WO2011093225A1 (fr) 2010-01-26 2011-08-04 国立大学法人静岡大学 Dispositif d'imagerie à semi-conducteurs et procédé de lecture de signaux de matrice de pixels de dispositif d'imagerie à semi-conducteurs
JP5500660B2 (ja) 2012-01-23 2014-05-21 国立大学法人東北大学 固体撮像装置
JP6089461B2 (ja) * 2012-06-22 2017-03-08 セイコーエプソン株式会社 プロジェクター、画像表示システム、プロジェクターの制御方法
JP6021626B2 (ja) * 2012-12-14 2016-11-09 キヤノン株式会社 撮像装置の駆動方法、撮像装置、撮像システム
JP6478488B2 (ja) * 2014-06-18 2019-03-06 キヤノン株式会社 Ａｄ変換装置及び固体撮像装置

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JP2010258817A (ja) * 2009-04-24 2010-11-11 Sony Corp 積分型ａｄ変換装置、固体撮像素子、およびカメラシステム
WO2013002957A2 (fr) * 2011-06-30 2013-01-03 Intel Corporation Convertisseur analogique-numérique à deux étages utilisant un sar et un tdc
JP2014007527A (ja) * 2012-06-22 2014-01-16 Canon Inc 固体撮像装置

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