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WO2018161624A1 - Substrat de réseau, son procédé de fabrication, transistor d'attaque et panneau d'affichage - Google Patents

Substrat de réseau, son procédé de fabrication, transistor d'attaque et panneau d'affichage Download PDF

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Publication number
WO2018161624A1
WO2018161624A1 PCT/CN2017/109284 CN2017109284W WO2018161624A1 WO 2018161624 A1 WO2018161624 A1 WO 2018161624A1 CN 2017109284 W CN2017109284 W CN 2017109284W WO 2018161624 A1 WO2018161624 A1 WO 2018161624A1
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Prior art keywords
active medium
gate insulating
pattern
grain size
substrate
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Ceased
Application number
PCT/CN2017/109284
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English (en)
Inventor
Wenqing Xu
Mingxuan Liu
Jing Wang
Xiaoxiang Zhang
Huibin GUO
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP17861198.4A priority Critical patent/EP3596753B1/fr
Priority to JP2018523816A priority patent/JP7001590B2/ja
Priority to US15/769,492 priority patent/US10644035B2/en
Publication of WO2018161624A1 publication Critical patent/WO2018161624A1/fr
Anticipated expiration legal-status Critical
Priority to US16/809,794 priority patent/US10943927B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

Definitions

  • the present disclosure generally relates to the field of display technologies and, more particularly, to an array substrate, a fabrication method thereof, a driving transistor, and a display panel.
  • An organic light-emitting diode (OLED) display panel includes an array substrate.
  • An array substrate includes a substrate, and a plurality of pixel regions disposed over the substrate and arranged in an array.
  • Each pixel region includes an OLED, and a pixel circuit for controlling the OLED such that the OLED emits light.
  • the pixel circuit may include a switching transistor and a driving transistor coupled to a control integrated circuit (IC) .
  • IC control integrated circuit
  • the control IC can input turn-on voltages to the switching transistor and the driving transistor, thereby turning on the switching transistor and the driving transistor.
  • the control IC can input a driving voltage to a source electrode of the driving transistor, and the driving transistor can input a driving current to the OLED according to the driving voltage.
  • the driving current of a driving transistor is related to the threshold voltage of the driving transistor. Thus, when two driving transistors have different threshold voltages, the two driving transistors may provide different driving currents under the same driving voltage.
  • the present disclosure provides an array substrate.
  • the array substrate includes a pixel circuit and a light-emitting diode coupled to the pixel circuit.
  • the pixel circuit includes a driving transistor and a switching transistor.
  • the driving transistor includes a first active medium made of polysilicon.
  • the first active medium has a first grain size.
  • the switching transistor includes a second active medium made of polysilicon.
  • the second active medium has a second grain size larger than the first grain size.
  • the driving transistor further includes a first gate electrode, a first source electrode and a first drain electrode, and a first gate insulating block.
  • the switching transistor further includes a second gate electrode, a second source electrode and a second drain electrode, and a second gate insulating block. A thickness of the first gate insulating block is larger than a thickness of the second gate insulating block.
  • the array substrate further includes a substrate and a buffer layer over the substrate.
  • the pixel circuit is over the buffer layer.
  • the light-emitting diode includes an organic light-emitting diode.
  • the method includes fabricating a pixel circuit and fabricating an organic light-emitting diode coupled to the pixel circuit.
  • the pixel circuit includes a driving transistor and a switching transistor.
  • the driving transistor includes a first active medium made of polysilicon.
  • the first active medium has a first grain size.
  • the switching transistor includes a second active medium made of polysilicon.
  • the second active medium has a second grain size larger than the first grain size.
  • fabricating the pixel circuit includes forming an amorphous silicon layer over a substrate; forming a gate insulating layer over the amorphous silicon layer; forming a preset pattern over the gate insulating layer, where an orthogonal projection of the preset pattern on the substrate overlaps an orthogonal projection of the first active medium on the substrate and does not overlap with an orthogonal projection of the second active medium on the substrate; performing laser annealing to turn the amorphous silicon layer into a polysilicon layer; removing the preset pattern; and forming the driving transistor and the switching transistor based on the polysilicon layer and the gate insulating layer.
  • forming the driving transistor and the switching transistor includes patterning the polysilicon layer and the gate insulating layer to form a polysilicon pattern and a gate insulating pattern, where a polysilicon pattern includes the first active medium and the second active medium, and a gate insulating pattern includes a first gate insulating block stacked over the first active medium and a second gate insulating block stacked over the second active medium; forming a gate electrode pattern over the gate insulating pattern, where the gate electrode pattern includes a first gate electrode stacked over the first gate insulating block and a second gate electrode stacked over the second gate insulating block; forming an interlayer insulating layer over the gate electrode pattern; and forming a source/drain electrode pattern over the interlayer insulating layer.
  • the source/drain electrode pattern includes a first source electrode and a first drain electrode coupled to the first active medium, and a second source electrode and a second drain electrode coupled to the second active medium.
  • the driving transistor includes the first gate electrode, the first source electrode, the first drain electrode, and the first active medium.
  • the switching transistor includes the second gate electrode, the second source electrode, the second drain electrode, and the second active medium.
  • removing the preset pattern includes applying a preset etching solution capable of etching the preset pattern and the gate insulating layer to remove the preset pattern and reduce a thickness of a region of the gate insulating layer not covered by the preset pattern.
  • the method further includes, before forming the interlayer insulating layer, doping portions of the polysilicon pattern.
  • forming the source/drain electrode pattern includes forming the first source electrode and the first drain electrode to be coupled to doped regions in the first active medium, and forming the second source electrode and the second drain electrode to be coupled to doped regions in the second active medium.
  • forming the preset pattern includes forming an amorphous silicon pattern.
  • forming the amorphous silicon layer includes forming an amorphous silicon layer having a thickness of approximately 500 angstroms.
  • Forming the amorphous silicon pattern includes forming an amorphous silicon pattern having a thickness in a range from approximately 100 angstroms to approximately 200 angstroms.
  • an orthogonal projection region of an un-doped region of the first active medium on the substrate overlaps an orthogonal projection region of the first gate electrode on the substrate.
  • An orthogonal projection region of an un-doped region of the second active medium on the substrate overlaps an orthogonal projection region of the second gate electrode on the substrate.
  • the method further includes, before fabricating the pixel circuit, forming a buffer layer over the substrate. Fabricating the pixel circuit includes fabricating the pixel circuit over the buffer layer.
  • the driving transistor includes a first active medium having a smaller grain size than a second active medium of a switching transistor.
  • the first active medium and the second active medium are polysilicon.
  • the driving transistor further includes a first gate insulating block, a first gate electrode, a first source electrode, and a first drain electrode.
  • the first gate insulating block is over the first active medium, and has a greater thickness than a second gate insulating block in the switching transistor.
  • the first gate electrode is over the first gate insulating block.
  • the first source electrode and a first drain electrode are over the first active medium and electrically coupled to the first active medium.
  • Another aspect of the present disclosure provides a display panel including an array substrate.
  • FIG. 1A illustrates a schematic view of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 1B illustrates schematic views showing two exemplary grain sizes according to various disclosed embodiments of the present disclosure
  • FIG. 1C illustrates a schematic view of an exemplary display panel according to various disclosed embodiments of the present disclosure
  • FIG. 2 illustrates a flow chart of an exemplary fabrication method for an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 3 illustrates a flow chart of another exemplary fabrication method for an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 4 illustrates a schematic view of an exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 5 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 6 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 7 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 8 illustrates a schematic view of exemplary laser annealing according to various disclosed embodiments of the present disclosure
  • FIG. 9 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure.
  • FIG. 10 illustrates a flow chart of an exemplary fabrication method for an exemplary driving transistor and an exemplary switching transistor according to various disclosed embodiments of the present disclosure
  • FIG. 11 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 12 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 13 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure
  • FIG. 14 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure.
  • FIG. 15 illustrates a schematic view of another exemplary local structure of an exemplary array substrate according to various disclosed embodiments of the present disclosure.
  • FIG. 1A illustrates a schematic view of an exemplary array substrate 100 according to various disclosed embodiments of the present disclosure.
  • the array substrate 100 includes a pixel circuit and an organic light-emitting diode (OLED) 02 (one electrode of the OLED 02 is shown in FIG. 1A) .
  • the pixel circuit includes a driving transistor and a switching transistor.
  • the driving transistor includes a first active medium A1, and the switching transistor includes a second active medium A2.
  • Both the first active medium A1 and the second active medium A2 may be polysilicon.
  • the grain size of the first active medium Al may be smaller than the grain size of the second active medium A2, where the grain size of the first active medium Al refers to the size of the grains in the first active medium, and the grain size of the second active medium A2 refers to the size of the grains in the second active medium.
  • both the first active medium in the driving transistor and the second active medium in the switching transistor may be polysilicon.
  • the first active medium may have a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor is smaller than the standard size. Further, a smaller grain size in the driving transistors can result in a less significant non-uniformity of the threshold voltages in the driving transistors caused by the non-uniform grain sizes.
  • the driving currents inputted to OLEDs from driving transistors of the OLED display panel may tend to be the same. Accordingly, the brightness of the light emitted from each pixel region may tend to be the same, and the display performance of the OLED display panel can be improved.
  • the polysilicon may be low temperature polysilicon.
  • FIG. 1B illustrates schematic views showing two exemplary grain sizes according to various disclosed embodiments of the present disclosure. As shown in FIG. 1B, the grain size of polysilicon 1210 is larger and hence less uniform, and the grain size of polysilicon 1220 is smaller and hence more uniform.
  • the driving transistor further includes a first gate electrode B1, first source/drain electrodes C1 (i.e. a first source electrode and a first drain electrode) , and a first gate insulating block D1.
  • the switching transistor includes a second gate electrode B2, second source/drain electrodes C2 (i.e. a second source electrode and a second drain electrode) , and a second gate insulating block D2.
  • the first gate insulating block D1 has a greater thickness than the second gate insulating block D2. A thicker gate insulating block in a transistor can result in a larger subthreshold swing (SS) coefficient of the transistor.
  • SS subthreshold swing
  • the driving transistor may need to have a greater SS coefficient than the switching transistor.
  • the thickness of the first gate insulating block D1 in the driving transistor may be set to be greater than the thickness of the second gate insulating block D2 in the switching transistor.
  • a thickness H1 of the gate insulating block D1 below the first gate electrode B1 is greater than a thickness H2 of the gate insulating block D2 below the second gate electrode B2.
  • the array substrate 100 further includes an interlayer insulating layer 012.
  • the first source/drain electrodes C1 are coupled to the first active medium A1 through via holes in the interlayer insulating layer 012.
  • the second source/drain electrodes C2 are coupled to the second active medium A2 through via holes in the interlayer insulating layer 012.
  • a flat layer 014 is formed over the first source/drain electrodes C1 and the second source/drain electrodes C2.
  • the OLED 02 is formed over the flat layer 014.
  • the OLED 02 is coupled to the pixel circuit through a via hole in the flat layer 014.
  • the array substrate 100 includes a substrate 03 and a buffer layer 04 disposed over the substrate 03.
  • the pixel circuit is disposed over the substrate 03 over which the buffer layer 04 has been disposed. That is, in some embodiments, prior to fabricating the pixel circuit, the buffer layer 04 may be formed over the substrate 03 to reduce the influence of impurities, which may be present on the surface of the substrate 03, on the pixel circuit.
  • the OLED 02 may be disposed directly on the substrate 03. In some other embodiments, the OLED 02 may be disposed over the buffer layer 04 which is above the substrate 03.
  • the uniformity of threshold voltage of multiple polysilicon transistors may be positively correlated with the uniformity of the grain size of the active medium (polysilicon) in the polysilicon transistors, i.e., a more uniform grain size in the active medium across the multiple polysilicon transistors may result in a more uniform threshold voltage across the multiple polysilicon transistors.
  • the magnitude of the grain size of the polycrystalline silicon may be negatively correlated with the uniformity of the grain size of the polycrystalline silicon.
  • the magnitude of the grain size of the polycrystalline silicon may also be positively correlated with the magnitude of the on-state current of a transistor.
  • the switching transistor may need to have a relatively large on-state current, and hence may need a relatively large grain size in the active medium.
  • a grain size of an active medium in a switching transistor may be approximately equal to a grain size of an active medium in a driving transistor.
  • the relatively large grain size of the active medium can allow the switching transistor to have a relatively large on-state current, but also may cause the grain size of the active medium in the driving transistor to be relatively non-uniform. Accordingly, the non-uniformity of the grain size of the active medium in the driving transistor may cause a relatively large non-uniformity in threshold voltage.
  • the grain size of the second active medium of the switching transistor may be smaller than the standard size.
  • the grain size may be more uniform. Accordingly, non-uniformity of the threshold voltage of the driving transistors caused by the non-uniformity of the grain size may be less significant.
  • the driving current provided by the driving transistor under a driving voltage may be related to the threshold voltage of the driving transistor. When the threshold voltages of two driving transistors are similar, the driving currents provided by the two driving transistors under the same driving voltages may be similar. Consequently, in the display panel, the driving currents provided by the driving transistors to OLEDs may tend to be the same.
  • the grain size of the second active medium in the switching transistor consistent with the disclosure may be approximately equal to a grain size of an active medium in a switching transistor in the conventional technologies. In some other embodiments, the grain size of the second active medium in the switching transistor consistent with the disclosure may not be equal to the grain size of the active medium in the switching transistor in the conventional technologies. In embodiments of the present disclosure, the grain size of the second active medium in the switching transistor consistent with the disclosure is not restricted, and may be selected according to various application scenarios. Further, in embodiments of the present disclosure, the grain size of the second active medium in the switching transistor does not have to be equal to the grain size of the first active medium. Thus, a second active medium having a relatively large grain size may be selected as needed, thereby ensuring a relatively large on-state current in the switching transistor.
  • the first active medium in the driving transistor and the second active medium in the switching transistor may both be polysilicon, and the grain size of the first active medium may be smaller than the grain size of the second active medium. That is, when the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size in the driving transistors is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain sizes may be smaller. As a result, in the OLED display panel, driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.
  • the driving transistor may be a driving transistor as shown in FIG. 1A.
  • the driving transistor includes the first active medium A1 which can include polysilicon.
  • the first active medium A1 may have a smaller grain size than the second active medium A2 in the switching transistor formed by polysilicon.
  • the driving transistor further includes the first gate electrode B1, the first source/drain electrodes C1 (i.e., the first source electrode and the first drain electrode) , and the first gate insulating block D1.
  • the first gate insulating block D1 may have a greater thickness than the second gate insulating block D2 in the switching transistor.
  • the first active medium of the driving transistor may include polysilicon, similar to the second active medium of the switching transistor.
  • the grain size of the first active medium may be smaller than the grain size of the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of the threshold voltages in driving transistors caused by non-uniform grain size may be smaller.
  • driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.
  • FIG. 1C illustrates a schematic view of an exemplary display panel 130 according to various disclosed embodiments of the present disclosure.
  • the display panel 130 includes an array substrate 132.
  • the array substrate 132 can be any array substrate consistent with the disclosure, such as the array substrate 100 shown in FIG. 1A.
  • the display panel 130 may form a display device, alone or together with one or more other appropriate structures.
  • the display device including the display panel may be an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any suitable product or component having a display function. Any display panel including an array substrate consistent with the disclosure is within the scope of the present disclosure.
  • the first active medium in the driving transistor and the second active medium in the switching transistor may both be polysilicon. Further, the first active medium may have a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain size may be smaller. As a result, in the OLED display panel, driving currents provided by driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, thereby improving the display performance of the OLED display panel.
  • FIG. 2 illustrates a flow chart of an exemplary fabrication method 2000 for an exemplary array substrate according to various disclosed embodiments of the present disclosure.
  • the exemplary fabrication method 2000 for the exemplary array substrate will be described with reference to FIG. 2.
  • a pixel circuit is fabricated.
  • an OLED is fabricated.
  • the OLED is coupled to the pixel circuit.
  • the pixel circuit may include a driving transistor and a switching transistor.
  • the driving transistor may include a first active medium
  • the switching transistor may include a second active medium.
  • the first active medium and the second active medium may both be polysilicon.
  • the first active medium may have a smaller grain size than the second active medium.
  • the first active medium in the driving transistor and the second active medium in the switching transistor may both be polysilicon, and the first active medium may have a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain sizes may be smaller. As a result, in the OLED display panel including the array substrate, driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.
  • FIG. 3 illustrates a flow chart of another exemplary fabrication method 3000 for an exemplary array substrate according to various disclosed embodiments of the present disclosure.
  • the exemplary fabrication method 3000 for the exemplary array substrate will be described in detail.
  • a buffer layer is formed over the substrate.
  • the substrate before the buffer layer is formed, the substrate can be cleaned to minimize impurities on the substrate as much as possible. After the cleaning, a buffer layer 04 as shown in FIG. 4 is formed over the substrate 03.
  • the buffer layer 04 is cleaner, containing less impurities.
  • the impurities on the buffer layer may have less influence on the pixel circuit.
  • an amorphous silicon layer is formed over the substrate over which the buffer layer has been formed.
  • the pixel circuit can be further fabricated over the buffer layer.
  • an amorphous silicon layer 05 is formed over the substrate 03 over which the buffer layer 04 has been formed.
  • the amorphous silicon layer 05 may have a thickness of approximately 500 angstroms.
  • the amorphous silicon layer 05 may be deposited over the substrate 03 by coating, magnetron sputtering, thermal evaporation, plasma enhanced chemical vapor deposition (PECVD) , or another appropriate method.
  • PECVD plasma enhanced chemical vapor deposition
  • a gate insulating layer is formed over the substrate over which the amorphous silicon layer has been formed.
  • a gate insulating layer 06 is formed over the substrate 03 over which the amorphous silicon layer 05 has been formed.
  • a preset pattern is formed over the substrate over which the gate insulating layer has been formed.
  • a preset pattern 07 is formed over the substrate 03 over which the gate insulating layer has been formed.
  • an orthogonal projection region of the preset pattern 07 on the substrate 03 is a preset region X. Because the thickness of the preset pattern 07 is non-zero, the absorbance of the preset pattern 07 of a laser can be greater than zero.
  • the material of the preset pattern 07 may include amorphous silicon, the preset pattern 07 can be an amorphous silicon pattern, and a thickness of the amorphous silicon pattern can range from approximately 100 angstroms to approximately 200 angstroms.
  • an amorphous silicon material layer can be deposited over the substrate 03 by coating, magnetron sputtering, thermal evaporation, PECVD, or another appropriate method and, then, the amorphous silicon material layer can be processed by a patterning process to obtain the amorphous silicon pattern 07.
  • the patterning process may include: photoresist coating, exposure, development, etching, and photoresist peeling.
  • the processing of the amorphous silicon material layer by the patterning process may include: coating a layer of photoresist over the amorphous silicon material layer; exposing the photoresist using a mask to form at least one fully exposed region and at least one non-exposed region; subsequently processing using a development process, such that the photoresist of the at least one fully exposed region is removed and the photoresist of the at least one non-exposed region is retained; etching away the portion of the amorphous silicon material layer corresponding to the at least one fully exposed region; and peeling off the photoresist of the at least one non-exposed region to obtain an amorphous silicon pattern after completing the etching.
  • the substrate over which the preset pattern has been formed is annealed by laser annealing, such that the amorphous silicon layer can turn into a polysilicon layer.
  • the substrate 03 over which the preset pattern 07 has been formed can be annealed by laser annealing, such that the amorphous silicon layer 05 formed at 302 can turn into a polysilicon layer 08 under the influence of laser.
  • the laser annealing can include excimer laser annealing (ELA) .
  • the polysilicon layer 08 includes a first region Y1 and a second region Y2.
  • An orthogonal projection region of the first region Y1 on the substrate 03 may be the preset region X, and an orthogonal projection region of the second region Y2 on the substrate 03 may be located outside the preset area X.
  • the preset pattern 07 may cover the first region Y1.
  • the preset pattern 07 may be capable of absorbing a portion of the laser that will irradiate the first region Y1.
  • the first region Y1 may absorb less laser energy
  • the second region Y2 may absorb more laser energy.
  • An amorphous silicon region absorbing less laser energy may turn into a polysilicon region having a smaller grain size.
  • the first region Y1 may have a smaller grain size than the second region Y2.
  • the amount of laser energy absorbed by the first region Y1 may be changed by adjusting the thickness of the preset pattern and thereby changing the extent of laser absorption of the preset pattern. Accordingly, the grain size of the first region Y1 may be changed.
  • the first active medium in the driving transistor and the second active medium in the switching transistor which need to be formed later can both be located in the polysilicon layer. And an orthogonal projection of the first active medium on the substrate can be located in the preset region, and an orthogonal projection of the second active medium on the substrate can be located outside the preset region.
  • the preset pattern is removed.
  • the preset pattern 07 can be removed.
  • a preset etching solution that can etch both the preset pattern 07 and the gate insulating layer 06 can be used to remove the preset pattern 07. That is, the preset etching solution can react chemically with the preset pattern 07 and the gate insulating layer 06.
  • the preset etching solution can be applied to the substrate 03 after laser annealing. As a result, the preset pattern 07 can be completely removed and, the region in the gate insulating layer 06 not covered by the preset pattern 07 in FIG. 7 can be thinned to obtain the structure shown in FIG. 9.
  • the gate insulating layer 06 includes a third region Y3 and a fourth region Y4.
  • An orthogonal projection region of the third region Y3 on the substrate 03 may be the preset region X, and an orthogonal projection region of the fourth region Y4 on the substrate may be located outside the preset area X.
  • the thickness H1 of the third region Y3 may be greater than the thickness H2 of the fourth region Y4.
  • the substrate is processed to form a driving transistor and a switching transistor.
  • the substrate is processed by patterning to obtain a polysilicon pattern and a gate insulating pattern.
  • the substrate is processed by patterning, such that a portion of the polysilicon layer 08 is removed to form the polysilicon pattern 09, and a portion of the gate insulating layer 06 is removed to form a gate insulating pattern 010.
  • the polysilicon pattern 09 includes the first active medium A1 and the second active medium A2.
  • the gate insulating pattern 010 includes the first gate insulating block D1 stacked over the first active medium A1, and the second gate insulating block D2 stacked over the second active medium A2.
  • a gate electrode pattern is formed over the substrate over which the gate insulating pattern has been formed.
  • a gate electrode pattern 011 is formed over the substrate 03 over which the gate insulating pattern 010 has been formed.
  • the gate electrode pattern 011 includes the first gate electrode B1 stacked over the first gate insulating block D1, and the second gate electrode B2 stacked over the second gate insulating block D2.
  • a gate electrode material layer may be deposited over the substrate 03 by coating, magnetron sputtering, thermal evaporation, PECVD, or another appropriate method and then the gate electrode material layer may be processed by a patterning process to obtain the gate electrode pattern 011.
  • the patterning process may include: photoresist coating, exposure, development, etching, and photoresist peeling.
  • the processing of the gate electrode material layer using the patterning process may include: coating a layer of photoresist over the gate electrode material layer; exposing the photoresist using a mask to form at least one fully exposed region and at least one non-exposed region; subsequently processing using a development process, such that the photoresist of the at least one fully exposed region is removed, and the photoresist of the at least one non-exposed region is retained; etching the region of the gate electrode material layer corresponding to the at least one fully exposed region; and peeling off the photoresist of the at least one non-exposed region to obtain the gate electrode pattern 011 after completing the etching.
  • the polysilicon pattern is doped.
  • the first active medium A1 and the second active medium A2 in the polysilicon pattern 09 are doped.
  • an orthogonal projection region of an un-doped region a11 in the first active medium A1 on the substrate 03 can be overlapped with an orthogonal projection region of the first gate electrode B1 on the substrate 03; and doped regions a12 in the first active medium A1 may be regions other than the un-doped region a11.
  • An orthogonal projection region of an un-doped region a21 in the second active medium A2 on the substrate 03 may be overlapped with an orthogonal projection region of the second gate electrode B2 on the substrate 03; and doped regions a22 in the second active medium A2 may be regions other than the un-doped region a21.
  • an interlayer insulating layer is formed over the substrate over which the gate electrode pattern has been formed.
  • an interlayer insulating layer 012 is formed over the substrate 03 over which the gate electrode pattern 011 has been formed.
  • a source/drain electrode pattern is formed over the substrate over which the interlayer insulating layer has been formed.
  • a source/drain electrode pattern 013 is formed over the substrate over which the interlayer insulating layer has been formed.
  • the source/drain electrode pattern 013 includes first source/drain electrodes C1, i.e., a first source electrode and a first drain electrode, and second source/drain electrodes C2, i.e., a second source electrode and a second drain electrode.
  • the first source/drain electrodes C1 are coupled to the first active medium A1 through via holes in the interlayer insulating layer 012, and the second source/drain electrodes C2 are coupled to the second active medium A2 through via holes in the interlayer insulating layer 012.
  • the doped regions a12 in the first active medium Al are coupled to the first source/drain electrodes C1, and the doped regions a22 in the second active medium A2 are coupled to the second source/drain electrode C2.
  • the driving transistor includes the first gate electrode B1, the first source/drain electrodes C1, and the first active medium A1.
  • the switching transistor includes the second gate electrode B1, the second source/drain electrode C1, and the second active medium A2.
  • the first active medium A1 and the second active medium A2 may both be polysilicon.
  • the grain size of the first active medium A1 may be smaller than the grain size of the second active medium A2.
  • the uniformity of threshold voltage of multiple polysilicon transistors may be positively correlated with the uniformity of the grain size of the active medium (polysilicon) in the polysilicon transistors, i.e., a more uniform grain size in the active medium across the multiple polysilicon transistors may result in a more uniform threshold voltage across the multiple polysilicon transistors.
  • the magnitude of the grain size of the polycrystalline silicon may be negatively correlated with the uniformity of the grain size of the polycrystalline silicon.
  • the magnitude of the grain size of the polycrystalline silicon may also be positively correlated with the magnitude of the on-state current of a transistor.
  • the switching transistor may need to have a relatively large on-state current, and hence may need a relatively large grain size in the active medium.
  • a grain size of an active medium in a switching transistor may be approximately equal to a grain size of an active medium in a driving transistor.
  • the relatively large grain size of the active medium can allow the switching transistor to have a relatively large on-state current, but also may cause the grain size of the active medium in the driving transistor to be relatively non-uniform. Accordingly, the non-uniformity of the grain size of the active medium in the driving transistor may cause a relatively large non-uniformity in threshold voltage.
  • the grain size of the second active medium of the switching transistor may be smaller than the standard size.
  • the grain size may be more uniform. Accordingly, non-uniformity of the threshold voltage of the driving transistors caused by the non-uniformity of the grain size may be less significant.
  • the driving current provided by the driving transistor under a driving voltage may be related to the threshold voltage of the driving transistor. When the threshold voltages of two driving transistors are similar, the driving currents provided by the two driving transistors under the same driving voltages may be similar. Consequently, in the display panel, the driving currents provided by the driving transistors to OLEDs may tend to be the same.
  • the grain size of the second active medium in the switching transistor consistent with the disclosure may be approximately equal to a grain size of an active medium in a switching transistor in the conventional technologies. In some other embodiments, the grain size of the second active medium in the switching transistor consistent with the disclosure may not be equal to the grain size of the active medium in the switching transistor in the conventional technologies. In embodiments of the present disclosure, the grain size of the second active medium in the switching transistor consistent with the disclosure is not restricted, and may be selected according to various application scenarios. Further, in embodiments of the present disclosure, the grain size of the second active medium in the switching transistor does not have to be equal to the grain size of the first active medium. Thus, a second active medium having a relatively large grain size may be selected as needed, thereby ensuring a relatively large on-state current in the switching transistor.
  • the first gate insulating block may have a greater thickness than the second gate insulating block.
  • a transistor having a thicker gate insulating block may have a larger subthreshold swing (SS) coefficient.
  • the driving transistor may need to have a greater SS coefficient than the switching transistor.
  • the thickness of the first gate insulating block of the driving transistor may be greater than the thickness of the second gate insulating block of the switching transistor.
  • the thickness of the gate insulating block below the first gate electrode may be greater than the thickness of the gate insulating block below the second gate electrode.
  • an organic light-emitting diode is fabricated, and the organic light-emitting diode is coupled to the pixel circuit.
  • the flat layer 014 is formed over the substrate 03 over which the sour/drain electrode pattern 013 has been formed, and the OLED 02 is formed over the substrate 03 over which the flat layer 014 has been formed (one electrode of the OLED 02 is shown in FIG. 1A) .
  • the OLED 02 is coupled to the pixel circuit through the via hole in the flat layer 014.
  • the first active medium in the driving transistor and the second active medium in the switching transistor may both be polysilicon, and the first active medium may have a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain sizes may be smaller. As a result, in the OLED display panel including the array substrate, driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.
  • the present disclosure provides an array substrate, a fabrication method thereof, a driving transistor, and a display panel.
  • the array substrate may include pixel circuits and organic light-emitting diodes (OLED) .
  • a pixel circuit may include: a driving transistor having a first active medium, and a switching transistor having a second active medium.
  • the first active medium and the second active medium may both be polysilicon.
  • the first active medium may have a smaller grain size than the second active medium.
  • the present disclosure is directed to improving display performance of the OLED display panel.
  • the embodiments of the driving transistor, the pixel circuit, the display panel, and the fabrication method for the array substrate provided by the embodiments of the present disclosure can be referred to each other.
  • the disclosed embodiments and the features of the disclosed embodiments can be combined under conditions without conflicts.
  • Example numbers of the disclosed embodiments of the present disclosure are merely for the illustration and description purposes, and do not represent the merits of the disclosed embodiments.
  • the term “the disclosure, ” “the present disclosure” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the disclosure does not imply a limitation on the invention, and no such limitation is to be inferred.
  • the claims may refer to “first, ” “second, ” etc., followed by a noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may or may not apply to all embodiments of the disclosure. It should be appreciated that variations may be made to the embodiments described by persons skilled in the art without departing from the scope of the present disclosure. Moreover, no element or component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.

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Abstract

Cette invention concerne un substrat de réseau (100), comprenant un circuit de pixels et une diode électroluminescente (02). Le circuit de pixels comprend un transistor d'attaque comprenant un premier milieu actif (A1) fait de polysilicium, et un transistor de commutation comprenant un second milieu actif (A2) fait de polysilicium. Le premier milieu actif (A1) a une première taille de grain. Le second milieu actif (A2) a une seconde taille de grain supérieure à la première taille de grain. La diode électroluminescente (02) est couplée au circuit de pixels.
PCT/CN2017/109284 2017-03-10 2017-11-03 Substrat de réseau, son procédé de fabrication, transistor d'attaque et panneau d'affichage Ceased WO2018161624A1 (fr)

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EP17861198.4A EP3596753B1 (fr) 2017-03-10 2017-11-03 Procédé de fabrication d'un substrat de réseau
JP2018523816A JP7001590B2 (ja) 2017-03-10 2017-11-03 アレイ基板およびその製造方法、駆動用トランジスタ、並びに表示パネル
US15/769,492 US10644035B2 (en) 2017-03-10 2017-11-03 Array substrate, fabrication method thereof, driving transistor and display panel
US16/809,794 US10943927B2 (en) 2017-03-10 2020-03-05 Array substrate, fabrication method thereof, driving transistor and display panel

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US20200203389A1 (en) 2020-06-25
CN108598040A (zh) 2018-09-28
US10943927B2 (en) 2021-03-09
US10644035B2 (en) 2020-05-05
EP3596753B1 (fr) 2024-10-16
EP3596753A1 (fr) 2020-01-22
CN108598040B (zh) 2021-03-16

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