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WO2018161206A1 - Procédé de fabrication d'un transistor à effet de tunnel et procédé de fabrication d'onduleur - Google Patents

Procédé de fabrication d'un transistor à effet de tunnel et procédé de fabrication d'onduleur Download PDF

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Publication number
WO2018161206A1
WO2018161206A1 PCT/CN2017/075717 CN2017075717W WO2018161206A1 WO 2018161206 A1 WO2018161206 A1 WO 2018161206A1 CN 2017075717 W CN2017075717 W CN 2017075717W WO 2018161206 A1 WO2018161206 A1 WO 2018161206A1
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Prior art keywords
region
protective layer
passivation protective
doping
rectangular ring
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PCT/CN2017/075717
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English (en)
Chinese (zh)
Inventor
蔡皓程
徐挽杰
张臣雄
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2017/075717 priority Critical patent/WO2018161206A1/fr
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Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]

Definitions

  • the present application relates to the field of semiconductor devices and, more particularly, to a method of fabricating a tunneling field effect transistor and a method of fabricating an inverter.
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the gate length of MOSFET is reduced to below 45 nm.
  • SS Subthreshold Swing
  • the power consumption of the MOSFET circuit is continuously increased. The energy consumption continues to rise, and the power consumption density of the chip increases sharply, which seriously hinders the application of the chip in system integration.
  • TFET Tunneling Field Effect Transistor
  • the TFET is a gate-controlled reverse-biased P-type doped-intrinsic-n-type doped junction (p-i-n junction) device with opposite source and drain doping types.
  • p-i-n junction P-type doped-intrinsic-n-type doped junction
  • the source region is heavily P-doped and the drain region is heavily doped with N-type;
  • P-type TFETs the source region is heavily doped with N-type and the drain region is doped with P-type.
  • the source and drain doping types are different such that the TFET is formed to be different from the MOSFET's operating mechanism, ie, the carrier quantum tunneling mechanism, which may also be referred to as band tunneling. Due to the different working mechanism of the MOSFET, the subthreshold swing of the TFET is not limited by the carrier thermal distribution. In theory, the TFET can achieve a subthreshold swing of less than 60mV/dec and can operate at a lower driving voltage. The static power consumption of the device can be reduced.
  • the present application provides a method for fabricating a tunneling field effect transistor and a method for fabricating an inverter.
  • a self-aligned process to fabricate a tunneling field effect transistor, a smaller size gate width can be realized by overcoming the limitation of the photolithography process. Good feasibility and repeatability.
  • a method of fabricating a tunneling field effect transistor comprising: fabricating a spindle on a substrate, an axis of the spindle being perpendicular to a first surface of the substrate; Covering the first passivation protective layer on the sidewall surface; a region in the first surface of the substrate not adjacent to the first passivation protective layer in a region not covered by the first passivation protective layer and the main axis Forming a doped region having a first doping type; covering a surface of the first passivation protective layer with a second passivation protective layer; and the doped region is not the second passivation protective layer
  • the covered region forms a source region having a second doping type, the region of the doped region covered by the second passivation protective layer forming a first doping type adjacent to the source region Doping a pocket, the second doping type being opposite to the first doping type; removing the major axis, and forming a drain region having the first doping type on
  • the position and size of the spindle and the thickness of the first passivation protective layer determine the position of the doped pocket, and the second passivation
  • the thickness of the protective layer determines the size of the doped pocket
  • the position and size of the spindle, and the thickness of the first passivation protective layer and the second passivation protective layer determine the position of the source region
  • the position and size of the spindle determine the drain region
  • the position and size; the position and size of the main shaft, and the position of the target portion determine the position of the metal gate.
  • the thickness of the first passivation protective layer and the second passivation protective layer determines the size (width) of the metal gate.
  • the present application achieves a more accurate positioning of the source region (source), the drain region (drain), and the metal gate of the tunneling field effect transistor through a self-aligned process.
  • the position of the metal gate can be specifically determined by the selection of the target portion (Gate Cut process).
  • a smaller-sized gate width can be designed by controlling the thicknesses of the first passivation protective layer and the second passivation protective layer; by controlling the position and size of the main shaft, the first passivation protective layer and the second passivation
  • the thickness of the protective layer is designed to suit the doping pocket of the application.
  • the method for fabricating a tunneling field effect transistor provided by the present application can realize a gate width of a smaller size by adopting a self-aligned process, and can also realize a flexible design of a doping pocket, thereby overcoming the limitation of the conventional photolithography process. It can also be compatible with the conventional semiconductor process; in addition, the embodiment of the present invention also provides a solution for determining the fabrication position of the gate by removing the passivation protective layer, so that the solution has good feasibility.
  • the target portion further includes a portion of the second side and the fourth side adjacent to the first side.
  • the target portion includes, in addition to the first side of the rectangular ring, a portion of the second side and the fourth side of the rectangular ring adjacent to the first side, such that the rectangle is removed.
  • the fabricating the metal gate on the region of removing the passivation protective layer corresponding to the target portion includes: removing the target Etching is performed on a portion of the corresponding passivation protective layer; the metal gate is formed on the region after the etching.
  • the means of etching may be wet etching using hydrofluoric acid or a similar solution, or dry etching of a CF series. It should be understood that by etching the region where the first passivation protective layer and the second passivation layer are removed, the overlapping area of the gate and the source region can be increased, thereby increasing the tunneling area and thereby increasing the turn-on current.
  • the spindle is made of polysilicon.
  • the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.
  • the passivation protective layer is formed in an isotropic deposition and etching.
  • a method of fabricating an inverter comprising: fabricating a first major axis and a second major axis on a first region and a second region of a substrate, respectively, the first major axis and the first spindle
  • the axis of the second spindle is perpendicular to the first surface of the substrate, the projection of the first spindle on the first surface is a first rectangle, and the second spindle is on the first surface Projecting as a second rectangle, the first side of the first rectangle being parallel to the second rectangle One side, and the interval between the first rectangle and the second rectangle in the first direction and the interval in the second direction are both equal to a threshold, the first direction being the first side of the first rectangle a direction perpendicular to the first direction; covering a first passivation protective layer on a sidewall surface of the first main shaft and a sidewall surface of the second main shaft, respectively, the first The thickness of the passivation protective layer is equal to the threshold; and the region where the first region
  • the inverters are constituted by the two tunneling field effect transistors, which can be overcome by using a self-aligned process.
  • the limitations of traditional lithography processes allow for the precision of more sophisticated inverters.
  • the method provided by the embodiments of the present invention can be compatible with a conventional semiconductor process, and has good feasibility and repeatability.
  • the target portion further includes at least a portion of the first portion: the second side and the fourth side of the first rectangular ring are adjacent to the first portion The first side of the rectangular ring And the second side and the fourth side of the second rectangular ring are adjacent to a portion of the first side of the second rectangular ring.
  • space is reserved when removing the passivation protective layer to prevent drift or variation of the process to avoid damage to the gate structure of the tunneling field effect transistor.
  • the fabricating the metal gate on the region of removing the passivation protective layer corresponding to the target portion includes: removing the target Etching is performed on a portion of the corresponding passivation protective layer; the metal gate is formed on the region after the etching.
  • the material of the main shaft is polysilicon.
  • the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.
  • the passivation protective layer is formed in an isotropic deposition and etching.
  • FIG. 1 is a schematic flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 2 to FIG. 14 are schematic diagrams showing processes of fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 15 is a schematic flowchart of fabricating an inverter provided by an embodiment of the present invention.
  • FIG. 16 to FIG. 29 are schematic diagrams showing processes of fabricating an inverter according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a method 100 for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • the method 100 includes the following steps:
  • a spindle is fabricated on the substrate, the axis of the spindle being perpendicular to the first surface of the substrate.
  • the first surface represents the surface of the region of the substrate on which the spindle is made. Specifically, the projection of the main shaft on the first surface is a rectangle or approximately a rectangle.
  • the spindle is made of polysilicon (Poly Si).
  • the first passivation protective layer is covered on the sidewall surface of the main shaft.
  • a source region having a second doping type in a region where the doping region is not covered by the second passivation protective layer, and the region covered by the second passivation protective layer is formed adjacent to the source A doped pocket of the first doping type, the second doping type being opposite to the first doping type.
  • the doped region formed in step 103 is transformed into a source region having a second doping type and a doping pocket having a first doping type in the vicinity of the source region after step 104 and step 105 (Pocket) ).
  • the upper projection is a rectangular ring, and the rectangular ring includes a first side, a second side, a third side, and a fourth side, wherein the first side is located between the drain area and the source area, and the third side The first side is opposite.
  • the projection of the first passivation protective layer and the second passivation protective layer on the first surface is a rectangular ring around a region where the main axis is located, wherein one side of the rectangular ring (ie, the first side) Located between the drain region and the source region.
  • the rectangular ring is shown in Figure 9 below, as described in more detail below in connection with Figure 9.
  • the doping type of the doping pocket is opposite to the doping type of the source region, the doping type of the doping pocket is consistent with the doping type of the drain region, and the doping pocket is adjacent to the source region.
  • the passivation protective layer corresponding to the target portion is removed, and a metal gate is formed on a region where the passivation protective layer corresponding to the target portion is removed, wherein the tunneling field effect transistor includes the substrate, and the substrate a source region, the doped pocket, the drain region, and the metal gate.
  • the gate should be formed between the source region and the drain region. Therefore, the gate should be formed at the position of the first side of the rectangular ring, and no gate is required at the position of the other three sides of the rectangular ring. .
  • the target portion referred to in step 107 and step 108 is used to indicate the position at which the gate needs to be made, and the portion of the rectangular ring other than the target portion indicates the position at which the gate is not required to be formed.
  • step 107 and step 108 the fabrication process of step 107 and step 108 may be referred to as a gate cut process.
  • the method 100 further includes forming a source on the source region and forming a drain on the drain region. That is, the tunneling field effect transistor fabricated by the method 100 includes an insulating substrate, a source region, a doping pocket, a drain region, a source, a drain, and a metal gate adjacent to the source region and opposite to the source region doping type.
  • the position and size of the main shaft and the thickness of the first passivation protective layer determine the position of the doped pocket
  • second The thickness of the passivation protective layer determines the size of the doped pocket
  • the position and size of the spindle, and the thickness of the first passivation protective layer and the second passivation protective layer determine the position of the source region
  • the position and size of the spindle determine The position and size of the drain region
  • the position and size of the spindle, and the position of the target portion determine the position of the metal gate.
  • the thickness of the first passivation protective layer and the second passivation protective layer determine the size of the metal gate (width) ).
  • the embodiment of the present invention achieves a more accurate positioning of the source region (source), the drain region (drain), and the metal gate of the tunneling field effect transistor by a self-aligned process.
  • the position of the metal gate can be specifically determined by the selection of the target portion (Gate Cut process).
  • a smaller-sized gate width can be designed by controlling the thicknesses of the first passivation protective layer and the second passivation protective layer; by controlling the position and size of the main shaft, the first passivation protective layer and the second passivation
  • the thickness of the protective layer is designed to suit the doping pocket of the application.
  • the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention can realize a gate width of a smaller size by using a self-aligned process, and can also realize a flexible design of a doping pocket, thereby overcoming the conventional photolithography process.
  • the limitation is also compatible with the conventional semiconductor process; in addition, the embodiment of the present invention further provides a solution for determining the fabrication position of the gate by removing the passivation protective layer, so that the solution has good feasibility.
  • the method for fabricating a tunneling field effect transistor provided by the embodiments of the present invention can be applied to a planar device, such as a Fin Field-Effect Transistor (FinFET) device, or On a silicon on insulator (SOI) device.
  • a planar device such as a Fin Field-Effect Transistor (FinFET) device, or On a silicon on insulator (SOI) device.
  • FinFET Fin Field-Effect Transistor
  • SOI silicon on insulator
  • the target portion further includes a portion of the second side and the fourth side adjacent to the first side.
  • the excess passivation protective layer is typically removed using a reticle, but process drift or variation may occur during the ablation process. If the target portion includes only the first side of the rectangular ring, then in step 107, the passivation protective layer corresponding to the portion other than the first side of the rectangular ring is to be cut, if a process drift occurs during the cutting process or Variation, it is possible to cut off the corresponding passivation protective layer in the first side, so that the gate prepared in step 108 is imperfect, corresponding to the destruction of the gate due to drift or variation of the process.
  • the target portion further includes a portion of the second side and the fourth side of the rectangular ring near the first side.
  • the second side and the fourth side of the rectangular ring are close to the third side and the passivation protective layer corresponding to the third side, and the second side is not close to the fourth side.
  • a passivation protective layer corresponding to the portion of the first side is not destroyed or a small probability.
  • the projection of the remaining uncut passivation protective layer on the first surface includes a first side of the rectangular ring, and further includes a protrusion of the first side opposite the drain region Part, as shown in Figure 14.
  • the embodiment of the present invention can avoid damage to the gate during the fabrication process.
  • the metal gate is formed on the region where the passivation protective layer corresponding to the target portion is removed, including:
  • Etching is performed on a region where the passivation protective layer corresponding to the target portion is removed;
  • a metal gate is formed on the area after etching.
  • the means of etching may be wet etching using hydrofluoric acid or a similar solution, or dry etching of a CF series. It should be understood that by etching the region where the first passivation protective layer and the second passivation layer are removed, the overlapping area of the gate and the source region can be increased, thereby increasing the tunneling area and thereby increasing the turn-on current.
  • the method 100 before removing the spindle, further includes: covering the region of the source region on the first surface with an oxide;
  • step 107 before removing the passivation protective layer corresponding to the portion other than the target portion in the rectangular ring, the method 100 further includes covering the oxide on the region of the drain region on the first surface.
  • the region where the source region is located on the first surface covers the oxide in order to protect the source region from the subsequent doping step; the region where the drain region is located on the first surface is covered with oxide to protect the drain region from being protected. The effect of subsequent doping steps.
  • the oxide is, for example, silicon dioxide (SiO 2 ), or the oxide may be FCVD (Flowable CVD), SOG (Spin on Glass), HDP (High Density Plasma CVD), or HARP (High-Aspect- Ratio Process CVD) is a similar material.
  • FCVD Flowable CVD
  • SOG Spin on Glass
  • HDP High Density Plasma CVD
  • HARP High-Aspect- Ratio Process CVD
  • the first surface is not adjacent to the region covered by the first passivation protective layer and the main axis.
  • the specific region of the region of the first passivation protective layer (referred to as region 1) forming the doped region having the first doping type is: ion implantation of region 1 using an N+ mask, or using a hard film pair region Etching and epitaxy to form an N-doped doped region; in step 105, forming a second doped region in the region where the doped region is not covered by the second passivation protective layer (referred to as region 2)
  • the specific mode of the impurity type source region is: ion implantation of the region 2 by using a P+ mask, or etching and epitaxy of the region 2 by a hard film method to form a P-type doped source region; in step 106, The specific manner of forming the drain region having the first doping type on the region where the main axis.
  • the material of the main shaft is polysilicon.
  • the material of the first passivation protective layer, the second passivation protective layer and the third passivation protective layer is any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.
  • the passivation protective layer is formed in an isotropic manner Product and etching.
  • FIG. 2 to FIG. 10 are schematic diagrams showing a process of a method 100 for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • Step 101 as shown in FIG. 2, a spindle 202 is formed on the first surface of the substrate 201, and the axis of the spindle 202 is perpendicular to the first surface.
  • the substrate 201 may be a substrate of a Fin structure.
  • the material of the substrate 201 may be poly-silicon or the like.
  • the surface of the substrate may be covered with a thin oxide layer.
  • the main axis 202 is formed on the substrate 201 by depositing on the first surface of the substrate 201 to form the spindle 202.
  • the material of the main shaft 202 may be polysilicon.
  • Step 102 covers the first passivation protective layer 203 on the sidewall surface of the main shaft 202.
  • the first passivation protective layer 203 is made of a nitride, and may be, for example, silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon oxynitride (SiON).
  • the first passivation protective layer 203 is covered on the sidewall surface of the main shaft 202 by depositing silicon nitride on the sidewall surface of the main shaft 202. Then, an isotropic etch is used to create a spacer or sidewall (ie, a first passivation protective layer).
  • the first passivation protective layer may also be referred to as a first nitride spacer.
  • Step 103 in a region immediately adjacent to the first passivation protective layer 203 in a region where the first surface of the substrate 201 is not covered by the main axis 202 and the first passivation protective layer 203 (referred to as region 1) A doped region 204 having a first doping type is formed thereon.
  • the substrate 201 may not be on the substrate 201 and the first axis
  • the doped region 204 may be formed on a portion of the region covered by the passivation protective layer 203 adjacent to the first passivation protective layer 203.
  • the region of the substrate 201 that is not covered by the main axis 202 and the first passivation protective layer 203 and adjacent to the first passivation protective layer 203 includes at least two parts: 204 in FIG.
  • the area indicated, and the area on the substrate 201 away from the area indicated by 204 and adjacent to 203, in this embodiment, the doped area having the first doping type can be formed only on the area indicated by 204. .
  • the first doping type mentioned in the embodiment of the present invention may be N-type or P-type, and if the first doping type is N-type, the second doping type appearing below For the P type, if the first doping type is P type, the second doping type appearing below is N type.
  • the specific manner of forming the doping region 204 is: using the existing N+ mask to ion-implant the region 1 to form an N-type doping, or to utilize The Hard mask method etches and epitaxes the region 1 to form an N-type hetero doping.
  • the doped region 204 formed in this step will subsequently form a doped pocket (Pocket layer) adjacent to the source region.
  • the energy of the ion implantation can control the depth of doping of the doping region 204. If the doping depth is deep, a "Full Pocket layer" is formed later, if the doping depth is shallow The follow-up will form the "Split Pocket Layer".
  • Step 104 covers the second passivation protective layer 205 on the surface of the first passivation protective layer 203.
  • the material of the second passivation protective layer 205 is also a nitride such as silicon nitride (Si3N4), silicon dioxide (SiO2) or silicon oxynitride (SiON).
  • a specific manner of forming the second passivation protective layer 205 To: deposit silicon nitride on the sidewall of the first passivation protective layer 203 away from the main axis 202, and then use an isotropic etching to create a spacer or a sidewall (ie, the second passivation protective layer 205).
  • the second passivation protective layer 205 may also be referred to as a “second nitride spacer”.
  • the thickness of the second passivation protective layer 205 is smaller than the size of the doping region 204 in the direction of the thickness. In other words, a portion of the second passivation protection layer 205 covers a portion of the doped region 204. It should be noted that the portion of the doping region 204 covered by the second passivation protective layer 205 may subsequently form a doping pocket adjacent to the source region and opposite to the doping type of the drain region.
  • Step 105 as shown in FIG. 6, forming a source region 206 having a second doping type in a region (referred to as region 2) where the doped region 204 is not covered by the second passivation protective layer 205, the second doping The type is opposite to the first doping type, and the remaining portion of the doped region 204 that is not formed as the source region 206 is defined as a doped pocket 207 having a first doping type proximate to the source region 206.
  • the specific way of forming the source region 206 is to use the existing P+ reticle to implant the region 2 into the P-type doping.
  • the P-type hetero-doping is formed by etching and epitaxy of the region 2 by a Hard mask method to form a P-type doped source region 206.
  • the first doping type is P-type and the second doping type is N-type, an N-doped source region 206 is formed in this step.
  • the thickness of the second passivation protective layer 205 determines the size of the doped pocket 207. Specifically, the thickness of the second passivation protective layer 205 is the width of the doped pocket 207 in the view shown in FIG.
  • Step 106 removes the spindle 202 and forms a drain region 209 having a first doping type on the region where the spindle 202 is removed (denoted as region 3).
  • the oxide region 208 is overlaid on the region of the source region 206 on the first surface of the substrate 201, in other words, the oxide 208 is filled in the second passivation protective layer 205 and the source region. 206 is located in a space enclosed by the area of the first surface to protect the source region 206.
  • the oxide 208 may be, for example, silicon dioxide (SiO2), or may be a similar material such as FCVD, SOG, HDP or HARP. It should be understood that after the oxide 208 is filled over the source region 206, the surface of the entire article can then be planarized by a planarization process, for example, etching and chemical mechanical polishing can be used to achieve a planarization process.
  • the spindle 202 is removed such that the region of the substrate 201 that was originally covered by the spindle 202 (ie, region 3) is exposed, and the region 3 is first
  • the doping type is doped to form a drain region 209 having a first doping type.
  • the major axis (poly Si) can be removed using a Tetramethylammonium Hydroxide (TMAH) solution or an ammonia-base solution.
  • TMAH Tetramethylammonium Hydroxide
  • the specific manner of forming the drain region 209 is: using the existing N+ mask to ion-implant the region 3 to form an N-type doping, or using a Hard mask.
  • the region 3 is etched and epitaxially formed to form an N-type hetero-doping to form an N-doped drain region 208.
  • FIG. 9 is a top view corresponding to FIG. 8.
  • the projection of the first passivation protective layer 203 and the second passivation protective layer 205 on the first surface is a rectangular ring, and the rectangular ring includes the first a side 10, a second side 20, a third side 30 and a fourth side 40, wherein the first side 10 is located between the drain area 209 and the source area 206, and the third side 30 is opposite to the first side 10 .
  • each side of the rectangular ring that the passivation protective layers 203 and 205 project on the first surface has a width property, and therefore, any two adjacent sides of the rectangular ring have overlapping portions.
  • the sides of the rectangular ring include overlapping portions of the side and adjacent sides.
  • the first side 10 includes its overlapping portion with the second side 20, and also includes an overlapping portion thereof with the fourth side 40.
  • Step 107 removes the passivation protective layer corresponding to the portion other than the target portion of the rectangular ring, and the target portion includes the first side 10 of the rectangular ring.
  • the passivation protective layer corresponding to the portion other than the target portion of the rectangular ring may be removed by a photomask process.
  • step 107 The result after performing step 107 is as shown in FIG. 11.
  • the passivation protective layers (203 and 205) formed after the completion of step 104 the passivation protective layer corresponding to the first side 10 is retained, and the remaining portions are removed. .
  • the passivation protective layer can be removed using phosphoric acid.
  • Step 108 as shown in FIG. 12 and FIG. 13, removing the passivation protective layer corresponding to the target portion, and forming a metal gate on the region (referred to as region 4) for removing the passivation protective layer corresponding to the target portion.
  • the pole 210 wherein the tunneling field effect transistor comprises the substrate, the source region, the doped pocket, the drain region and the metal gate.
  • the oxide 208 is first covered on the region of the drain region 209 on the first surface of the substrate 201 to protect the drain region 209. It should also be understood that after the oxide 208 is filled over the drain region 209, the surface of the entire article can then be planarized by a planarization process, for example, etching and chemical mechanical polishing can be used to achieve a planarization process.
  • a planarization process for example, etching and chemical mechanical polishing can be used to achieve a planarization process.
  • the passivation protective layer corresponding to the target portion is removed, so that the region of the substrate 201 that is originally covered by the passivation protective layer corresponding to the target portion (ie, the region) 4) Exposed, and a metal gate 210 is formed on the region 4.
  • the region of the substrate 201 that was originally covered by the passivation protective layer corresponding to the target portion is the gate underlayer of the tunneling field effect transistor.
  • the region 4 may be first etched, for example, wet etching using hydrofluoric acid or a similar solution, or CF series Dry etching; then metal gate 210 is fabricated over the area after etching.
  • etching the region of the passivation protective layer corresponding to the removal target portion can enlarge the underlying area of the gate, thereby increasing the overlapping area of the gate and the source region (source), thereby increasing the on-state current. .
  • oxide 208 for protecting source region 206 and drain region 209 may be removed after fabrication of metal gate 210 is completed.
  • the field effect transistor fabricated by the method provided by the embodiment of the present invention includes an insulating substrate 201, a source region 206 (source), an adjacent source region, and a source region.
  • the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention can realize a gate width of a smaller size by using a self-aligned process, and can also realize a flexible design of a doping pocket, thereby overcoming the conventional photolithography process.
  • the limitation is also compatible with the conventional semiconductor process; in addition, the embodiment of the present invention further provides a solution for determining the fabrication position of the gate by removing the passivation protective layer, so that the solution has good feasibility.
  • the type of tunneling field effect transistor fabricated by using the process flow of FIG. 2 to FIG. 13 is pnin;
  • the doping type is P type, and the second doping type is N type, and the type of tunneling field effect transistor fabricated by using the process flow of FIG. 2 to FIG. 13 is npip. That is, two types of tunneling field effect transistors having a doped pocket structure can be prepared by the method provided by the embodiments of the present invention.
  • the target portion includes a portion of the second side 20 and the fourth side 40 of the rectangular ring adjacent to the first side 10 in addition to the first side 10 of the rectangular ring.
  • the portion of the second side 20 adjacent to the first side 10 refers to a portion of the second side 20 that is adjacent to the first side 10 except for the overlapping portion with the first side 10, and the same reason,
  • the portion of the four sides 40 near the first side 10 refers to a portion of the fourth side 40 other than the overlapping portion with the first side 10, which is close to the first side 10, as in the case shown in FIG.
  • the portion includes a first side 10 and further includes two protrusions at both ends of the first side 10 in the direction of the deflecting drain region 209.
  • the passivation protective layer corresponding to the first side is not destroyed or a small probability.
  • an embodiment of the present invention further provides a method 300 for fabricating an inverter, the method 300 comprising the following steps:
  • first main axis and a second main axis on the first region and the second region of the substrate, wherein the axes of the first main axis and the second main axis are perpendicular to the first surface of the substrate, the first The interval between the main shaft and the second main shaft in two mutually perpendicular directions is equal to a threshold value, in other words, the projection of the first main shaft on the first surface is a first rectangle, and the second main shaft is on the first surface
  • the upper projection is a second rectangle, the first side of the first rectangle is parallel to one side of the second rectangle, and the interval between the first rectangle and the second rectangle in the first direction and the interval in the second direction Both are equal to a threshold, and the first direction is a direction in which the first side of the first rectangle is located, and the second direction is perpendicular to the first direction.
  • the material of the first main shaft and the second main shaft are both polysilicon (Poly Si).
  • the first passivation protective layer is covered on a sidewall surface of the first main shaft and a sidewall surface of the second main shaft, and a thickness of the first passivation protective layer is equal to the threshold.
  • the threshold may be set according to actual needs.
  • the threshold can be determined according to the size of the gate of the tunneling field effect transistor (the width of the gate in the top view) that is actually desired to be fabricated.
  • N-type doping is performed on a region of the first region that is not covered by the first passivation protective layer and the first main axis, and the first doped region is formed.
  • the region is an N-doped first doped pocket
  • the second passivation is in the region where the second region is not covered by the first passivation protective layer, the second passivation protective layer and the second spindle P-type doping is performed on the region of the protective layer to form a second drain region.
  • the first main axis and the second main axis are removed, and P-type doping is performed on a region where the second main axis is removed to form a second doped region.
  • the third passivation protective layer is covered on the surface of the first passivation protective layer away from the second passivation protective layer, the first passivation protective layer, the second passivation protective layer and the third passivation protection
  • the projection of the layer on the first surface is a figure-eight pattern comprising a first rectangular ring surrounding a region from which the first major axis is removed and a second rectangular ring surrounding a region from which the second major axis is removed, the first rectangle
  • the ring includes a first side, a second side, a third side, and a fourth side, the first side of the first rectangular ring is located between the first source region and the first drain region, and the third side of the first rectangular ring Opposite the first side of the first rectangular ring, the second rectangular ring includes a first side, a second side, a third side and a fourth side, and the first side of the second rectangular ring is located in the second source area Between the second drain region, a third side of the second rectangular ring is opposite the first
  • the substrate, the first source region, the first source, the first drain region, the first drain, and a metal gate between the first source region and the first drain region are of a type pnin a tunneling field effect transistor, the substrate, the second source region, the second source, the second drain region, the second drain, and between the second source region and the second drain region
  • the metal gate constitutes a tunneling field effect transistor of the type npip
  • the inverter comprising a tunneling field effect transistor of the type pnin and a tunneling field effect transistor of the type npip
  • the metal gate being used as the inverse An input end of the phase converter
  • the first drain is connected to the second drain and used as an output end of the inverter
  • the second source is used as a power input end of the inverter, the first source Extremely used as the ground for this inverter.
  • the interval between the projection of the first major axis in the first plane (the first rectangle) and the projection of the second major axis in the first plane (the second rectangle) is based on the tunneling field effect to be finally formed.
  • the size of the gate of the transistor is determined, in particular, the width of the gate of the finally formed tunneling field effect transistor (from the perspective of the top view) is equal to the first passivation protective layer, the second passivation protective layer and the third blunt.
  • the sum of the thicknesses of the protective layers which is equal to the thickness of the first passivation protective layer, such that the gates of the two tunneling field effect transistors are connected together, and also the resulting two tunneling field effect transistors It is just right to form an inverter.
  • the embodiment of the present invention two types of tunneling field effect transistors are simultaneously fabricated by using a self-aligned process, and the inverters are constituted by the two tunneling field effect transistors, and a self-aligned process is adopted. Therefore, the limitations of the conventional lithography process can be overcome, so that the precision of a relatively precise inverter can be made.
  • the method provided by the embodiments of the present invention can be compatible with a conventional semiconductor process, and has good feasibility and repeatability.
  • the target part further includes at least a part of the following parts:
  • a second side and a fourth side of the first rectangular ring are adjacent to a portion of the first side of the first rectangular ring, and the second side and the fourth side of the second rectangular ring are adjacent to the first side of the second rectangular ring section.
  • space is reserved when the passivation protective layer is removed to prevent drift or variation of the process to avoid damage to the gate structure of the tunneling field effect transistor.
  • the metal gate is formed on the region where the passivation protective layer corresponding to the target portion is removed, including: etching on the region where the passivation protective layer corresponding to the target portion is removed The metal gate is fabricated on the area after the etching.
  • the means of etching may be wet etching using hydrofluoric acid or a similar solution, or dry etching of a CF series. It should be understood that by etching the region where the first passivation protective layer and the second passivation layer are removed, the overlapping area of the gate and the source region can be increased, thereby increasing the tunneling area and thereby increasing the turn-on current.
  • the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.
  • the passivation protective layer is formed in an isotropic deposition and etching.
  • FIG. 16 to FIG. 29 are schematic diagrams showing processes corresponding to the method 300 for fabricating the inverter 400 according to an embodiment of the present invention.
  • Step 301 as shown in FIG. 16, respectively, on the first region 501 and the second region 601 of the substrate 401 A spindle and a second spindle.
  • the axes of the first main axis and the second main axis are both perpendicular to the first surface of the substrate 401, and the first surface represents the surfaces of the first region 501 and the second region 602.
  • the projection of the first main axis on the first surface is a first rectangle 502
  • the projection of the second main axis on the first surface is a second rectangle 602, the first of the first rectangle 502
  • the side is parallel to one side of the second rectangle 602, and the interval between the first rectangle 502 and the second rectangle 602 in the first direction (L1 labeled in FIG. 16) and the interval in the second direction (as shown in FIG. L1) denoted in 16 is equal to a threshold
  • the first direction is a direction in which the first side of the first rectangle is located
  • the second direction is perpendicular to the first direction.
  • Step 302 as shown in FIG. 17, covering a sidewall surface of the first main shaft and a sidewall surface of the second main shaft with a first passivation protective layer, and a projection of the first passivation protective layer on the first surface
  • the thickness of the first passivation protective layer is equal to the threshold, that is, the width of the projection 402 shown in FIG. 17 is equal to L1 or L2.
  • Step 303 as shown in FIG. 18, in the region where the first region 501 is not covered by the first passivation protective layer (corresponding to the projection 402) and the first main axis (corresponding to the rectangle 502) is in close proximity to the first blunt N-type doping is performed on the region of the protective layer to form a first doped region 503.
  • Step 304 covering the surface of the first passivation protective layer with a second passivation protective layer, and the projection of the second passivation protective layer on the first surface is as shown by the numeral 403 in FIG. Hereinafter referred to as projection 403).
  • the thickness of the second passivation protective layer 403 is smaller than the dimension of the first doping region 503 in the direction of the thickness.
  • a portion of the second passivation protection layer 403 covers a portion of the first doped region 503. It should be noted that the portion of the first doping region 503 covered by the second passivation protective layer 403 may subsequently form a first doping pocket adjacent to the first source region and opposite to the doping type of the first drain region.
  • Step 305 as shown in FIG. 20, performing P-type doping on the region where the first doping region 503 is not covered by the second passivation protective layer (corresponding to the projection 403), forming a first source region 504.
  • the region of the first doping region 503 covered by the second passivation protective layer is an N-doped first doping pocket 505, and the second region 601 is not the first passivation protective layer, the second blunt The protective layer and the second spindle cover (corresponding to the projections 402, 403 and 602) are P-type doped on the region immediately adjacent to the second passivation protective layer to form a second drain region 603.
  • Step 306 as shown in FIG. 21, remove the first main axis and the second main axis (corresponding to the projection 502 and the projection 602), and perform P-type doping on the region where the second main axis is removed to form a second doping. Area 604.
  • first main axis and the second main axis may be removed using a TMAH solution or an amino solution.
  • Step 307 as shown in FIG. 22, the third passivation protective layer is covered on the surface of the first passivation protective layer away from the second passivation protective layer, and the projection of the third passivation protective layer on the first surface is as shown in FIG.
  • the label 404 is shown (hereinafter referred to as projection 404).
  • the thickness of the third passivation protective layer 404 is smaller than the dimension of the second doping region 603 in the direction of the thickness.
  • a portion of the third passivation protection layer 603 covers a portion of the second doped region 604. It should be noted that the portion of the second doping region 604 covered by the third passivation protective layer 404 may subsequently form a second doping pocket adjacent to the second source region and opposite to the second drain region doping type.
  • Step 308 as shown in FIG. 23, N-type doping is performed in a region where the second doping region 604 is not covered by the third passivation protective layer (corresponding to the projection 403), and a second source region 605 is formed.
  • the region of the second doping region 604 covered by the third passivation protective layer (corresponding to the projection 404) is a P-doped second doping pocket 606, and N-type doping is performed in a region where the first major axis is removed.
  • the first passivation protective layer, the second passivation protective layer and the third passivation protective layer are at the first
  • the projection of the surface is a figure-eight pattern comprising a first rectangular ring surrounding a region from which the first major axis is removed and a second rectangular ring surrounding a region from which the second major axis is removed, the first rectangular ring including the first side
  • the second side 52, the third side 53 and the fourth side 54 are located between the first source region 504 and the first drain region 506, the first rectangular ring
  • the third side 53 is opposite to the first side 51 of the first rectangular ring
  • the second rectangular ring includes a first side 61, a second side 62, a third side 63 and a fourth side 64, the second rectangular ring
  • One side 61 is located between the second source region 605 and the second drain region 603, and the third side 63 of the second rectangular ring is opposite to the first side 61 of the second rectangular ring.
  • Step 309 removing the passivation protective layer corresponding to the portion other than the target portion of the figure-eight pattern shown in FIG. 23, the target portion including the first side 51 of the first rectangular ring and the second rectangle The first side of the ring 61.
  • the sides of the rectangular ring referred to in the embodiments of the present invention include an overlapping portion of the side and the adjacent side, that is, the first side 51 of the first rectangular ring includes the second side 52 and
  • the overlapping portion of the fourth side 54 includes a first portion 61 of the second rectangular ring that overlaps the second side 62 and the fourth side 64.
  • the result after performing step 309 is as shown in FIG. 24, in the passivation protective layer corresponding to the figure-eight pattern shown in FIG. 23, the first side 51 and the second rectangular ring of the first rectangular ring The passivation protective layer corresponding to the first side 61 is retained, and the portion is removed.
  • the passivation protective layer can be removed using phosphoric acid.
  • the target portion further includes at least a portion of the second portion 52 and the fourth side 54 of the first rectangular ring adjacent to a portion of the first side 51 of the first rectangular ring,
  • the second side 62 and the fourth side 64 of the second rectangular ring are adjacent to a portion of the first side 61 of the second rectangular ring.
  • the portion of the second side 52 that is close to the first side 51 refers to the portion of the second side 52 that is adjacent to the first side 51 except for the overlapping portion with the first side 51.
  • the portion of the four sides 54 that is adjacent to the first side 51 refers to a portion of the fourth side 54 that is adjacent to the first side 51 except for the overlapping portion with the first side 51.
  • the portion of the second side 62 that is adjacent to the first side 61 refers to a portion of the second side 62 that is adjacent to the first side 61 except for the overlapping portion with the first side 61.
  • the fourth side The portion of the 64 adjacent to the first side 61 refers to a portion of the fourth side 64 other than the overlapping portion with the first side 61, which is close to the first side 61.
  • the target portion includes the first side 51 of the first rectangular ring, and the portion of the second side 52 and the fourth side 54 that are close to the first side 51
  • the result of the completion of the step 309 is as shown in FIG. 25
  • the target portion includes the first side 61 of the second rectangular ring, and the portion of the second side 62 and the fourth side 64 that are closer to the first side 61
  • the result of the completion of the step 309 is as shown in FIG.
  • the portion includes a first side 51 of the first rectangular ring, and a portion of the second side 52 and the fourth side 54 adjacent to the first side 51, and further includes a first side 61 of the second rectangular ring, and a second side 62 and a fourth side
  • the edge 64 is close to the portion of the first side 61, and the result of the completion of the step 309 is as shown in FIG.
  • Step 310 as shown in FIG. 28, removing the passivation protective layer corresponding to the target portion, and forming a metal gate on the region where the passivation protective layer corresponding to the target portion is removed, wherein the first region 501 is The metal gate formed thereon is denoted by 507, the metal gate formed on the second region 601 is denoted as 607, and a first source is formed in the first source region 504, and a first drain is formed in the first drain region 506. a second source is formed in the second source region 605, and a second drain is formed in the second drain region 603, wherein
  • the substrate 401, the first source region 504, the first source, the first drain region 506, the first drain, the first doping pocket 505, and the metal gate 507 form a tunnel of the type pnin
  • the field effect transistor, the substrate 401, the second source region 605, the second source, the second drain region 603, the second doping pocket 606, and the metal gate 607 form a tunneling field of the type npip Effect transistor.
  • the inverter 400 to be fabricated in the embodiment of the present invention includes a tunneling field effect transistor of the type pnin and a tunneling field effect transistor of the type npip, as shown in FIG. 29, the metal gate (507 and 607)
  • the first drain is connected to the second drain and used as an output terminal of the inverter 400, and the second source is used as a power source of the inverter 400.
  • the first source is used as a ground terminal of the inverter 400.
  • the inverter based on the tunneling field effect transistor can be fabricated by the method provided by the embodiment of the present invention. Since the self-aligned process is adopted, the limitation of the conventional photolithography process can be overcome, and a relatively precise device can be fabricated. In addition, the method provided by the embodiments of the present invention can be compatible with a conventional semiconductor process, and has good feasibility and repeatability.
  • the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention can achieve a smaller gate width by overcoming the limitation of the photolithography process by using a self-aligned process to fabricate a tunneling field effect transistor.
  • the flexible design of the doping pocket can be realized, and it can be compatible with the traditional semiconductor process, and has good feasibility and repeatability, so that it can be applied to the actual manufacturing process of the tunneling field effect transistor.
  • the method for fabricating an inverter provided by the embodiment of the invention also has good feasibility and repeatability, and thus can be applied to the actual manufacturing process of the inverter.

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Abstract

Cette invention concerne également un procédé de fabrication d'un transistor à effet tunnel et un procédé de fabrication d'un onduleur. Le procédé de fabrication d'un transistor à effet tunnel comprend : la fabrication d'un axe principal (202) sur un substrat (201) ; la couverture de l'axe principal (202) par une première couche protectrice de passivation (203) ; la formation d'une région dopée (204) sur une zone immédiatement adjacente à la première couche protectrice de passivation (203) dans une zone qui n'est pas couverte par la première couche protectrice de passivation (203) et l'axe principal (202) ; la couverture de la première couche protectrice de passivation (203) par une seconde couche protectrice de passivation (205) ; la formation d'une région de source (206), dont le type de dopage est opposé à celui de la région dopée (204), dans une zone dans la région dopée qui n'est pas recouverte par la seconde couche protectrice de passivation (205) ; l'élimination de l'axe principal (202), et la formation d'une région de drain (209) sur la zone de laquelle l'axe principal (202) est éliminé, une projection de la première couche protectrice de passivation (203) et de la seconde couche protectrice de passivation (205) sur une première surface formant un anneau rectangulaire ; l'élimination d'une couche protectrice de passivation correspondant à une partie de l'anneau rectangulaire autre qu'une partie cible ; l'élimination d'une couche protectrice de passivation correspondant à la partie cible, et la fabrication d'une grille métallique (210) sur la zone à partir de laquelle la couche protectrice de passivation correspondant à la partie cible a été éliminée. Ainsi, les limitations du processus de photolithographie peuvent être surmontées.
PCT/CN2017/075717 2017-03-06 2017-03-06 Procédé de fabrication d'un transistor à effet de tunnel et procédé de fabrication d'onduleur Ceased WO2018161206A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104027A (zh) * 2010-12-17 2011-06-22 复旦大学 一种在单块芯片上集成高性能器件与低功耗器件的制造方法
CN102623495A (zh) * 2012-04-09 2012-08-01 北京大学 一种多掺杂口袋结构的隧穿场效应晶体管及其制备方法
CN104201175A (zh) * 2014-09-03 2014-12-10 东南大学 一种基于薄膜晶体管的反相器
CN104465657A (zh) * 2013-09-22 2015-03-25 中芯国际集成电路制造(上海)有限公司 互补tfet及其制造方法
DE102014018382A1 (de) * 2014-12-15 2016-06-16 Forschungszentrum Jülich GmbH Tunnel-Feldeffekttransistor sowie Verfahren zu dessen Herstellung

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104027A (zh) * 2010-12-17 2011-06-22 复旦大学 一种在单块芯片上集成高性能器件与低功耗器件的制造方法
CN102623495A (zh) * 2012-04-09 2012-08-01 北京大学 一种多掺杂口袋结构的隧穿场效应晶体管及其制备方法
CN104465657A (zh) * 2013-09-22 2015-03-25 中芯国际集成电路制造(上海)有限公司 互补tfet及其制造方法
CN104201175A (zh) * 2014-09-03 2014-12-10 东南大学 一种基于薄膜晶体管的反相器
DE102014018382A1 (de) * 2014-12-15 2016-06-16 Forschungszentrum Jülich GmbH Tunnel-Feldeffekttransistor sowie Verfahren zu dessen Herstellung

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